Integrated circuit, power supply circuit

Abstract

The integrated circuit of the present invention switches a transistor that controls the inductor current based on the inductor current flowing through an inductor to which a rectified voltage from a rectifier circuit that rectifies an AC voltage is applied and an output voltage generated from the AC voltage, and includes: a sample-and-hold circuit that samples and holds a voltage corresponding to the rectified voltage at a prescribed timing; an output circuit that outputs a limit voltage indicating a limit value for limiting the inductor current based on the voltage held by the sample-and-hold circuit; and a first signal output circuit that outputs a first signal for turning off the transistor based on a voltage corresponding to the inductor current and the limit voltage when a current value of the inductor current is greater than the limit value.

Description

Technical Field

[0001] The present invention relates to an integrated circuit and a power supply circuit. Background Art

[0002] In a general power factor improvement circuit, an overcurrent protection circuit is provided. When the inductor current exceeds a specified value indicating overcurrent, the overcurrent protection circuit turns off the transistor to protect the transistor from overcurrent (for example, Patent Document 1).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Laid-Open No. 2009-11147 Summary of the Invention

[0006] Technical Problem to be Solved by the Invention

[0007] However, when the AC voltage input to the power factor improvement circuit suddenly increases, the inductor current also increases accordingly. At this time, although the inductor current is less than the specified value indicating overcurrent, it may sometimes be large enough to generate a surge voltage in the transistor. Since the overcurrent protection circuit cannot prevent such a surge voltage, the characteristics of the transistor deteriorate.

[0008] The present invention has been made in view of the above-described problems of the prior art, and an object thereof is to provide an integrated circuit that can appropriately protect a transistor for controlling an inductor current.

[0009] Technical Solution for Solving the Technical Problem

[0010] A first aspect of the present invention for solving the above technical problem is an integrated circuit that switches a transistor for controlling the inductor current based on an inductor current flowing through an inductor and an output voltage generated from an AC voltage. The inductor is applied with a rectified voltage from a rectifier circuit that rectifies the AC voltage, and includes: a sample-and-hold circuit that samples and holds a voltage corresponding to the rectified voltage at a specified timing; an output circuit that outputs a limit voltage indicating a limit value for limiting the inductor current based on the voltage held by the sample-and-hold circuit; and a first signal output circuit that outputs a first signal for turning off the transistor when a current value of the inductor current is greater than the limit value based on a voltage corresponding to the inductor current and the limit voltage.

[0011] A second aspect of the present invention is a power supply circuit that generates an output voltage based on a specified AC voltage, comprising: a rectifier circuit that rectifies the specified AC voltage; an inductor to which the rectified voltage from the rectifier circuit is applied; and an integrated circuit that drives a transistor for controlling the inductor current based on the inductor current flowing through the inductor and the output voltage. The integrated circuit includes: a sample-and-hold circuit that samples and holds a voltage corresponding to the rectified voltage at a specified timing; an output circuit that outputs a limit voltage representing a limit value for limiting the inductor current based on the voltage held by the sample-and-hold circuit; and a first signal output circuit that outputs a first signal for turning off the transistor when the current value of the inductor current is greater than the limit value based on a voltage corresponding to the inductor current and the limit voltage.

[0012] Advantages of the Invention

[0013] According to the present invention, an integrated circuit can be provided that can appropriately protect a transistor for controlling an inductor current. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. is a diagram showing an example of the AC-DC converter 10.

[0015] Figure 2 FIG. is a diagram showing an example of the power factor improvement IC 25.

[0016] Figure 3 FIG. is a diagram showing an example of the surge prevention circuit 79.

[0017] Figure 4 FIG. is a diagram for explaining the operation of the power factor improvement IC 25.

[0018] Figure 5 FIG. is a diagram for explaining the operation of the AC-DC converter 10.

[0019] Figure 6 FIG. is a diagram showing the main waveforms of the AC-DC converter 10 when the AC voltage Vac changes rapidly.

[0020] Figure 7 FIG. is a diagram showing the main waveforms of the AC-DC converter 10 when the AC voltage Vac changes rapidly.

[0021] Figure 8 FIG. is a diagram showing an example of the AC-DC converter 15.

[0022] Figure 9 FIG. is a diagram showing an example of the power factor improvement IC 310.

[0023] Figure 10 This is a diagram showing an example of the surge prevention circuit 400. DETAILED DESCRIPTION

[0024] CROSS-REFERENCE TO RELATED APPLICATIONS

[0025] This application claims priority based on Japanese Patent Application No. 2019-115104 filed on June 21, 2019, and incorporates its content.

[0026] From the description of this specification and the drawings, at least the following matters become clear.

[0027] ===== THIS EMBODIMENT =====

[0028] Figure 1 This is a diagram showing the structure of the AC-DC converter 10 according to an embodiment of the present invention. The AC-DC converter 10 is a boost chopper type power supply circuit that generates an output voltage Vout of a target level from the AC voltage Vac of a commercial power supply.

[0029] The load 11 is, for example, a DC-DC converter or an electronic device that operates using a DC voltage.

[0030] <<< OUTLINE OF AC-DC CONVERTER 10 >>>

[0031] The AC-DC converter 10 includes a full-wave rectifier circuit 20, capacitors 21, 24, 34A, 34B, a transformer 22, a diode 23, a power factor improvement IC 25, an NMOS transistor 26, and resistors 30 to 33.

[0032] The full-wave rectifier circuit 20 applies the rectified voltage Vrec obtained by full-wave rectifying the applied specified AC voltage Vac to the capacitor 21 and the primary coil L1 of the transformer 22. Here, the AC voltage Vac is, for example, a voltage of 100 to 240V and a frequency of 50 to 60Hz.

[0033] The capacitor 21 is an element for filtering the rectified voltage Vrec, and the transformer 22 has a primary coil L1 and an auxiliary coil L2 magnetically coupled to the primary coil L1. Here, in the present embodiment, the auxiliary coil L2 is wound such that the polarity of the voltage generated in the auxiliary coil L2 is opposite to the polarity of the voltage generated in the primary coil L1. Moreover, the voltage Vzcd generated in the auxiliary coil L2 is applied to the terminal ZCD.

[0034] The primary coil L1 corresponds to an "inductor", and the current flowing through the primary coil L1 is the "inductor current IL". The rectified voltage Vrec is directly applied to the primary coil L1, but it can be applied to the primary coil L1 through an element such as a resistor (not shown), for example.

[0035] In addition, the main coil L1, together with the diode 23, the capacitor 24, and the NMOS transistor 26, constitutes a boost chopper circuit. Therefore, the charging voltage of the capacitor 24 becomes the DC output voltage Vout. The output voltage Vout is, for example, 400V.

[0036] The power factor improvement IC 25 is an integrated circuit that improves the power factor of the AC-DC converter 10 and controls the switching of the NMOS transistor 26 so that the level of the output voltage Vout becomes a target level (e.g., 400V). Specifically, the power factor improvement IC 25 drives the NMOS transistor 26 based on the inductor current IL flowing through the main coil L1 and the output voltage Vout.

[0037] Details of the power factor improvement IC 25 will be described later. Terminals CS, FB, ZCD, COMP, and OUT are provided on the power factor improvement IC 25. In addition to the above five terminals CS, FB, ZCD, COMP, and OUT, terminals are also provided on the power factor improvement IC 25, but for convenience, they are omitted here.

[0038] The NMOS transistor 26 is a transistor for controlling the power supplied by the AC-DC converter 10 to the load 11. In addition, in the present embodiment, the NMOS transistor 26 is a MOS (Metal Oxide Semiconductor) transistor, but it is not limited thereto. The NMOS transistor 26 may be any transistor that can control power, such as a bipolar transistor. In addition, the gate electrode of the NMOS transistor 26 is connected to be driven by a signal from the terminal OUT.

[0039] The resistors 30 and 31 constitute a voltage dividing circuit for dividing the output voltage Vout and generate a feedback voltage Vfb used when the NMOS transistor 26 switches. The feedback voltage Vfb generated at the node connecting the resistors 30 and 31 is applied to the terminal FB.

[0040] The resistor 32 is a resistor for detecting the inductor current IL. One end of it is connected to the source electrode of the NMOS transistor 26, and the other end is connected to the terminal CS. In the present embodiment, the voltage corresponding to the inductor current IL input to the terminal CS is set as the voltage Vcs.

[0041] The voltage Vcs is the voltage applied to the terminal CS from an inverting amplifier circuit (not shown), which inverts and amplifies, for example, the voltage generated in the resistor 32 with respect to the source electrode of the grounded NMOS transistor 26 (0V) as a reference. In this case, the voltage Vcs applied to the terminal CS increases as the inductor current IL increases. Further, such positive and negative inversion can be implemented inside the power factor improvement IC25. For example, by inserting a voltage dividing resistor (not shown) between the power supply inside the power factor improvement IC25 and the terminal CS, the voltage Vcs of the terminal CS can be level-shifted to a positive voltage and then used.

[0042] Moreover, the voltage Vcs of the present embodiment is represented by, for example, Equation (1).

[0043] Vcs = A × IL…(1)

[0044] "A" in Equation (1) is a prescribed coefficient and is a prescribed value determined based on the resistance value of the resistor 32 and the magnification factor.

[0045] Details will be described later. The resistor 33 and the capacitors 34A and 34B are elements for phase compensation of the power factor improvement IC25 that performs feedback control. The resistor 33 and the capacitor 34A are connected in series between the terminal COMP and the ground, and the capacitor 34B is connected in parallel with the resistor 33 and the capacitor 34A.

[0046] <<<Structure of the power factor improvement IC25>>>

[0047] Figure 2 is a diagram showing an example of the structure of the power factor improvement IC25. The power factor improvement IC25 includes a drive signal generation circuit 50, a drive circuit 51, and a comparator 52. In Figure 2 for convenience, the terminals are depicted at positions different from Figure 1 however, the wirings, components, etc. connected to each terminal are the same in Figure 1 and Figure 2 are the same.

[0048] <<Drive signal generation circuit 50>>

[0049] The drive signal generation circuit 50 is a circuit that generates a drive signal Vq1 for turning on and off the NMOS transistor 26 based on the voltage Vcs corresponding to the inductor current IL and the feedback voltage Vfb. The drive signal generation circuit 50 includes a zero current detection circuit 70, a delay circuit 71, a pulse circuit 72, a conduction timer circuit 73, OR gate circuits 74, 78, 80, an error amplifier circuit 75, an oscillation circuit 76, a comparator 77, a surge prevention circuit 79, and an SR flip-flop 81.

[0050] The zero-current detection circuit 70 is a circuit that detects whether the current value of the inductor current IL is the "current value Ia" indicating approximately zero (hereinafter, for convenience, "approximately zero" is simply referred to as zero) based on the voltage Vzcd of the terminal ZCD. When the zero-current detection circuit 70 of the present embodiment detects that the current value of the inductor current IL is the "current value Ia" of "zero", it outputs a signal Vz of a high level (hereinafter referred to as "H" level). In addition, the zero-current detection circuit 70 includes a comparator (not shown), which compares a specified voltage of the auxiliary coil L2 when the inductor current IL becomes the "current value Ia" with the voltage Vzcd.

[0051] When the signal Vz of "H" level is output from the zero-current detection circuit 70, the delay circuit 71 delays it for a specified time and then outputs it.

[0052] When the signal Vz of "H" level is output from the delay circuit 71, the pulse circuit 72 outputs a pulse signal Vp1 of H level.

[0053] When the power factor improvement IC 25 starts, or when the AC voltage Vac is cut off and no pulse signal Vp1 is output, the conduction timer circuit 73 outputs a pulse signal Vp2 for turning on the NMOS transistor 26. Specifically, when no pulse signal Vp1 is output within a specified period, a pulse signal Vp2 of "H" level is output at every specified cycle.

[0054] The OR gate circuit 74 calculates and outputs the logical sum of the pulse signals Vp1 and Vp2. Therefore, in the present embodiment, the pulse signal Vp1 or the pulse signal Vp2 is output as the signal Vp3 from the OR gate circuit 74.

[0055] The error amplifier circuit 75 is a circuit that amplifies the error between the feedback voltage Vfb applied to the terminal FB and the specified reference voltage Vref0. The reference voltage Vref0 is a voltage determined according to the target level of the output voltage Vout. In addition, the resistor 33 for phase compensation and the capacitors 34A and 34B are connected between the output of the error amplifier circuit 75 and the ground via the terminal COMP. Here, the voltage of the node connecting the output of the error amplifier circuit 75 and the terminal COMP is set as the voltage Ve.

[0056] Whenever the "H" level signal Vp3 from the OR gate circuit 74 is input, the oscillation circuit 76 outputs a ramp wave Vr with an increasingly larger amplitude.

[0057] Comparator 77 compares the magnitudes of voltage Ve and ramp wave Vr, and outputs signal Vc1 as the comparison result. Here, voltage Ve is applied to the inverting input terminal of comparator 77, and ramp wave Vr is applied to the non-inverting input terminal of comparator 77. Therefore, when the level of ramp wave Vr is lower than the level of voltage Ve, signal Vc1 becomes low level (hereinafter denoted as "L" level), and when the level of ramp wave Vr is higher than the level of voltage Ve, signal Vc1 becomes "H" level.

[0058] OR gate circuit 78 operates and outputs the logical sum of signal Vc1 and signal Voc (described later) which represents the "H" level indicating overcurrent generation. Therefore, when signal Vc1 or signal Voc becomes "H" level, signal Vp4 of "H" level is output from OR gate circuit 78.

[0059] Surge prevention circuit 79 is a circuit for suppressing the surge voltage generated along with the increase of inductor current IL in NMOS transistor 26 when the AC voltage Vac rises sharply, for example. When the voltage Vcs corresponding to inductor current IL is greater than the limit voltage Vlimt determined based on the past inductor current IL, in order to turn off NMOS transistor 26, surge prevention circuit 79 outputs signal Vp5 of "H" level. In addition, the detailed situation of surge prevention circuit 79 will be described later.

[0060] OR gate circuit 80 operates and outputs the logical sum of signal Vp4 from OR gate circuit 78 and signal Vp5 from surge prevention circuit 79. Therefore, when signal Vp4 or signal Vp5 becomes "H" level, signal Vp6 also becomes "H" level.

[0061] Signal Vp3 is input to the S input terminal of SR flip-flop 81, and signal Vp6 is input to the R input terminal. Therefore, when signal Vp3 becomes "H" level, the Q output of SR flip-flop 81, that is, drive signal Vq1, becomes "H" level. On the other hand, when signal Vp6 becomes "H" level, drive signal Vq1 becomes "L" level.

[0062] <<Driver circuit 51>>

[0063] Driver circuit 51 is a buffer circuit that drives NMOS transistor 26 based on drive signal Vq1. Specifically, driver circuit 51 drives NMOS transistor 26 with a large gate capacitance, etc. using signal Vdr having the same logic level as the input signal. In addition, driver circuit 51 turns on NMOS transistor 26 based on the "H" level drive signal Vq1, and turns off NMOS transistor 26 based on the "L" level drive signal Vq1.

[0064] <<Comparator 52>>

[0065] Comparator 52 is an overcurrent protection circuit that prevents the inductor current IL from being in an overcurrent state by comparing the voltage Vcs with the reference voltage Vref1. "Overcurrent" refers to a state where the inductor current IL becomes the "current value Ib" (for example, a current value that is 90% of the current value allowed by the main coil L1 and the NMOS transistor 26).

[0066] Therefore, in the present embodiment, the level of the voltage Vref1 is determined such that when the inductor current IL exceeds the "current value Ib", the voltage Vcs is greater than the reference voltage Vref1. When the inductor current IL is in an overcurrent state and the voltage Vcs is greater than the reference voltage Vref1, the comparator 52 changes the voltage Voc to the "H" level. As a result, since the drive signal Vq1 becomes the "L" level, the NMOS transistor 26 is turned off. The comparator 52 corresponds to the "second signal output circuit", and the voltage Voc at the "H" level corresponds to the "second signal".

[0067] <<<Surge prevention circuit 79>>>

[0068] Figure 3 FIG. is a diagram showing an example of the surge prevention circuit 79. The surge prevention circuit 79 samples the voltage Vcs corresponding to the inductor current IL each time the NMOS transistor 26 is turned off, and sets the "limit value Lim" for limiting the inductor current IL in the next sampling period based on the sampling result. When the inductor current IL is greater than the limit value Lim, the surge prevention circuit 79 outputs a signal Vp5 at the "H" level to turn off the NMOS transistor 26.

[0069] In the present embodiment, as described above, there is a relationship of Equation (1) between the inductor current IL and the voltage Vcs.

[0070] Vcs = A × IL...(1)

[0071] Therefore, details will be described below. The surge prevention circuit 79 detects whether the inductor current IL exceeds the limit value Lim based on the comparison result between the voltage Vcs corresponding to the inductor current IL and the "limit voltage Vlimit" representing the "limit value Lim".

[0072] The surge prevention circuit 79 includes an edge detection circuit 100, a sampling prevention circuit 101, a sample and hold circuit 102, an amplifier circuit 103, a selection circuit 104, and a comparator 105.

[0073] <<Edge detection circuit 100>>>

[0074] The edge detection circuit 100 outputs a pulse signal Vs1 for sampling the voltage Vcs corresponding to the inductor current IL at the timing when the NMOS transistor 26 is turned off. Specifically, the edge detection circuit 100 detects the falling edge of the drive signal Vq1 and outputs a pulse signal Vs1 at the "H" level.

[0075] <<Sampling prevention circuit 101>>

[0076] The sampling prevention circuit 101 is a circuit that prevents the sample and hold circuit 102 (described later) from sampling the voltage Vcs when the inductor current IL is greater than the limit value Lim, that is, when the voltage Vcs is greater than the limit voltage Vlimit.

[0077] As will be described in detail later, in this embodiment, the set limit value Lim is, for example, 1.1 times the inductor current IL obtained by sampling each time the NMOS transistor 26 is turned off. Therefore, when the inductor current IL exceeds the limit value Lim, it is possible to prevent the limit value Lim from becoming larger.

[0078] The sampling prevention circuit 101 includes a D flip-flop 120, an inverter 121, and an AND gate circuit 122.

[0079] The comparison result, that is, the signal Vp5, of the comparator 105 (described later) for determining whether the inductor current IL is greater than the limit value Lim is input to the D input terminal of the D flip-flop 120. When the inductor current IL is greater than the limit value Lim, the comparator 105 outputs a signal Vp5 at the "H" level, and when the inductor current IL is less than the limit value Lim, the comparator 105 outputs a signal Vp5 at the "L" level.

[0080] Therefore, when the inductor current IL is less than the limit value Lim at the timing of inputting the pulse signal Vs1 to the CK input terminal of the D flip-flop, the Q output of the D flip-flop 120 becomes the "L" level.

[0081] As a result, the output of the inverter 121 becomes the "H" level, so the AND gate circuit 122 allows the pulse signal Vs1 at the "H" level to pass through. Therefore, when the inductor current IL is less than the limit value Lim, a pulse signal Vs2 for sampling the voltage Vcs is output to the sample and hold circuit 102.

[0082] On the other hand, when the inductor current IL is greater than the limit value Lim at the timing of inputting the pulse signal Vs1 to the CK input terminal of the D flip-flop, the Q output of the D flip-flop 120 becomes the "H" level.

[0083] As a result, since the output of the inverter 121 changes to the "L" level, a signal Vs2 of the "L" level is always output from the AND gate circuit 122. Therefore, when the inductor current IL is greater than the limit value Lim, the pulse signal Vs2 for sampling the voltage Vcs is not output to the sample-and-hold circuit 102.

[0084] <<Sample-and-hold circuit 102>>

[0085] The sample-and-hold circuit 102 samples and holds the inductor current IL when the NMOS transistor 26 is turned off. Specifically, when a pulse signal Vs2 of the "H" level for performing sampling is input, the sample-and-hold circuit 102 samples and holds the voltage Vcs.

[0086] The sample-and-hold circuit 102 includes an NMOS transistor 130 and a capacitor 131. Since the NMOS transistor 130 is turned on only during the period when the pulse signal Vs2 of the "H" level is input, the voltage Vcs during this period is held as the voltage Vs3 of the capacitor 131.

[0087] <<Amplification circuit 103>>

[0088] The amplification circuit 103 is a circuit that generates a voltage Vd1 for setting the limit voltage Vlimit based on the sampled voltage Vcs. Specifically, in the amplification circuit 103, the operational amplifier 140 amplifies the voltage Vs3 of the capacitor 131 at a magnification corresponding to the resistance ratio of the resistors 141 and 142 and outputs it. The voltage Vd1 output from the amplification circuit 103 is represented by Equation (2).

[0089] Vd1 = (1 + (R2 / R1)) × Vs3…(2)

[0090] Here, the resistance value of the resistor 141 is set to "R2", and the resistance value of the resistor 142 is set to "R1". In addition, as will be described in detail later, when the voltage Vd1 is greater than the voltage Vmin described later, the voltage Vd1 becomes the limit voltage Vlimit. The voltage Vs3 is the voltage Vcs corresponding to the inductor current IL.

[0091] Therefore, by selecting the value of "R2 / R1" and adjusting the limit voltage Vlimit, the limit value Lim can be set to a specified multiple X (e.g., 1.1 times) of the sampled inductor current IL. In addition, the amplification circuit 103 corresponds to a "voltage generation circuit", and the voltage Vd1 corresponds to a "first voltage".

[0092] <<Selection circuit 104>>

[0093] The selection circuit 104 is a circuit that compares the voltage Vd1 generated by the amplifier circuit 103 with the voltage Vref2 representing the level of the voltage Vcs when the inductor current IL becomes a specified "current value Ic", and outputs a voltage with an increased limit value Lim as the limit voltage Vlimit.

[0094] For example, when the phase angle of the AC voltage Vac is within the range of 0° ± 30° and the amplitude of the AC voltage Vac is small, the level of the rectified voltage Vrec is also low. As a result, when setting the limit value Lim based on the inductor current IL sampled within such a range, although the possibility of generating a surge voltage is low, the inductor current IL may still be restricted.

[0095] Therefore, when the inductor current IL for the voltage Vd1 is less than the specified value Ic, the selection circuit 104 sets the specified value Ic as the limit value Lim, and when the inductor current IL for the voltage Vd1 is greater than the specified value Ic, the selection circuit 104 sets the value based on the voltage Vd1 as the limit value Lim. In addition, the "current value Ic" is, for example, 30% of the inductor current IL when the phase angle is 90°.

[0096] The selection circuit 104 includes a comparator 150, NMOS transistors 151, 153, and an inverter 152.

[0097] The comparator 150 compares the voltage Vd1 representing a specified multiple X (e.g., 1.1 times) of the sampled inductor current IL with the voltage Vref2 representing the "current value Ic".

[0098] When the voltage Vd1 is less than the voltage Vref2, the comparator 150 outputs a signal with an "H" level. As a result, since the NMOS 151 is turned on and the NMOS 153 is turned off, the voltage Vref2 is output as the limit voltage Vlimit to the comparator 105.

[0099] On the other hand, when the voltage Vd1 is greater than the voltage Vref2, the comparator 150 outputs a signal with an "L" level. As a result, since the NMOS 151 is turned off and the NMOS 153 is turned on, the voltage Vd1 is output as the limit voltage Vlimit to the comparator 105. In addition, the voltage Vref2 corresponds to the "second voltage".

[0100] <<Comparator 105>>

[0101] When the voltage Vcs corresponding to the inductor current IL is greater than the limit voltage Vlimit representing the limit value Lim, the comparator 105 outputs a signal Vp5 with an "H" level, and when the voltage Vcs is less than the limit voltage Vlimit, the comparator 105 outputs a signal Vp5 with an "L" level.

[0102] When the signal Vp5 of "H" level is output, Figure 2 the output of the OR gate circuit 80 in Figure 2 also becomes "H" level. As a result, the Q output of the SR flip-flop 81, i.e., the drive signal Vq1, becomes "L" level, and thus the NMOS transistor 26 is turned off. Therefore, in this embodiment, the inductor current IL flows without exceeding the limit value Lim.

[0103] In addition, the amplifier circuit 103 and the selection circuit 104 correspond to an "output circuit", the comparator 105 corresponds to a "first signal output circuit", and the signal Vp5 of "H" level corresponds to a "first signal".

[0104] ====Operation of the power factor improvement IC 25====

[0105] <<<When a specified AC voltage Vac is input>>>

[0106] Refer to Figure 4 , and the operation of the power factor improvement IC 25 when the AC-DC converter 10 generates an output voltage Vout of a target level from the specified AC voltage Vac and supplies power to a certain load will be described. Here, it is assumed that the AC voltage Vac does not rise sharply or an overcurrent occurs. Therefore, Figure 2 both the surge protection circuit 79 and the comparator 52 in Figure 2 output signals of "L" level.

[0107] First, when the inductor current IL decreases to approximately zero "current value Ia" at time t0, the zero current detection circuit 70 detects that the current value of the inductor current IL is "zero" and outputs a signal Vz of "H" level.

[0108] In addition, the pulse circuit 72 outputs a pulse signal Vp1 at time t1 after the delay time of the delay circuit 71 from time t0. As a result, a pulse signal Vp3 of "H" level is output from the OR gate circuit 74.

[0109] Moreover, when the pulse signal Vp3 is output, since the SR flip-flop 81 outputs a drive signal Vq1 of "H" level, the signal Vdr also becomes "H" level. As a result, the NMOS transistor 26 is turned on, and the inductor current IL increases.

[0110] In addition, when the pulse signal Vp3 of "H" level is output, the amplitude of the ramp wave Vr from the oscillation circuit 76 increases. Moreover, when the amplitude level of the ramp wave Vr is higher than the level of the voltage Ve at time t2, the comparator 77 changes the signal Vc1 to "H" level. As a result, the SR flip-flop 81 is reset, and the signal Vdr becomes "L" level.

[0111] When the signal Vdr becomes an L level, the NMOS transistor 26 is turned off, and thus the inductor current IL gradually decreases. In addition, when the inductor current IL decreases at time t3 and becomes a "current value Ia" that is approximately zero, the operation at time t0 is repeated.

[0112] Here, when the AC-DC converter 10 generates an output voltage Vout of a target level from a prescribed AC voltage Vac and supplies power to a certain load, the feedback voltage Vfb becomes constant. As a result, since the voltage Ve output from the error amplifier circuit 75 also becomes constant, the period during which the NMOS transistor 26 is turned on (for example, the period from time t1 to t2) also becomes constant.

[0113] In addition, when the NMOS transistor 26 is turned on, if the level of the rectified voltage Vrec obtained by rectifying the AC voltage Vac becomes high, the current value of the inductor current IL also becomes large. As a result, as Figure 5 shown, the spectral peak waveform of the inductor current IL is a waveform similar to the waveform of the voltage Vrec, and the power factor is improved.

[0114] <<<When the AC voltage Vac changes rapidly>>>

[0115] When the AC voltage Vac changes rapidly and rises, the rectified voltage Vrec also increases rapidly accordingly. As a result, the inductor current IL increases, and thus when the NMOS transistor 26 is turned off, a surge voltage may sometimes be generated in the NMOS transistor 26.

[0116] Here, referring to Figure 6 and Figure 7 , with Figure 3 's surge prevention circuit 79 as the center, the operation when the power factor improvement IC 25 suppresses the surge voltage when this phenomenon occurs will be described. Here, it is assumed that the AC voltage Vac changes rapidly at time t13 of Figure 6 , and the rapid change of the AC voltage Vac stops at time t16 of Figure 7 .

[0117] First, at time t10, in order to turn off the NMOS transistor 26, when the drive signal Vq1 becomes an "L" level, the edge detection circuit 100 of the surge prevention circuit 79 outputs a pulse signal Vs1 of an "H" level for sampling the voltage Vcs.

[0118] At this timing, the inductor current IL is less than the limit value Lim, so the signal Vp5 of the comparator 105 is at an "L" level. Therefore, the sampling prevention circuit 101 outputs the pulse signal Vs1 as a pulse signal Vs2 to the sample and hold circuit 102 without preventing the sampling of the inductor current IL.

[0119] The sample-and-hold circuit 102 holds the voltage Vcs representing the inductor current IL at time t10 at the voltage Vs3. However, since the voltage Vd1 which is "a specified multiple X" of the voltage Vs3 at this time t10 is lower than the voltage Vref2, "the voltage Vref2" is output as the limit voltage Vlimit.

[0120] Moreover, after the NMOS transistor 26 is turned off, when the inductor current IL becomes the "current value Ia" which is approximately zero at time t11 (for example, as described in Figure 4 ), the drive signal Vq1 becomes the "H" level and the NMOS transistor 26 is turned on. As a result, the inductor current IL increases. In Figure 6 and Figure 7 , for the sake of convenience, the "current value Ia" at which the inductor current IL is approximately zero is omitted.

[0121] Then, similar to the time t2 in Figure 4 , at time t12, when the ramp wave Vr is greater than the voltage Ve, the drive signal Vq1 becomes the "L" level and the NMOS transistor 26 is turned off again. As a result, the sample-and-hold circuit 102 holds the voltage Vcs representing the inductor current IL at time t12 as the voltage Vs3.

[0122] Here, since the voltage Vd1 which is "a specified multiple X" of the voltage Vs3 at time t12 is higher than the voltage Vref2, "the voltage Vd1" is output as the limit voltage Vlimit. Thereafter, in order to turn off the NMOS transistor 26, whenever the drive signal Vq1 becomes the "L" level, the operation at time t12 is repeated. Therefore, the limit value Lim of the inductor current IL increases stepwise as the inductor current IL increases.

[0123] When the AC voltage Vac changes sharply and rises at time t13, the level of the rectified voltage Vrec also becomes higher. Moreover, when the inductor current IL increases and is greater than the limit value Lim, the comparator 105 outputs a signal Vp5 of the "H" level. As a result, Figure 2 the SR flip-flop 81 in

[0124] changes the drive signal Vq1 output at Q to the "L" level at time t14, and thus the NMOS transistor 26 is turned off.

[0125] Moreover, after time t15, the operation of turning on the NMOS transistor 26 when the inductor current IL becomes zero and turning off the NMOS transistor 26 when the inductor current IL becomes the limit value Lim at time t14 is repeated.

[0126] At Figure 7 time t16, the rapid change of the AC voltage Vac stops and becomes a waveform of a prescribed AC voltage Vac. As a result, the inductor current IL becomes smaller than the limit value Lim, and each circuit of the power factor improvement IC25 performs a normal operation as described, for example, in Figure 4 .

[0127] Then, at time t17, the ramp wave Vr becomes higher than the voltage Ve, the drive signal Vq1 becomes the "L" level, and the NMOS transistor 26 is turned off.

[0128] In addition, at time t17, since the voltage Vcs is lower than the limit voltage Vlimit, the signal Vp5 of the comparator 105 is output at the "L" level. Therefore, the Q output of the D flip-flop 120 becomes the "L" level.

[0129] After time t18, every time the NMOS transistor 26 is turned off, the sample hold circuit 102 samples the voltage Vcs and updates the limit voltage Vlimit. At time t19, the voltage Vd1 is continuously output as the limit voltage Vlimit until the voltage Vd1 becomes lower than the voltage Vref2.

[0130] When the voltage Vd1 becomes lower than the voltage Vref2 at time t19, the output voltage Vref2 is used as the limit voltage Vlimit. Therefore, even in a region where the phase angle is close to 0° and the inductor current IL becomes small, the limit value Lim does not become too low. As a result, the surge prevention circuit 79 can operate stably even in a region where the inductor current IL is small.

[0131] ===Other Embodiments===

[0132] Figure 8 FIG. is a diagram showing an example of the AC-DC converter 15. The AC-DC converter 15 includes a full-wave rectifier circuit 20, capacitors 21, 24, 34A, 34B, a transformer 22, a diode 23, a power factor improvement IC310, an NMOS transistor 26, and resistors 30 to 33, 300, 301.

[0133] Next, in the AC-DC converter 15 and Figure 1 the AC-DC converter 10, modules with the same reference numerals are the same. Therefore, the resistors 300, 301 and the power factor improvement IC310 are described here.

[0134] Resistors 300 and 301 are a voltage dividing circuit that divides the rectified voltage Vrec to generate a voltage with a shape similar to that of the rectified voltage Vrec. The voltage obtained by dividing the rectified voltage Vrec by resistors 300 and 301 is designated as voltage Vin.

[0135] The power factor improvement IC 310 is an integrated circuit that switches the NMOS transistor 26 in the same manner as the power factor improvement IC 25, and in addition to the five terminals of the power factor improvement IC 25, it also has a terminal IN to which the voltage Vin is applied.

[0136] <<Power factor improvement IC 310>>

[0137] Figure 9 is a diagram showing an example of the power factor improvement IC 310. The power factor improvement IC 310 uses the drive signal generation circuit 53 in place of Figure 2 the drive signal generation circuit 50 of the power factor improvement IC 25. In the drive signal generation circuit 53, the surge prevention circuit 400 is used in place of the surge prevention circuit 79. Therefore, the surge prevention circuit 400 will be described here.

[0138] <<Surge prevention circuit 400>>

[0139] In the surge prevention circuit 400, the sample and hold circuit 500 is used in place of the sample and hold circuit 102 of the surge prevention circuit 79, and the amplifier circuit 510 is used in place of the amplifier circuit 103.

[0140] The sample and hold circuit 500 is a circuit that samples the voltage Vin based on the signal Vs2, and includes an NMOS transistor 501 and a capacitor 502.

[0141] The amplifier circuit 510 is a circuit that generates a voltage Vd1 representing the limit value Lim based on the voltage Vin held by the sample and hold circuit 500, and includes an operational amplifier 520 and resistors 521 and 522.

[0142] Here, since the inductor current IL is IL = (Ton × Vrec) / L, the inductor current IL and the voltage Vin corresponding to the rectified voltage Vrec have a similar shape. "Ton" is the on-time of the NMOS transistor 26, and "L" is the inductance value of the main coil L1.

[0143] Therefore, similar to the above-described amplifier circuit 103, the amplifier circuit 510 can generate a voltage Vd1 representing the limit value Lim based on the voltage Vin. As a result, even when using the surge prevention circuit 400, the surge voltage generated in the NMOS transistor 26 can be prevented.

[0144] ===Summary===

[0145] The AC-DC converters 10 and 15 of the present embodiment have been described above. For example, the power factor improvement IC 25 generates the limit value Lim for restricting the inductor current IL based on the voltage Vcs sampled in the past. Therefore, the limit value Lim can be changed according to the inductor current IL, and a surge voltage can be prevented from being generated in the NMOS transistor 26. As a result, the NMOS transistor 26 can be appropriately protected.

[0146] In addition, as Figure 8 shown, even when using the power factor improvement IC 310 that samples the voltage Vin obtained by dividing the rectified voltage Vrec, a surge voltage can be prevented. However, in Figure 1 the power factor improvement IC 25, it is not necessary to divide the rectified voltage Vrec with the resistors 300 and 301. Therefore, the power factor improvement IC 25 can further reduce the power consumption.

[0147] In addition, the sample-and-hold circuit 102 samples the voltage Vcs corresponding to the inductor current IL, for example, at the timing when the NMOS transistor 26 is turned off. That is, the sample-and-hold circuit 102 acquires the voltage Vcs representing the peak value (i.e., the maximum value) of the inductor current IL. In the present embodiment, since the limit value Lim is generated based on the peak value of the inductor current IL, a surge voltage can be appropriately prevented.

[0148] In addition, when the inductor current IL reaches the limit value Lim, the sampling prevention circuit 101 prevents the sample-and-hold circuit 102 from sampling the voltage Vcs. As a result, the limit value Lim remains unchanged, and a large inductor current IL exceeding the limit value Lim does not flow. As a result, the NMOS transistor 26 can be appropriately protected.

[0149] In addition, since the inductor current IL usually becomes very small near the phase angle of 0°, when the limit value Lim is generated based on the voltage Vcs corresponding to such an inductor current IL, the inductor current IL is sometimes restricted even in a state where no surge voltage is generated. However, in the present embodiment, the limit value Lim is not less than a prescribed "current value Ic". Therefore, for example, the surge prevention circuit 79 can appropriately suppress the generation of a surge voltage regardless of the range of the phase angle of the AC voltage Vac.

[0150] In addition, since the limit value Lim is generated based on the sampled voltage Vcs, when the sampled voltage Vcs becomes large, the limit value Lim also becomes large.

[0151] In addition, the limit value Lim can be adjusted based on the resistance ratio of the resistors 141 and 142. Therefore, an appropriate limit value Lim can be set according to the inductance value of the main coil L1, the period of the drive signal Vq1, the conduction time of the NMOS transistor 26, and the like.

[0152] In addition, the power factor improvement IC 25 includes a comparator 52 that turns off the NMOS transistor 26 when the inductor current IL becomes an overcurrent. Therefore, the NMOS transistor 26 can be prevented from being damaged by the overcurrent.

[0153] The above-described embodiments are for easily understanding the present invention and are not intended to limit and interpret the present invention. In addition, without departing from the spirit of the present invention, the present invention can be changed and improved, and equivalent inventions of the present invention are of course included in the present invention.

[0154] Reference Numeral Explanation

[0155] 10, 15 AC-DC converter

[0156] 20 Full-wave rectifier circuit

[0157] 21, 24, 34A, 34B, 131,502 Capacitor

[0158] 22 Transformer

[0159] 23 Diode

[0160] 25, 310 Power factor improvement IC

[0161] 26, 130, 151, 153, 501 NMOS transistor

[0162] 30~33, 141, 142, 300, 301, 521, 522 Resistor

[0163] 50, 53 Drive signal generation circuit

[0164] 51 Drive circuit

[0165] 52, 77, 105, 150 Comparator

[0166] 70 Zero-current detection circuit

[0167] 71 Delay circuit

[0168] 72 Pulse circuit

[0169] 73 Turn-on timer circuit

[0170] 74, 78, 80 OR gate circuit

[0171] 75 Error amplification circuit

[0172] 76 Oscillation circuit

[0173] 79, 400 Surge prevention circuit

[0174] 81 SR flip-flop

[0175] 100 Edge detection circuit

[0176] 101 Sampling prevention circuit

[0177] 102, 500 Sample and hold circuit

[0178] 103, 510 Amplification circuit

[0179] 104 Selection circuit

[0180] 120 D flip-flop

[0181] 121, 152 Inverter

[0182] 122 AND gate circuit

[0183] 140, 520 Operational amplifier

Claims

1. An integrated circuit switches a transistor that controls the inductor current based on the inductor current flowing through an inductor and an output voltage generated from an alternating voltage, and the inductor is applied with a rectified voltage from a rectifier circuit that rectifies the alternating voltage. The integrated circuit is characterized by including: A sample-and-hold circuit that samples and holds a voltage corresponding to the rectified voltage at a timing when the transistor is turned off; An output circuit that outputs a limit voltage representing a limit value for limiting the inductor current based on the voltage held by the sample-and-hold circuit; And A first signal output circuit that outputs a first signal for turning off the transistor when the current value of the inductor current is greater than the limit value based on a voltage corresponding to the inductor current and the limit voltage; The output circuit has: A voltage generation circuit that generates a first voltage for limiting the inductor current based on the voltage held by the sample-and-hold circuit; And A selection circuit that selects, as the limit voltage, a voltage with a larger limit value from a second voltage that limits the inductor current with a specified current value and the first voltage.

2. The integrated circuit according to claim 1, wherein The sample-and-hold circuit samples and holds a voltage corresponding to the inductor current as a voltage corresponding to the rectified voltage.

3. The integrated circuit according to claim 1 or 2, wherein It further includes a sampling prevention circuit that prevents the sample-and-hold circuit from sampling a voltage corresponding to the rectified voltage when the first signal is output.

4. The integrated circuit according to claim 1, wherein The voltage generation circuit generates the first voltage based on the voltage held by the sample-and-hold circuit, and the first voltage represents a current value that is a specified multiple of the inductor current when the sample-and-hold circuit samples.

5. The integrated circuit according to claim 4, wherein The voltage generation circuit is an amplifier circuit that amplifies the voltage held by the sample-and-hold circuit based on a specified resistance ratio and outputs the voltage as the first voltage.

6. The integrated circuit according to claim 1 or 2, wherein It further includes a second signal output circuit that outputs a second signal for turning off the transistor when the current flowing through the transistor becomes an overcurrent.

7. A power supply circuit that generates an output voltage based on a specified AC voltage, characterized in that, Including: A rectifier circuit that rectifies the specified alternating voltage; An inductor to which the rectified voltage from the rectifier circuit is applied; And An integrated circuit that drives a transistor for controlling the inductor current based on the inductor current flowing through the inductor and the output voltage, The integrated circuit includes: A sample-and-hold circuit that samples and holds a voltage corresponding to the rectified voltage at a timing when the transistor is turned off; An output circuit that outputs a limit voltage representing a limit value for limiting the inductor current based on the voltage held by the sample-and-hold circuit; and A first signal output circuit that outputs a first signal for turning off the transistor when the current value of the inductor current is greater than the limit value based on the voltage corresponding to the inductor current and the limit voltage The output circuit includes: A voltage generation circuit that generates a first voltage for limiting the inductor current based on the voltage held by the sample-and-hold circuit; and A selection circuit that selects, as the limit voltage, a voltage with an increasing limit value from a second voltage that limits the inductor current with a specified current value and the first voltage.

8. The power supply circuit according to claim 7, wherein It further includes a sampling prevention circuit that prevents the sample-and-hold circuit from sampling the voltage corresponding to the rectified voltage when the first signal is output.

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