Package structure

Abstract

The present disclosure provides a packaging structure, which includes: a wiring substrate; an interposer, which is arranged on the wiring substrate and electrically connected to the wiring substrate; a semiconductor die, which is arranged on the interposer and electrically connected to the interposer; a first insulating encapsulation, which is arranged on the interposer; a second insulating encapsulation, which is arranged on the wiring substrate; and a cover. The semiconductor die is encapsulated by the first insulating encapsulation in the lateral direction. The semiconductor die and the first insulating encapsulation are encapsulated by the second insulating encapsulation in the lateral direction. The top surface of the first insulating encapsulation is substantially flush with the top surface of the second insulating encapsulation and the surface of the semiconductor die. The cover is arranged on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

Description

Technical Field

[0001] The present disclosure relates to a packaging structure Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In large part, this increase in integration density is derived from the repeated reduction in minimum feature size, which enables more components to be integrated into a given area. With the recent increase in demand for miniaturization, higher speed and greater bandwidth, and lower power consumption and latency, the need for smaller semiconductor dies and thermally enhanced packaging techniques for semiconductor dies has also increased. Summary of the invention

[0003] An embodiment of the present disclosure proposes a packaging structure, which includes: a wiring substrate; an interposer, which is arranged on the wiring substrate and electrically connected to the wiring substrate; a semiconductor die, which is arranged on the interposer and electrically connected to the interposer; a first insulating package, which is arranged on the interposer, wherein the semiconductor die is laterally encapsulated by the first insulating package; a second insulating package, which is arranged on the wiring substrate, wherein the semiconductor die and the first insulating package are laterally encapsulated by the second insulating package; and a cover, which is arranged on the semiconductor die, the first insulating package and the second insulating package, wherein the top surface of the first insulating package is substantially flush with the top surface of the second insulating package and the surface of the semiconductor die.

[0004] The present disclosure provides a packaging structure, which includes: a wiring substrate; an interposer, which is arranged on the wiring substrate, wherein the interposer is electrically connected to the wiring substrate via a first conductive bump; a semiconductor die, which is arranged on the interposer, wherein the semiconductor die is electrically connected to the interposer via a second conductive bump; a first insulating package, which is arranged on the interposer, wherein the first insulating package laterally encapsulates the semiconductor die and the second conductive bump; a bottom filling glue, which is filled between the wiring substrate and the interposer, wherein the bottom filling glue laterally encapsulates the first conductive bump; a second insulating package, which is arranged on the wiring substrate, wherein the second insulating package laterally encapsulates the first insulating package and the bottom filling glue; and a heat sink, which is bonded to the semiconductor die, the first insulating package and the second insulating package via a thermal interface material.

[0005] The present disclosure provides a packaging structure, which includes: a wiring substrate; an interposer disposed on the wiring substrate and electrically connected to the wiring substrate; a semiconductor die disposed on the interposer and electrically connected to the interposer; a first insulating package disposed on the interposer, wherein the semiconductor die is laterally encapsulated by the first insulating package; a second insulating package disposed on the wiring substrate, wherein the semiconductor die and the first insulating package are laterally encapsulated by the second insulating package; and a cover disposed on the semiconductor die, the first insulating package and the second insulating package, wherein the minimum distance between the cover and the wiring substrate is greater than the maximum thickness of the second insulating package. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 7 is a cross-sectional view schematically illustrating a process flow for manufacturing a packaging structure according to some embodiments of the present disclosure.

[0008] Figures 8 to 12 is a cross-sectional view schematically showing various packaging structures according to some other embodiments of the present disclosure.

[0009] FIG. 13A to FIG. 13G is a top view schematically showing various reinforcing structures according to some other embodiments of the present disclosure.

[0010] Fig.14 and Fig.15 2 is a cross-sectional view schematically illustrating various packaging structures according to some alternative embodiments of the present disclosure.

[0011] FIG. 16A to FIG. 16E is a top view schematically showing various reinforcing structures according to some other embodiments of the present disclosure.

[0012] Figures 17 to 21 is a cross-sectional view schematically showing various packaging structures according to some other embodiments of the present disclosure.

[0013] [Explanation of Symbols]

[0014] 110: Substrate

[0015] 112, 114: Bump pads

[0016] 116: Semiconductor through-hole via (TSV)

[0017] 120a, 120b: semiconductor die

[0018] 122a, 122b: Conductive bumps / bumps

[0019] 130: Insulation material

[0020] 130a: Insulation enclosure

[0021] 130a': insulation enclosure / first insulation enclosure

[0022] 140: Conductive bump

[0023] 150: Wiring substrate

[0024] 152: Conductive terminal

[0025] 160: Insulation enclosure / second insulation enclosure

[0026] 165: Strengthening structure

[0027] 170, 170a: Thermal interface material (TIM)

[0028] 180: Adhesive

[0029] 190, 190a: Cover

[0030] 190b: Thermally enhanced cover / cap

[0031] 191: Entrance

[0032] 192: Substrate

[0033] 193: Export

[0034] 194: Cooling fins

[0035] 195: Flow channel

[0036] 197: Waterproof ring

[0037] 198: Back metal

[0038] 199: Solder material

[0039] 200: Circuit board

[0040] 300: Jack board

[0041] 310: Conductive pin

[0042] 400, 500, 600: Screws

[0043] C: Coolant

[0044] D: Minimum distance

[0045] INT: Intermediary layer

[0046] M1, M1': metal layer / first metal layer

[0047] M2, M2': Metal layer / second metal layer

[0048] P1, P2, P3, P4, P5: Package structure / Chip on Wafer on Substrate (CoWoS) package structure

[0049] P6, P7, P8, P9, P10, P11, P12: Package structure

[0050] SL: Cutting Lane

[0051] SS: Monomer structure

[0052] T1: Maximum thickness / thickness

[0053] T2: Thickness

[0054] UF1, UF2, UF3: bottom filler

[0055] W: Interposer chip

[0056] W1: Reconstruction chip DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed by itself.

[0058] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0059] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which enables testing of a 3D package or 3DIC device, use of a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method including intermediate verification of a known good die to improve yield and reduce cost.

[0060] Figures 1 to 7 is a cross-sectional view schematically illustrating a process flow for manufacturing a packaging structure according to some embodiments of the present disclosure.

[0061] Reference Figure 1, providing an interposer wafer W including interposers INT arranged in an array. The interposer wafer W may be a silicon interposer wafer including a plurality of silicon interposers or other suitable semiconductor interposer wafers. The interposer wafer W may include a substrate 110, a bump pad 112 disposed on an upper surface of the substrate 110, a bump pad 114 disposed on a lower surface of the substrate 110, and a semiconductor through-hole (TSV) 116 penetrating the substrate 110, wherein the bump pad 112 is electrically connected to the bump pad 114 through the TSV 116. Semiconductor die 120a and semiconductor die 120b are disposed and mounted on a surface of the interposer wafer W, so that the semiconductor die 120a and semiconductor die 120b are electrically connected to the interposer INT of the interposer wafer W. In some embodiments, the semiconductor die 120a and semiconductor die 120b are electrically connected to the bump pad 112 of the interposer wafer W via conductive bumps 122a and conductive bumps 122b. Conductive bump 122a is located between semiconductor die 120a and bump pad 112, and conductive bump 122b is located between semiconductor die 120b and bump pad 112. In some embodiments, conductive bump 122a may be formed on semiconductor die 120a before semiconductor die 120a is mounted on interposer wafer W, and conductive bump 122b may be formed on semiconductor die 120b before semiconductor die 120b is mounted on interposer wafer W. Conductive bump 122a may be formed by a wafer-level bumping process performed on a semiconductor wafer including semiconductor die 120a arranged in an array, and conductive bump 122b may be formed by another wafer-level bumping process performed on a semiconductor wafer including semiconductor die 120b arranged in an array. In some embodiments, the semiconductor die 120a includes a logic die, a system-on-chip (SoC) die, or other suitable semiconductor die, and the semiconductor die 120b includes: a high bandwidth memory (HBM) cube, each having a stacked memory die or other suitable semiconductor die.

[0062] In some embodiments, the conductive bumps 122a and the conductive bumps 122b include microbumps. The conductive bumps 122a and the conductive bumps 122b may each include a copper (Cu) column covered by a nickel (Ni) cap, and the nickel (Ni) cap may be electrically connected to the bump pad 112 by a solder material. For example, the solder material includes a Sn-Ag solder material or other suitable solder materials.

[0063] After the semiconductor die 120a and the semiconductor die 120b are mounted on the interposer wafer W and electrically connected to the interposer wafer W via the conductive bumps 122a and the conductive bumps 122b, an underfill UF1 is formed on the interposer wafer W to fill the gap between the semiconductor die 120a and the interposer wafer W and the gap between the semiconductor die 120b and the interposer wafer W. The conductive bumps 122a and the conductive bumps 122b are encapsulated and protected by the underfill UF1 in the lateral direction, so that the conductive bumps 122a and the conductive bumps 122b can be prevented from being damaged by the mismatch of the coefficient of thermal expansion (CTE) between the interposer wafer W and the semiconductor die 120a and 120b. Therefore, the reliability of the conductive bumps 122a and the conductive bumps 122b can be improved.

[0064] Reference Figure 2 and Figure 3 , an insulating material 130 is formed on the interposer wafer W to cover the semiconductor die 120a and the semiconductor die 120b. The insulating material 130 may be formed by an over-molding process or a deposition process and a subsequent removal process. In some embodiments, an insulating material 130 (e.g., epoxy resin) is formed on the interposer wafer W to cover the rear surfaces and sidewalls of the semiconductor dies 120a and 120b by an over-molding process, and then a grinding process, a chemical mechanical polishing (CMP) process, or other suitable removal process is performed to remove a portion of the epoxy resin until the rear surfaces of the semiconductor dies 120a and 120b are exposed. In some alternative embodiments, an insulating material 130 (e.g., an oxide formed from tetraethoxysilane (TEOS)) is formed on the interposer wafer W by a chemical vapor deposition (CVD) process to cover the rear surfaces and sidewalls of the semiconductor dies 120a and 120b, and then a grinding process, a CMP process, or other suitable removal process is performed to remove portions of the oxide formed from TEOS until the rear surfaces of the semiconductor dies 120a and 120b are exposed. After performing the above removal process, Figure 3 As shown in FIG. 1 , the insulating encapsulation body 130 a is formed to laterally encapsulate the semiconductor dies 120 a and 120 b , and a top surface of the insulating encapsulation body 130 a is substantially flush with rear surfaces of the semiconductor dies 120 a and 120 b .

[0065] In some embodiments, during the removal process of the insulating material 130 , the insulating material 130 , the semiconductor die 120 a , and the semiconductor die 120 b are partially removed, so that the thickness of the semiconductor die 120 a and the semiconductor die 120 b is reduced.

[0066] A wafer-level bumping process may be performed to form conductive bumps 140 on bump pads 114 of interposer wafer W. In some embodiments, the wafer-level bumping process for forming conductive bumps 140 is performed before forming insulating encapsulation body 130 a. In some alternative embodiments, the wafer-level bumping process for forming conductive bumps 140 is performed after forming insulating encapsulation body 130 a.

[0067] After the insulating encapsulation body 130 a and the conductive bumps 140 are formed, a reconstructed wafer W1 including the interposer wafer W, the semiconductor die 120 a , the semiconductor die 120 b , the underfill UF1 , the insulating encapsulation body 130 a and the conductive bumps 140 is formed.

[0068] Reference Figure 3 and Figure 4 , and then a wafer sawing process is performed along the scribe line SL, so that the reconstructed wafer W1 is singulated into a plurality of singulated structures SS. The singulated structures SS may each include an interposer INT, at least one semiconductor die 120a, at least one semiconductor die 120b, a conductive bump 122a, a conductive bump 122b, an underfill UF1, an insulating encapsulant 130a' and a conductive bump 140. The conductive bump 122a is electrically connected between the semiconductor die 120a and the interposer INT. The conductive bump 122b is electrically connected between the semiconductor die 120b and the interposer INT. The underfill UF1 laterally encapsulates the conductive bumps 122a and 122b. The underfill UF1 may further cover the sidewalls of the semiconductor die 120a and 120b. The insulating encapsulation body 130a' encapsulates the semiconductor die 120a and 120b in the lateral direction, wherein the sidewall of the insulating encapsulation body 130a' is substantially aligned with the sidewall of the interposer INT. In addition, the conductive bumps 122a and 122b are disposed on a surface (e.g., an upper surface) of the interposer INT, and the conductive bump 140 is disposed on another surface (e.g., a lower surface) of the interposer INT.

[0069] Reference Figure 5, providing a wiring substrate 150 including a conductive terminal 152 formed thereon. In some embodiments, the wiring substrate 150 includes a dielectric core layer, a build-up or laminated dielectric layer stacked on an opposite surface of the dielectric core layer, a conductive wiring layer embedded in the build-up or laminated dielectric layer, and a via penetrating the dielectric core layer and the build-up or laminated dielectric layer. The conductive terminal 152 is formed on the lower surface of the wiring substrate 150 and is electrically connected to the bottommost conductive wiring layer of the wiring substrate 150.

[0070] You can Figure 3 At least one of the singulated structures SS singulated on the reconstructed wafer W1 shown in FIG. 1 is picked up and placed on the upper surface of the wiring substrate 150. The singulated structure SS is electrically connected to the conductive wiring of the wiring substrate 150 via the conductive bump 140. After the at least one singulated structure SS is mounted on the wiring substrate 150, an underfill glue UF2 may be formed to fill the gap between the wiring substrate 150 and the interposer INT of the singulated structure SS. The conductive bump 140 is encapsulated and protected by the underfill glue UF2 in the lateral direction, so that damage to the conductive bump 140 caused by the CTE mismatch between the interposer INT and the wiring substrate 150 can be prevented. Therefore, the reliability of the conductive bump 140 can be improved.

[0071] In some embodiments, the bottom filler UF2 not only fills the gap between the wiring substrate 150 and the interposer INT of the singulated structure SS, but also covers the sidewalls of the singulated structure SS. Figure 5 As shown in FIG. 1 , the underfill UF2 not only fills the gap between the wiring substrate 150 and the interposer INT of the singulated structure SS, but also covers the sidewalls of the interposer INT and the sidewalls of the insulating encapsulation body 130 a ′.

[0072] Reference Figure 6, an insulating material is formed on the wiring substrate 150 to cover the bottom filler UF2 and the singulated structure SS mounted on the wiring substrate 150. The insulating material can be formed by an overmolding process or a deposition process and a subsequent removal process. In some embodiments, an insulating material (e.g., epoxy resin) is formed on the interposer wafer W by an overmolding process to cover the rear surface and sidewalls of the singulated structure SS, and then a grinding process, a chemical mechanical polishing (CMP) process, or other suitable removal process is performed to remove a portion of the epoxy resin until the rear surface of the semiconductor die 120a and 120b in the singulated structure SS is exposed. In some alternative embodiments, an insulating material (e.g., oxide formed by tetraethoxysilane (TEOS)) is formed on the interposer wafer W by a chemical vapor deposition (CVD) process to cover the rear surface and sidewalls of the singulated structure SS, and then a grinding process, a CMP process, or other suitable removal process is performed to remove a portion of the oxide formed by TEOS until the rear surface of the semiconductor die 120a and 120b in the singulated structure SS is exposed. After performing the above-mentioned removal process, an insulating encapsulation body 160 is formed, and a top surface of the insulating encapsulation body 160 is substantially flush with the rear surfaces of the semiconductor dies 120 a and 120 b in the singulated structure SS.

[0073] In addition, if Figure 6 As shown in , the top surface of the insulating encapsulant 160 is substantially flush with the top surface of the insulating encapsulant 130a' and the top surfaces of the semiconductor dies 120a and 120b, and the sidewalls of the insulating encapsulant 160 are substantially aligned with the sidewalls of the wiring substrate 150. In some alternative embodiments, the top surface of the insulating encapsulant 160 is substantially flush with the top surface of the insulating encapsulant 130a' and the top surfaces of the semiconductor dies 120a and 120b, and the sidewalls of the insulating encapsulant 160 are kept at a certain distance from the sidewalls of the wiring substrate 150 in the lateral direction.

[0074] Reference Figure 7After forming the insulating encapsulation 160, a thermal interface material (TIM) 170 and an adhesive 180 are applied to cover the singulated structure SS and the insulating encapsulation 160. The thermal interface material 170 may cover the top surface of the singulated structure SS and a portion of the top surface of the insulating encapsulation 160, and the adhesive 180 may cover the remaining portion of the top surface of the insulating encapsulation 160. The material of the thermal interface material 170 may include a metal TIM, such as an indium (In) sheet or film, indium foil, indium solder, silver (Ag) paste, silver alloy, or a combination thereof. The thermal interface material 170 may also be a polymer-based TIM with a thermally conductive filler. The thermally conductive filler material that may be applied may include aluminum oxide, boron nitride, aluminum nitride, aluminum, copper, silver, indium, a combination thereof, and the like. The thermal interface material 170 may include a film-based or sheet-based material, such as a sheet having a synthetic carbon nanotube (CNT) structure integrated into the sheet, a thermally conductive sheet having a vertically oriented graphite filler, etc., and the material of the adhesive 180 may include a thermally conductive adhesive or an epoxy-based adhesive, etc. Then, a cover 190 is disposed on the thermal interface material 170 and the adhesive 180 and attached to the thermal interface material 170 and the adhesive 180. The cover 190 is thermally coupled to the rear surface of the semiconductor die 120a and 120b in the singulated structure SS via the thermal interface material 170, and the cover 190 is bonded to the top surface of the insulating package 160 by the adhesive 180. The material of the cover 190 may include copper, aluminum, cobalt, nickel-coated copper, stainless steel, tungsten, silver diamond, aluminum silicon carbide, etc. In addition, the cover 190 may be used as a heat sink and perform the function of a heat sink.

[0075] In some alternative embodiments not shown in the figures, the top surface of the singulated structure SS and the top surface of the insulating enclosure 160 are covered by the thermal interface material 170, and the formation of the adhesive 180 is omitted. In other words, the cover 190 is attached to the singulated structure SS and the insulating enclosure 160 via the thermal interface material 170.

[0076] like Figure 7As shown in , after forming the cover 190, a chip-on-wafer-on-substrate (CoWoS) packaging structure P1 is formed. The CoWoS packaging structure P1 includes a wiring substrate 150, an interposer INT disposed on the wiring substrate 150 and electrically connected to the wiring substrate 150, semiconductor dies 120a and 120b disposed on the interposer INT and electrically connected to the interposer INT, a first insulating encapsulation 130a' disposed on the interposer INT, a second insulating encapsulation 160 disposed on the wiring substrate 150, and a cover 190. The semiconductor dies 120a and 120b are encapsulated by the first insulating encapsulation 130a' in the lateral direction. The semiconductor dies 120a and 120b and the first insulating encapsulation 130a' are encapsulated by the second insulating encapsulation 160 in the lateral direction. The sidewalls of the cover 190 are substantially aligned with the sidewalls of the second insulating encapsulation 160 and the sidewalls of the wiring substrate 150. The cover 190 is disposed on the semiconductor die 120a and 120b, the first insulating encapsulation 130a' and the second insulating encapsulation 160. In some embodiments, the CoWoS package structure P1 further includes an adhesive 180 and a thermal interface material 170, wherein the adhesive is disposed between the second insulating encapsulation 160 and the cover 190, and the thermal interface material 170 is disposed between the semiconductor die 120a and 120b and the cover 190. In some embodiments, the first top surface of the first insulating encapsulation 130a' is substantially flush with the second top surface of the second insulating encapsulation 160. In some embodiments, the CoWoS package structure P1 further includes an underfill UF2 disposed between the interposer INT and the wiring substrate 150, wherein the underfill UF2 is laterally encapsulated by the second insulating encapsulation 160.

[0077] like Figure 7 As shown in , the cover 190 may be a metal plate with good thermal conductivity and structural strength. The minimum distance D between the cover 190 and the wiring substrate 150 is greater than the maximum thickness T2 of the second insulating enclosure 160. In some embodiments, the minimum distance D between the cover 190 and the wiring substrate 150 is substantially equal to the sum of the maximum thickness T2 of the second insulating enclosure 160 and the thickness T1 of the thermal interface material 170. The minimum distance D between the cover 190 and the wiring substrate 150 may be in the range from about 800 microns to about 1200 microns, the maximum thickness T2 of the second insulating enclosure 160 may be in the range from about 600 microns to about 900 microns, and the thickness T1 of the thermal interface material 170 may be in the range from about 50 microns to about 300 microns.

[0078] Since the singulated structure SS is laterally encapsulated by the insulating encapsulation body 160 , the warpage of the CoWoS package structure P1 is controlled, and the delamination problem of the adhesive 180 and the crack problem of the conductive bumps 122 a and 122 b caused by the warpage of the CoWoS package structure P1 can be minimized.

[0079] Figures 8 to 12 is a cross-sectional view schematically showing various packaging structures according to some other embodiments of the present disclosure.

[0080] Reference Figure 7 and Figure 8 In addition to the CoWoS package structure P2 further including a first metal layer M1 disposed between the thermal interface material 170 and the semiconductor die 120 a and a second metal layer M2 disposed between the thermal interface material 170 and the cover 190 , Figure 8 The CoWoS package structure P2 shown in FIG is similar to Figure 7 . In the present embodiment, the first metal layer M1 covers the rear surface of the semiconductor die 120a and a portion of the insulating encapsulant 130a', and the rear surface of the semiconductor die 120b and the top surface of the insulating encapsulant 1160 are not covered by the first metal layer M1. In the present embodiment, the second metal layer M2 covers a portion of the thermal interface material 170 and is located directly above the first metal layer M1, and the second metal layer M2 does not cover the adhesive 180. For example, the materials of the first metal layer M1 and the second metal layer M2 include conductive materials or metals, such as gold, indium, copper, silver, titanium-gold alloy, lead, tin, nickel-vanadium or a combination thereof.

[0081] The coverage of the first metal layer M1 and the second metal layer M2 can be modified according to design requirements. According to design requirements, the first metal layer M1 can cover not only the rear surface of the semiconductor die 120a, but also the rear surface of the semiconductor die 120b.

[0082] Reference Figure 7 and Fig. 9 In addition to the CoWoS package structure P3 further including a first metal layer M1′ disposed between the thermal interface material 170 and the semiconductor die 120 a and a second metal layer M2′ disposed between the thermal interface material 170 and the cover 190 , Fig. 9 The CoWoS package structure P3 shown in Figure 1 is similar to Figure 7. In the present embodiment, the first metal layer M1' completely covers the top surface of the insulating encapsulant 130a', the top surface of the insulating encapsulant 160, and the rear surfaces of the semiconductor dies 120a and 120b. In the present embodiment, the second metal layer M2' completely covers the top surface of the thermal interface material 170 and the top surface of the adhesive 180. In other words, the thermal interface material 170 and the adhesive 180 are separated from the singulated structure SS and the insulating encapsulant 160 by the first metal layer M1', and the thermal interface material 170 and the adhesive 180 are separated from the cover 190 by the second metal layer M2'. For example, the material of the first metal layer M1' and the second metal layer M2' includes a conductive material or metal, such as gold, indium, copper, silver, titanium-gold alloy, lead, tin, nickel-vanadium, or a combination thereof.

[0083] The metal layers M1 , M2 , M1 ′ and M2 ′ can further improve the heat dissipation performance of the CoWoS packaging structures P2 and P3 .

[0084] Reference Fig.10 , a packaging structure including a CoWoS packaging structure P1, an underfill UF3, and a circuit board 200 (e.g., a printed circuit board) is shown. The CoWoS packaging structure P1 is disposed on the circuit board 200 and is electrically connected to the circuit board 200 through a conductive terminal 152. The underfill UF3 fills the gap between the CoWoS packaging structure P1 and the circuit board 200 to encapsulate the conductive terminal 152. The conductive terminal 152 is encapsulated and protected by the underfill UF3 in the lateral direction, thereby preventing damage to the conductive terminal 152 caused by a mismatch in the coefficient of thermal expansion (CTE) between the CoWoS packaging structure P1 and the circuit board 200. Therefore, the reliability of the conductive terminal 152 can be improved.

[0085] In some embodiments, the bottom filler UF3 not only fills the gap between the CoWoS package structure P1 and the circuit board 200, but also covers the sidewalls of the CoWoS package structure P1. Fig.10 As shown in , the underfill UF3 not only fills the gap between the CoWoS package structure P1 and the circuit board 200 , but also covers the sidewalls of the wiring substrate 150 .

[0086] although Fig.10 The CoWoS packaging structure P1 is shown to be mounted on a circuit board, but the present embodiment is not limited thereto. Figure 8 The CoWoS package structure P2 or Fig. 9 The CoWoS packaging structure P3) shown in FIG. 1 can be mounted on a circuit board 200 .

[0087] Reference Fig.11, shows a packaging structure including a CoWoS packaging structure P4, a circuit board 200 (e.g., a printed circuit board), and a socket board 300 disposed between a wiring substrate 150 of the CoWoS packaging structure P4 and the circuit board 200, wherein the wiring substrate 150 of the CoWoS packaging structure P4 is electrically connected to the circuit board 200 via the socket board 300. In addition, the packaging structure shown in the figure does not include a bottom filling glue located between the circuit board 200 and the socket board 300.

[0088] like Fig.11 As shown in the figure, the CoWoS package structure P4 is Figure 7 The CoWoS package structure P4 is modified from the CoWoS package structure P1 shown in FIG. Figure 7 The CoWoS package structure P4 is similar to the CoWoS package structure P1 except for the conductive terminals 152 shown in FIG. The jack board 300 includes a plurality of conductive pins 310 that contact the wiring in the wiring substrate 150 and the circuit board 200. In some embodiments, the jack board 300 includes pogo pins arranged in an array, wherein the pogo pins contact and are electrically connected to the wiring in the wiring substrate 150 and the circuit board 200.

[0089] although Fig.11 The CoWoS packaging structure P4 is shown to be mounted on the circuit board, but the present embodiment is not limited thereto. Other types of CoWoS packaging structures can be mounted on the circuit board 200 via the socket board 300. In some other embodiments, Figure 8 The CoWoS package structure modified from the CoWoS package structure P2 shown in FIG. 1 can be mounted on the circuit board 200 via the socket board 300, and the CoWoS package structure modified from the CoWoS package structure P2 does not include a conductive terminal (ie, Figure 8 In some alternative embodiments, the conductive terminal 152 shown in FIG. Fig. 9 The CoWoS package structure modified from the CoWoS package structure P3 shown in FIG. 1 can be mounted on the circuit board 200 via the socket board 300, and the CoWoS package structure modified from the CoWoS package structure P3 does not include a conductive terminal (ie, Fig. 9 Conductive terminals 152 shown in FIG.

[0090] Reference Figure 7 and Fig.12 In addition to the CoWoS packaging structure P5 also including a reinforcement structure 165 embedded in the insulating encapsulation body 160, Fig.12 The CoWoS package structure P5 shown in Figure 1 is similar to Figure 7The CoWoS package structure P1 shown in FIG. The reinforcement structure 165 is disposed on the wiring substrate 150 and surrounds the singulated structure SS. The reinforcement structure 165 is separated from the singulated structure SS by the insulating encapsulation body 160. The reinforcement structure 165 is in contact with the adhesive 180 and is covered by the adhesive 180. In addition, the thickness of the reinforcement structure 165 is substantially equal to the thickness of the insulating encapsulation body 160 (i.e., Figure 7 The thickness T2 shown in FIG.

[0091] FIG. 13A to FIG. 13G Schematically illustrating top views of various reinforcement structures according to some other embodiments of the present disclosure.

[0092] Reference FIG. 13A to FIG. 13G , showing various reinforcing structures 165. In some embodiments, as Fig.13A As shown in , the reinforcement structure 165 includes a single ring pattern, and the semiconductor dies 120a and 120b are surrounded by the single ring pattern. In some other embodiments, such as Fig. 13B As shown in , the reinforcement structure 165 includes a pair of C-shaped patterns, and the semiconductor dies 120a and 120b are surrounded by the pair of C-shaped patterns. Fig. 13C As shown in , the reinforcement structure 165 includes a set of stripe patterns, the set of stripe patterns including a pair of horizontal stripe patterns and a pair of vertical stripe patterns, and the semiconductor dies 120a and 120b are surrounded by the set of stripe patterns. Fig.13D As shown in , the reinforcement structure 165 includes an inner ring pattern and an outer ring pattern surrounding the inner ring pattern, and the semiconductor dies 120a and 120b are surrounded by the inner ring pattern and the outer ring pattern. In some other embodiments, as Fig.13E As shown in , the reinforcement structure 165 includes a pair of vertical strip patterns, and the semiconductor dies 120a and 120b are located between the pair of vertical strip patterns. In some alternative embodiments, as Fig.13F As shown in , the reinforcement structure 165 includes a pair of horizontal strip patterns, and the semiconductor dies 120a and 120b are located between the pair of horizontal strip patterns. In some alternative embodiments, as Figure 13G As shown in FIG. 1 , the reinforcement structure 165 includes a pair of L-shaped patterns, and the semiconductor dies 120 a and 120 b are located between the pair of L-shaped patterns.

[0093] In the present disclosure, the shape, distribution and size of the reinforcing structure 165 are not limited. FIG. 13A to FIG. 13G Other types of reinforcement structures not shown.

[0094] Fig.14 and Fig.15 2 is a cross-sectional view schematically illustrating various packaging structures according to some alternative embodiments of the present disclosure.

[0095] Reference Fig.12 and Fig.14 In addition to the packaging structure P6 further including screws 400 penetrating the cover 190 and the adhesive 180, wherein the cover 190 is fastened to the reinforcement structure 165 by the screws 400, Fig.14 The package structure P6 shown in FIG. Fig.12 The package structure P5 shown in FIG.

[0096] Reference Fig.15 In addition to the package structure P7 including screws 500 penetrating the cover 190, the adhesive 180 and the reinforcement structure 165, wherein the cover 190 is fastened to the reinforcement structure 165 and the wiring substrate 150 by the screws 500, Fig.15 The package structure P7 shown in Fig.12 The package structure P5 shown in FIG.

[0097] FIG. 16A to FIG. 16E Schematically illustrating top views of various reinforcement structures according to some other embodiments of the present disclosure.

[0098] Reference FIG. 16A to FIG. 16E , showing various reinforcing structures 165 fastened by screws 400 or 500. In some embodiments, as Fig.16A As shown in , the reinforcement structure 165 includes a single ring pattern fastened by screws 400 or 500, and the semiconductor dies 120a and 120b are surrounded by the single ring pattern. In some other embodiments, such as Fig. 16B As shown in , the reinforcement structure 165 includes a pair of C-shaped patterns fastened by screws 400 or 500, and the semiconductor dies 120a and 120b are surrounded by the pair of C-shaped patterns. Fig. 16C As shown in , the reinforcement structure 165 includes a set of stripe patterns, the set of stripe patterns includes a pair of horizontal stripe patterns and a pair of vertical stripe patterns, and the semiconductor dies 120a and 120b are surrounded by the set of stripe patterns. In some other embodiments, as Fig.16D As shown in , the reinforcement structure 165 includes a pair of vertical strip patterns fastened by screws 400 or 500, and the semiconductor dies 120a and 120b are located between the pair of vertical strip patterns. In some alternative embodiments, as Fig.16E As shown in FIG. 1 , the reinforcement structure 165 includes a pair of horizontal stripe patterns fastened by screws 400 or 500 , and the semiconductor dies 120 a and 120 b are located between the pair of horizontal stripe patterns.

[0099] In the present disclosure, the shape, distribution and size of the reinforcing structure 165 are not limited. FIG. 16A to FIG. 16E Other types of reinforcement structures not shown.

[0100] Figures 17 to 21 is a cross-sectional view schematically showing various packaging structures according to some other embodiments of the present disclosure.

[0101] Reference Fig.17 In addition to the package structure P8, the package structure P8 also includes a reinforcing structure 165 embedded in the insulating package 160 and a screw 600 that penetrates the cover 190, the adhesive 180, the reinforcing structure 165, the wiring substrate 150, the jack board 300 and the circuit board 200. Fig.17 The package structure P8 shown in Fig.11 The package structure P4 shown in FIG.

[0102] Reference Fig.18 , except that the package structure P9 includes a cover 190a having enhanced heat dissipation performance, Fig.18 The package structure P9 shown in is similar to Fig.17 The package structure P8 shown in FIG. The cover 190 a may be used as a heat sink and perform the function of a heat sink. The cover 190 a may include a base plate 192 and a plurality of heat dissipation fins 194 protruding upward from the base plate 192 .

[0103] Reference Fig.19 In addition to the cover 190 being attached to the insulating enclosure 160, the reinforcement structure 165 and the unitized structure SS via the thermal interface material 170a, Fig.19 The package structure P10 shown in FIG. Fig.17 In other words, the top surface of the single structure SS and the top surface of the insulating package 160 are completely covered by the thermal interface material 170a, and the top surface of the single structure SS and the insulating package 160 are completely covered by the thermal interface material 170a, and the top surface of the insulating package 160 is ... Fig.17 The formation of adhesive 180 shown in FIG.

[0104] Reference Fig. 20 In addition to the cover 190a being attached to the insulating enclosure 160, the reinforcement structure 165 and the unitized structure SS by means of the thermal interface material 170a, Fig. 20 The package structure P11 shown in Fig.18 In other words, the top surface of the individualized structure SS and the top surface of the insulating encapsulation body 160 are completely covered by the thermal interface material 170a, and the top surface of the insulating encapsulation body 160 is completely covered by the thermal interface material 170a. Fig.18 The formation of adhesive 180 shown in FIG.

[0105] Reference Fig.21, except that the packaging structure P12 includes a thermally enhanced cover 190 b, and the cover 190 b includes an inlet 191, an outlet 193, and a flow channel 195, the flow channel 195 is connected to the inlet 191 and the outlet 193, and the coolant C enters the flow channel 195 through the inlet 191 and leaves the flow channel 195 through the outlet 193, Fig.21 The package structure P12 shown in FIG. Figure 7 The CoWoS package structure P1 is shown in FIG. In some embodiments, the sidewall of the insulating encapsulation 130 a ′ is substantially aligned with the sidewall of the interposer INT.

[0106] like Fig.21 As shown in , the package structure P12 may further include a waterproof ring 197 (e.g., an O-ring) disposed between the cover 190b and the insulating encapsulation body 160, so that the coolant C can be confined in the flow channel 195. In addition, the package structure P12 may further include a backside metal 198 and a solder material 199 located on the backside metal 198, wherein the backside metal 198 covers a portion of the singulated structure SS and the insulating encapsulation body 160, the solder material 199 is disposed on the backside metal 198, and the solder material is sandwiched between the backside metal 198 and the cover 190b. The cover 190b is attached to the singulated structure SS via the backside metal 198 and the solder material 199, and the cover 190b is bonded to the insulating encapsulation body 160 via the adhesive 180.

[0107] In the above-described embodiment, since the singulated structure SS is laterally encapsulated by the insulating encapsulation body 160, the warpage of the package structures P1 to P12 can be properly controlled. In addition, the delamination problem and the crack problem of the conductive bumps (i.e., the bumps 122a and 122b) occurring in the package structures P1 to P12 can be minimized. The insulating encapsulation body 160 in the package structures P1 to P12 provides good support for the cover 190, 190a or 190b, and therefore, the manufacturing yield of the package structures P1 to P12 can be increased.

[0108] According to some embodiments of the present disclosure, a packaging structure is provided, the structure comprising: a wiring substrate; an interposer disposed on the wiring substrate and electrically connected to the wiring substrate; a semiconductor die disposed on the interposer and electrically connected to the interposer; a first insulating encapsulation disposed on the interposer; a second insulating encapsulation disposed on the wiring substrate; and a cover. The semiconductor die is encapsulated by the first insulating encapsulation in the lateral direction. The semiconductor die and the first insulating encapsulation are encapsulated by the second insulating encapsulation in the lateral direction. The top surface of the first insulating encapsulation is substantially flush with the top surface of the second insulating encapsulation and the surface of the semiconductor die. The cover is disposed on the semiconductor die, the first insulating encapsulation, and the second insulating encapsulation. In some embodiments, the structure further comprises: an adhesive disposed between the second insulating encapsulation and the cover; and a thermal interface material disposed between the semiconductor die and the cover. In some embodiments, the structure further comprises: a first metal layer disposed between the thermal interface material and the semiconductor die; and a second metal layer disposed between the thermal interface material and the cover. In some embodiments, the cover includes an inlet, an outlet, and a flow channel, the flow channel is connected to the inlet and the outlet, and the coolant enters the flow channel via the inlet and leaves the flow channel via the outlet. In some embodiments, the side wall of the first insulating enclosure is substantially aligned with the side wall of the interposer. In some embodiments, the first top surface of the first insulating enclosure is substantially flush with the second top surface of the second insulating enclosure. In some embodiments, the structure further includes: an underfill, disposed between the interposer and the wiring substrate, wherein the underfill is laterally encapsulated by the second insulating enclosure. In some embodiments, the structure further includes: a reinforcement structure embedded in the second insulating enclosure. In some embodiments, the structure further includes: a circuit board; and a jack board, disposed between the wiring substrate and the circuit board, wherein the wiring substrate is electrically connected to the circuit board via the jack board.

[0109] In one embodiment, the package structure further comprises: an adhesive disposed between the second insulating encapsulation body and the cover; and a thermal interface material disposed between the semiconductor die and the cover. In one embodiment, the package structure further comprises: a first metal layer disposed between the thermal interface material and the semiconductor die; and a second metal layer disposed between the thermal interface material and the cover. In one embodiment, the cover comprises an inlet, an outlet, and a flow channel, the flow channel is connected to the inlet and the outlet, and the coolant enters the flow channel through the inlet and leaves the flow channel through the outlet. In one embodiment, the sidewall of the first insulating encapsulation body is substantially aligned with the sidewall of the interposer. In one embodiment, the first top surface of the first insulating encapsulation body is substantially flush with the second top surface of the second insulating encapsulation body. In one embodiment, the package structure further comprises: an underfill glue disposed between the interposer and the wiring substrate, wherein the underfill glue is laterally encapsulated by the second insulating encapsulation body. In one embodiment, the package structure further comprises: a reinforcement structure embedded in the second insulating encapsulation body. In one embodiment, the packaging structure further includes: a circuit board; and a socket board disposed between the wiring substrate and the circuit board, wherein the wiring substrate is electrically connected to the circuit board via the socket board.

[0110] According to some other embodiments of the present disclosure, a packaging structure is provided, the structure comprising: a wiring substrate; an interposer disposed on the wiring substrate; a semiconductor die disposed on the interposer; a first insulating encapsulant disposed on the interposer; an underfill filled between the wiring substrate and the interposer; a second insulating encapsulant disposed on the wiring substrate; and a heat sink. The interposer is electrically connected to the wiring substrate via a first conductive bump. The semiconductor die is electrically connected to the interposer via a second conductive bump. The first insulating encapsulant laterally encapsulates the semiconductor die and the second conductive bump. The underfill laterally encapsulates the first conductive bump. The second insulating encapsulant laterally encapsulates the first insulating encapsulant and the underfill. The heat sink is attached to the semiconductor die, the first insulating encapsulant, and the second insulating encapsulant via a thermal interface material. In some embodiments, the structure further comprises: an adhesive disposed between the second insulating encapsulant and the cover, wherein the adhesive surrounds and contacts the thermal interface material. In some embodiments, the sidewalls of the first insulating enclosure are substantially aligned with the sidewalls of the interposer, and the first top surface of the first insulating enclosure is substantially flush with the second top surface of the second insulating enclosure. In some embodiments, the structure further comprises: a circuit board, wherein the wiring substrate is electrically connected to the circuit board. In some embodiments, the structure further comprises: a jack plate, disposed between the wiring substrate and the circuit board, wherein the wiring substrate is electrically connected to the circuit board via the jack plate. In some embodiments, the structure further comprises: a reinforcement structure embedded in the second insulating enclosure. In some embodiments, the heat sink is fastened to the reinforcement structure by screws. In some embodiments, the heat sink is fastened to the reinforcement structure and the wiring substrate by screws.

[0111] In one embodiment, the packaging structure further includes: an adhesive disposed between the second insulating enclosure and the cover, wherein the adhesive surrounds and contacts the thermal interface material. In one embodiment, the sidewalls of the first insulating enclosure are substantially aligned with the sidewalls of the interposer, and the first top surface of the first insulating enclosure is substantially flush with the second top surface of the second insulating enclosure. In one embodiment, the packaging structure further includes: a circuit board, wherein the wiring substrate is electrically connected to the circuit board. In one embodiment, the packaging structure further includes: a socket plate disposed between the wiring substrate and the circuit board, wherein the wiring substrate is electrically connected to the circuit board via the socket plate. In one embodiment, the packaging structure further includes: a reinforcement structure embedded in the second insulating enclosure. In one embodiment, the heat sink is fastened to the reinforcement structure by screws. In one embodiment, the heat sink is fastened to the reinforcement structure and the wiring substrate by screws.

[0112] According to some other embodiments of the present disclosure, a packaging structure is provided, the structure comprising: a wiring substrate; an interposer disposed on the wiring substrate and electrically connected to the wiring substrate; a semiconductor die disposed on the interposer and electrically connected to the interposer; a first insulating encapsulation disposed on the interposer; a second insulating encapsulation disposed on the wiring substrate; and a cover. The semiconductor die is encapsulated by the first insulating encapsulation in the lateral direction. The semiconductor die and the first insulating encapsulation are encapsulated by the second insulating encapsulation in the lateral direction. The cover is disposed on the semiconductor die, the first insulating encapsulation, and the second insulating encapsulation, wherein the minimum distance between the cover and the wiring substrate is greater than the maximum thickness of the second insulating encapsulation. In some embodiments, the structure further comprises: a thermal interface material disposed between the semiconductor die and the cover. In some embodiments, the minimum distance between the cover and the wiring substrate is substantially equal to the sum of the maximum thickness of the second insulating encapsulation and the thickness of the thermal interface material.

[0113] In one embodiment, the package structure further includes: a thermal interface material disposed between the semiconductor die and the cover.

[0114] In one embodiment, the minimum distance between the cover and the wiring substrate is substantially equal to the sum of the maximum thickness of the second insulating enclosure and the thickness of the thermal interface material.

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, characterized by: Wiring substrate; an interposer disposed on the wiring substrate and electrically connected to the wiring substrate; a semiconductor die disposed on and electrically connected to the interposer; a first insulating encapsulation body disposed on the interposer, wherein the semiconductor die is laterally encapsulated by the first insulating encapsulation body; A second insulating encapsulation body is disposed on the wiring substrate, wherein the semiconductor die and the first insulating encapsulation body are laterally encapsulated by the second insulating encapsulation body; as well as A cover is arranged on the semiconductor die, the first insulating package and the second insulating package, wherein the top surface of the first insulating package is substantially flush with the top surface of the second insulating package and the surface of the semiconductor die, and the minimum distance between the cover and the wiring substrate is greater than the maximum thickness of the second insulating package.

2. The packaging structure according to claim 1, further comprising: an adhesive disposed between the second insulating enclosure and the cover; as well as A thermal interface material is disposed between the semiconductor die and the lid.

3. The packaging structure according to claim 2, further comprising: a first metal layer disposed between the thermal interface material and the semiconductor die; as well as A second metal layer is disposed between the thermal interface material and the cover. 4 . The packaging structure according to claim 1 , wherein the cover comprises an inlet, an outlet, and a flow channel, the flow channel is in communication with the inlet and the outlet, and a coolant enters the flow channel through the inlet and leaves the flow channel through the outlet. The package structure according to claim 1 , wherein a sidewall of the first insulating encapsulation is substantially aligned with a sidewall of the interposer. The package structure according to claim 1 , wherein a first top surface of the first insulating encapsulation body is substantially flush with a second top surface of the second insulating encapsulation body.

7. The package structure according to claim 1, further comprising: An underfill is disposed between the interposer and the wiring substrate, wherein the underfill is laterally encapsulated by the second insulating encapsulation body.

8. The package structure according to claim 1, further comprising: The reinforcement structure is embedded in the second insulating enclosure.

9. The package structure according to claim 1, further comprising: Circuit boards; as well as A jack board is provided between the wiring substrate and the circuit board, wherein the wiring substrate is electrically connected to the circuit board via the jack board.

10. A packaging structure, characterized by: Wiring substrate; an interposer disposed on the wiring substrate, wherein the interposer is electrically connected to the wiring substrate via a first conductive bump; a semiconductor die disposed on the interposer, wherein the semiconductor die is electrically connected to the interposer via a second conductive bump; A first insulating encapsulation body is disposed on the interposer, wherein the first insulating encapsulation body laterally encapsulates the semiconductor die and the second conductive bump; An underfill glue is filled between the wiring substrate and the interposer, wherein the underfill glue laterally encapsulates the first conductive bump; A second insulating encapsulation body is disposed on the wiring substrate, wherein the second insulating encapsulation body laterally encapsulates the first insulating encapsulation body and the bottom filling glue; as well as A heat sink is attached to the semiconductor die, the first insulating package and the second insulating package via a thermal interface material, wherein a minimum distance between the heat sink and the wiring substrate is greater than a maximum thickness of the second insulating package.

11. The package structure according to claim 10, further comprising: An adhesive is disposed between the second insulating enclosure and the cover, wherein the adhesive surrounds and contacts the thermal interface material. 12 . The package structure according to claim 10 , wherein a sidewall of the first insulating encapsulation is substantially aligned with a sidewall of the interposer, and a first top surface of the first insulating encapsulation is substantially flush with a second top surface of the second insulating encapsulation.

13. The package structure according to claim 10, further comprising: A circuit board, wherein the wiring substrate is electrically connected to the circuit board.

14. The package structure according to claim 13, further comprising: A jack board is provided between the wiring substrate and the circuit board, wherein the wiring substrate is electrically connected to the circuit board via the jack board.

15. The package structure according to claim 10, further comprising: The reinforcement structure is embedded in the second insulating enclosure.

16. The package structure according to claim 15, further comprising: The heat sink is fastened to the reinforcement structure by screws.

17. The package structure according to claim 15, further comprising: The heat sink is fastened to the reinforcement structure and the wiring substrate by screws.

18. A packaging structure, characterized by: Wiring substrate; an interposer disposed on the wiring substrate and electrically connected to the wiring substrate; a semiconductor die disposed on and electrically connected to the interposer; a first insulating encapsulation body disposed on the interposer, wherein the semiconductor die is laterally encapsulated by the first insulating encapsulation body; A second insulating encapsulation body is disposed on the wiring substrate, wherein the semiconductor die and the first insulating encapsulation body are laterally encapsulated by the second insulating encapsulation body; as well as A cover is disposed on the semiconductor die, the first insulating package, and the second insulating package, wherein a minimum distance between the cover and the wiring substrate is greater than a maximum thickness of the second insulating package.

19. The package structure according to claim 18, further comprising: A thermal interface material is disposed between the semiconductor die and the lid. 20 . The package structure of claim 19 , wherein the minimum distance between the lid and the wiring substrate is substantially equal to the sum of the maximum thickness of the second insulating encapsulation body and the thickness of the thermal interface material.

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