Chip packaging structure and manufacturing method thereof

Abstract

The present invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure includes the following steps. A carrier board having a plurality of conductive blocks and at least one metal layer formed thereon is provided. The carrier board includes a substrate and a stainless steel layer sputtered on the substrate. The substrate has a plurality of first grooves and at least one second groove surrounding the first groove. The stainless steel layer conformally covers the first groove and the second groove to define a plurality of third grooves and at least one fourth groove. The conductive blocks fill the third grooves. The metal layer covers the stainless steel layer, the conductive blocks and the fourth groove to define at least one fifth groove. At least one chip is arranged in the fifth groove. At least one circuit structure layer is formed on the carrier board. The patterned circuit layer of the circuit structure layer is electrically connected to a plurality of electrodes of the chip. The carrier board and the circuit structure layer are separated to expose the conductive blocks and the metal layer.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] In the well-known coreless process, the edge of the local carrier and the edge of the local circuit board are first combined by adhesive or copper plating. Another conventional method is to use a thin substrate (thickness is, for example, 100 microns) containing glass fiber cloth, with a piece of copper foil on each side and a removable ultra-thin copper foil (thickness is, for example, 3 to 5 microns) attached thereto as a carrier. After the circuit board has undergone multiple processes, the portion with adhesive or copper plating between the carrier and the circuit board is cut off to obtain the circuit board for the packaging process. However, in the well-known coreless process, part of the carrier and part of the circuit board need to be cut off, thereby reducing the size of the circuit board and the carrier after cutting cannot be reused, resulting in increased manufacturing costs.

[0003] In order to solve the above problems, it is conventional to use a stainless steel plate as the basis of the carrier. In the process of manufacturing the circuit structure, the stainless steel plate can provide good stability and does not need to be cut when dismantling the plate, so it can be reused, thereby effectively saving manufacturing costs. However, the stainless steel plate is large and heavy, and is often difficult to carry during the manufacturing process. In addition, its edges and corners are relatively sharp, which often causes damage to the substrate itself or the base.

[0004] In addition, for most packaging structures, electromagnetic interference (EMI) is a common but unwelcome interference, wherein the so-called interference may interrupt, hinder, reduce or limit the performance of the overall circuit. Therefore, with the continuous increase in the demand for packaging structures of high-frequency devices, better EMI shielding performance is also being improved. In conventional technology, after the packaging is completed, a metal coating is usually made on the outside of the packaging colloid by electroplating or sputtering to improve the EMI shielding performance of the packaging structure, but this will result in a thicker packaging structure and higher process costs. Summary of the invention

[0005] The present invention provides a chip packaging structure and a manufacturing method thereof, which is safer and simpler to manufacture, can effectively reduce manufacturing costs and improve product yield, and can have better heat dissipation and electromagnetic interference prevention effects.

[0006] According to an embodiment of the present invention, a method for manufacturing a chip packaging structure includes the following steps. A carrier having a plurality of conductive blocks and at least one metal layer formed thereon is provided. The carrier includes a substrate and a stainless steel layer sputtered on the substrate. The substrate has a plurality of first grooves and at least one second groove surrounding the first grooves. The stainless steel layer conformally covers the first grooves and the second grooves to define a plurality of third grooves and at least one fourth groove. The conductive blocks fill the third grooves. The metal layer covers the stainless steel layer, the conductive blocks and the fourth grooves to define at least one fifth groove. At least one chip is arranged in the fifth groove. At least one circuit structure layer is formed on the carrier. The patterned circuit layer of the circuit structure layer is electrically connected to a plurality of electrodes of the chip. The carrier and the circuit structure layer are separated to expose the conductive blocks and the metal layer.

[0007] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the carrier includes a sheet or roll core substrate, a sheet or roll stainless steel plate, a soft copper foil substrate or a glass substrate electroplated with a titanium layer and a copper layer.

[0008] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the stainless steel layer has a central area and a peripheral area surrounding the central area. Before forming the metal layer on the carrier, the method further includes: forming an insulating layer to cover the peripheral area of ​​the stainless steel layer. The insulating layer extends from the upper surface of the stainless steel layer and covers the side of the carrier. The insulating layer exposes the central area.

[0009] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the manufacturing method of the chip packaging structure further includes: before configuring the chip in the fifth groove of the carrier, forming a plurality of first copper pillars on the metal layer corresponding to the conductive block. Before configuring the chip in the fifth groove of the carrier, forming a plurality of second copper pillars on the electrodes of the chip.

[0010] In the manufacturing method of the chip packaging structure according to an embodiment of the present invention, the step of forming a circuit structure layer on a carrier includes: forming a dielectric layer on a metal layer. The dielectric layer covers the metal layer and the chip, and covers the first copper column and the second copper column. Forming a patterned circuit layer on the dielectric layer. The patterned circuit layer is electrically connected to the metal layer through the first copper column. The patterned circuit layer is electrically connected to the electrode of the chip through the second copper column. Forming a solder mask on the patterned circuit layer. The solder mask has a plurality of openings, and the openings expose a portion of the patterned circuit layer.

[0011] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the step of forming a circuit structure layer on a carrier includes: forming a dielectric layer on the metal layer. The dielectric layer covers the metal layer and the chip. Forming a plurality of through holes in the dielectric layer. The through holes expose a portion of the metal layer and the electrode of the chip. Forming conductive through holes in the through holes respectively. Forming a patterned circuit layer on the dielectric layer. The patterned circuit layer is electrically connected to the metal layer and the electrode through the conductive through holes. Forming a solder mask on the patterned circuit layer. The solder mask has a plurality of openings, and the openings expose a portion of the patterned circuit layer.

[0012] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the electrodes of the chip include a plurality of copper electrodes or a plurality of aluminum electrodes, and the material of the dielectric layer includes a photosensitive dielectric (PID) material or a prepreg (PP).

[0013] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, after separating the carrier and the circuit structure layer to expose the conductive blocks and the metal layer, the method further includes: removing the metal layer to expose at least the back side of the chip and a portion of the circuit structure layer.

[0014] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the step of forming a circuit structure layer on a carrier includes: forming a dielectric layer on the metal layer. The dielectric layer covers the first part of the metal layer and the chip. Forming a plurality of through holes in the dielectric layer. The through holes expose a portion of the first part of the metal layer and the electrode of the chip. Forming conductive through holes in the through holes respectively. Forming a patterned circuit layer on the dielectric layer. The patterned circuit layer is electrically connected to the metal layer and the electrode through the conductive through holes. Forming a packaging colloid on the patterned circuit layer and the second part of the metal layer.

[0015] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, after separating the carrier and the circuit structure layer to expose the conductive block and the metal layer, the method further includes: removing the second part and part of the first part of the metal layer to expose the dielectric layer and the packaging colloid. The third part of the remaining metal layer covers the back side of the chip, and the fourth part of the remaining metal layer is located between the conductive block and the dielectric layer. A surface treatment layer is formed on the surface of the conductive block and on the third part of the remaining metal layer.

[0016] According to an embodiment of the present invention, a method for manufacturing a chip packaging structure includes the following steps. A carrier having at least one metal layer formed thereon is provided. The carrier includes a substrate and a stainless steel layer sputtered on the substrate. The substrate has at least one first groove, and the stainless steel layer conformally covers the first groove to define at least one second groove. The metal layer covers the stainless steel layer to define at least one third groove. At least one chip is arranged in the third groove. At least one circuit structure layer is formed on the carrier, wherein the patterned circuit layer of the circuit structure layer is electrically connected to a plurality of electrodes of the chip. The carrier and the circuit structure layer are separated to expose the metal layer.

[0017] According to an embodiment of the present invention, a chip packaging structure includes a chip, a circuit structure layer, a metal layer and a plurality of conductive blocks. The circuit structure layer includes at least one dielectric layer and at least one patterned circuit layer. The patterned circuit layer is electrically connected to a plurality of electrodes of the chip. A portion of the metal layer covers the back side of the chip. The conductive blocks are electrically connected to the patterned circuit layer through another portion of the metal layer.

[0018] In the chip packaging structure according to the embodiment of the present invention, the chip packaging structure further includes: packaging colloid to cover the dielectric layer, the conductive block and the metal layer.

[0019] In the chip packaging structure according to an embodiment of the present invention, at least one dielectric layer includes a first dielectric layer and a second dielectric layer. At least one patterned circuit layer includes a first patterned circuit layer and a second patterned circuit layer. The circuit structure layer also includes a plurality of first conductive vias, a plurality of second conductive vias and a packaging colloid. The first patterned circuit layer is electrically connected to the electrode of the chip through the first conductive via. The first patterned circuit layer is electrically connected to the conductive block through the first conductive via and another part of the metal layer. The second patterned circuit layer is electrically connected to the first patterned circuit layer through the second conductive via. The packaging colloid covers the first dielectric layer, the second dielectric layer and the second patterned circuit layer.

[0020] In the chip packaging structure according to the embodiment of the present invention, the chip packaging structure further includes: a surface treatment layer, covering the metal layer. In summary, in the manufacturing method of the chip packaging structure of the present invention, a stainless steel layer is formed on the substrate of the carrier by sputtering, so as to utilize the separation characteristics between the stainless steel layer and the electroplated copper layer (i.e., the metal layer) thereon to achieve the effect of separating the product board and the carrier. Furthermore, the stainless steel layer formed by sputtering can have a smaller volume and weight than the conventional stainless steel plate, and the conventional glass fiber resin substrate can be used in operation, which is safer and simpler. In addition, when separating the carrier and the circuit structure layer, no cutting is required, so the carrier can be reused, thereby effectively saving manufacturing costs. In addition, the metal layer exposed after separating the carrier and the circuit structure layer can be directly used as a shielding layer to prevent electromagnetic interference. Compared with the conventional method of making a metal coating film on the outside of the packaging colloid by electroplating or sputtering after the packaging is completed, the chip packaging structure of the present invention can have a thinner packaging thickness and can reduce the process cost.

[0021] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0023] Figures 1A to 1J A cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present invention;

[0024] Figure 1K is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present invention;

[0025] FIG. 2A to FIG. 2D is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to another embodiment of the present invention;

[0026] Figure 2E is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention;

[0027] FIG. 3A to FIG. 3D A cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to another embodiment of the present invention;

[0028] Figure 3E is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention;

[0029] FIG. 4A to FIG. 4DA cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to yet another embodiment of the present invention;

[0030] Figure 5 is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present invention;

[0031] FIG. 6A to FIG. 6B A cross-sectional schematic diagram of partial steps of a method for manufacturing a chip packaging structure according to another embodiment of the present invention;

[0032] Figure 6C The figure is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention.

[0033] Description of Figure Numbers

[0034] 10a, 10a', 10b, 10b', 10c, 10c', 10d, 10e, 10f, 10f': chip packaging structure;

[0035] 100, 100': carrier board;

[0036] 101: side;

[0037] 110, 110': base material;

[0038] 111: first surface;

[0039] 112: core layer;

[0040] 113: second surface;

[0041] 114: a first conductive layer;

[0042] 116: second conductive layer;

[0043] 120: patterned conductive layer;

[0044] 130: stainless steel layer;

[0045] 131: upper surface;

[0046] 132: Central area;

[0047] 134: surrounding area;

[0048] 210: conductive block;

[0049] 220, 220', 220", 220a, 220b, 220c, 220f: metal layer;

[0050] 222: Part I;

[0051] 224: Part II;

[0052] 226: Part III;

[0053] 228: Part IV;

[0054] 230: insulation layer;

[0055] 240: First Copper Column;

[0056] 250: The second copper column;

[0057] 300a, 300b, 300c, 300d, 300f: chips;

[0058] 301a, 301b, 301c, 301d, 301f: back side;

[0059] 310a, 310b, 310c, 310d: electrodes;

[0060] 400a, 400b, 400c, 400d, 400f: circuit structure layer;

[0061] 410a, 410b, 410c, 410d, 410e1, 410e2: dielectric layers;

[0062] 420, 420e1, 420e2: patterned circuit layer;

[0063] 430: solder mask;

[0064] 432: Opening;

[0065] 440b, 440c, 440d: conductive vias;

[0066] 440e1: first conductive via;

[0067] 440e2: second conductive via;

[0068] 450, 600: Encapsulation colloid;

[0069] 500: surface treatment layer;

[0070] C1, C1': first groove;

[0071] C2, C2': second groove;

[0072] C3, C3': the third groove;

[0073] C4: fourth groove;

[0074] C5: fifth groove;

[0075] T1, T2, T3: through holes. DETAILED DESCRIPTION

[0076] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0077] Figures 1A to 1J FIG. 1 is a cross-sectional view of a method for manufacturing a chip packaging structure according to an embodiment of the present invention. Regarding the method for manufacturing a chip packaging structure according to this embodiment, first, please refer to Figure 1F , a carrier 100 having a plurality of conductive blocks 210 and at least one metal layer 220 (two metal layers 220 are schematically shown) is provided. For details, please refer to Figure 1A , a substrate 110 is provided, wherein the substrate 110 includes a core layer 112, a first conductive layer 114, and a second conductive layer 116. The first conductive layer 114 and the second conductive layer 116 are respectively disposed on two opposite surfaces of the core layer 112, wherein the material of the core layer 112 is, for example, a glass fiber resin substrate, and the material of the first conductive layer 114 and the second conductive layer 116 is, for example, a copper foil, and the substrate 110 can be regarded as a core substrate. In another embodiment, the material of the core layer 112 can also be, for example, a polyimide (PI) substrate, and the substrate 110 can be regarded as a flexible copper clad laminate (FCCL). In another embodiment not shown, the substrate can also be a glass substrate or a sheet or roll of stainless steel plate that has been electroplated with a titanium layer and a copper layer, which still belongs to the scope of protection of the present invention.

[0078] Next, please refer to Figure 1B , a patterned conductive layer 120 is formed on the first surface 111 and the second surface 113 of the substrate 110, respectively, wherein the patterned conductive layer 120 exposes a portion of the first surface 111 and a portion of the second surface 113 of the substrate 110, and defines a plurality of first grooves C1 and at least one second groove (two second grooves C2 are schematically shown). Here, the first groove C1 surrounds the second groove C2, and the diameter of the first groove C1 is smaller than the diameter of the second groove C2, wherein the depth of the second groove C2 is, for example, 70 micrometers to 100 micrometers, but is not limited thereto.

[0079] Next, please also refer to Figure 1B and Figure 1C, a stainless steel layer 130 is sputtered on the substrate 110, wherein the stainless steel layer 130 conformally covers the first groove C1, the second groove C2 and the patterned conductive layer 120, and defines a plurality of third grooves C3 and at least one fourth groove (two fourth grooves C4 are schematically shown). The material of the stainless steel layer 130 is, for example, SUS 304 or other suitable types, wherein the thickness of the stainless steel layer 130 is, for example, between 0.05 microns and 0.5 microns. In other words, the stainless steel layer 130 can be regarded as a stainless steel film. At this point, the manufacturing of the carrier 100 has been completed.

[0080] Next, please refer to Figure 1D , a conductive block 210 is formed on the carrier 100 , wherein the conductive block 210 fills the third groove C3 . Here, the surface of the conductive block 210 is flush with the stainless steel layer 130 .

[0081] Next, please refer to Figure 1E , an insulating layer 230 is formed on the stainless steel layer 130, wherein the stainless steel layer 130 has a central region 132 and a peripheral region 134 surrounding the central region 132, and the insulating layer 230 covers the peripheral region 134 of the stainless steel layer 130. The insulating layer 230 extends from the upper surface 131 of the stainless steel layer 130 and covers the side 101 of the carrier 100, and the insulating layer 230 exposes the central region 132 of the stainless steel layer 130.

[0082] Next, please also refer to Figure 1E and Figure 1F The metal layer 220 is formed to cover the stainless steel layer 130, the conductive block 210 and the fourth groove C4 to define at least one fifth groove C5 (two fifth grooves C5 are schematically shown). Here, the metal layer 220 can be bottom copper, and its thickness is, for example, 5 microns to 10 microns, but not limited thereto.

[0083] Next, please also refer to Figure 1F and Figure 1G , forming a plurality of first copper pillars 240 on the metal layer 220 corresponding to the conductive block 210. Here, the orthographic projection of the first copper pillar 240 on the metal layer 220 completely overlaps the orthographic projection of the conductive block 210 on the metal layer 220. Next, at least one chip (two chips 300a are schematically shown) is arranged in the fifth groove C5. Here, a plurality of electrodes 310a of the chip 300a are exposed to the outside, and the electrodes 310a are roughly cut to the metal layer 220, and a plurality of second copper pillars 250 are provided on the electrodes 310a of the chip 300a.

[0084] Next, please refer to Figure 1H, forming at least one circuit structure layer 400a on the carrier 100. In detail, a dielectric layer 410a is formed on the metal layer 220, wherein the dielectric layer 410a covers the metal layer 220, the chip 300a and the insulating layer 230, and covers the first copper pillar 240 and the second copper pillar 250. Here, the method of forming the dielectric layer 410a is, for example, through lamination, but is not limited thereto. Next, a patterned circuit layer 420 is formed on the dielectric layer 410a, wherein the patterned circuit layer 420 is electrically connected to the metal layer 220 through the first copper pillar 240, and the patterned circuit layer 420 is electrically connected to the electrode 310a of the chip 300a through the second copper pillar 250. Thereafter, a solder mask 430 is formed on the patterned circuit layer 420, wherein the solder mask 430 has a plurality of openings 432, and the openings 432 expose a portion of the patterned circuit layer 420. At this point, the manufacturing of the circuit structure layer 400a has been completed.

[0085] It is worth mentioning that in some embodiments not shown, a surface treatment layer may be further formed on the portion of the patterned circuit layer exposed by the opening to prevent oxidation of the patterned circuit layer, which may have better structural reliability and electrical performance, and this still falls within the scope of protection of the present invention.

[0086] Afterwards, please refer to Fig. 1I , the carrier 100 and the circuit structure layer 400 a are separated to expose the conductive blocks 210 and the metal layer 220 .

[0087] Finally, please refer to Figure 1J , the metal layer 220 exposed after separating the carrier 100 and the circuit structure layer 400a can retain the metal layer 220a that partially corresponds to the chip 300a, and the other metal layer 220 exposed outside the conductive block 210 can be completely removed. Afterwards, a packaging colloid 600 is formed to cover the dielectric layer 410a, the conductive block 210 and the metal layer 220a. At this point, the production of the chip packaging structure 10a has been completed. Since the metal layer 220a can be directly used as a shielding layer to prevent electromagnetic interference, compared with the conventional method of making a metal coating film on the outside of the packaging colloid by electroplating or sputtering after the packaging is completed, the chip packaging structure 10a of this embodiment can have a thinner packaging thickness and can reduce the process cost.

[0088] In short, in the manufacturing method of the chip packaging structure 10a of the present embodiment, the stainless steel layer 130 is formed on the substrate 110 of the carrier 100 by sputtering, so as to utilize the separation property between the stainless steel layer 130 and the electroplated copper layer (i.e., the metal layer) thereon to achieve the effect of separating the product board and the carrier 100. Furthermore, the stainless steel layer 130 formed by sputtering can have a smaller volume and weight than the conventional stainless steel plate, and the conventional glass fiber resin substrate can be used in operation, which is safer and simpler. In addition, when separating the carrier 100 and the circuit structure layer 400a, no cutting is required, so the carrier 100 can be reused, thereby effectively saving manufacturing costs.

[0089] It is worth mentioning that, in another embodiment, Fig. 1I After the step of separating the carrier 100 and the circuit structure layer 400a to expose the conductive block 210 and the metal layer 220, please refer to Figure 1K , the metal layer 220 exposed outside the conductive block 210 is removed by etching to expose at least the back side 301a of the chip 300a and the dielectric layer 410a of the circuit structure layer 400a. Then, a packaging gel 600 is formed to cover the dielectric layer 410a, the conductive block 210 and the back side 301a of the chip 300a. At this point, the chip packaging structure 10a' is completed.

[0090] FIG. 2A to FIG. 2D This is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. This embodiment uses the component numbers and some contents of the previous embodiment, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the previous embodiment, and this embodiment will not be repeated.

[0091] At Figure 1F After the step of forming the metal layer 220 to cover the stainless steel layer 130, the conductive block 210 and the fourth groove C4 to define the fifth groove C5, please also refer to Figure 1F and Figure 2A , at least one chip (two chips 300b are schematically shown) is disposed in the fifth groove C5. Here, a plurality of electrodes 310b of the chip 300b are exposed to the outside, and the electrodes 310b are approximately aligned with the metal layer 220. Here, the electrodes 310b of the chip 300b are, for example, copper electrodes, but are not limited thereto.

[0092] Next, please refer to Figure 2B, forming a circuit structure layer 400b on the carrier 100. First, a dielectric layer 410b is formed on the metal layer 220, wherein the dielectric layer 410b covers the metal layer 220, the chip 300b and the insulating layer 230. Here, the method of forming the dielectric layer 410b is, for example, lamination, and the material of the dielectric layer 410b is, for example, prepreg (PP), but not limited to this. Next, a plurality of through holes T1 are formed in the dielectric layer 410b, wherein the through holes T1 expose a portion of the metal layer 220 and the electrode 310b of the chip 300b. Here, the method of forming the through holes T1 is, for example, laser ablation, but not limited to this. Next, conductive through holes 440b are formed in the through holes T1 respectively, wherein the conductive through holes 440b fill the through holes T1 and connect the metal layer 220 and the electrode 310b of the chip 300b. Next, a patterned circuit layer 420 is formed on the dielectric layer 410b, wherein the patterned circuit layer 420 is electrically connected to the metal layer 220 and the electrode 310b through the conductive via 440b. A solder mask 430 is formed on the patterned circuit layer 420, wherein the solder mask 430 has a plurality of openings 432, and the openings 432 expose a portion of the patterned circuit layer 420. At this point, the production of the circuit structure layer 400b has been completed.

[0093] It is worth mentioning that in some embodiments not shown, a surface treatment layer may be further formed on the portion of the patterned circuit layer exposed by the opening to prevent oxidation of the patterned circuit layer, which may have better structural reliability and electrical performance, and this still falls within the scope of protection of the present invention.

[0094] Afterwards, please refer to Figure 2C , the carrier 100 and the circuit structure layer 400 b are separated to expose the conductive blocks 210 and the metal layer 220 .

[0095] Finally, please refer to Figure 2D , the metal layer 220 exposed after separating the carrier 100 and the circuit structure layer 400b can retain the metal layer 220b that partially corresponds to the chip 300b, and the other metal layer 220 exposed outside the conductive block 210 can be completely removed. Afterwards, a packaging colloid 600 is formed to cover the dielectric layer 410b, the conductive block 210 and the metal layer 220b. At this point, the production of the chip packaging structure 10b has been completed. Since the metal layer 220b can be directly used as a shielding layer to prevent electromagnetic interference, compared with the conventional method of making a metal coating film on the outside of the packaging colloid by electroplating or sputtering after the packaging is completed, the chip packaging structure 10b of this embodiment can have a thinner packaging thickness and reduce the process cost.

[0096] It is worth mentioning that, in another embodiment, Figure 2C After the step of separating the carrier 100 and the circuit structure layer 400b to expose the conductive block 210 and the metal layer 220, please refer to Figure 2E , the metal layer 220 exposed outside the conductive block 210 is removed by etching to expose at least the back side 301b of the chip 300b and the dielectric layer 410b of the circuit structure layer 400b. Afterwards, a packaging gel 600 is formed to cover the dielectric layer 410b, the conductive block 210 and the back side 301b of the chip 300b. Thus, the chip packaging structure 10b' is completed.

[0097] FIG. 3A to FIG. 3D This is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. This embodiment uses the component numbers and some contents of the previous embodiment, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the previous embodiment, and this embodiment will not be repeated.

[0098] At Figure 1F After the step of forming the metal layer 220 to cover the stainless steel layer 130, the conductive block 210 and the fourth groove C4 to define the fifth groove C5, please also refer to Figure 1F and Figure 3A , at least one chip (two chips 300c are schematically shown) is disposed in the fifth groove C5. Here, a plurality of electrodes 310c of the chip 300c are exposed to the outside, and the electrodes 310c are approximately aligned with the metal layer 220. Here, the electrodes 310c of the chip 300c are, for example, aluminum electrodes, but are not limited thereto.

[0099] Next, please refer to Figure 3B, forming a circuit structure layer 400c on the carrier 100. First, a dielectric layer 410c is formed on the metal layer 220, wherein the dielectric layer 410c covers the metal layer 220, the chip 300c and the insulating layer 230. Here, the method of forming the dielectric layer 410c is, for example, coating or lamination, and the material of the dielectric layer 410c is, for example, a photosensitive dielectric (Photo-ImageableDielectric, PID) material, but is not limited thereto. Then, the dielectric layer 410c is directly exposed and developed to form a plurality of through holes T2 in the dielectric layer 410c, wherein the through holes T2 expose a portion of the metal layer 220 and the electrode 310c of the chip 300c. Next, conductive through holes 440c are formed in the through holes T2 respectively, and titanium / copper is sputtered as the electroplated bottom copper, and the conductive through holes 440c are made of electroplated copper to fill the through holes T2 and connect the metal layer 220 and the electrode 310c of the chip 300c. Next, a patterned circuit layer 420 is formed on the dielectric layer 410c, wherein the patterned circuit layer 420 is electrically connected to the metal layer 220 and the electrode 310c through the conductive via 440c. A solder mask layer 430 is formed on the patterned circuit layer 420, wherein the solder mask layer 430 has a plurality of openings 432, and the openings 432 expose a portion of the patterned circuit layer 420. At this point, the production of the circuit structure layer 400c has been completed.

[0100] It is worth mentioning that in some embodiments not shown, a surface treatment layer may be further formed on the portion of the patterned circuit layer exposed by the opening to prevent oxidation of the patterned circuit layer, which may have better structural reliability and electrical performance, and this still falls within the scope of protection of the present invention.

[0101] Afterwards, please refer to Figure 3C , the carrier 100 and the circuit structure layer 400 c are separated to expose the conductive blocks 210 and the metal layer 220 .

[0102] Finally, please refer to Figure 3D , the metal layer 220 exposed after separating the carrier 100 and the circuit structure layer 400c can retain the metal layer 220c that partially corresponds to the chip 300c, and the other metal layer 220 exposed outside the conductive block 210 can be completely removed. Afterwards, a packaging colloid 600 is formed to cover the dielectric layer 410c, the conductive block 210 and the metal layer 220c. At this point, the production of the chip packaging structure 10c has been completed. Since the metal layer 220c can be directly used as a shielding layer to prevent electromagnetic interference, compared with the conventional method of making a metal coating film on the outside of the packaging colloid by electroplating or sputtering after the packaging is completed, the chip packaging structure 10c of this embodiment can have a thinner packaging thickness and can reduce the process cost.

[0103] It is worth mentioning that, in another embodiment, Figure 3CAfter the step of separating the carrier 100 and the circuit structure layer 400c to expose the conductive block 210 and the metal layer 220, please refer to Figure 3E , the metal layer 220 exposed outside the conductive block 210 is removed by etching to expose at least the back side 301c of the chip 300c and the dielectric layer 410c of the circuit structure layer 400c. Then, a packaging gel 600 is formed to cover the dielectric layer 410c, the conductive block 210 and the back side 301c of the chip 300c. Thus, the chip packaging structure 10c' is completed.

[0104] FIG. 4A to FIG. 4D The cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. This embodiment uses the component numbers and some contents of the previous embodiment, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the previous embodiment, and this embodiment will not be repeated.

[0105] At Figure 1D After the step of forming the conductive block 210 on the carrier 100, please also refer to Figure 1D and Figure 4A , forming a metal layer 220' to cover the stainless steel layer 130, the conductive block 210 and the fourth groove C4 to define a fifth groove C5. Next, at least one chip (two chips 300d are schematically shown) is disposed in the fifth groove C5. Here, a plurality of electrodes 310d of the chip 300d are exposed to the outside, and the electrodes 310d are approximately aligned with the metal layer 220.

[0106] Next, please refer to Figure 4B, forming a circuit structure layer 400d on the carrier 100. First, a dielectric layer 410d is formed on the metal layer 220, wherein the dielectric layer 410d covers the first portion 222 of the metal layer 220' and the chip 310d. Here, the method of forming the dielectric layer 410d is, for example, lamination, and the material of the dielectric layer 410d is, for example, prepreg (PP), but is not limited to this. Then, a plurality of through holes T3 are formed in the dielectric layer 410d, wherein the through holes T3 expose part of the first portion 212 of the metal layer 220' and the electrode 310d of the chip 300d. Then, conductive through holes 440d are formed in the through holes T3 respectively, wherein the conductive through holes 440d fill the through holes T3 and connect the metal layer 220 and the electrode 310d of the chip 300d. Next, a patterned circuit layer 420 is formed on the dielectric layer 410d, wherein the patterned circuit layer 420 is electrically connected to the metal layer 220' and the electrode 310d through the conductive via 440d. Afterwards, a packaging colloid 450 is formed on the patterned circuit layer 420 and the second portion 224 of the metal layer 220', wherein the packaging colloid 450 covers the dielectric layer 410d, the patterned circuit layer 420 and the second portion 224 of the metal layer 220. At this point, the production of the circuit structure layer 400d has been completed.

[0107] Afterwards, please refer to Figure 4C , separate the carrier 100 and the circuit structure layer 400d to expose the conductive block 210 and the metal layer 220. Figure 4C and Figure 4D , the second portion 224 and part of the first portion 222 of the metal layer 220 are removed by etching to expose the dielectric layer 410d and the packaging colloid 450. The third portion 226 of the remaining metal layer 220' covers the back side 310d of the chip 330d, and the fourth portion 228 of the remaining metal layer 220' is located between the conductive block and the dielectric layer 410d. Afterwards, a surface treatment layer 500 is formed on the surface of the conductive block 210 and on the third portion 226 of the remaining metal layer 220', wherein the material of the surface treatment layer 500 is, for example, tin, but not limited thereto. At this point, the production of the chip packaging structure 10d has been completed.

[0108] Figure 5 The cross-sectional diagram of a chip packaging structure of an embodiment of the present invention is shown in FIG. This embodiment uses the component numbers and some contents of the previous embodiment, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the previous embodiment, and this embodiment will not be repeated.

[0109] Please also refer to Figure 4D as well as Figure 5 The chip packaging structure 10e of this embodiment is Figure 4DThe chip packaging structure 10d' of the present embodiment is similar to the chip packaging structure 10d' of the present embodiment, and the difference between the two is that the circuit structure layer 400 of the chip packaging structure 10e of the present embodiment is composed of two dielectric layers 410e1, 410e2, two patterned circuit layers 420e1, 420e2, a plurality of first conductive vias 440e1, a plurality of second conductive vias 440e2 and a packaging colloid 450. The patterned circuit layer 420e1 is electrically connected to the electrode 310d of the chip 310d through the first conductive vias 440e1, and the patterned circuit layer 420e1 is electrically connected to the conductive block 210 through the first conductive vias 440e1 and the fourth portion 228 of the metal layer 220'. The patterned circuit layer 420e2 is electrically connected to the patterned circuit layer 420e1 through the second conductive vias 440e2. The packaging colloid 450 covers the dielectric layers 410e1, 410e2 and the patterned circuit layer 420e2.

[0110] FIG. 6A to FIG. 6B This is a cross-sectional schematic diagram of a partial step of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. This embodiment uses the component numbers and some contents of the previous embodiment, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the previous embodiment, and this embodiment will not be repeated.

[0111] Please refer to Fig. 6A , providing a carrier 100' having a metal layer 220' formed thereon. The carrier 100' comprises a substrate 110' and a stainless steel layer 130 sputtered on the substrate 110'. The substrate 110' has at least one first groove C1', and the stainless steel layer 130 conformally covers the first groove C1' to define at least one second groove C2'. The metal layer 220' covers the stainless steel layer 130 to define at least one third groove C3'. Next, proceed to Figure 1F The next step is to configure the chip 300f (please refer to Figure 6B ) in the third groove C3' (please refer to Fig. 6A ) to form a circuit structure layer 400f (please refer to Figure 6B ) on carrier board 100' (please refer to Fig. 6A ) and separate carrier 100' (please refer to Fig. 6A ) and the circuit structure layer 400f (please refer to Figure 6B ) to expose the metal layer 220 (please refer to Figure 6B ).

[0112] Next, the metal layer 220" is exposed after the carrier 100' and the circuit structure layer 400f are separated. Figure 6B, the metal layer 220f partially corresponding to the chip 300f can be retained, and the other metal layers 220" can be completely removed. Afterwards, a packaging colloid 600 is formed to cover the circuit structure layer 400f and the metal layer 220f. At this point, the chip packaging structure 10f has been completed. Since the metal layer 220f can be directly used as a shielding layer to prevent electromagnetic interference, compared with the conventional method of making a metal coating film on the outside of the packaging colloid by electroplating or sputtering after the packaging is completed, the chip packaging structure 10f of this embodiment can have a thinner packaging thickness and reduce the process cost.

[0113] It is worth mentioning that, in another embodiment, Figure 6B After the step of separating the carrier 100" and the circuit structure layer 400f to expose the metal layer 220", please refer to Figure 6C The metal layer 220' is removed by etching to expose at least the back side 301f of the chip 300f and the circuit structure layer 400f. Then, a packaging colloid 600 is formed to cover the circuit structure layer 400f and the back side 301f of the chip 300f. Thus, the chip packaging structure 10f' is completed.

[0114] In summary, in the manufacturing method of the chip packaging structure of the present invention, a stainless steel layer is formed on the substrate of the carrier by sputtering, so as to utilize the separation property between the stainless steel layer and the electroplated copper layer (i.e., the metal layer) thereon to achieve the effect of separating the product board and the carrier. Furthermore, the stainless steel layer formed by sputtering can have a smaller volume and weight than the conventional stainless steel plate, and the conventional glass fiber resin substrate can be used in operation, which is safer and simpler. In addition, when separating the carrier and the circuit structure layer, no cutting is required, so the carrier can be reused, thereby effectively saving manufacturing costs. In addition, the metal layer exposed after separating the carrier and the circuit structure layer can be directly used as a shielding layer to prevent electromagnetic interference. Compared with the conventional method of making a metal coating on the outside of the packaging colloid by electroplating or sputtering after the packaging is completed, the chip packaging structure of the present invention can have a thinner packaging thickness and can reduce the process cost.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a chip packaging structure, characterized in that: include: A carrier having a plurality of conductive blocks and at least one metal layer formed thereon is provided, the carrier comprising a substrate and a stainless steel layer sputtered on the substrate, the substrate having a plurality of first grooves and at least one second groove surrounding the plurality of first grooves, the stainless steel layer conformally covers the plurality of first grooves and the at least one second groove to define a plurality of third grooves and at least one fourth groove, the plurality of conductive blocks fill the plurality of third grooves, and the at least one metal layer covers the stainless steel layer, the plurality of conductive blocks and the at least one fourth groove to define at least one fifth groove; Disposing at least one chip in the at least one fifth groove; forming at least one circuit structure layer on the carrier, wherein the patterned circuit layer of the at least one circuit structure layer is electrically connected to a plurality of electrodes of the at least one chip; as well as Separating the carrier and the at least one circuit structure layer to expose the plurality of conductive blocks and the at least one metal layer; as well as The at least one metal layer partially corresponding to the at least one chip portion is retained, and the other at least one metal layer exposed outside the plurality of conductive blocks is completely removed.

2. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The carrier includes a sheet-shaped or rolled core substrate, a sheet-shaped or rolled stainless steel plate, a soft copper foil substrate or a glass substrate plated with a titanium layer and a copper layer.

3. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The stainless steel layer has a central area and a peripheral area surrounding the central area. Before forming the at least one metal layer on the carrier, the method further includes: An insulating layer is formed to cover the peripheral area of ​​the stainless steel layer, wherein the insulating layer extends from the upper surface of the stainless steel layer and covers the side of the carrier, and the insulating layer exposes the central area.

4. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: Also includes: Before disposing the at least one chip in the at least one fifth groove of the carrier, forming a plurality of first copper pillars on the at least one metal layer corresponding to the plurality of conductive blocks; as well as Before disposing the at least one chip in the at least one fifth cavity of the carrier, a plurality of second copper pillars are formed on the plurality of electrodes of the at least one chip.

5. The method for manufacturing a chip packaging structure according to claim 4, characterized in that: The step of forming the at least one circuit structure layer on the carrier includes: Forming a dielectric layer on the at least one metal layer, wherein the dielectric layer covers the at least one metal layer and the at least one chip, and encapsulates the plurality of first copper pillars and the plurality of second copper pillars; forming a patterned circuit layer on the dielectric layer, wherein the patterned circuit layer is electrically connected to the at least one metal layer through the plurality of first copper pillars, and the patterned circuit layer is electrically connected to the plurality of electrodes of the at least one chip through the plurality of second copper pillars; and A solder mask is formed on the patterned circuit layer, wherein the solder mask has a plurality of openings, and the plurality of openings expose a portion of the patterned circuit layer.

6. The method for manufacturing a chip packaging structure according to claim 1, characterized in that: The step of forming the at least one circuit structure layer on the carrier includes: forming a dielectric layer on the at least one metal layer, wherein the dielectric layer covers the at least one metal layer and the at least one chip; Forming a plurality of through holes in the dielectric layer, wherein the plurality of through holes expose a portion of the at least one metal layer and the plurality of electrodes of the at least one chip; forming the plurality of conductive vias in the plurality of through holes respectively; forming a patterned circuit layer on the dielectric layer, wherein the patterned circuit layer is electrically connected to the at least one metal layer and the plurality of electrodes through the plurality of conductive vias; and A solder mask is formed on the patterned circuit layer, wherein the solder mask has a plurality of openings, and the plurality of openings expose a portion of the patterned circuit layer.

7. The method for manufacturing a chip packaging structure according to claim 6, characterized in that: The electrodes of the at least one chip include copper electrodes or aluminum electrodes, and the material of the dielectric layer includes photosensitive dielectric material or prepreg.

8. A method for manufacturing a chip packaging structure, characterized in that: include: A carrier having a plurality of conductive blocks and at least one metal layer formed thereon is provided, the carrier comprising a substrate and a stainless steel layer sputtered on the substrate, the substrate having a plurality of first grooves and at least one second groove surrounding the plurality of first grooves, the stainless steel layer conformally covers the plurality of first grooves and the at least one second groove to define a plurality of third grooves and at least one fourth groove, the plurality of conductive blocks fill the plurality of third grooves, and the at least one metal layer covers the stainless steel layer, the plurality of conductive blocks and the at least one fourth groove to define at least one fifth groove; Disposing at least one chip in the at least one fifth groove; forming at least one circuit structure layer on the carrier, wherein the patterned circuit layer of the at least one circuit structure layer is electrically connected to a plurality of electrodes of the at least one chip; Separating the carrier and the at least one circuit structure layer to expose the plurality of conductive blocks and the at least one metal layer; as well as The at least one metal layer is removed to expose at least the back side of the at least one chip and a portion of the at least one circuit structure layer.

9. A method for manufacturing a chip packaging structure, characterized in that: include: A carrier having a plurality of conductive blocks and at least one metal layer formed thereon is provided, the carrier comprising a substrate and a stainless steel layer sputtered on the substrate, the substrate having a plurality of first grooves and at least one second groove surrounding the plurality of first grooves, the stainless steel layer conformally covers the plurality of first grooves and the at least one second groove to define a plurality of third grooves and at least one fourth groove, the plurality of conductive blocks fill the plurality of third grooves, and the at least one metal layer covers the stainless steel layer, the plurality of conductive blocks and the at least one fourth groove to define at least one fifth groove; Disposing at least one chip in the at least one fifth groove; At least one circuit structure layer is formed on the carrier, wherein the patterned circuit layer of the at least one circuit structure layer is electrically connected to a plurality of electrodes of the at least one chip, and the step of forming the at least one circuit structure layer on the carrier includes: forming a dielectric layer on the at least one metal layer, wherein the dielectric layer covers a first portion of the at least one metal layer and the at least one chip; forming a plurality of through holes in the dielectric layer, wherein the plurality of through holes expose a portion of the first portion of the at least one metal layer and the plurality of electrodes of the at least one chip; forming the plurality of conductive vias in the plurality of through holes respectively; forming a patterned circuit layer on the dielectric layer, wherein the patterned circuit layer is electrically connected to the at least one metal layer and the plurality of electrodes through the plurality of conductive vias; and forming a packaging colloid on the patterned circuit layer and the second portion of the at least one metal layer; Separating the carrier and the at least one circuit structure layer to expose the plurality of conductive blocks and the at least one metal layer; and removing the second portion and part of the first portion of the at least one metal layer to expose the dielectric layer and the encapsulation colloid, wherein a third portion of the at least one metal layer remaining covers the back side of the at least one chip, and a fourth portion of the at least one metal layer remaining is located between the plurality of conductive blocks and the dielectric layer; and A surface treatment layer is formed on the surfaces of the plurality of conductive blocks and on the third portion of the remaining at least one metal layer.

10. A method for manufacturing a chip packaging structure, characterized in that: include: A carrier having at least one metal layer formed thereon is provided, the carrier comprising a substrate and a stainless steel layer sputtered on the substrate, the substrate having at least one first groove, the stainless steel layer conformally covering the at least one first groove to define at least one second groove, and the at least one metal layer covering the stainless steel layer to define at least one third groove; Disposing at least one chip in the at least one third groove; forming at least one circuit structure layer on the carrier, wherein the patterned circuit layer of the at least one circuit structure layer is electrically connected to a plurality of electrodes of the at least one chip; Separating the carrier board and the at least one circuit structure layer to expose the at least one metal layer; as well as The at least one metal layer is removed to expose at least the back side of the at least one chip and a portion of the at least one circuit structure layer.

11. A method for manufacturing a chip packaging structure, characterized in that: include: A carrier having at least one metal layer formed thereon is provided, the carrier comprising a substrate and a stainless steel layer sputtered on the substrate, the substrate having at least one first groove, the stainless steel layer conformally covering the at least one first groove to define at least one second groove, and the at least one metal layer covering the stainless steel layer to define at least one third groove; Disposing at least one chip in the at least one third groove; forming at least one circuit structure layer on the carrier, wherein the patterned circuit layer of the at least one circuit structure layer is electrically connected to a plurality of electrodes of the at least one chip; Separating the carrier board and the at least one circuit structure layer to expose the at least one metal layer; as well as The at least one metal layer partially corresponding to the at least one chip portion is retained, and the rest of the at least one metal layer is completely removed.

12. A chip packaging structure manufactured by the method for manufacturing a chip packaging structure according to claim 1, characterized in that: include: chip; A circuit structure layer, comprising at least one dielectric layer and at least one patterned circuit layer, wherein the at least one patterned circuit layer is electrically connected to a plurality of electrodes of the chip; a metal layer, a portion of which covers the back side of the chip; as well as A plurality of conductive blocks are electrically connected to the at least one patterned circuit layer through another portion of the metal layer.

13. The chip packaging structure according to claim 12, characterized in that: Also includes: The packaging colloid covers the at least one dielectric layer, the plurality of conductive blocks and the metal layer.

14. The chip packaging structure according to claim 12, characterized in that: The at least one dielectric layer includes a first dielectric layer and a second dielectric layer, the at least one patterned circuit layer includes a first patterned circuit layer and a second patterned circuit layer, the circuit structure layer also includes a plurality of first conductive vias, a plurality of second conductive vias and a packaging colloid, wherein the first patterned circuit layer is electrically connected to the plurality of electrodes of the chip through the plurality of first conductive vias, and the first patterned circuit layer is electrically connected to the plurality of conductive blocks through the plurality of first conductive vias and the other portion of the metal layer, the second patterned circuit layer is electrically connected to the first patterned circuit layer through the plurality of second conductive vias, and the packaging colloid covers the first dielectric layer, the second dielectric layer and the second patterned circuit layer.

15. The chip packaging structure according to claim 14, characterized in that: Also includes: A surface treatment layer covers the metal layer.

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