Semiconductor device and method of manufacturing semiconductor device

Abstract

Semiconductor device and method of manufacturing semiconductor device. In one example, an electronic assembly includes a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor device includes: a substrate, the substrate including a top surface and a conductive structure; an electronic component, the electronic component is above the top surface of the substrate; a dielectric material, the dielectric material is above the top surface of the substrate and contacts one side of the electronic component; a substrate contact, the substrate contact is at one end of the substrate and is not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate contact; and an interconnect, the interconnect electrically coupled to the conductive structure at the substrate contact of the first semiconductor device and the conductive structure at the substrate contact of the second semiconductor device. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to semiconductor devices and methods for manufacturing semiconductor devices. Background Art

[0002] Existing semiconductor packages and methods for forming semiconductor packages have deficiencies, such as resulting in excessive cost, reduced reliability, relatively low performance, or package size that is too large. Additional limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the accompanying drawings. Summary of the invention

[0003] According to an aspect of the present invention, an electronic assembly includes: a first semiconductor device and a second semiconductor device, wherein each of the first semiconductor device and the second semiconductor device includes: a substrate, the substrate including a top surface and a conductive structure; an electronic component, the electronic component is above the top surface of the substrate; a dielectric material, the dielectric material is above the top surface of the substrate and contacts one side of the electronic component; a substrate contact, the substrate contact is at one end of the substrate and is not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate contact; and an interconnection, the interconnection electrically coupled to the conductive structure at the substrate contact of the first semiconductor device and the conductive structure at the substrate contact of the second semiconductor device. The electronic assembly further includes a base structure, the base structure including a top surface, wherein the first semiconductor device is above the top surface of the base structure, and the second semiconductor device is above the top surface of the base structure. In the electronic assembly, the interconnection includes a bonding wire. In the electronic assembly, the interconnection includes a wire clip. In an electronic assembly, the second semiconductor device is inverted relative to the first semiconductor device, and the substrate tab of the second semiconductor device is above the substrate tab of the first semiconductor device. In the electronic assembly, the interconnect includes solder. In the electronic assembly, the interconnect includes a copper pillar. In the electronic assembly, the interconnect includes an interconnect substrate. In the electronic assembly, the interconnect includes a flexible substrate. In the electronic assembly, the interconnect includes a lead frame. In the electronic assembly: the base structure includes a first support structure, a second support structure, and an intermediate structure between the first support structure and the second support structure, the first semiconductor device is coupled to a top surface of the first support structure and the second semiconductor device is coupled to a top surface of the second support structure, and the second semiconductor device is inverted relative to the first semiconductor device, wherein the substrate tab of the second semiconductor device is above the substrate tab of the second semiconductor device.

[0004] According to another aspect of the present invention, a method includes: providing a first electronic component on a top surface of a first substrate, wherein the first substrate includes a first conductive structure coupled to the first electronic component, the first substrate has a first substrate contact on the top surface, and the first conductive structure is exposed at the first substrate contact; and providing a first dielectric structure on the top surface of the first substrate, wherein the first dielectric structure contacts a side of the first electronic component and the first substrate contact is not covered by the first dielectric structure. The method further includes providing the first substrate on a carrier before providing the first electronic component on the top surface of the first substrate, and removing the carrier after providing the first dielectric structure on the top surface of the first substrate. The method further includes: providing a second electronic component over a top surface of a second substrate, wherein the second substrate includes a second conductive structure coupled to the second electronic component, the second substrate has a second substrate tab on the top surface, and the second conductive structure is exposed at the second substrate tab; providing a second dielectric structure over the top surface of the second substrate, wherein the second dielectric structure contacts a side of the second electronic component and the second substrate tab is not covered by the second dielectric structure; and coupling the first substrate tab of the first substrate to the second substrate tab of the second substrate.

[0005] According to yet another aspect of the present invention, a method includes: providing a first semiconductor device and a second semiconductor device, wherein providing each of the first semiconductor device and the second semiconductor device includes: providing a substrate including a top surface and a conductive structure; providing an electronic component on the top surface of the substrate; providing a substrate contact at one end of the substrate, wherein the conductive structure of the substrate is exposed at the substrate contact; and providing an interconnect, the interconnect being electrically coupled to the conductive structure at the substrate contact of the first semiconductor device and the conductive structure at the substrate contact of the second semiconductor device. In the method, the interconnect includes a bonding wire. In the method, the interconnect includes a wire clip. In the method, the interconnect includes solder. In the method, the interconnect includes a copper pillar. The method further includes providing a dielectric material, the dielectric material being on the top surface of the substrate and contacting a side of the electronic component, wherein the dielectric material does not cover the substrate contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0007] Figures 2A to 2D A cross-sectional view of an example method for fabricating an example semiconductor device is shown.

[0008] Figures 3A to 3F A cross-sectional view of an example method for fabricating an example semiconductor device is shown.

[0009] Figure 4 A cross-sectional view of an example electronic assembly is shown.

[0010] Figures 5A to 5D A cross-sectional view of an example method for manufacturing an example electronic assembly is shown.

[0011] Figure 6 A cross-sectional view of an example electronic assembly is shown.

[0012] Fig. 7A and 7B A cross-sectional view of an example method for manufacturing an example electronic assembly is shown.

[0013] Figure 8 A cross-sectional view of an example electronic assembly is shown.

[0014] Figures 9A to 9C A cross-sectional view of an example method for manufacturing an example electronic assembly is shown.

[0015] Fig.10 A cross-sectional view of an example electronic assembly is shown.

[0016] Fig.11A and 11B A cross-sectional view of an example method for manufacturing an example electronic assembly is shown.

[0017] Fig.12 A cross-sectional view of an example electronic assembly is shown.

[0018] Figures 13A to 13D A cross-sectional view of an example method for manufacturing an example electronic assembly is shown.

[0019] Fig.14 A cross-sectional view of an example electronic assembly is shown.

[0020] Figures 15A to 15E A cross-sectional view of an example method for manufacturing an example electronic assembly is shown. DETAILED DESCRIPTION

[0021] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0022] The accompanying drawings illustrate the overall construction method, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, the elements in the accompanying drawings are not necessarily drawn to scale. For example, the size of some of the elements in the accompanying drawings may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different drawings indicate the same elements.

[0023] The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. The terms "comprises", "comprising", "includes" or "including" are "open" terms and specify the presence of stated features, but do not exclude the presence or addition of one or more other features. The terms "first", "second", etc. can be used in this article to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, for example, without departing from the teachings of the present disclosure, the first element discussed in the present disclosure can be referred to as the second element.

[0024] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly connected to element B through an intermediate element C. Similarly, the terms "above" or "on" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements.

[0025] In one example, an electronic assembly includes a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor device includes: a substrate including a top surface and a conductive structure; an electronic component located above the top surface of the substrate; a dielectric material located above the top surface of the substrate and contacting a side of the electronic component; a substrate tab located at one end of the substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab; and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device.

[0026] In another example, a method for manufacturing a semiconductor device or an assembly of semiconductor devices includes: providing a first electronic component over a top surface of a first substrate, wherein the first substrate includes a first conductive structure coupled to the first electronic component, the first substrate has a first substrate contact on the top surface, and the first conductive structure is exposed at the first substrate contact; and providing a first dielectric structure over the top surface of the first substrate, wherein the first dielectric structure contacts a side of the first electronic component and the first substrate contact is not covered by the first dielectric structure.

[0027] In another example, a method of manufacturing a semiconductor device or an assembly of semiconductor devices includes providing a first semiconductor device and a second semiconductor device. Providing each of the first semiconductor device and the second semiconductor device includes: providing a substrate including a top surface and a conductive structure; providing an electronic component on the top surface of the substrate; providing a substrate tab at one end of the substrate, wherein the conductive structure of the substrate is exposed at the substrate tab; and providing an interconnect, the interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device.

[0028] The present disclosure includes other examples. Such examples may be found in the drawings, claims or description of the present disclosure.

[0029] Figure 1 A cross-sectional view of an example semiconductor device 100 is shown. Figure 1 In the example shown, the semiconductor device 100 may include a substrate 110 , an electronic component 121 , 122 or 123 , a dielectric 130 , and an external interconnect 150 .

[0030] In some examples, the substrate 110 may include a dielectric structure 110a, a conductive structure 110b, and a substrate tab 111. The substrate 110 may include a top surface 110c and a bottom surface 110d opposite the top surface 110c. In some examples, the dielectric material 130 may be above the top surface 110c of the substrate 110 and may contact one side of one or more of the electronic components 121, 122, or 123. One or more electronic components 121, 122, or 123 may be above the top surface of the substrate 110. The substrate 110, the dielectric 130, and the external interconnect 150 may be referred to as a semiconductor package or package and may protect the electronic components 121, 122, or 123 from external elements or environmental exposure. In some examples, the semiconductor package may provide an electrical connection between an external component and the electronic component 121, 122, or 123. In some examples, the substrate tab 111 may be at one end of the substrate 110 and not covered by the dielectric material 130. The conductive structure 110 b may be exposed at the substrate tab 111 .

[0031] Figures 2A to 2D A cross-sectional view of an example method for fabricating a semiconductor device 100 is shown. Figure 2A A cross-sectional view of a semiconductor device 100 at an early stage of fabrication is shown.

[0032] exist Figure 2A In the example shown, the substrate 110 may include a top surface 110c and a bottom surface 110d opposite to the top surface 110c, and the bottom surface 110d of the substrate 110 may be coupled to the surface of the carrier 1. Although a single substrate 110 is shown, this is not a limitation of the present disclosure. In other examples, a plurality of substrates 110 may be arranged on the carrier 1 to be spaced apart from each other in a row or column direction.

[0033] The substrate 110 may include a dielectric structure 110a, a conductive structure 110b, and a substrate tab 111. The substrate tab 111 may include a conductive structure 110b exposed at a top surface 110c of the substrate 110. The substrate tab 111 may be located at or near at least one side or one end of the substrate 110. In addition, the substrate tab 111 may be exposed to form an electrical connection path between the semiconductor device 100 and an external component or another semiconductor device.

[0034] In some examples, substrate 110 can be a preformed substrate. The preformed substrate can be manufactured before being attached to an electronic component or electronic device and can include a dielectric layer between corresponding conductive layers. The conductive layer can include copper and can be formed or provided using an electroplating process. The dielectric layer can be a relatively thick non-light definable layer that can be attached in the form of a preformed film rather than in the form of a liquid and can include a resin with fillers such as strands, fabrics or other inorganic particles for rigid or structural support. Since the dielectric layer is non-light definable, features such as through holes or openings can be formed or provided by using a drill or laser. In some examples, the dielectric layer can include a prepreg material or an Ajinomoto Buildup Film (ABF). The preformed substrate can include a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric layer and the conductive layer can be formed or provided on the permanent core structure. In some examples, the preformed substrate may be a coreless substrate and the permanent core structure may be omitted, and the dielectric and conductive layers may be formed or provided on a sacrificial carrier that is removed after the dielectric and conductive layers are formed and before being attached to the electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminate substrate. Such a preformed substrate may be formed or provided by a semi-additive process or a modified semi-additive process.

[0035] In some instances, substrate 110 may be a redistribution layer (“RDL”) substrate. The RDL substrate may include one or more dielectric layers and one or more conductive redistribution layers, which may: (a) be formed or provided layer by layer on an electronic component to which the RDL substrate is to be electrically coupled; or (b) be formed or provided layer by layer on a carrier, which may be completely or at least partially removed after the electronic component and the RDL substrate are coupled together. The RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer in a wafer-level process or layer by layer as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate may be formed or provided in an additive stacking process, which may include one or more dielectric layers alternately stacked with one or more conductive layers defining corresponding conductive redistribution patterns or traces, which are configured to collectively: (a) fan the electrical traces out of the footprint of the electronic component; or (b) fan the electrical traces into the footprint of the electronic component. The conductive pattern can be formed or provided using a plating process, such as an electroplating process or an electroless plating process. The conductive pattern may include a conductive material, such as copper or other plateable metals. A photopatterning process, such as a photolithography process and a photoresist material, may be used to form a photolithography mask to make the location of the conductive pattern. The dielectric layer of the RDL substrate may be patterned using a photopatterning process that may include a photolithography mask, through which light is exposed to the desired features of the light pattern, such as through holes in the dielectric layer. Therefore, the dielectric layer may be made of a light-definable organic dielectric material, such as polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO). Such dielectric materials may be spin-coated or otherwise applied in liquid form rather than attached in the form of a preformed film. In order to allow the desired light-definable features to be properly formed, such light-definable dielectric materials may omit structural reinforcing agents or may be free of fillers, and may not have strands, fabrics or other particles that may interfere with the light from the light patterning process. In some instances, such filler-free properties of filler-free dielectric materials can allow the thickness of the resulting dielectric layer to be reduced. Although the photo-definable dielectric material described above can be an organic material, in some instances, the dielectric material of the RDL substrate can include one or more inorganic dielectric layers. Some examples of one or more inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON). The one or more inorganic dielectric layers can be formed or provided by growing the inorganic dielectric layer using an oxidation or nitridation process rather than using a photo-defined organic dielectric material. Such inorganic dielectric layers can be filler-free, without strands, fabrics, or other different inorganic particles. In some instances, the RDL substrate can omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates can be referred to as coreless substrates.

[0036] In some instances, substrate 110 may include or be referred to as a preformed substrate, an RDL substrate, a printed circuit board (PCB), a cavity substrate, a printed wiring board, a multilayer substrate, a through-hole substrate, a rigid substrate, a flexible substrate, a glass epoxy substrate, a polyimide substrate, a polyester substrate, a molded plastic substrate, a ceramic substrate, an etched foil process substrate, an additive process substrate, a build-up substrate, or a molded lead frame.

[0037] In some examples, the dielectric structure 110a may have a flat top surface and bottom surface. The top surface and bottom surface of the dielectric structure 110a may be parallel to the top surface 110c and the bottom surface 110d of the substrate 110. In some examples, the dielectric structure 110a may be referred to as a dielectric layer or a core layer. The dielectric structure 110a may include one or more dielectric layers. In some examples, the dielectric structure 110a may include epoxy resin, phenolic resin, glass epoxy resin, polyimide, polyester, epoxy molding compound, ceramic, bismaleimide triazine (BT) or FR4. In some examples, the thickness of the dielectric structure 110a may be in the range of about 0.1 millimeter (mm) to about 10 mm. The dielectric structure 110a may be used to prevent warping or maintain the flatness of the substrate 110.

[0038] Conductive structure 110b can be coupled to dielectric structure 110a. In some instances, conductive structure 110b can be referred to as a conductor, a conductive material, a conductive via, a circuit pattern, a trace, or a wiring pattern. In some instances, a portion of conductive structure 110b can be exposed for electrical coupling to electronic components 121, 122, or 123 or external interconnects 150. In some instances, conductive structure 110b can be electrically coupled to electronic components 121, 122, or 123 or external interconnects 150 through conductors, conductive materials, conductive vias, substrate lands, conductive pads, substrate pads, wiring pads, connection pads, micro pads, or under-bump metal (UBM). In some instances, conductive structure 110b may include copper, aluminum, iron, nickel, gold, silver, palladium, or tin.

[0039] In some examples, substrate tab 111 may be exposed at or near top surface 110c of substrate 110. Substrate tab 111 may include conductive structure 110b exposed at or near one side of substrate 110. In some examples, substrate tab 111 may include conductive structure 110b bent upward and exposed. In some examples, substrate tab 111 may provide an exposed electrical connection path.

[0040] In some examples, the carrier 1 may include a flat structure. The carrier 1 may be referred to as a plate, a wafer, a panel, a semiconductor carrier, or a strip. In some examples, the carrier 1 may include steel, stainless steel, aluminum, copper, ceramic, glass, silicon, metal, alloy, or semiconductor material. The thickness of the carrier 1 may be in the range of about 1 mm to about 1.5 mm and the width may be in the range of about 200 mm to about 510 mm.

[0041] In some examples, carrier 1 may support multiple components during fabrication of semiconductor device 100. For example, carrier 1 may provide a base structure for supporting substrate 110, electronic components 121, 122, or 123, and dielectric 130. In some examples, electronic assembly 10 may include a base structure including a top surface, wherein semiconductor devices 100 and 200 may be located above the top surface of the base structure.

[0042] In some examples, the bonding layer 2 can be formed or provided on the top surface of the carrier 1. Examples for forming the bonding layer 2 can include using: coating processes such as spin coating, blade coating, casting, brush coating, spray coating, slot die coating, curtain coating, slide coating, or knife over edge coating; printing processes such as screen printing, pad printing, gravure printing, flexographic coating, or offset printing; inkjet printing processes with intermediate features of coating and printing; or direct attachment of adhesive films or tapes. The substrate 110 can be formed or provided on the bonding layer 2.

[0043] The bonding layer 2 may be referred to as a temporary adhesive film or a temporary adhesive tape. The bonding layer 2 may include a thermal release tape or an ultraviolet (UV) release tape. In some instances, the bonding strength of the bonding layer 2 may be reduced by heat or UV radiation. In some instances, the temporary bonding layer 2 may be removed from the substrate 110 or the carrier 1 in a later manufacturing stage.

[0044] Figure 2B 1 shows a cross-sectional view of a semiconductor device 100 in a later stage of manufacturing. Figure 2B In the example shown, electronic components 121 and 122 may be provided on or above surface 110c of substrate 110, and electronic component 123 may be on electronic component 122. In some examples, electronic components 121, 122, or 123 may be electrically coupled to conductive structure 110b of substrate 110.

[0045] In some examples, a pick and place device may pick up electronic components 121, 122, or 123, place electronic components 121 and 122 on substrate 110, and place component 123 on component 122. In some examples, mass reflow, thermal compression, or laser assisted bonding (LAB) processes may be used to attach components 121, 122, or 123 to each other and to substrate 110 or to electrically couple substrate 110 to components 121, 122, or 123.

[0046] In some instances, electronic components 121, 122, or 123 may include a semiconductor die or a semiconductor chip. In some instances, electronic components 121, 122, or 123 may include a semiconductor material, such as silicon (Si). Electronic components 121, 122, or 123 may include passive electronic circuit elements (not shown) or active electronic circuit elements (not shown), such as transistors. In some instances, electronic components 121, 122, or 123 may include a dedicated integrated circuit, a logic die, a microcontroller unit, a memory, a digital signal processor, a network processor, a power management unit, an audio processor, a radio frequency (RF) circuit, or a wireless baseband system-on-chip processor.

[0047] In some examples, electronic component 122 may include a through silicon via (TSV) interposer and may provide a conductive path between electronic component 123 and substrate 110. The thickness of each of electronic component 121, 122, or 123 may be in a range of about 50 μm to about 780 μm. The width of each of electronic component 121, 122, or 123 may be in a range of about 3 mm to about 10 mm.

[0048] In some examples, the electronic component 121, 122 or 123 may include a passive device. In some examples, the electronic component 121, 122 or 123 may include a resistor, a capacitor, an inductor or a connector. In addition, the electronic component 121, 122 or 123 may be electrically coupled to the conductive structure 110b of the substrate 110.

[0049] In some examples, the electronic components 121, 122, or 123 may include an electrical interconnect, such as an interconnect 125. In some examples, the interconnect 125 may electrically couple the die terminals of the electronic components 121, 122, or 123 to the substrate 110. In some examples, the interconnect 125 may include a wafer bump, a pillar wafer bump, a copper pillar wafer bump, a copper pillar wafer bump including a solder tip formed or provided on the outer end of the copper pillar, a copper stud bump, a gold stud bump, or a solder wafer bump. In some examples, the interconnect 125 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), aluminum, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu.

[0050] Figure 2C 1 shows a cross-sectional view of a semiconductor device 100 in a later stage of manufacturing. Figure 2C In the example shown, dielectric 130 may be formed or provided on or over top surface 110c of substrate 110 and on components 121, 122, or 123. In some examples, dielectric 130 may contact top surface 110c of substrate 110 and top, bottom, or side surfaces of components 121, 122, or 123 to encapsulate electronic components 121, 122, or 123. In some examples, dielectric 130 may be referred to as an encapsulant.

[0051] In some examples, the encapsulant 130 may be formed or provided to expose the substrate tab 111, wherein the substrate tab 111 is not covered by the encapsulant or dielectric material 130. In some examples, the substrate tab 111 may be electrically coupled to an external circuit or another semiconductor device.

[0052] In some examples, the encapsulant 130 may include an epoxy molding compound, an epoxy molding resin, or a sealant. In some examples, the encapsulant 130 may be referred to as a molded component, a sealing component, an encapsulation component, a protective component, or a body. In some examples, the encapsulant 130 may include an organic resin, an inorganic filler, a curing agent, a catalyst, a coupling agent, a colorant, or a flame retardant. In some examples, the encapsulant 130 may be formed or provided by compression molding, transfer molding, liquid phase encapsulant molding, vacuum lamination, paste printing, or film assisted molding. The thickness of the encapsulant 130 may be in the range of about 0.1 mm to about 1 mm. The encapsulant 130 may protect the substrate 110 and the electronic components 121, 122, or 123 from being exposed to external elements or the environment. In some examples, before providing the electronic components 121, 122, or 123 on the top surface of the substrate 110, the substrate 110 may be provided on the carrier 1.

[0053] Figure 2D1 shows a cross-sectional view of a semiconductor device 100 in a later stage of manufacturing. Figure 2D In the example shown, the carrier 1 can be Figure 2C In some examples, the assembly can be separated by Figure 2C The assembly shown applies heat or UV light to reduce the bonding strength of the bonding layer 2 to remove the carrier 1. In some examples, the bonding layer 2 and the carrier 1 can be removed by applying a physical force to pull the bonding layer 2 and the carrier 1 out of the substrate 110. In other examples, a grinding process can be used to remove the bonding layer 2 and the carrier 1. In some examples, the carrier 1 can be removed after providing a dielectric or encapsulant 130 on the top surface substrate 110.

[0054] In addition, the external interconnect 150 may be coupled to the bottom surface 110d of the substrate 110. In some examples, the external interconnect 150 may include a conductive material. In some examples, the external interconnect 150 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), aluminum, gold, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some examples, the external interconnect 150 may be formed or provided by a solder ball drop process, screen printing, or electroplating. Examples for manufacturing the interconnect 150 may include: forming a conductive material including solder on the bottom surface 110d of the substrate 110 using a solder ball drop process, and then performing a solder reflow process to apply heat to the semiconductor device 100. In some examples, the external interconnect 150 may be referred to as a conductive ball, a solder ball, a conductive pillar, or a copper pillar. In some examples, the interconnect 150 may include a copper pillar including a solder cap on an end region of the copper pillar. The width of the external interconnect 150 may be in a range of about 0.1 mm to about 0.5 mm. In some examples, the external interconnect 150 may be referred to as an external input / output (I / O) terminal of the semiconductor device 100.

[0055] Figures 3A to 3F A cross-sectional view of an example method for fabricating a semiconductor device 100 is shown. Figure 3A 1 shows a cross-sectional view of a semiconductor device 100 at an early stage of manufacture. Figure 3A In the example shown, the carrier 1 may include a planar structure and may support a plurality of components during the manufacturing of the semiconductor device 100 .

[0056] Figure 3B 1 shows a cross-sectional view of a semiconductor device 100 in a later stage of manufacturing. Figure 3BIn the example shown, a bonding layer 2 may be formed or provided on the carrier 1 . In some examples, the electronic components 121 and 122 may be on the bonding layer 2 , and the electronic component 123 may be on the electronic component 122 .

[0057] Figure 3C 1 shows a cross-sectional view of a semiconductor device 100 in a later stage of manufacturing. Figure 3C In the example shown, dielectric 130 may be formed or provided on the top surface of bonding layer 2 and on component 121, 122, or 123. In some examples, dielectric 130 may contact the top surface of bonding layer 2 and the top, bottom, and side surfaces of component 121, 122, or 123 to encapsulate electronic component 121, 122, or 123. In some examples, dielectric 130 may be referred to as an encapsulant.

[0058] Figure 3D 1 shows a cross-sectional view of a semiconductor device 100 in a later stage of manufacturing. Figure 3D In the example shown, the carrier 1 can be Figure 3C In some examples, the assembly can be separated by Figure 3C The assembly shown applies heat or UV light to reduce the bonding strength of the bonding layer 2 to remove the carrier 1. In some examples, the bonding layer 2 and the carrier 1 can be removed by applying a physical force to pull the bonding layer 2 and the carrier 1. In some examples, after removing the bonding layer 2 and the carrier 1, the lower portion of the encapsulant 130 and the interconnect 125 can be exposed.

[0059] Figure 3E 1 shows a cross-sectional view of a semiconductor device 100 in a later stage of manufacturing. Figure 3E In the example shown, a bonding layer 4 may be formed or provided on a carrier 3. In some examples, the manufacturing process for forming the bonding layer 4 and the carrier 3 and the configuration of the bonding layer and the carrier may be the same as in reference Figure 1 and Figures 2A to 2D The manufacturing processes and configurations of the bonding layer 2 and the carrier 1 discussed above are the same or similar. In some examples, after the bonding layer 4 is coupled to the carrier 3 , the substrate 110 may be coupled to the bonding layer 4 .

[0060] In some examples, after the substrate 110 is coupled to the bonding layer 4, Figure 3D The illustrated assembly can be coupled to the substrate 110. In some examples, the bottom surface of the encapsulant 130 and the lower portion of the interconnect 125 can be coupled to the top surface 110c of the substrate 110.

[0061] Figure 3F 1 shows a cross-sectional view of a semiconductor device 100 in a later stage of manufacturing. Figure 3FIn the example shown, the carrier 3 can be Figure 3E In some examples, the assembly can be separated by Figure 3E The assembly shown applies heat or UV light to reduce the bonding strength of the bonding layer 4 to remove the carrier 3. In some examples, the bonding layer 4 and the carrier 3 can be removed by applying a physical force to pull the bonding layer 4 and the carrier 3 out of the substrate 110. In other examples, a grinding process can be used to remove the bonding layer 4 and the carrier 3. In some examples, after removing the bonding layer 4 and the carrier 3, the external interconnect 150 can be coupled to the bottom surface 110d of the substrate 110.

[0062] Figure 4 A cross-sectional view of an example electronic assembly 10 is shown. Figure 4 In the example shown, the electronic assembly 10 may include a base structure 11, an electrical interconnect 12 (such as a bonding wire or a clip), and semiconductor devices 100 and 200. In some examples, the base structure 11 may include a dielectric structure 11a and a conductive structure 11b. In some examples, the electronic assembly 10 may include a semiconductor device 100 and a semiconductor device 200 electrically coupled to each other, wherein each of the semiconductor devices 100 and 200 may include, for example, a semiconductor device 100 and a semiconductor device 200. Figure 1 1 and 2. In some examples, electronic assembly 10 may include a base structure 11 including a top surface, wherein semiconductor devices 100 and 200 may be located above the top surface of base structure 11. In some examples, semiconductor devices 100 and 200 may be connected to each other via electrical interconnects coupled to substrate tabs 111 of the semiconductor devices, such as by Figure 4 The electrical interconnection 12 shown, through Figure 6 The electrical interconnection 22 shown may be connected via Figure 8 The illustrated electrical interconnects 32 are electrically coupled to one another, and the scope of the disclosed subject matter is not limited in these respects.

[0063] In some examples, semiconductor device 200 may include substrate 210, electronic components 221, 222, or 223, electrical interconnects 225, encapsulation 230, external interconnects 250, and capping layer 260. In some examples, substrate 210 may include top surface 210c, bottom surface 210d, dielectric structure 210a, conductive structure 210b, and substrate tab 211. In some examples, electrical interconnects 225 may be referred to as bonding wires, and electrical interconnects 225 may include conductive materials such as alloys, gold, silver, copper, or palladium-coated copper (PCC). In some examples, the die terminals of component 223 may be electrically coupled to conductive structure 210b of substrate 210 using electrical interconnects 225.

[0064] In some examples, the substrate 210, the encapsulation 230, and the external interconnect 250 may be referred to as a semiconductor package and may protect the electronic components 221, 222, or 223 from external elements or environmental exposure. The semiconductor package may provide electrical coupling between external components and the electronic components 221, 222, or 223. In some examples, the manufacturing process for forming the semiconductor device 200 and the configuration of the semiconductor device may be similar to those described in reference to FIG. Figure 1 , Figures 2A to 2D as well as Figures 3A to 3F The manufacturing process for forming the semiconductor device 100 and the configuration of the semiconductor device described in the present disclosure are the same or similar. In some examples, the semiconductor device 200 can be coupled to the semiconductor device 100 by coupling the substrate tab 211 to the substrate tab 111 .

[0065] In some examples, the semiconductor device 200 may include a cover layer 260 on an outer surface of the encapsulation 230. In some examples, the cover layer 260 may be referred to as a conformal shield. In some examples, the encapsulation may include four side surfaces, and the cover layer 260 may include a conductive material and may be located on the top surface and the four side surfaces of the encapsulation 230. In some examples, the layer 260 may provide electromagnetic interference (EMI) shielding for the electronic components 221, 222, or 223. In some examples, the cover layer 260 may be electrically coupled to ground through the conductive structure 211b of the substrate 210 to provide EMI shielding.

[0066] Figures 5A to 5D A cross-sectional view of an example method for manufacturing electronic assembly 10 is shown. Figure 5A A cross-sectional view of electronic assembly 10 is shown at an early stage of manufacture.

[0067] exist Figure 5A In the example shown, the base structure 11 may include a dielectric structure 11a and a conductive structure 11b. In some examples, the base structure 11 may include or be referred to as a preformed substrate, an RDL substrate, a printed circuit board, a cavity substrate, a printed wiring board, a multilayer substrate, a through-hole substrate, a rigid substrate, a flexible substrate, a glass epoxy substrate, a polyimide substrate, a polyester substrate, a molded plastic substrate, a ceramic substrate, an etched foil process substrate, an additive process substrate, a build-up substrate, or a molded lead frame.

[0068] In some examples, the dielectric structure 11a may have a flat top surface and a bottom surface. The top surface and the bottom surface of the dielectric structure 11a may be parallel to the top surface and the bottom surface of the base structure 11. In some examples, the dielectric structure 11a may be referred to as a dielectric layer or a core layer. The dielectric structure 11a may include one or more dielectric layers. In some examples, the dielectric structure 11a may include epoxy resin, phenolic resin, glass epoxy resin, polyimide, polyester, epoxy molding compound, ceramic, bismaleimide triazine (BT) or FR4.

[0069] Conductive structure 11b may be coupled to dielectric structure 11a. In some examples, conductive structure 11b may be referred to as a conductor, a conductive material, a conductive via, a circuit pattern, a trace, or a wiring pattern.

[0070] Figure 5B A cross-sectional view of electronic assembly 10 is shown in a later stage of manufacture. Figure 5B In the example shown, semiconductor device 100 may be on a portion of the top surface of base structure 11. Semiconductor device 100 may be electrically coupled to conductive structure 11b. In some examples, interconnect 150 may be attached to base structure 11 or electrically coupled to conductive structure 11b of base structure 11 using a mass reflow process, a thermal compression process, or a laser assisted bonding process.

[0071] Figure 5C A cross-sectional view of electronic assembly 10 is shown in a later stage of manufacture. Figure 5C In the example shown, semiconductor device 200 can be on a portion of the top surface of base structure 11. In some examples, substrate tab 211 of semiconductor device 200 can be adjacent to substrate tab 111 of semiconductor device 100. In some examples, substrate tab 111 can contact substrate tab 211. In other examples, substrate tab 111 can be spaced apart from substrate tab 211.

[0072] In some examples, the conductive structure 11b of the base structure 11 may be electrically coupled to the semiconductor device 100 or 200 through a conductor, a conductive material, a conductive via, a substrate pad, a conductive pad, a substrate pad, a wiring pad, a connection pad, a micro pad, or an under bump metal (UBM). In some examples, the conductive structure 11b may include copper, aluminum, iron, nickel, gold, silver, palladium, or tin.

[0073] Figure 5D A cross-sectional view of electronic assembly 10 is shown in a later stage of manufacture. Figure 5DIn the example shown, the electrical interconnect 12 can be coupled to the substrate tabs 111 and 211. In some examples, the interconnect 12 can include a conductive bonding wire or a wire clip or a plurality of bonding wires and wire clips. In some examples, the interconnect 12 can include a conductive material, such as an alloy, gold, silver, copper, or palladium-coated copper (PCC). In some examples, the conductive structure 110b of the substrate 110 can be electrically coupled to the conductive structure 210b of the substrate 210 through the interconnect 12. In some examples, the interconnect 12 can provide a conductive path between the semiconductor devices 100 and 200. Compared to other electronic assemblies, the interconnect 12 of the electronic assembly 10 can provide relatively low thermal resistance and relatively high performance due to the relatively short electrical path.

[0074] Figure 6 A cross-sectional view of an electronic assembly 20 is shown. Figure 6 In the example shown, electronic assembly 20 may include electrical interconnect 22 and semiconductor devices 100 and 300 .

[0075] In some examples, semiconductor device 300 may include substrate 310, electronic component 321, interconnect 325, encapsulation 330, and external interconnect 350. Substrate 310 may include dielectric structure 310a, conductive structure 310b, and substrate tab 311. Figure 6 In the example shown, semiconductor device 300 can be inverted relative to semiconductor device 100 to allow substrate tab 311 of semiconductor device 300 to be above substrate tab 111 of semiconductor device 100 to facilitate coupling of semiconductor devices 100 and 300. In some examples, any of the interconnects described herein including electrical interconnect 12, electrical interconnect 22, or interconnect 32 may include an interconnect substrate including a conductive material and any suitable substrate material, dielectric material, rigid material, or flexible material for forming a substrate. In some examples, any of the interconnects described herein may include a lead frame. In some examples, when semiconductor device 300 is as shown in FIG. Figure 6 When the semiconductor device 100 is inverted as shown in the configuration shown in FIG. 1 , the external interconnect 350 can be at the same height as the top surface of the encapsulant 130 or can extend above the top surface or otherwise be higher than the top surface. Similarly, in such an inverted configuration, the external interconnect 150 can be at the same height as the top surface of the encapsulant 330 or can extend below the top surface or otherwise be lower than the top surface.

[0076] In some instances, substrate 310, encapsulation 330, and external interconnects 350 may be referred to as a semiconductor package and may protect electronic component 321 from external elements or environmental exposure. The semiconductor package may provide electrical coupling between external components and electronic component 321. In some instances, substrate 310 may include or be referred to as a preformed substrate, an RDL substrate, a printed circuit board, a cavity substrate, a printed wiring board, a multilayer substrate, a through-hole substrate, a rigid substrate, a flexible substrate, a glass epoxy substrate, a polyimide substrate, a polyester substrate, a molded plastic substrate, a ceramic substrate, an etched foil process substrate, an additive process substrate, a build-up substrate, or a molded lead frame. In some instances, the manufacturing process for forming semiconductor device 300 and the configuration of the semiconductor device may be the same as described in reference to Figure 1 , Figures 2A to 2D as well as Figures 3A to 3F The manufacturing process for forming the semiconductor device 100 and the configuration of the semiconductor device described in the present disclosure are the same or similar. In some examples, the semiconductor device 300 can be coupled to the semiconductor device 100 by coupling the substrate tab 311 to the substrate tab 111 .

[0077] Fig. 7A and 7B A cross-sectional view of an example method for manufacturing electronic assembly 20 is shown. Fig. 7A A cross-sectional view of an electronic assembly 20 is shown at an early stage of manufacture.

[0078] exist Fig. 7A In the example shown, the interconnect 22 may be located on the substrate tab 111 of the semiconductor device 100. In some examples, the interconnect 22 may include a conductive material, such as a solder or a copper pillar. In some examples, the interconnect 22 may be electrically coupled to the conductive structure 110b. In some examples, the interconnect 22 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), gold, aluminum, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi or Sn-Ag-Cu. In some examples, the interconnect 22 may be formed or provided by a solder ball drop process, screen printing or electroplating. In some examples, the interconnect 22 may include a copper pillar, which includes a solder cap on the end region of the copper pillar.

[0079] Figure 7B A cross-sectional view of an electronic assembly 20 is shown in a later stage of manufacture. Figure 7BIn the example shown, semiconductor device 300 can be coupled to semiconductor device 100. In some examples, substrate tab 311 of semiconductor device 300 can be coupled to interconnect 22, and substrate tabs 111 and 311 can be electrically and mechanically coupled to each other through interconnect 22. In some examples, substrate tab 311 is above substrate tab 111, and substrate tabs 111 and 311 can provide an electrical path between semiconductor devices 100 and 300. In some examples, a mass reflow process, a thermal compression process, or a laser assisted bonding process can be used to attach tab 311 to interconnect 22 or to electrically couple a component of device 100 to a component of device 300. Compared to other electronic assemblies, interconnect 22 of electronic assembly 20 can provide relatively low thermal resistance and relatively high performance due to the relatively short electrical path.

[0080] Figure 8 A cross-sectional view of an example electronic assembly 30 is shown. Figure 8 In the example shown, electronic assembly 30 may include interconnect 32 and semiconductor devices 100 and 300 .

[0081] Figures 9A to 9C A cross-sectional view of an example method for manufacturing electronic assembly 30 is shown. Fig. 9A A cross-sectional view of an electronic assembly 30 is shown at an early stage of manufacture.

[0082] exist Fig. 9A In the example shown, the interconnect 32 may be on a substrate tab 111 of the semiconductor device 100. In some examples, the interconnect 32 may include or be referred to as a preformed substrate, an RDL substrate, a printed circuit board, a cavity substrate, a printed wiring board, a multilayer substrate, a through-hole substrate, a rigid substrate, a flexible substrate, a glass epoxy substrate, a polyimide substrate, a polyester substrate, a molded plastic substrate, a ceramic substrate, an etched foil process substrate, an additive process substrate, a build-up substrate, or a molded lead frame. In some examples, the interconnect 32 may have a top surface and a bottom surface and may include a conductive pattern on its bottom surface. In some examples, a mass reflow process, a thermal compression process, or a laser-assisted bonding process may be used to attach the interconnect 32 to the substrate tab 111 of the semiconductor device 100 or to electrically couple components of the device 100 to the conductive pattern of the interconnect 32.

[0083] Fig. 9B A cross-sectional view of an electronic assembly 30 is shown in a later stage of manufacture. Fig. 9BIn the example shown, semiconductor device 300 can be coupled to semiconductor device 100. In some examples, after interconnect 32 is coupled to substrate tab 111, substrate tab 311 of semiconductor device 300 can be coupled to the top surface of interconnect 32, and substrate tabs 111 and 311 can be electrically and mechanically coupled to each other through interconnect 32. In some examples, tab 111 contacts a first portion of interconnect 32 and tab 311 contacts a second portion of interconnect 32. In some examples, tab 111 contacts the bottom surface of interconnect 32 and tab 311 contacts the top surface of interconnect 32. In some examples, interconnect 32 and substrate tabs 111 and 311 can provide an electrical path between semiconductor devices 100 and 300. In some examples, a mass reflow process, a thermal compression process, or a laser assisted bonding process can be used to attach tab 311 to interconnect 32 or electrically couple a component of device 100 to a component of device 300. Compared to other electronic assemblies, interconnect 32 of electronic assembly 30 may provide relatively low thermal resistance and relatively high performance due to relatively short electrical paths.

[0084] Fig. 9C A cross-sectional view of an electronic assembly 30 is shown in a later stage of manufacture. Fig. 9C In the example shown, except that the interconnect 32 is shown as being bent so that the semiconductor device 300 and the semiconductor device can be in a folded arrangement, the semiconductor device 300 can be as shown. Fig. 9B 300 is coupled to the semiconductor device 100. In such a folded arrangement, the flexibility of the interconnect 32 may allow the semiconductor device 300 to be folded over the top side of the semiconductor device 100 or vice versa and may allow the semiconductor device 300 and the semiconductor device 100 to be provided in a stacked package arrangement. Fig. 9C In the illustrated example, semiconductor device 300 is shown as being inverted relative to the orientation of semiconductor device 100. In other examples, semiconductor device 300 is not inverted relative to the orientation of semiconductor device 100, and the scope of the disclosed subject matter is not limited in this respect.

[0085] Fig.10 A cross-sectional view of an electronic assembly 40 is shown. Fig.10 In the example shown, electronic assembly 40 may include electrical interconnect 32 and semiconductor devices 100 and 400 .

[0086] In some examples, semiconductor device 400 may include substrate 410, electronic components 421, 422, or 423, interconnects 425, encapsulation 430, and external interconnects 450. Substrate 410 may include dielectric structure 410a, conductive structure 410b, and substrate tab 411.

[0087] In some instances, substrate 410, encapsulation 430, and external interconnects 450 may be referred to as a semiconductor package and may protect electronic components 421, 422, or 423 from external elements or environmental exposure. The semiconductor package may provide electrical coupling between external components and electronic components 421, 422, or 423. In some instances, substrate 410 may include or be referred to as a preformed substrate, an RDL substrate, a printed circuit board, a cavity substrate, a printed wiring board, a multi-layer substrate, a through-hole substrate, a rigid substrate, a flexible substrate, a glass epoxy substrate, a polyimide substrate, a polyester substrate, a molded plastic substrate, a ceramic substrate, an etched foil process substrate, an additive process substrate, a build-up substrate, or a molded lead frame. In some instances, the manufacturing process for forming semiconductor device 400 and the configuration of the semiconductor device may be the same as described in reference to Figure 1 , Figures 2A to 2D as well as Figures 3A to 3F The manufacturing process for forming the semiconductor device 100 and the configuration of the semiconductor device described in the present disclosure are the same or similar. In some examples, the semiconductor device 400 can be coupled to the semiconductor device 100 by coupling the substrate tab 411 to the substrate tab 111 .

[0088] Fig.11A and 11B A cross-sectional view of an example method for manufacturing an electronic assembly 40 is shown. Fig.11A A cross-sectional view of an electronic assembly 40 is shown at an early stage of manufacture.

[0089] exist Fig.11A In the example shown, substrate tab 411 of semiconductor device 400 can be adjacent to substrate tab 111 of semiconductor device 100. In some examples, substrate tab 111 can be spaced apart from substrate tab 411. In other examples, substrate tab 111 can contact substrate tab 411.

[0090] Fig. 11B A cross-sectional view of an electronic assembly 40 is shown in a later stage of manufacture. Fig. 11B In the example shown, interconnect 32 can be coupled to substrate tabs 111 and 411. In some examples, a mass reflow process, a thermal compression process, or a laser-assisted bonding process can be used to attach interconnect 32 to substrate tabs 111 and 411, electrically couple components of device 100 to conductive patterns of interconnect 32, electrically couple components of device 400 to conductive patterns of interconnect 32, or electrically couple components of device 100 to components of device 400.

[0091] In some examples, semiconductor device 400 may be coupled to semiconductor device 100. In some examples, substrate tabs 111 and 411 may be coupled to the bottom surface of interconnect 32, and substrate tabs 111 and 411 may be electrically and mechanically coupled to each other through interconnect 32. In some examples, substrate tab 111 contacts a first portion of the bottom surface of interconnect 32 and substrate tab 411 contacts a second portion of the bottom surface of interconnect 32. In some examples, interconnect 32 and substrate tabs 111 and 411 may provide an electrical path between semiconductor devices 100 and 400. In some examples, a mass reflow process, a thermal compression process, or a laser assisted bonding process may be used to attach interconnect 32 to tabs 111 and 411 or to electrically couple a component of device 100 to a component of device 400. Compared to other electronic assemblies, interconnect 32 of electronic assembly 40 may provide relatively low thermal resistance and relatively high performance due to a relatively short electrical path.

[0092] Fig.12 A cross-sectional view of an example electronic assembly 50 is shown. Fig.12 In the example shown, the electronic assembly 50 may include the electrical interconnect 22, the support structure 51, the intermediate structure 52, the support structure 53, and the semiconductor devices 100 and 300. In some examples, the base structure may include the support structure 51, the support structure 53, and the intermediate structure 52 between the support structure 51 and the support structure 53. The semiconductor device 100 may be coupled to the top surface of the support structure 51, and the semiconductor device 300 may be coupled to the top surface of the support structure 53. The semiconductor device 300 together with the support structure 53 may be inverted relative to the semiconductor device 100 and the support structure 51, wherein the substrate tab 311 of the semiconductor device 300 is above the substrate tab 111 of the semiconductor device 100 to facilitate coupling of the substrate tabs through the interconnect 22.

[0093] In some examples, support structures 51 and 53 may include dielectric structures 51a and 53a, respectively. Support structures 51 and 53 may include conductive structures 51b and 53b, respectively. Intermediate structure 42 may include dielectric structure and conductive structure 52a. In some examples, intermediate structure 52 may be located between support structure 51 and support structure 53.

[0094] Figures 13A to 13D A cross-sectional view of an example method for manufacturing an electronic assembly 50 is shown. Fig.13A A cross-sectional view of an electronic assembly 50 is shown at an early stage of manufacture.

[0095] exist Fig.13AIn the example shown, the support structure 51 may include a dielectric structure 51a and a conductive structure 51b. In some examples, the support structure 51 may include or be referred to as a liquid crystal polymer, a preform substrate, an RDL substrate, a printed circuit board, a cavity substrate, a printed wiring board, a multilayer substrate, a through-hole substrate, a rigid substrate, a flexible substrate, a glass epoxy substrate, a polyimide substrate, a polyester substrate, a molded plastic substrate, a ceramic substrate, an etched foil process substrate, an additive process substrate, a build-up substrate, or a molded lead frame.

[0096] In some instances, the dielectric structure 51a may have a flat top surface and a bottom surface. The top surface and the bottom surface of the dielectric structure 51a may be parallel to the top surface and the bottom surface of the support structure 51. In some instances, the dielectric structure 51a may be referred to as a dielectric layer or a core layer. The dielectric structure 51a may include one or more dielectric layers. In some instances, the dielectric structure 51a may include epoxy resin, phenolic resin, glass epoxy resin, polyimide, polyester, epoxy molding compound, ceramic, bismaleimide triazine (BT) or FR4. The conductive structure 51b may be coupled to the dielectric structure 51a. In some instances, the conductive structure 51b may be referred to as a conductor, a conductive material, a conductive via, a circuit pattern, a trace or a wiring pattern.

[0097] exist Fig.13A In the example shown, the semiconductor device 100 may be on a portion of the top surface of the support structure 51. The semiconductor device 100 may be electrically coupled to the conductive structure 51 b of the support structure 51. In some examples, a mass reflow process, a thermal compression process, or a laser assisted bonding process may be used to attach the interconnect 150 to the support structure 51 or to electrically couple the interconnect 150 to the conductive structure 51 b of the base structure 51.

[0098] Fig. 13B A cross-sectional view of an electronic assembly 50 is shown in a later stage of manufacture. Fig. 13BIn the example shown, semiconductor device 300 can be coupled to semiconductor device 100. In some examples, after interconnect 22 is formed or provided on tab 111, substrate tab 311 of semiconductor device 300 can be coupled to interconnect 22, and substrate tabs 111 and 311 can be electrically and mechanically coupled to each other through interconnect 22. In some examples, substrate tab 311 is on substrate tab 111, and interconnect 22 and substrate tabs 111 and 311 can provide an electrical path between semiconductor devices 100 and 300. In some examples, a mass reflow process, a thermal compression process, or a laser assisted bonding process can be used to attach tab 311 to interconnect 22 or electrically couple a component of device 100 to a component of device 300. Compared to other electronic assemblies, interconnect 22 of electronic assembly 50 can provide relatively low thermal resistance and relatively high performance due to a relatively short electrical path.

[0099] Fig. 13C A cross-sectional view of an electronic assembly 50 is shown in a later stage of manufacture. Fig. 13C In the example shown, the intermediate structure 52 can be coupled to the top surface of the support structure 51. In some examples, the intermediate structure 52 can be a single, unitary rectangular structure. In other examples, the intermediate structure 52 can include multiple spaced-apart components.

[0100] In some instances, the intermediate structure 52 may include or be referred to as a liquid crystal polymer, a preformed substrate, an RDL substrate, a printed circuit board, a cavity substrate, a printed wiring board, a multilayer substrate, a through-hole substrate, a rigid substrate, a flexible substrate, a glass epoxy substrate, a polyimide substrate, a polyester substrate, a molded plastic substrate, a ceramic substrate, an etched foil process substrate, an additive process substrate, a stacked substrate, or a molded lead frame. In some instances, the intermediate structure 52 may have a top surface and a bottom surface and may include a conductive pattern on its top surface and bottom surface. In some instances, a mass reflow process, a thermal compression process, or a laser-assisted bonding process may be used to attach the intermediate structure 52 to the support structure 51, electrically couple the components of the devices 100 and 300 to the conductive patterns of the intermediate structure 52, or electrically couple the conductive structure 52a to the conductive structure 51b. In other instances, the intermediate structure 52 may be coupled to the support structure 51 using an adhesive.

[0101] Fig.13D A cross-sectional view of an electronic assembly 50 is shown in a later stage of manufacture. Fig.13DIn the example shown, the support structure 53 can be on the intermediate structure 52, the device 100, or the device 300. The support structure 53 can include a dielectric structure 53a and a conductive structure 53b. In some examples, the support structure 53 can include or be referred to as a liquid crystal polymer, a preform substrate, an RDL substrate, a printed circuit board, a cavity substrate, a printed wiring board, a multilayer substrate, a through-hole substrate, a rigid substrate, a flexible substrate, a glass epoxy substrate, a polyimide substrate, a polyester substrate, a molded plastic substrate, a ceramic substrate, an etched foil process substrate, an additive process substrate, a build-up substrate, or a molded lead frame.

[0102] In some instances, the dielectric structure 53a may have a flat top surface and a bottom surface. The top surface and the bottom surface of the dielectric structure 53a may be parallel to the top surface and the bottom surface of the support structure 53. In some instances, the dielectric structure 53a may be referred to as a dielectric layer or a core layer. The dielectric structure 53a may include one or more dielectric layers. In some instances, the dielectric structure 53a may include epoxy resin, phenolic resin, glass epoxy resin, polyimide, polyester, epoxy molding compound, ceramic, bismaleimide triazine (BT) or FR4. The conductive structure 53b may be coupled to the dielectric structure 53a. In some instances, the conductive structure 53b may be referred to as a conductor, a conductive material, a conductive via, a circuit pattern, a trace or a wiring pattern.

[0103] In some examples, semiconductor device 300 may be electrically coupled to conductive structure 53b of support structure 53. In some examples, interconnect 350 may be attached to support structure 53, interconnect 350 may be electrically coupled to conductive structure 53b of base structure 53, or conductive structure 52a may be electrically coupled to conductive structure 53b using a mass reflow process, a thermal compression process, or a laser assisted bonding process. In other examples, intermediate structure 52 may be coupled to support structure 53 using an adhesive.

[0104] Fig.14 A cross-sectional view of an example electronic assembly 60 is shown. Fig.14 In the example shown, electronic assembly 60 may include interconnect 32 , support structure 51 , intermediate structure 52 , support structure 53 , and semiconductor devices 100 and 300 .

[0105] Figures 15A to 15E A cross-sectional view of an example method for manufacturing an electronic assembly 60 is shown. Fig.15A A cross-sectional view of an electronic assembly 60 is shown at an early stage of manufacture.

[0106] exist Fig.15AIn the example shown, semiconductor device 100 may be on a portion of the top surface of support structure 51. Semiconductor device 100 may be electrically coupled to conductive structure 51 b. In some examples, a mass reflow process, a thermal compression process, or a laser assisted bonding process may be used to attach interconnect 150 to support structure 51 or to electrically couple interconnect 150 to conductive structure 51 b of base structure 51.

[0107] Fig. 15B A cross-sectional view of an electronic assembly 60 is shown in a later stage of manufacture. Fig. 15B In the example shown, interconnect 32 may be on substrate tab 111 of semiconductor device 100. In some examples, a mass reflow process, a thermal compression process, or a laser assisted bonding process may be used to attach interconnect 32 to substrate tab 111 of semiconductor device 100 or to electrically couple components of device 100 to conductive patterns of interconnect 32.

[0108] Fig. 15C A cross-sectional view of an electronic assembly 30 is shown in a later stage of manufacture. Fig. 15C In the example shown, semiconductor device 300 can be coupled to semiconductor device 100. In some examples, substrate tab 311 of semiconductor device 300 can be coupled to the top surface of interconnect 32, and substrate tabs 111 and 311 can be electrically and mechanically coupled to each other through interconnect 32. In some examples, substrate tab 111 contacts a first portion of interconnect 32 and substrate tab 311 contacts a second portion of interconnect 32. In some examples, substrate tab 111 contacts the bottom surface of interconnect 32 and substrate tab 311 contacts the top surface of interconnect 32. In some examples, interconnect 32 and substrate tabs 111 and 311 can provide an electrical path between semiconductor devices 100 and 300. In some examples, a mass reflow process, a thermal compression process, or a laser assisted bonding process can be used to attach tab 311 to interconnect 32 or electrically couple a component of device 100 to a component of device 300. Compared to other electronic assemblies, the interconnect 32 of the electronic assembly 60 may provide relatively low thermal resistance and relatively high performance due to the relatively short electrical paths.

[0109] Fig.15D A cross-sectional view of an electronic assembly 50 is shown in a later stage of manufacture. Fig.15D In the example shown, the intermediate structure 52 can be coupled to the top surface of the support structure 51. In some examples, the intermediate structure 52 can be a single, unitary rectangular structure. In other examples, the intermediate structure 52 can include multiple spaced-apart components.

[0110] Fig.15E A cross-sectional view of an electronic assembly 60 is shown in a later stage of manufacture. Fig.15E In the example shown, the support structure 53 may be on the intermediate structure 52 , the device 100 , or the device 300 .

[0111] In some examples, semiconductor device 300 may be electrically coupled to conductive structure 53b of support structure 53. In some examples, interconnect 350 may be attached to support structure 53, interconnect 350 may be electrically coupled to conductive structure 53b of support structure 53, or conductive structure 52a may be electrically coupled to conductive structure 53b using a mass reflow process, a thermal compression process, or a laser assisted bonding process. In other examples, intermediate structure 52 may be coupled to support structure 53 using an adhesive.

[0112] The present disclosure includes references to certain examples. However, it will be appreciated by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, the disclosed examples may be modified without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the disclosed examples, but the present disclosure will include all examples falling within the scope of the appended claims.

Claims

1. An electronic assembly comprising: a first semiconductor device and a second semiconductor device, wherein each of the first semiconductor device and the second semiconductor device comprises: a substrate comprising a top surface and a conductive structure; an electronic component located above the top surface of the substrate; a dielectric material overlying the top surface of the substrate and contacting a side of the electronic component; and a substrate tab at a first end of a substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab; an interconnect electrically coupled to the conductive structure at the substrate contact of the first semiconductor device and the conductive structure at the substrate contact of the second semiconductor device; and a base structure comprising a top surface, wherein the first semiconductor device is above the top surface of the base structure and the second semiconductor device is above the top surface of the base structure; The first semiconductor device and the second semiconductor device are located side by side on the top surface of the base structure, and the first end of the substrate of the first semiconductor device faces the first end of the substrate of the second semiconductor device.

2. The electronic assembly of claim 1, wherein the interconnect comprises a bond wire. The electronic assembly of claim 1 , wherein the interconnect comprises a wire clip.

4. The electronic assembly of claim 1, wherein the second semiconductor device is inverted relative to the first semiconductor device, and the substrate tab of the second semiconductor device is above the substrate tab of the first semiconductor device.

5. The electronic assembly of claim 4, wherein the interconnect comprises solder.

6. The electronic assembly of claim 4, wherein the interconnect comprises a copper pillar.

7. The electronic assembly of claim 1, wherein the interconnect comprises an interconnect substrate.

8. The electronic assembly of claim 1, wherein the interconnect comprises a flexible substrate.

9. The electronic assembly of claim 1, wherein the interconnect comprises a lead frame.

10. The electronic assembly according to claim 1, wherein: The basic structure includes a first supporting structure, a second supporting structure and an intermediate structure between the first supporting structure and the second supporting structure. The first semiconductor device is coupled to a top surface of the first support structure and the second semiconductor device is coupled to a top surface of the second support structure, and The second semiconductor device is inverted relative to the first semiconductor device, wherein the substrate tab of the second semiconductor device is above the substrate tab of the second semiconductor device.

11. The electronic assembly of claim 1 , wherein a first lateral side of the dielectric material is coplanar with a first lateral side of the substrate.

12. A method for preparing an electronic assembly, comprising: providing a base structure including a top surface; providing a first electronic component over a top surface of a first substrate, wherein the first substrate includes a first conductive structure coupled to the first electronic component, the first substrate having a first substrate tab on the top surface, and the first conductive structure is exposed at the first substrate tab; as well as providing a first dielectric structure over the top surface of the first substrate, wherein the first dielectric structure contacts a side of the first electronic component and the first substrate tab is not covered by the first dielectric structure; providing a second electronic component over a top surface of a second substrate, wherein the second substrate includes a second conductive structure coupled to the second electronic component, the second substrate having a second substrate tab on the top surface, and the second conductive structure is exposed at the second substrate tab; providing a second dielectric structure over the top surface of the second substrate, wherein the second dielectric structure contacts a side of the second electronic component and the second substrate tab is not covered by the second dielectric structure; as well as coupling the first substrate tab of the first substrate to the second substrate tab of the second substrate; The first substrate and the second substrate are located side by side on the top surface of the base structure, and the first substrate tab is oriented toward the second substrate tab.

13. The method of claim 12, further comprising providing the first substrate on a carrier before providing the first electronic component over the top surface of the first substrate, and removing the carrier after providing the first dielectric structure on the top surface of the first substrate.

14. A method for preparing an electronic assembly, comprising: providing a first semiconductor device and a second semiconductor device, wherein providing each of the first semiconductor device and the second semiconductor device comprises: providing a substrate including a top surface and a conductive structure; providing an electronic component over the top surface of the substrate; and providing a substrate tab at a first end of a substrate, wherein the conductive structure of the substrate is exposed at the substrate tab; providing an interconnect electrically coupled to the conductive structure at the substrate contact of the first semiconductor device and the conductive structure at the substrate contact of the second semiconductor device; and providing a base structure including a top surface, wherein the first semiconductor device is located above the top surface of the base structure, and the second semiconductor device is located above the top surface of the base structure; The first semiconductor device and the second semiconductor device are located side by side on the top surface of the base structure, and the first end of the substrate of the first semiconductor device faces the first end of the substrate of the second semiconductor device. The method of claim 14 , wherein the interconnect comprises a bond wire. The method of claim 14 , wherein the interconnect comprises a wire clip. The method of claim 14 , wherein the interconnect comprises solder. The method of claim 14 , wherein the interconnect comprises a copper pillar.

19. The method of claim 14, further comprising providing a dielectric material over the top surface of the substrate and contacting a side of the electronic component, wherein the dielectric material does not cover the substrate tab.

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