A zero-power-consumption power switching circuit and electronic equipment

Abstract

The present invention relates to a zero-power consumption power switching circuit and an electronic device, comprising: a power output terminal, a main input path and N auxiliary input paths from the first to the Nth auxiliary input paths, N being greater than or equal to 1; the main input path comprises a main power input terminal, a first and a second switch unit; the first end of the first switch unit is grounded, the second end is connected to the power output terminal, and the third end is connected to the main power input terminal, the first end of the second switch unit is connected to the main power input terminal, the second end is connected to the power output terminal, and the third end is connected to the second end of the first switch unit; each auxiliary input path comprises an auxiliary power input terminal and a third switch unit, in any nth auxiliary input path, wherein n is less than or equal to N, the first end of the third switch unit is connected to the auxiliary power input terminal, the second end is connected to the power output terminal, and the third end is connected to the main input path, when N is greater than 1, the first to the N-1th auxiliary input paths also include a fourth switch unit, the circuit of the present invention is simple and has low power consumption.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and more specifically, to a zero-power consumption power switching circuit and electronic equipment. Background Art

[0002] The current electronic products, especially the field of small household appliances, have higher and higher requirements for cost. Especially in the power supply circuit, when designing a multi-input power supply mode, the current switching method usually uses a control chip to perform corresponding connection identification to perform corresponding power switching, and its circuit cost is relatively high. At the same time, its switching control circuit needs to be powered, which will generate energy consumption and consume the power of the internal circuit. Increasing the energy consumption of the battery will inevitably reduce the battery life accordingly. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a zero-power consumption power switching circuit and an electronic device in view of the above-mentioned technical defects of the prior art.

[0004] The technical solution adopted by the present invention to solve the technical problem is: construct a zero-power consumption power switching circuit, including: a power output terminal, a main input path and N auxiliary input paths including a first auxiliary input path to an Nth auxiliary input path, wherein N is greater than or equal to 1;

[0005] The main input path includes a main power input terminal, a first switch unit and a second switch unit; the first terminal of the first switch unit is grounded, the second terminal of the first switch unit is connected to the power output terminal, the third terminal of the first switch unit is connected to the main power input terminal, and is used to drive the first switch unit to conduct when there is an input voltage at the main power input terminal, the first terminal of the second switch unit is connected to the main power input terminal, the second terminal of the second switch unit is connected to the power output terminal, and the third terminal of the second switch unit is connected to the second terminal of the first switch unit;

[0006] Each of the auxiliary input paths includes an auxiliary power input terminal and a third switch unit. In any nth auxiliary input path, where n is less than or equal to N, the first end of the third switch unit is connected to the auxiliary power input terminal corresponding to the auxiliary input path, the second end of the third switch unit is connected to the power output terminal, and the third end of the third switch unit is respectively connected to the main input path. When N is greater than 1, the first to N-1th auxiliary input paths also include a fourth switch unit, the second end of the fourth switch unit is grounded, the first end of the fourth switch unit is connected to the third end of the third switch unit, and the third end of the fourth switch unit is connected to the auxiliary power input terminal of the auxiliary input path. When n is greater than 1, the third end of the third switch unit in the nth auxiliary input path is also respectively connected to the auxiliary power input terminals of the n+1th to Nth auxiliary input paths and the first to n-1th auxiliary input paths.

[0007] Preferably, the first switch unit comprises a first MOS tube, a gate of the first MOS tube is connected to the main power input terminal, a source of the first MOS tube is grounded, and a drain of the first MOS tube is connected to the third terminal of the second switch unit.

[0008] Preferably, the first MOS transistor is an NMOS transistor.

[0009] Preferably, the second switch unit includes a second MOS tube and a first resistor, the source of the second MOS tube is connected to the power output end, the drain of the second MOS tube is connected to the main power input end, the gate of the second MOS tube is connected to the second end of the first switch unit, and the gate of the second MOS tube is connected to the first end of the first resistor, and the second end of the first resistor is connected to the source of the second MOS tube.

[0010] Preferably, the second MOS tube is a PMOS tube.

[0011] Preferably, in any nth auxiliary input path, the third switch unit includes a third MOS tube and a second resistor; the drain of the third MOS tube is connected to the auxiliary power input terminal of the auxiliary input path, the source of the third MOS tube is connected to the power output terminal, and when N is 1, the gate of the third MOS tube is connected to the main power input terminal and the first end of the second resistor, and the second end of the second resistor is grounded.

[0012] Preferably, when N is greater than 1,

[0013] In any m-th auxiliary input path, where m is less than N, the fourth switch unit includes a fourth MOS transistor, a gate of the fourth MOS transistor is connected to an auxiliary power input terminal of the auxiliary input path, a source of the fourth MOS transistor is grounded, and a drain of the fourth MOS transistor is connected to the second end of the second resistor;

[0014] The main input path includes a first isolation unit, a first end of the first isolation unit is connected to the main power input end, and a second end of the first isolation unit is respectively connected to the gates of the third MOS transistors in the first to Nth auxiliary input paths.

[0015] Preferably,

[0016] The first to N-1th auxiliary input paths further include a second isolation unit and a third isolation unit, respectively; in any mth auxiliary input path, the first end of the second isolation unit is respectively connected to the auxiliary power input end of the input path, the second end of the second isolation unit is respectively connected to the gate of the third MOS tube of the m+1th to Nth auxiliary input paths, the first end of the third isolation unit is respectively connected to the second end of the second resistor of the auxiliary input path, and the second end of the third isolation unit is respectively connected to the auxiliary power input end of the m+1th to Nth auxiliary input paths.

[0017] Preferably,

[0018] The first isolation unit includes N groups of first diodes; anodes of the N groups of first diodes are all connected to the main power input terminal, and cathodes of the N groups of first diodes are respectively connected to the gates of the third MOS tubes of the first to Nth auxiliary input paths.

[0019] Preferably,

[0020] In the mth auxiliary input path, the second isolation unit includes Nm groups of second diodes, the anodes of the Nm groups of second diodes are all connected to the auxiliary power input terminal of the auxiliary input path, and the cathodes of the Nm groups of second diodes are respectively connected to the gates of the third MOS transistors of the (m+1)th to the (N)th auxiliary input paths; and / or

[0021] The third isolation unit includes Nm groups of third diodes and current limiting resistors, the cathodes of the Nm groups of third diodes are connected to the second end of the second resistor of the auxiliary input path through the current limiting resistor, and the anodes of the Nm groups of third diodes are respectively connected to the auxiliary power supply input ends of the (m+1)th to the (N)th auxiliary input paths.

[0022] The present invention also constructs an electronic device, comprising the zero-power consumption power switching circuit as described in any one of the above.

[0023] A zero-power-consumption power switching circuit and electronic equipment implementing the present invention have the following beneficial effects: the circuit is simple and the power consumption is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0025] Figure 1 It is a logic block diagram of an embodiment of a zero-power consumption power switching circuit of the present invention;

[0026] Figure 2 It is a circuit principle diagram of an embodiment of a zero-power consumption power switching circuit of the present invention;

[0027] Figure 3 It is a circuit schematic diagram of another embodiment of a zero-power consumption power switching circuit of the present invention;

[0028] Figure 4 It is a circuit principle diagram of another embodiment of a zero-power consumption power switching circuit of the present invention. DETAILED DESCRIPTION

[0029] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described in detail with reference to the accompanying drawings.

[0030] like Figure 1As shown, in a first embodiment of a zero-power switching circuit of the present invention, it includes: a power output terminal 110, a main input path 120 and N auxiliary input paths 130 including a first auxiliary input path to an Nth auxiliary input path, wherein N is greater than or equal to 1; the main input path 120 includes a main power input terminal 123, a first switch unit 121 and a second switch unit 122; the first end of the first switch unit 121 is grounded, the second end of the first switch unit 121 is connected to the power output terminal 110, the third end of the first switch unit 121 is connected to the main power input terminal 123, and is used to drive the first switch unit 121 to turn on when there is an input voltage at the main power input terminal 123, the first end of the second switch unit 122 is connected to the main power input terminal 123, the second end of the second switch unit 122 is connected to the power output terminal 110, and the third end of the second switch unit 122 is connected to the second end of the first switch unit 121; each auxiliary input path 130 includes An auxiliary power input terminal 132 and a third switch unit 131, in any nth auxiliary input path, where n is less than or equal to N, a first end of the third switch unit 131 is connected to the auxiliary power input terminal corresponding to the auxiliary input path, a second end of the third switch unit 131 is connected to the power output terminal 110, a third end of the third switch unit 131 is respectively connected to the main input path 120, and when N is greater than 1, the first to N-1th auxiliary input paths also include a fourth switch unit, a second end of the fourth switch unit 135 is grounded, a first end of the fourth switch unit 135 is connected to the third end of the third switch unit 131 in the auxiliary input path, a third end of the fourth switch unit 135 is connected to the auxiliary power input terminal of the auxiliary input path, and when n is greater than 1, the third end of the third switch unit 131 in the nth auxiliary input path is also respectively connected to the auxiliary power input terminals of the first to n-1th auxiliary input paths and the n+1th to Nth auxiliary input paths. Specifically, the main input path 120 is the power input path with the highest priority. When the main input path 120 has power input, no matter whether the auxiliary input path has power input or not, the power output terminal 110 is powered and output through the main input path 120. When the main power input terminal 123 in the main input path 120 has power input, for example, when a power supply battery is connected, its input voltage triggers the first switch unit 121 to turn on. When the first switch unit 121 is turned on, the input of the main power input terminal 123 supplies power to the third terminal of the second switch unit 122 through the first switch unit 121 to drive the second switch unit 122 to turn on. After the second switch unit 122 is turned on, the input voltage of the main power input terminal 123 is output to the power output terminal 110 through the second switch unit 122. At the same time, the input voltage of the main power input terminal 123 supplies power to the third terminal of the third switch unit 131 in all the auxiliary input paths to drive the third switch unit 131 to be in the off state. At this time, no matter whether the auxiliary input path 130 has power input or not, it cannot supply power to the power output terminal 110.At this time, the power output terminal 110 is powered by the power input of the main input path 120. When there is no voltage input to the main input path 120, for example, the main power input terminal 123 is in an idle state, the third terminal of the first switch unit 121 in the main input path 120 has no driving level, and it is maintained in an off state. At this time, the second switch unit 122 is also maintained in an off state. At this time, the main power input terminal 123 no longer controls the third switch unit 131 in the auxiliary input path to turn off. According to the priority of the auxiliary input path. When it is not controlled to turn off by other auxiliary input paths, for example, the auxiliary input path with the highest priority in the first auxiliary input path, its third switch unit 131 is connected to the main input path. At this time, when there is no input in the main input path, the third switch unit 131 is turned on. At this time, if there is power input at the auxiliary power input terminal of the auxiliary input path, the power output terminal is powered by the auxiliary input, and the output maintains the second switch unit 122 off. If an auxiliary input path of other priority, such as the nth auxiliary input path, is powered on, and the auxiliary input path before the auxiliary input path is powered on, that is, no auxiliary input path is powered on in the first to n-1th auxiliary input paths, then the third switch unit 131 of the nth auxiliary input path is maintained in the on state, and at the same time, the third switch units 131 in the auxiliary input paths after the auxiliary input path, that is, the n+1th to Nth auxiliary input paths, are driven to the off state by the power supply of the nth auxiliary input path, and the power supply output terminal 110 is powered through the nth auxiliary input path. If any auxiliary input path is powered on in the first to n-1th auxiliary input paths before the nth auxiliary input path, the powered-on auxiliary input path can drive the third switch unit 131 in the nth auxiliary input path to be turned off, and the power supply of the nth auxiliary input path to the power supply output terminal 110 is cut off. Based on the above description, the conduction priority of the auxiliary input path can be realized in the order of the first to Nth auxiliary input paths, that is, the conduction priority of the first auxiliary input path is higher than that of the N-1 auxiliary input paths behind it, and the conduction priority of the nth auxiliary input path is higher than that of the n+1th to Nth auxiliary input paths. When N is greater than 1, the first to N-1th auxiliary input paths are provided with a fourth switch unit. When there is power input at the auxiliary power input end, the fourth switch unit can be driven to conduct through the power input of the auxiliary power input end, so as to finally drive the third switch of the auxiliary power path to conduct. Since the third end of the third switch unit 131 in the nth auxiliary input path is respectively connected to the auxiliary power input ends of the n+1th to Nth auxiliary input paths, when any auxiliary power input of the auxiliary power input ends of the n+1th to Nth auxiliary input paths is turned on to supply power to the output end, the nth auxiliary input path can be maintained in the off state through the conduction input to avoid the backflow of the power output to the upper power input end.When both the upper auxiliary power input and the lower auxiliary power input have power input, in order to prevent the lower auxiliary power input from shutting off the upper auxiliary power input path, the upper auxiliary power input drives the fourth switch unit 135 to turn on, so as to connect the lower auxiliary power input directly to the ground.

[0031] Optional, such as Figures 3 to 4 As shown, in any nth auxiliary input path, the third switch unit 131 includes a third MOS tube and a second resistor; the drain of the third MOS tube is connected to the auxiliary power input terminal of the auxiliary input path, the source of the third MOS tube is connected to the power output terminal, and when N is 1, the gate of the third MOS tube is connected to the main power input terminal and the first end of the second resistor, and the second end of the second resistor is grounded. Specifically, the third switch unit 131 can realize the conduction or shutoff of its corresponding auxiliary input path by turning on or off the third MOS tube. The gate of the third MOS tube is connected to the main power input terminal 123 and the second resistor. When there is power input at the main power input terminal 123, the gate of the third MOS tube is high level and it is turned off. Among them, the third MOS tube can be a PMOS tube.

[0032] Further, when N is greater than 1, in any m-th auxiliary input path, where m is less than N, the fourth switch unit 135 includes a fourth MOS transistor, the gate of the fourth MOS transistor is connected to the auxiliary power input terminal of the auxiliary input path, the source of the fourth MOS transistor is grounded, and the drain of the fourth MOS transistor is connected to the second end of the second resistor; the main input path includes a first isolation unit, the first end of the first isolation unit is connected to the main power input terminal, and the second end of the first isolation unit is respectively connected to the gates of the third MOS transistors in the first to N-th auxiliary input paths. That is, the third MOS transistor can be driven to turn on or off by the fourth MOS transistor. Specifically, when the number of auxiliary input paths exceeds one, a first isolation unit can also be provided in the main input path 120, and the main input path can drive the third MOS transistor to turn off by the first isolation unit. The middle power input of the main input path 120 is respectively connected to the first to N-th auxiliary input paths through the first isolation unit to avoid power backflow to the main power input terminal 123 when the auxiliary power input terminal has power input and is turned on.

[0033] Furthermore, the first isolation unit 124 includes N groups of first diodes; the anodes of the N groups of first diodes are all connected to the main power input terminal, and the cathodes of the N groups of first diodes are respectively connected to the gates of the third MOS tubes of the first to Nth auxiliary input paths. The first isolation unit 124 can be a diode, the anode of which is connected to the main power input terminal 123, which is forward-conducted when there is power input to the main power input terminal 123, and is reversely isolated when there is no power input to the main power input terminal 123 to prevent signal backflow.

[0034] Furthermore, the first to N-1 auxiliary input paths also include a second isolation unit 133 and a third isolation unit 134 respectively; in any mth auxiliary input path, the first end of the second isolation unit 133 is respectively connected to the auxiliary power input end of the input path, the second end of the second isolation unit 133 is respectively connected to the gate of the third MOS tube of the m+1th to Nth auxiliary input paths, the first end of the third isolation unit 134 is respectively connected to the second end of the second resistor of the auxiliary input path, and the second end of the third isolation unit 134 is respectively connected to the auxiliary power input end of the m+1th to Nth auxiliary input paths. Specifically, in the auxiliary input path, its power input drives the third MOS in the lower auxiliary input path to turn off through the second isolation unit 133, and is used to prevent the power input of the main power input end from backflowing to the power input end. At the same time, the power input in the auxiliary input path can drive the third MOS tube in the upper auxiliary input path to remain in the off state through the third isolation unit 134.

[0035] Optionally, the second isolation unit 133 includes Nm groups of second diodes, and in the mth auxiliary input path, the anodes of the second diodes are all connected to the auxiliary power input terminal 132 of the auxiliary input path, and the cathodes of the second diodes are respectively connected to the gates of the third MOS tubes of the m+1th to Nth auxiliary input paths. Specifically, the second isolation unit can use a diode, the anode of which is connected to the corresponding auxiliary power input terminal, and is normally turned on when there is power input to the auxiliary power input terminal, and is reversely isolated when there is no power input to the auxiliary power input terminal to prevent signal backflow.

[0036] The third isolation unit 134 includes a third diode of Nm group and a current limiting resistor, wherein the cathode of the third diode of Nm group is connected to the second end of the second resistor of the auxiliary input path through the current limiting resistor, and the anode of the third diode of Nm group is respectively connected to the auxiliary power input terminal of the (m+1)th to (N)th auxiliary input paths. Specifically, the third isolation unit 134 may be a diode, wherein the anode of the diode is connected to the auxiliary power input terminal of the lower auxiliary input path, and the cathode of the diode is connected to the corresponding second resistor and connected to the gate of the third MOS tube through the second resistor.

[0037] Optional, such as Figures 2 to 4 As shown, the first switch unit 121 includes a first MOS transistor, the gate of the first MOS transistor is connected to the main power input terminal 123, the source of the first MOS transistor is grounded, and the drain of the first MOS transistor is connected to the third terminal of the second switch unit 122. The first switch unit 121 can be composed of a first MOS transistor, the gate of which is connected to the main power input terminal 123, and is driven to be turned on by an input voltage at the book power input terminal. The first MOS transistor is an NMOS transistor, which can be turned on when a high level is input to the gate.

[0038] Optionally, the second switch unit 122 includes a second MOS tube and a first resistor, the source of the second MOS tube is connected to the power output terminal 110, the drain of the second MOS tube is connected to the main power input terminal 123, the gate of the second MOS tube is connected to the second end of the first switch unit 121, and the gate of the second MOS tube is connected to the first end of the first resistor, and the second end of the first resistor is connected to the source of the second MOS tube. Specifically, the second switch unit 122 can realize the conduction or disconnection of the main power input terminal 123 and the power output terminal 110 by turning on or off the second MOS tube, wherein the gate of the second MOS tube is connected to the first switch unit 121, and when the first switch unit 121 is turned on, the gate voltage of the second MOS tube is pulled down, and the second MOS tube is turned on. And when the first switch unit 121 is turned off, a high level is provided through the first resistor to turn off the second MOS tube, wherein the second MOS tube can be a PMOS tube.

[0039] In a specific embodiment:

[0040] Embodiment 1, as shown in FIG2, wherein N is 1, that is, there is only one auxiliary input path, wherein VIN_A is the main power input terminal 123, and VIN_B is the auxiliary power input terminal. When VIN_A has power input, the gate of MOS tube QX is high level, MOS tube QX1 is turned on, at this time, the gate level of MOS tube Q1 is pulled down, MOS tube Q1 is turned on, and VIN_A and VOUT are turned on. At the same time, when VIN_A has power input, the gate of MOS tube Q2 is high level, MOS tube Q2 is turned off, and the path between VIN_B and VOUT is in the off state. Regardless of whether VIN_B has power input, its VOUT will not be powered by VIN_B. When VIN_A has no power input, if VIN_B has power input, the gate of MOS tube QX1 is low level, MOS tube QX1 is turned off, the gate level of MOS tube Q1 is high level, MOS tube Q1 is turned off, the gate of MOS tube Q2 is low level, MOS tube Q2 is turned on, and VIN_B is turned on with VOUT. When VOUT and VIN_B are turned on and there is voltage output, the voltage at the output end generates a high level at the gate of MOS tube Q1 through resistor RX, keeping the MOS tube Q1 turned off.

[0041] Embodiment 2, as Figure 3As shown, N is 2, that is, there are two auxiliary input paths, where VIN_A is the main power input terminal 123, VIN_B and VIN_C are auxiliary power input terminals, when VIN_A has power input, the gate of MOS tube QX1 is high level, MOS tube QX1 is turned on, at this time the gate level of MOS tube Q1 is pulled down, MOS tube Q1 is turned on, VIN_A and VOUT are turned on. At the same time, when VIN_A has power input, the gates of MOS tubes Q2 and MOS tubes Q3 are high level, MOS tubes Q2 and MOS tubes Q3 are turned off, at this time the path between VIN_B, VIN_C and VOUT is in the off state, regardless of whether VIN_B and VIN_C have power input, their VOUT will not be powered by VIN_B and VIN_C. When there is no power input to VIN_A, if there is power input to VIN_B, the gate of MOS tube QX1 is low level, MOS tube QX1 is turned off, the gate level of MOS tube Q1 is high level, MOS tube Q1 is turned off, and MOS tube QX2 is high level and turned on, so that the gate of MOS tube Q2 is low level, MOS tube Q2 is turned on, and VIN_B is turned on with VOUT. When there is power input to VIN_B, the gate of MOS tube Q3 is high level, MOS tube Q3 is turned off, and the path between VIN_C and VOUT is turned off. Regardless of whether VIN_C has power input, its VOUT will not be powered by VIN_C. Only when there is no power input to VIN_A and VIN_B, MOS tube QX1, MOS tube QX2, MOS tube Q1 and MOS tube Q2 are all turned off, MOS tube Q3 is turned on, and VIN_C is turned on with VOUT. When VOUT is connected to VIN_B or VIN_C and has a voltage output, the voltage at the output end generates a high level at the gate of the MOS tube Q1 through the resistor RX, maintaining the MOS tube Q1 off. Among them, the diode ZB1 corresponds to the second isolation unit, which is unidirectionally conductive and is used to prevent the signal from being fed back to the VIN_B terminal when VIN_A has an input. Diodes ZA1 and ZA2 correspond to the first isolation unit, which are unidirectionally conductive, wherein ZA2 is used to prevent the signal from being fed back to the VIN_A terminal when VIN_B has an input, and ZA1 is used to prevent the signal from being fed back to the VIN_A terminal when VIN_C has an input. Diode ZC1 corresponds to the third isolation unit, which is unidirectionally conductive and is used to prevent the signal from being fed back to the VIN_C terminal when VIN_A has an input.

[0042] Embodiment three, as Figure 4As shown, N is 3, that is, there are two auxiliary input paths, where VIN_A is the main power input terminal 123, and VIN_B, VIN_C and VIN_D are auxiliary power input terminals. When VIN_A has power input, the gate of MOS tube QX1 is high level, MOS tube QX1 is turned on, and the gate level of MOS tube Q1 is pulled down, MOS tube Q1 is turned on, and VIN_A is turned on with VOUT. At the same time, when VIN_A has power input, the gates of MOS tubes Q2, MOS tubes Q3 and MOS tubes Q4 are high level, MOS tubes Q2, MOS tubes Q3 and MOS tubes Q4 are all turned off, and the paths between VIN_B, VIN_C and VIN_D and VOUT are in the off state. Regardless of whether VIN_B, VIN_C and VIN_D have power input, their VOUT will not be powered by VIN_B, VIN_C and VIN_D. When there is no power input to VIN_A, if there is power input to VIN_B, the gate of MOS tube QX1 is low level, MOS tube QX1 is turned off, the gate level of MOS tube Q1 is high level, MOS tube Q1 is turned off, the gate of MOS tube QX2 is high level, MOS tube QX2 is turned on, so that the gate of MOS tube Q2 is low level, MOS tube Q2 is turned on, and VIN_B is turned on with VOUT. When there is power input to VIN_B, the gates of MOS tubes Q3 and MOS tubes Q4 are high level, MOS tubes Q3 and MOS tubes Q4 are turned off, and the path between VIN_C and VIN_D and VOUT is in the off state. Regardless of whether VIN_C and VIN_D have power input, their VOUT will not be powered by VIN_C and VIN_D. Only when there is no power input to VIN_A and VIN_B, MOS tubes QX1, QX2, Q1 and Q2 are all in the off state. When there is power input to VIN_C, MOS tubes QX3 and Q3 are turned on. At this time, VIN_C and VOUT are turned on, making MOS tube Q4 in the off state. And only when there is no power input to VIN_A, VIN_B and VIN_C, MOS tubes QX1, QX2, QX3, Q1, Q2 and Q3 are all in the off state, MOS tube Q4 is in the on state, and VIN_D and VOUT are turned on. When VOUT is turned on with VIN_B, VIN_C or VIN_D and there is voltage output, the voltage at the output end generates a high level at the gate of MOS tube Q1 through resistor RX, maintaining the MOS tube Q1 off. The diode ZB1 corresponds to the second isolation unit, which is unidirectionally conductive and is used to prevent the signal from being fed back to the VIN_B terminal when VIN_A has an input.Diode ZB2 corresponds to the second isolation unit, which is unidirectionally conducted and used to prevent the VIN_C terminal from generating a signal backflow when VIN_A has an input. Diodes ZA1, ZA2 and ZA2 correspond to the first isolation unit, which are unidirectionally conducted, wherein ZA2 is used to prevent the VIN_A terminal from generating a signal backflow when VIN_B has an input, ZA1 is used to prevent the VIN_A terminal from generating a signal backflow when VIN_C and VIN_D have inputs, and ZA3 is used to prevent the VIN_A terminal from generating a signal backflow when VIN_C has an input. Diode ZC1 corresponds to the third isolation unit, which is unidirectionally conducted and used to prevent the VIN_C terminal from generating a signal backflow when VIN_A has an input, diode ZD1 corresponds to the third isolation unit, which is unidirectionally conducted and used to prevent the VIN_D terminal from generating a signal backflow when VIN_A has an input, and diode ZD2 corresponds to the third isolation unit, which is unidirectionally conducted and used to prevent the VIN_D terminal from generating a signal backflow when VIN_B has an input.

[0043] In addition, an electronic device of the present invention includes any of the above zero-power switching circuits. The zero-power switching circuit can reduce the overall power consumption of the electronic device.

[0044] It can be understood that the above embodiments only express the preferred implementation modes of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the patent scope of the present invention. It should be pointed out that, for ordinary technicians in this field, without departing from the concept of the present invention, the above technical features can be freely combined, and several deformations and improvements can be made, which all belong to the protection scope of the present invention. Therefore, all equivalent changes and modifications made to the scope of the claims of the present invention should belong to the scope covered by the claims of the present invention.

Claims

1. A zero-power switching circuit, It is characterized in that include: A power output terminal, a main input path, and N auxiliary input paths including a first auxiliary input path to an Nth auxiliary input path, wherein N is greater than or equal to 1; The main input path includes a main power input terminal, a first switch unit and a second switch unit; the first terminal of the first switch unit is grounded, the second terminal of the first switch unit is connected to the power output terminal, the third terminal of the first switch unit is connected to the main power input terminal, and is used to drive the first switch unit to conduct when there is an input voltage at the main power input terminal, the first terminal of the second switch unit is connected to the main power input terminal, the second terminal of the second switch unit is connected to the power output terminal, and the third terminal of the second switch unit is connected to the second terminal of the first switch unit, so that the input of the main power input terminal supplies power to the third terminal of the second switch unit through the first switch unit to drive the second switch unit to conduct; Each of the auxiliary input paths includes an auxiliary power input terminal and a third switch unit. In any nth auxiliary input path, where n is less than or equal to N, a first terminal of the third switch unit is connected to the auxiliary power input terminal corresponding to the auxiliary input path, a second terminal of the third switch unit is connected to the power output terminal, and a third terminal of the third switch unit is respectively connected to the main input path, so as to drive the third switch unit to be in an off state when there is an input voltage at the main power input terminal. When N is greater than 1, the first to N-1th auxiliary input paths further include a fourth switch unit, a first end of the fourth switch unit is connected to a third end of the third switch unit, a second end of the fourth switch unit is grounded, and a third end of the fourth switch unit is connected to an auxiliary power input end of the auxiliary input path, so that when there is power input at the auxiliary power input end, the fourth switch unit is driven to conduct through the power input at the auxiliary power input end; When n is greater than 1, the third end of the third switch unit in the nth auxiliary input path is also connected to the auxiliary power input ends of the first to n-1th auxiliary input paths and the n+1th to Nth auxiliary input paths, respectively, so that when no auxiliary input path in the first to n-1th auxiliary input paths is powered on, the third switch unit of the nth auxiliary input path is maintained in a conductive state through the conductive fourth switch unit, and at the same time, the third switch units in the n+1th to Nth auxiliary input paths are driven to a closed state by the power supply of the nth auxiliary input path; The conduction priority of the auxiliary input paths is implemented in the order of the first to the Nth auxiliary input paths.

2. The zero-power switching circuit according to claim 1, It is characterized in that The first switch unit includes a first MOS tube, a gate of the first MOS tube is connected to the main power input terminal, a source of the first MOS tube is grounded, and a drain of the first MOS tube is connected to the third terminal of the second switch unit.

3. The zero-power switching circuit according to claim 2, It is characterized in that The first MOS tube is an NMOS tube.

4. The zero-power switching circuit according to claim 1, It is characterized in that The second switch unit includes a second MOS tube and a first resistor, the source of the second MOS tube is connected to the power output end, the drain of the second MOS tube is connected to the main power input end, the gate of the second MOS tube is connected to the second end of the first switch unit, and the gate of the second MOS tube is connected to the first end of the first resistor, and the second end of the first resistor is connected to the source of the second MOS tube.

5. The zero-power switching circuit according to claim 4, It is characterized in that The second MOS tube is a PMOS tube.

6. The zero-power switching circuit according to claim 1, It is characterized in that In any nth auxiliary input path, the third switch unit includes a third MOS tube and a second resistor; the drain of the third MOS tube is connected to the auxiliary power input terminal of the auxiliary input path, the source of the third MOS tube is connected to the power output terminal, and when N is 1, the gate of the third MOS tube is connected to the main power input terminal and the first end of the second resistor, and the second end of the second resistor is grounded.

7. The zero-power switching circuit according to claim 6, It is characterized in that When N is greater than 1, In any m-th auxiliary input path, where m is less than N, the fourth switch unit includes a fourth MOS transistor, a gate of the fourth MOS transistor is connected to an auxiliary power input terminal of the auxiliary input path, a source of the fourth MOS transistor is grounded, and a drain of the fourth MOS transistor is connected to the second end of the second resistor; The main input path includes a first isolation unit, a first end of the first isolation unit is connected to the main power input end, and a second end of the first isolation unit is respectively connected to the gates of the third MOS transistors in the first to Nth auxiliary input paths.

8. The zero-power switching circuit according to claim 7, It is characterized in that The first to N-1th auxiliary input paths further include a second isolation unit and a third isolation unit, respectively; in any mth auxiliary input path, the first end of the second isolation unit is respectively connected to the auxiliary power input end of the input path, the second end of the second isolation unit is respectively connected to the gate of the third MOS tube of the m+1th to Nth auxiliary input paths, the first end of the third isolation unit is respectively connected to the second end of the second resistor of the auxiliary input path, and the second end of the third isolation unit is respectively connected to the auxiliary power input end of the m+1th to Nth auxiliary input paths.

9. The zero-power switching circuit according to claim 7, It is characterized in that The first isolation unit includes N groups of first diodes; anodes of the N groups of first diodes are all connected to the main power input terminal, and cathodes of the N groups of first diodes are respectively connected to the gates of the third MOS tubes of the first to Nth auxiliary input paths.

10. The zero-power switching circuit according to claim 8, It is characterized in that In the mth auxiliary input path, the second isolation unit includes Nm groups of second diodes, the anodes of the Nm groups of second diodes are all connected to the auxiliary power input terminal of the auxiliary input path, and the cathodes of the Nm groups of second diodes are respectively connected to the gates of the third MOS transistors of the (m+1)th to the (N)th auxiliary input paths; and / or The third isolation unit includes Nm groups of third diodes and current limiting resistors, the cathodes of the Nm groups of third diodes are connected to the second end of the second resistor of the auxiliary input path through the current limiting resistor, and the anodes of the Nm groups of third diodes are respectively connected to the auxiliary power supply input ends of the (m+1)th to the (N)th auxiliary input paths.

11. An electronic device, It is characterized in that Comprising a zero-power switching circuit as described in any one of claims 1 to 10.

Images