A capacitance-voltage conversion circuit

Abstract

This invention discloses a capacitor-to-voltage conversion circuit, comprising a first operational amplifier, two compensation capacitors, two holding capacitors, multiple switches, a first clock signal, and a second clock signal. The first operational amplifier is a differential amplifier with dual-ended input and dual-ended output. The two input terminals of the capacitor-to-voltage conversion circuit are respectively connected to the differential input terminals of the first operational amplifier, namely nodes b5 and b6, through the compensation capacitors. One end of the first holding capacitor is connected to node b5 or a reference potential through a switch, and the other end is connected to the negative signal terminal of the differential output terminal. One end of the second holding capacitor is connected to node b6 or a reference potential through a switch, and the other end is connected to the positive signal terminal of the differential output terminal. The switching is controlled by the first clock signal and the second clock signal, realizing the conversion between the sampling phase and the amplification phase of this conversion circuit. The capacitor-to-voltage conversion circuit of this invention has the characteristics of large signal bandwidth, excellent dynamic range, and low power consumption, and can meet the accuracy requirements.

Description

Technical Field

[0001] The invention relates to the application field of gyroscopes, and in particular to a capacitance-voltage conversion circuit. Background Art

[0002] In recent years, with the rapid development of micromechanical systems (MEMS), capacitive MEMS gyroscopes have been widely used in satellite, vehicle-mounted, deep-sea and other inertial navigation systems due to their advantages such as low power consumption, low temperature drift, high precision and compatibility with CMOS processes. As a sensor transducer unit, the capacitive MEMS gyroscope converts angular velocity into differential capacitance variables. In order to perform subsequent data processing, it is necessary to add an analog front-end circuit (mainly including capacitance-voltage conversion circuit and Sigma delta analog-to-digital converter) between the processor and the MEMS gyroscope to convert the physical quantity of capacitance into digital quantity. As the first-level capacitance-voltage conversion circuit of the analog front-end circuit, its parameters such as noise floor, dynamic range, linearity, and settling time are the key to the success of the system. Summary of the invention

[0003] The purpose of the present invention is to provide a capacitance-voltage conversion circuit with large signal bandwidth, excellent dynamic range, low power consumption and satisfactory accuracy.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] A capacitance-voltage conversion circuit comprises a source differential input terminal, a source differential output terminal, a fully differential amplifier circuit unit, a first clock signal input terminal and a second clock signal input terminal; the first clock signal input terminal and the second clock signal input terminal are respectively used to input a first clock signal clk1 and a second clock signal clk2; the fully differential amplifier circuit unit comprises a first operational amplifier, a switch S25, a switch S26, a switch S34, a switch S35, a compensation capacitor Cc1, a compensation capacitor Cc2, a holding capacitor CH1, and a holding capacitor CH2; the first operational amplifier is a differential amplifier, comprising a differential input terminal and a differential output terminal; the negative signal terminal of the differential input terminal of the first operational amplifier is connected to a node b5, and the positive signal terminal of the differential input terminal of the first operational amplifier is connected to a node b6; the two ends of the compensation capacitor Cc1 are respectively connected to a node b5 and a node a1, and the node a1 is connected to the positive signal terminal of the source differential input terminal; the compensation capacitor Cc1 is ... The two ends of capacitor Cc2 are connected to node b6 and node a2 respectively, and node a2 is connected to the negative signal end of the source differential input end; the two ends of holding capacitor CH1 are connected to node b4 and node a4 respectively; the two ends of switch S25 are connected to node a4 and reference potential Vref respectively; the two ends of switch S26 are connected to node a4 and node b5 respectively; the two ends of holding capacitor CH2 are connected to node b7 and node a7 respectively; the two ends of switch S34 are connected to node a7 and reference potential Vref respectively; the two ends of switch S35 are connected to node a7 and node b6 respectively; the switch S26 and the switch S35 are controlled by the first clock signal clk1; the switch S25 and the switch S34 are controlled by the second clock signal clk2; the first clock signal clk1 and the second clock signal clk2 are used to realize the conversion between the sampling phase and the amplification phase of the capacitor-voltage conversion circuit.

[0006] Technical effect: One end of the compensation capacitors Cc1 and Cc2 is connected to the reference potential Vref in the sampling phase, and one end of the holding capacitors CH1 and CH2 is also connected to the reference potential Vref in the amplification phase. Therefore, a real "virtual ground point" is formed at the input end of the first operational amplifier U1 in the next sampling phase cycle, and one end of the holding capacitors CH1 and CH2 is connected to the reference potential Vref in the amplification phase, and the other end maintains the output voltage value of the first operational amplifier U1 in the previous amplification phase, eliminating the zeroing operation in the traditional structure, which is conducive to the rapid establishment of the output voltage in this cycle.

[0007] Further, the fully differential amplifier circuit unit also includes a first gain capacitor array, a second gain capacitor array, a switch S18, a switch S27, a switch S23, a switch S24, a switch S32, and a switch S33;

[0008] The circuit configuration of the first gain capacitor array and the second gain capacitor is the same; one end of the first gain capacitor array is connected to the node a1, and is connected to the reference potential Vref through the switch S18; the other end is connected to the node b4 through the switch S24, and is connected to the reference potential Vref through the switch S23; one end of the second gain capacitor array is connected to the node a2, and is connected to the reference potential Vref through the switch S27; the other end is connected to the node b7 through the switch S33, and is connected to the reference potential Vref through the switch S32; the switch S18, the switch S23, the switch S27, and the switch S32 are controlled by the first clock signal clk1; the switch S24 and the switch S33 are controlled by the second clock signal clk2.

[0009] Furthermore, the gain capacitor array includes a basic gain capacitor and multiple extended gain capacitors, each of the extended gain capacitors is connected in series with a switch and then in parallel with the basic gain capacitor, and the capacitance of the gain capacitor array is adjusted by selecting the switch.

[0010] Further, the first operational amplifier includes a transistor M0, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, and a transistor M10; the first operational amplifier includes a differential input terminal, a differential output terminal, and a plurality of control input terminals; the differential input terminal of the first operational amplifier is used to input a signal Vin and a signal Vip; the differential output terminal of the first operational amplifier is used to output a signal Voutp and a signal Voutn; the control input terminal of the first operational amplifier is used to input a control signal, including: a signal Vbtail, a signal Vcnfbout, a signal Vb1, a signal Vb2, a signal Vb3, and a reference potential Vref; the circuit connection relationship of the internal circuit of the first operational amplifier is: the gate of the transistor M0 is connected to the signal Vbtail, the source is grounded, and the drain is connected to a node t6; the gate of the transistor M1 is connected to the signal Vin, the source node t6, and the drain node t5; the gate of the transistor M2 is connected to the signal The gate of the transistor M3 is connected to the signal Vb1, the source is grounded, and the drain is connected to the source of the transistor M5; the gate of the transistor M4 is connected to the signal Vb1, the source is grounded, and the drain is connected to the source of the transistor M6; the gate of the transistor M5 is connected to the signal Vb2, the source is connected to the drain of the transistor M3, and the drain is connected to the node t8, and the signal Voutp is connected to the node t8; the gate of the transistor M6 is connected to the signal Vb2, the source is connected to the transistor M6, and the drain is connected to the transistor M7. The drain of transistor M4 and the drain node t9, the signal Voutn node t9; the gate of transistor M7 is connected to the signal Vb3, the source node t5, and the drain node t8; the gate of transistor M8 is connected to the signal Vb3, the source node t7, and the drain node t9; the gate of transistor M9 is connected to the signal Vcmfout, the source is connected to the power supply potential, and the drain node t5; the gate of transistor M10 is connected to the signal Vcmfout, the source is connected to the power supply potential, and the drain node t7.

[0011] Further, the first operational amplifier also includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a switch S36, a switch S37, a switch S38, a switch S39, a switch S40, a switch S41, a third clock signal input terminal, and a fourth clock signal input terminal; the circuit connection relationship of the internal circuit of the first operational amplifier also includes: the signal Voutn is connected to the node r1; the signal Voutp is connected to the node r3; the two ends of the capacitor C1 are respectively connected to the node r1 and the node r2; the two ends of the capacitor C2 are respectively connected to the node r2 and the node r3; the two ends of the capacitor C3 are respectively connected to the node r4 and the node r5; the two ends of the capacitor C4 are respectively connected to the node r5 and the node r6; the two ends of the switch S36 are respectively connected to the node r1 and the node r4; the two ends of the switch S37 are respectively connected to the node r4 and the signal Vcm; The two ends of switch S38 are respectively connected to node r2 and node r5; the two ends of switch S39 are respectively connected to node r5 and reference potential Vref; the two ends of switch S40 are respectively connected to node r3 and node r6; the two ends of switch S41 are respectively connected to node r6 and signal Vcm; the third clock signal input end and the fourth clock signal input end are respectively used to input the third clock signal clk1a and the fourth clock signal clk2a, the third clock signal clk1a is an early shutdown signal of the first clock signal clk1, and the fourth clock signal clk2a is an early shutdown signal of the second clock signal clk2; the opening of switch S36, switch S38 and switch S40 is controlled by the third clock signal clk1a, and the opening of switch S37, switch S39 and switch S41 is controlled by the fourth clock signal clk2a.

[0012] Technical effect: The fully differential operational amplifier of the present invention adopts a double-ended input and double-ended output folded common source and common gate structure, which can provide a large output swing. Two early shutdown clock signals clk1a and clk2a are set in the fully differential amplifier, which reduces the charge sharing effect on the capacitors CH1 and CH2 during the amplification phase and improves the output signal accuracy.

[0013] Furthermore, it also includes an input common-mode feedback amplifier circuit unit, which includes a second operational amplifier, a switch S4, a first feedback capacitor and a second feedback capacitor, the second operational amplifier includes a differential input terminal and an output terminal; the two ends of the differential input terminal of the second operational amplifier are respectively connected to the two ends of the source differential input terminal; the output terminal of the second operational amplifier is respectively connected to the two ends of the source differential input terminal through the first feedback capacitor, the second feedback capacitor and the two ends of the source differential input terminal, and is connected to the reference potential Vref through the switch S4; the switch S4 is controlled by the first clock signal clk1.

[0014] Technical effect: The common-mode value of the two differential input terminals of the second operational amplifier U2 is compared with the voltage value of the reference potential Vref, thereby eliminating the error charge generated in this part, thereby ensuring the stability of the input common-mode voltage of the second operational amplifier U2 and effectively suppressing the thermal noise caused by the common-mode voltage drift.

[0015] Furthermore, the input common-mode feedback amplifier circuit unit further includes a switch S3 and a switch S5, and the two ends of the source differential input terminal are respectively connected to a reference potential Vref through the switch S3, the switch S5, and the switch S3 and the switch S5 are controlled by a first clock signal clk1.

[0016] Further, the internal circuit of the second operational amplifier includes a transistor M0, a transistor M1a, a transistor M1b, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, and a transistor M10; the differential input terminal of the second operational amplifier includes a differential input terminal, an output terminal, and a plurality of control input terminals; the differential input terminal of the second operational amplifier is used for inputting a signal Vin2 and a signal Vip2; the output terminal of the second operational amplifier is used for outputting a signal Vo utp2; the control input terminal of the second operational amplifier is used to input control signals, including: signal Vbp1, signal Vbp2, signal Vbn1, signal Vbn2 and reference potential Vref; the gate of the transistor M0 is connected to the signal Vbn2, the source is grounded, and the drain is connected to the node t2; the gate of the transistor M1a is connected to the signal Vin2, the source is connected to the node t2, and the drain is connected to the node t1; the gate of the transistor M1b is connected to the signal Vip2, the source is connected to the node t2, and the drain is connected to the node t1; the transistor M2 The gate of the transistor M3 is connected to the reference potential Vref, the source is connected to the node t2, and the drain is connected to the node t3; the gate of the transistor M3 is connected to the node t4, the source is grounded, and the drain is connected to the source of the transistor M5; the gate of the transistor M4 is connected to the node t4, the source is grounded, and the drain is connected to the source of the transistor M6; the gate of the transistor M5 is connected to the signal Vbn1, the source is connected to the drain of the transistor M3, and the drain is connected to the node t5; the signal Voutp2 is connected to the node t5; the gate of the transistor M6 is connected to the signal Vbn1 , the source is connected to the drain of the transistor M4 and the drain node t4; the gate of the transistor M7 is connected to the signal Vbp2, the source node t1, and the drain node t5; the signal Voutp2 node t5; the gate of the transistor M8 is connected to the signal Vbp2, the source node t3, and the drain node t4; the gate of the transistor M9 is connected to the signal Vbp1, the source is connected to the power supply potential, and the drain node t1; the gate of the transistor M10 is connected to the signal Vbp1, the source is connected to the power supply potential, and the drain node t3.

[0017] Furthermore, it also includes a compensation capacitor array, which includes a first sub-capacitor array and a second sub-capacitor array, and the circuit configuration of the first sub-capacitor array and the second sub-capacitor array is the same; one end of the first sub-capacitor array and one end of the second sub-capacitor array are connected to node b2, and the node b2 is connected to the ground potential through switch S16, and is connected to the reference potential through switch S17; the other end of the first sub-capacitor array and the other end of the second sub-capacitor array are respectively connected to the two ends of the source differential input terminal; the switch S16 is controlled by the second clock signal clk2, and the switch S17 is controlled by the first clock signal clk1.

[0018] Furthermore, the sub-capacitor array includes a basic compensation capacitor and a plurality of extended compensation capacitors, each of the extended compensation capacitors is connected in series with a switch and then connected in parallel with the basic compensation capacitor, and the capacitance of the sub-capacitor array is adjusted by turning on the switch.

[0019] Technical effect: The compensation capacitor array can select the compensation capacitor by controlling the switch to form different capacitance values ​​to compensate for the parasitic capacitance and eliminate gain error and DC offset.

[0020] The present invention achieves the following technical effects:

[0021] The capacitor-to-voltage conversion circuit proposed in the patent of this invention adopts a two-step approximation circuit strategy combining a compensation capacitor and a holding capacitor for differential amplification, which can effectively reduce the impact of 1 / A error and realize a capacitor-to-voltage conversion circuit with large signal bandwidth, excellent dynamic range, low power consumption and satisfactory accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a principle block diagram of the capacitance-voltage conversion circuit of the present invention;

[0023] Figure 2 It is an embodiment of the circuit diagram of the capacitance-voltage conversion circuit of the present invention;

[0024] Figure 3 This is the internal circuit diagram of the first op amp;

[0025] Figure 4 This is the internal circuit diagram of the second op amp. DETAILED DESCRIPTION

[0026] To further illustrate the various embodiments, the present invention provides drawings. These drawings are part of the disclosure of the present invention, which are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, a person of ordinary skill in the art should be able to understand other possible implementations and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0027] The present invention will now be further described with reference to the accompanying drawings and specific implementation methods.

[0028] like Figure 1 As shown, the present invention discloses a capacitance-voltage conversion circuit, including a source differential input terminal, a source differential output terminal, a compensation capacitor array Ccin, an input common-mode feedback amplifier circuit unit, a fully differential amplifier circuit unit, a first clock signal input terminal and a second clock signal input terminal; wherein the differential input signal of the source differential input terminal is identified as inp, inn, and the differential output signal of the source differential output terminal is identified as: vop, von. The two ends of the compensation capacitor array are connected across the source differential input end; the input common-mode feedback amplifier circuit unit includes a differential input end, two feedback signal input ends, an output end and a plurality of switches, the differential input end is respectively connected to the two ends of the source differential input end, the two feedback signal input ends are respectively connected to the two ends of the source differential input end, and its output end is connected to the reference potential Vref; the fully differential amplifier circuit unit includes a differential input end, a differential output end and a plurality of switches, the differential input end of the fully differential amplifier circuit unit is connected to the source differential input end, and the two ends of the differential output end of the fully differential amplifier circuit unit are respectively connected to the two ends of the source differential output end; the first clock signal input end and the second clock signal input end are used to input a first clock signal clk1 and a second clock signal clk2, the first clock signal clk1 and the second clock signal clk2 are used to control the switches in the input common-mode feedback amplifier circuit unit and the fully differential amplifier circuit unit to realize the conversion between the sampling phase and the amplification phase of the capacitance-voltage conversion circuit.

[0029] In such Figure 2 In the illustrated embodiment, the fully differential amplifier circuit unit includes: a first operational amplifier U1, a switch S26, a switch S35, a compensation capacitor Cc1, a compensation capacitor Cc2, a holding capacitor CH1, and a holding capacitor CH2; wherein the first operational amplifier U1 is a differential amplifier with a differential output;

[0030] The circuit connection relationship of this part of the circuit unit is:

[0031] The negative signal terminal of the differential input terminal of the first operational amplifier U1 is connected to the node b5, and the positive signal terminal of the differential input terminal is connected to the node b6;

[0032] The differential output terminal of the first operational amplifier U1 is the differential output terminal of the fully differential amplifier circuit unit, the negative signal terminal of the differential output terminal of the first operational amplifier U1 is connected to the negative signal terminal von of the source differential output terminal, and the positive signal terminal of the differential output terminal is connected to the positive signal terminal vop of the source differential output terminal;

[0033] The two ends of the feedback capacitor Cc1 are connected to the node b5 and the node a1 respectively, and the node a1 is connected to the positive signal terminal inp of the source differential input terminal;

[0034] The two ends of the feedback capacitor Cc2 are connected to the node b6 and the node a2 respectively, and the node a2 is connected to the negative signal terminal inn of the source differential input terminal;

[0035] The two ends of the holding capacitor CH1 are connected to the node b4 and the node a4 respectively; the two ends of the switch S25 are connected to the node a4 and the reference potential Vref respectively; the two ends of the switch S26 are connected to the node a4 and the node b5 respectively; wherein the node b4 is connected to the negative signal end of the differential output end of the first operational amplifier U1;

[0036] The two ends of the holding capacitor CH2 are connected to the node b7 and the node a7 respectively; the two ends of the switch S34 are connected to the node a7 and the reference potential Vref respectively; the two ends of the switch S35 are connected to the node a7 and the node b6 respectively; wherein the node b7 is connected to the positive signal end of the differential output end of the first operational amplifier U1;

[0037] The opening of the switch S26 and the switch S35 is controlled by the first clock signal clk1;

[0038] The opening of the switch S25 and the switch S34 is controlled by the second clock signal clk2.

[0039] In such Figure 2 In the illustrated embodiment, the input common-mode feedback amplifier circuit unit includes: a second operational amplifier U2, a switch S4, a feedback capacitor Cic1 and a feedback capacitor Cic2, wherein the second operational amplifier U2 is a differential amplifier.

[0040] The circuit connection relationship of this part of the circuit unit is:

[0041] Two ends of the differential input terminal of the second operational amplifier U2 are connected to the node a1 and the node a2 respectively;

[0042] The output end of the second operational amplifier U2 is connected to the node b1, which is connected to the node a1 through the feedback capacitor Cic1 and to the node a2 through the feedback capacitor Cic2; it is connected to the reference potential Vref through the switch S4; wherein the opening of the switch S4 is controlled by the first clock signal clk1.

[0043] The input common-mode feedback amplifier circuit unit further includes a switch S3 and a switch S5. The two ends of the source differential input terminal are connected to the reference potential Vref through the switch S3, the switch S5, respectively. The opening of the switch S3 and the switch S5 is controlled by the first clock signal clk1.

[0044] carrier_input is a carrier modulation signal, which is output to an off-chip gyroscope. carrier_input is connected to the ground point through switch S1 and to the reference potential Vref through switch S2, wherein the opening of switch S1 is controlled by clk1 and the opening of switch S2 is controlled by clk2.

[0045] Working principle:

[0046] Switches S1-S5, S16-S18, S23-S27, and S32-S35 control the conversion between the sampling phase and the amplification phase of the capacitor-to-voltage conversion circuit. When clk1=1 and clk2=0, the switch controlled by the first clock signal clk1 is opened (closed), and the capacitor-to-voltage conversion circuit enters the sampling phase; when clk1=0 and clk2=1, the switch controlled by the first clock signal clk1 is opened, and the switch controlled by the second clock signal clk2 is opened (closed), and the capacitor-to-voltage conversion circuit enters the amplification phase.

[0047] The feedback loop composed of feedback capacitors Cic1, Cic2 and the second operational amplifier U2 forms a three-input, single-ended output folded common-source common-gate structure, which can compare the common-mode value of the two differential input terminals of the second operational amplifier U2 with the voltage value of the reference potential Vref, and eliminate the error charge generated by this part, thereby ensuring the stability of the input common-mode voltage of the second operational amplifier U2 while also effectively suppressing the thermal noise caused by the common-mode voltage drift; the two-step approximation circuit strategy combining compensation capacitors Cc1, Cc2 and holding capacitors CH1, CH2 avoids the output voltage from returning to the zero state in the two-phase clock, thereby realizing high-speed and high-precision signal output.

[0048] The left plates of the compensation capacitors Cc1 and Cc2 are connected to the reference potential Vref in the sampling phase, and the left plates of the holding capacitors CH1 and CH2 are also connected to the reference potential Vref in the amplification phase. Therefore, a real "virtual ground point" is formed at the input end of the first operational amplifier U1 in the next sampling phase cycle, and the left plates of the holding capacitors CH1 and CH2 are connected to the reference potential Vref in the amplification phase, and the right plates maintain the output voltage value of the first operational amplifier U1 in the previous amplification phase, eliminating the zeroing operation in the traditional structure, which is conducive to the rapid establishment of the output voltage in this cycle.

[0049] The compensation capacitor array Ccin can select compensation capacitors by controlling switches S6-S10 and S11-S15 to form different capacitance values ​​to compensate for the parasitic capacitance generated by the gyroscope and bonding, and eliminate gain error and DC offset.

[0050] In the sampling phase, both plates of the gain capacitor array Ci are connected to the reference potential Vref, which will eliminate the residual charge of the amplification phase of the previous cycle. Different gain capacitors are selected by controlling switches S19-S22 and S28-S31 to achieve continuous gain adjustment of the circuit.

[0051] In the present invention, an internal circuit example of a first operational amplifier U1 is provided, such as Figure 3 As shown. The first operational amplifier U1 is a fully differential operational amplifier. In this example, it includes capacitors C1-C4, switches S36-S41, and transistors M0-M10. The input of the first operational amplifier U1 includes signals Vin, Vip, Vbtail, Vcnfbout, Vb1, Vb2, Vb3, and reference potential Vref. The differential output of the first operational amplifier U1 includes signals Voutp and Voutn. Among them, signal Vbtail is the output voltage of transistor M0 (tail). The gate bias voltage of the transistor M3 and the transistor M4 is used to make the transistors M3 and M4 work in the saturation region; the gate bias voltage of the transistor M5 and the transistor M6 is used to make the transistors M5 and M6 work in the saturation region; the gate bias voltage of the transistor M7 and the transistor M8 is used to make the transistors M7 and M8 work in the saturation region.

[0052] The specific circuit connection is as follows:

[0053] Signal Voutn is connected to node r1;

[0054] Signal Voutp is connected to node r3;

[0055] The two ends of capacitor C1 are connected to node r1 and node r2 respectively;

[0056] Two ends of capacitor C2 are connected to node r2 and node r3 respectively;

[0057] Two ends of capacitor C3 are connected to node r4 and node r5 respectively;

[0058] Two ends of capacitor C4 are connected to node r5 and node r6 respectively;

[0059] The two ends of the switch S36 are connected to the node r1 and the node r4 respectively;

[0060] The two ends of the switch S37 are connected to the node r4 and the signal Vcm respectively;

[0061] The two ends of the switch S38 are connected to the node r2 and the node r5 respectively;

[0062] Two ends of the switch S39 are connected to the node r5 and the reference potential Vref respectively;

[0063] Two ends of the switch S40 are connected to the node r3 and the node r6 respectively;

[0064] The two ends of the switch S41 are connected to the node r6 and the signal Vcm respectively;

[0065] The gate of transistor M0 is connected to the signal Vbtail, the source is grounded, and the drain is connected to the node t6;

[0066] The gate of transistor M1 is connected to the signal Vin, the source is connected to the node t6, and the drain is connected to the node t5;

[0067] The gate of transistor M2 is connected to signal Vip, the source is connected to node t6, and the drain is connected to node t7;

[0068] The gate of the transistor M3 is connected to the signal Vb1, the source is connected to the ground potential, and the drain is connected to the source of the transistor M5;

[0069] The gate of the transistor M4 is connected to the signal Vb1, the source is connected to the ground potential, and the drain is connected to the source of the transistor M6;

[0070] The gate of transistor M5 is connected to the signal Vb2, the source is connected to the drain of transistor M3, the drain is connected to the node t8, and the signal outp is connected to the node t8;

[0071] The gate of transistor M6 is connected to the signal Vb2, the source is connected to the drain of transistor M4, the drain is connected to the node t9, and the signal outn is connected to the node t9;

[0072] The gate of transistor M7 is connected to the signal Vb3, the source is connected to the node t5, and the drain is connected to the node t8;

[0073] The gate of transistor M8 is connected to the signal Vb3, the source is connected to the node t7, and the drain is connected to the node t9;

[0074] The gate of transistor M9 is connected to the signal Vcmfout, the source is connected to the power supply potential, and the drain is connected to the node t5;

[0075] The gate of the transistor M10 is connected to the signal Vcmfout, the source is connected to the power supply potential, and the drain is connected to the node t7.

[0076] The fully differential operational amplifier adopts a double-ended input and double-ended output folded common source and common gate structure, which can provide a large output swing. Two early shutdown clock signals, clk1a and clk2a, are set in the fully differential amplifier to reduce the charge sharing effect on the capacitors CH1 and CH2 during the amplification phase (clk1=0, clk2=1), thereby improving the output signal accuracy.

[0077] How the two-step approximation works:

[0078] In the sampling phase (clk1=1, clk2=0), the left plates of the compensation capacitors Cc1 and Cc2 sample the voltage value of the reference potential Vref, and the right plates are connected to the input of the first operational amplifier U1 and the left plates of the holding capacitors CH1 and CH2. Because the right plates of the holding capacitors CH1 and CH2 are connected to the output terminals von and vop of the first operational amplifier U1, respectively, and the left plates are connected to the reference potential Vref in the amplification phase (clk1=0, clk2=1) of the previous cycle, in the sampling phase (clk1=1, clk2=0) of this cycle, the reference voltage held by the left plates of CH1 and CH2 is transmitted to the right plates of Cc1 and Cc2 and the input of the first operational amplifier U1. This mechanism makes the input of the first operational amplifier U1 a real "virtual ground point" (due to the clamping effect of the reference potential Vref, the offset generated at the input of the first operational amplifier U1 is eliminated). At the same time, both plates of the gain capacitor array Ci are connected to the reference potential Vref to eliminate the residual charge of the amplification phase of the previous cycle.

[0079] In the amplification phase (clk1=0, clk2=1), the left plate of the gain capacitor array Ci is connected to the input of the first operational amplifier U1, and the right plate is connected to the output of the first operational amplifier U1, forming ΔC / C i ratio relationship, and amplification operation is performed. At the same time, the left plates of CH1 and CH2 are connected to the reference potential Vref, and the right plates maintain the output voltage value of the previous amplification phase (clk1=0, clk2=1), eliminating the zeroing operation in the traditional structure, thereby realizing a two-step approximation circuit strategy, which is conducive to the rapid establishment of the output voltage in this cycle.

[0080] In the present invention, an internal circuit example of the second operational amplifier U2 is provided, such as Figure 4The second operational amplifier U2 is an input common-mode feedback operational amplifier, including transistors M0, M1a, M1b, M2, M3, M4, M5, M6, M7, M8, M9, and M10. The input common-mode feedback operational amplifier includes a differential input terminal, an output terminal and a plurality of control input terminals, wherein the differential input terminal inputs signals Vin2 and Vip2; the output terminal outputs signal outp2; the control input terminal inputs signals Vbp1, Vbp2, Vbn1, Vbn2 and reference potential Vref; wherein signal Vbp1 is the gate bias voltage of transistors M9 and M10, so that transistors M9 and M10 work in a saturation region; signal Vbp2 is the gate bias voltage of transistors M7 and M8, so that transistors M7 and M8 work in a saturation region; signal Vbn1 is the gate bias voltage of transistors M5 and M6, so that transistors M5 and M6 work in a saturation region; signal Vbn2 is the gate bias voltage of transistor M0, so that transistors M0 and M10 work in a saturation region.

[0081] The specific circuit connection is as follows:

[0082] The gate of transistor M0 is connected to the signal Vbn2, the source is grounded, and the drain is connected to the node t2;

[0083] The gate of transistor M1a is connected to signal Vin2, the source is connected to node t2, and the drain is connected to node t1;

[0084] The gate of transistor M1b is connected to signal Vip2, the source is connected to node t2, and the drain is connected to node t1;

[0085] The gate of transistor M2 is connected to the signal Vref, the source is connected to the node t2, and the drain is connected to the node t3;

[0086] The gate of the transistor M3 is connected to the node t4, the source is connected to the ground potential, and the drain is connected to the source of the transistor M5;

[0087] The gate of the transistor M4 is connected to the node t4, the source is connected to the ground potential, and the drain is connected to the source of the transistor M6;

[0088] The gate of transistor M5 is connected to the signal Vbn1, the source is connected to the drain of transistor M3, and the drain is connected to the node t5; the signal outp2 is connected to the node t5;

[0089] The gate of transistor M6 is connected to the signal Vbn1, the source is connected to the drain of transistor M4, and the drain is connected to the node t4;

[0090] The gate of transistor M7 is connected to the signal Vbp2, the source is connected to the node t1, and the drain is connected to the node t5; the signal outp2 is connected to the node t5;

[0091] The gate of transistor M8 is connected to the signal Vbp2, the source is connected to the node t3, and the drain is connected to the node t4;

[0092] The gate of transistor M9 is connected to the signal Vbp1, the source is connected to the power supply potential, and the drain is connected to the drain node t1 of transistor M1a;

[0093] The gate of the transistor M10 is connected to the signal Vbp1, the source is connected to the power supply potential, and the drain is connected to the node t3.

[0094] The input common-mode feedback operational amplifier circuit proposed in the present invention adopts a three-input, single-ended output folded common-source common-gate structure, which can compare the common-mode value of the two differential input terminals of the main operational amplifier with the reference voltage and eliminate the error charge generated by this part, thereby ensuring the stability of the common-mode voltage input of the main operational amplifier and effectively suppressing the thermal noise caused by the common-mode voltage drift.

[0095] The capacitor-to-voltage conversion circuit proposed in the patent of this invention adopts a two-step approximation circuit strategy combining a compensation capacitor and a holding capacitor for differential amplification, which can effectively reduce the impact of 1 / A error and realize a capacitor-to-voltage conversion circuit with large signal bandwidth, excellent dynamic range, low power consumption and satisfactory accuracy.

[0096] Although the present invention has been specifically shown and described in conjunction with the preferred embodiments, it should be understood by those skilled in the art that various changes may be made to the present invention in form and details without departing from the spirit and scope of the present invention as defined by the appended claims, all of which are within the scope of protection of the present invention.

Claims

1. A capacitance-voltage conversion circuit, characterized in that: It includes a source differential input terminal, a source differential output terminal, a compensation capacitor array, an input common-mode feedback amplifier circuit unit, a fully differential amplifier circuit unit, a first clock signal input terminal and a second clock signal input terminal; The first clock signal input terminal and the second clock signal input terminal are used to input a first clock signal clk1 and a second clock signal clk2 respectively; The fully differential amplifier circuit unit includes a first operational amplifier, a switch S25, a switch S26, a switch S34, a switch S35, a compensation capacitor Cc1, a compensation capacitor Cc2, a holding capacitor CH1, and a holding capacitor CH2; The first operational amplifier is a differential amplifier, comprising a differential input terminal and a differential output terminal; The negative signal terminal of the differential input terminal of the first operational amplifier is connected to the node b5, and the positive signal terminal of the differential input terminal of the first operational amplifier is connected to the node b6; Two ends of the compensation capacitor Cc1 are connected to a node b5 and a node a1 respectively, and the node a1 is connected to the positive signal end of the source differential input end; Two ends of the compensation capacitor Cc2 are connected to the node b6 and the node a2 respectively, and the node a2 is connected to the negative signal end of the source differential input end; The two ends of the holding capacitor CH1 are connected to the node b4 and the node a4 respectively; the two ends of the switch S25 are connected to the node a4 and the reference potential Vref respectively; the two ends of the switch S26 are connected to the node a4 and the node b5 respectively; The two ends of the holding capacitor CH2 are connected to the node b7 and the node a7 respectively; the two ends of the switch S34 are connected to the node a7 and the reference potential Vref respectively; the two ends of the switch S35 are connected to the node a7 and the node b6 respectively; The switch S26 and the switch S35 are controlled by the first clock signal clk1; The switch S25 and the switch S34 are controlled by the second clock signal clk2; The first clock signal clk1 and the second clock signal clk2 are used to realize the conversion between the sampling phase and the amplification phase of the capacitance-voltage conversion circuit; The fully differential amplifier circuit unit further includes a first gain capacitor array, a second gain capacitor array, a switch S18, a switch S27, a switch S23, a switch S24, a switch S32, and a switch S33; The circuit configuration of the first gain capacitor array and the second gain capacitor array is the same; One end of the first gain capacitor array is connected to the node a1 and is connected to the reference potential Vref through the switch S18; the other end is connected to the node b4 through the switch S24 and is connected to the reference potential Vref through the switch S23; One end of the second gain capacitor array is connected to the node a2, and is connected to the reference potential Vref through the switch S27; the other end is connected to the node b7 through the switch S33, and is connected to the reference potential Vref through the switch S32; The switch S18, the switch S23, the switch S27, and the switch S32 are controlled by the first clock signal clk1; the switch S24 and the switch S33 are controlled by the second clock signal clk2; The input common-mode feedback amplifier circuit unit includes a second operational amplifier, a switch S4, a first feedback capacitor and a second feedback capacitor. The second operational amplifier includes a differential input terminal and an output terminal; Two ends of the differential input terminal of the second operational amplifier are respectively connected to two ends of the source differential input terminal; The output terminal of the second operational amplifier is connected through the first feedback capacitor, the second feedback capacitor and two ends of the source differential input terminal respectively, and is connected to the reference potential Vref through the switch S4; The switch S4 is controlled by the first clock signal clk1; The input common-mode feedback amplifier circuit unit further includes a switch S3 and a switch S5, and the two ends of the source differential input terminal are connected to the reference potential Vref through the switch S3, the switch S5, respectively, and the switch S3 and the switch S5 are controlled by the first clock signal clk1; The compensation capacitor array includes a first sub-capacitor array and a second sub-capacitor array, and the circuit configuration of the first sub-capacitor array and the second sub-capacitor array is the same; One end of the first sub-capacitor array and one end of the second sub-capacitor array are connected to a node b2, and the node b2 is connected to a ground potential through a switch S16, and is connected to the reference potential through a switch S17; The other end of the first sub-capacitor array and the other end of the second sub-capacitor array are respectively connected to two ends of the source differential input terminal; The switch S16 is controlled by the second clock signal clk2 , and the switch S17 is controlled by the first clock signal clk1 .

2. The capacitance-to-voltage conversion circuit according to claim 1, wherein: The gain capacitor array includes a basic gain capacitor and a plurality of extended gain capacitors. Each of the extended gain capacitors is connected in series with a switch and then connected in parallel with the basic gain capacitor. The capacitance of the gain capacitor array is adjusted by selecting the switch.

3. The capacitance-to-voltage conversion circuit according to claim 1, wherein: The first operational amplifier includes a transistor M0, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, and a transistor M10; The first operational amplifier includes a differential input terminal, a differential output terminal and a plurality of control input terminals; The differential input terminal of the first operational amplifier is used for inputting a signal Vin and a signal Vip; The differential output terminal of the first operational amplifier is used to output a signal Voutp and a signal Voutn; The control input terminal of the first operational amplifier is used to input control signals, including: a signal Vbtail, a signal Vcnfbout, a signal Vb1, a signal Vb2, a signal Vb3 and a reference potential Vref; The circuit connection relationship of the internal circuit of the first operational amplifier is: The gate of the transistor M0 is connected to the signal Vbtail, the source is connected to the ground potential, and the drain is connected to the node t6; The gate of the transistor M1 is connected to the signal Vin, the source is connected to the node t6, and the drain is connected to the node t5; The gate of the transistor M2 is connected to the signal Vip, the source is connected to the node t6, and the drain is connected to the node t7; The gate of the transistor M3 is connected to the signal Vb1, the source is connected to the ground potential, and the drain is connected to the source of the transistor M5; The gate of the transistor M4 is connected to the signal Vb1, the source is connected to the ground potential, and the drain is connected to the source of the transistor M6; The gate of the transistor M5 is connected to the signal Vb2, the source is connected to the drain of the transistor M3, the drain is connected to the node t8, and the signal Voutp is connected to the node t8; The gate of the transistor M6 is connected to the signal Vb2, the source is connected to the drain of the transistor M4, the drain is connected to the node t9, and the signal Voutn is connected to the node t9; The gate of the transistor M7 is connected to the signal Vb3, the source is connected to the node t5, and the drain is connected to the node t8; The gate of the transistor M8 is connected to the signal Vb3, the source is connected to the node t7, and the drain is connected to the node t9; The gate of the transistor M9 is connected to the signal Vcmfout, the source is connected to the power supply potential, and the drain is connected to the node t5; The gate of the transistor M10 is connected to the signal Vcmfout, the source is connected to the power supply potential, and the drain is connected to the node t7.

4. The capacitance-to-voltage conversion circuit according to claim 3, wherein: The first operational amplifier further includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a switch S36, a switch S37, a switch S38, a switch S39, a switch S40, a switch S41, a third clock signal input terminal, and a fourth clock signal input terminal; The circuit connection relationship of the internal circuit of the first operational amplifier also includes: The signal Voutn is connected to the node r1; The signal Voutp is connected to the node r3; The two ends of the capacitor C1 are connected to the node r1 and the node r2 respectively; The two ends of the capacitor C2 are connected to a node r2 and a node r3 respectively; The two ends of the capacitor C3 are connected to a node r4 and a node r5 respectively; The two ends of the capacitor C4 are connected to a node r5 and a node r6 respectively; The two ends of the switch S36 are connected to the node r1 and the node r4 respectively; The two ends of the switch S37 are connected to the node r4 and the signal Vcm respectively; The two ends of the switch S38 are connected to the node r2 and the node r5 respectively; The two ends of the switch S39 are connected to the node r5 and the reference potential Vref respectively; The two ends of the switch S40 are connected to the node r3 and the node r6 respectively; The two ends of the switch S41 are connected to the node r6 and the signal Vcm respectively; The third clock signal input terminal and the fourth clock signal input terminal are respectively used to input a third clock signal clk1a and a fourth clock signal clk2a, the third clock signal clk1a is an early shutdown signal of the first clock signal clk1, the fourth clock signal clk2a is an early shutdown signal of the second clock signal clk2, the opening of the switch S36, the switch S38, and the switch S40 is controlled by the third clock signal clk1a, and the opening of the switch S37, the switch S39, and the switch S41 is controlled by the fourth clock signal clk2a.

5. The capacitance-to-voltage conversion circuit according to claim 1, wherein: The internal circuit of the second operational amplifier includes a transistor M0, a transistor M1a, a transistor M1b, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, and a transistor M10; The differential input terminal of the second operational amplifier includes a differential input terminal, an output terminal and a plurality of control input terminals; The differential input terminal of the second operational amplifier is used to input a signal Vin2 and a signal Vip2; The output terminal of the second operational amplifier is used to output a signal Voutp2; The control input terminal of the second operational amplifier is used to input control signals, including: signal Vbp1, signal Vbp2, signal Vbn1, signal Vbn2 and reference potential Vref; The gate of the transistor M0 is connected to the signal Vbn2, the source is connected to the ground potential, and the drain is connected to the node t2; The gate of the transistor M1a is connected to the signal Vin2, the source is connected to the node t2, and the drain is connected to the node t1; The gate of the transistor M1b is connected to the signal Vip2, the source is connected to the node t2, and the drain is connected to the node t1; The gate of the transistor M2 is connected to the reference potential Vref, the source is connected to the node t2, and the drain is connected to the node t3; The gate of the transistor M3 is connected to the node t4, the source is connected to the ground potential, and the drain is connected to the source of the transistor M5; The gate of the transistor M4 is connected to the node t4, the source is connected to the ground potential, and the drain is connected to the source of the transistor M6; The gate of the transistor M5 is connected to the signal Vbn1, the source is connected to the drain of the transistor M3, and the drain is connected to the node t5; the signal Voutp2 is connected to the node t5; The gate of the transistor M6 is connected to the signal Vbn1, the source is connected to the drain of the transistor M4, and the drain is connected to the node t4; The gate of the transistor M7 is connected to the signal Vbp2, the source is connected to the node t1, and the drain is connected to the node t5; the signal Voutp2 is connected to the node t5; The gate of the transistor M8 is connected to the signal Vbp2, the source is connected to the node t3, and the drain is connected to the node t4; The gate of the transistor M9 is connected to the signal Vbp1, the source is connected to the power supply potential, and the drain is connected to the node t1; The gate of the transistor M10 is connected to the signal Vbp1, the source is connected to the power supply potential, and the drain is connected to the node t3.

6. The capacitance-to-voltage conversion circuit according to claim 1, wherein: The sub-capacitor array includes a basic compensation capacitor and a plurality of extended compensation capacitors. Each of the extended compensation capacitors is connected in series with a switch and then connected in parallel with the basic compensation capacitor. The capacitance of the sub-capacitor array is adjusted by turning on the switch.

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