Preventing timing-based security attacks against reorder buffers

Abstract

The present disclosure describes methods, systems, and apparatuses related to reorder buffers and for preventing timing-based security attacks. A processor can have a functional unit configured to execute instructions out of order, a reorder buffer configured to buffer results of the instructions for output in order, and a controller configured to randomize timing of data in the reorder buffer. For example, the controller can randomly adjust a capacity of the reorder buffer when buffering and / or classifying results of the instructions, thereby randomizing timing of data in the reorder buffer.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Patent Application Serial No. 16 / 210,609, filed December 5, 2018, entitled “Protection against Timing-based Security Attacks on Re-Order Buffers,” the entire disclosure of which is hereby incorporated by reference. TECHNICAL FIELD

[0003] At least some embodiments disclosed herein relate generally to computer architecture, and more particularly but not by way of limitation, to techniques for protection against security attacks on re-order buffers. BACKGROUND

[0004] Instructions are typically programmed to be executed in order. The program order of instructions is the order in which the instructions are programmed for execution in a processor.

[0005] Some instructions can be executed according to an alternative order and achieve the same result as executing the instructions according to the program order.

[0006] Out-of-order execution has been implemented in some processors to improve the utilization of the processing power of the processor and to improve the overall speed of executing programs having sequences of instructions.

[0007] For example, when a processor is to process an instruction configured to operate on an operand, the operand can be in the process of being loaded from a cache memory or main memory or storage device. However, the operand of the next instruction in program order can already be ready for processing in the processor. Thus, the processor can execute the next instruction rather than pause execution of the instruction to wait for the operand being loaded from the cache memory, main memory, or storage device.

[0008] The “data order” of instructions is the order in which the data or operands of the instructions become available for processing in the processor. The data order is typically different from the program order in contemporary processor designs. Processors can be configured to execute instructions according to the data order of the instructions rather than the program order of the instructions.

[0009] A reorder buffer can be used to hold results of instructions executed out of their program order in time. For example, instructions can be executed in data order of the instructions. Results stored in the reorder buffer can be moved out of the reorder buffer in program order of the corresponding instructions as if the results were generated by executing the instructions in program order. For example, a sequence of 3 instructions can be a first instruction to load an operand A into a first register (e.g., "load A, r1"), a second instruction to load another operand B into a second register (e.g., "load B, r2"), and a third instruction to add a number to the second register (e.g., "add #1, r2"). The second instruction (e.g., "load B, r2") can be executed out of order before the first instruction (e.g., "load A, r1") is executed, the third instruction (e.g., "add #1, r2") is executed, and then the first instruction (e.g., "load A, r1") is executed. This alternative execution sequence can be desirable when a memory system can return operand B before operand A. For example, when data is ready in the order B, #1, A, the instructions can be executed in the order "load B, r2", "add #1, r2", and "load A, r1", which is different from the program order "load A, r1", "load B, r2", and "add #1, r2".

[0010] Implementations of out-of-order execution can have security vulnerabilities. Examples of such security vulnerabilities in computer processors include Meltdown and Spectre, which were disclosed in 2018. For example, a security vulnerability can allow data to be cached from a privileged secure boundary, resulting in a race condition that can be timed to leak privileged information. An example of data in a privileged secure boundary is data located in an operating system kernel. BRIEF DESCRIPTION OF DRAWINGS

[0011] Embodiments are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which like references indicate similar elements.

[0012] Figure 1 A buffer controller configured to prevent timing-based security attacks against a reorder buffer is shown, according to one embodiment.

[0013] Figure 2 Out-of-order execution controlled by a buffer capacity controller is shown, according to one embodiment.

[0014] Figure 3 A method of preventing timing-based security attacks against a reorder buffer is shown, according to one embodiment.

[0015] Figure 4 A computing system in which the method of Figure 3 may be implemented is shown. DETAILED DESCRIPTION

[0016] The present disclosure includes techniques for preventing timing-based security attacks against a reorder buffer.

[0017] Timing-based security attacks rely on a timing pattern of results in a reorder buffer. By randomizing the timing pattern of results in a reorder buffer, such attacks can be prevented and / or made difficult to implement.

[0018] For example, the timing pattern of results in a reorder buffer can depend on the operational capacity of the reorder buffer. The actual / operational capacity of a reorder buffer that can be used to reorder results of instructions that are executed out of their program order can be randomly changed over time, such that the timing pattern changes over time. Such capacity adjustments can be performed randomly in time, or periodically, to introduce randomness in the timing of results in the reorder buffer.

[0019] Figure 1 A buffer controller (115) configured to prevent timing-based security attacks against a reorder buffer (113) is shown, according to one embodiment. For example, the buffer controller (115) can be implemented in a processor of the computer system shown. Figure 4

[0020] In Figure 1 the reorder buffer (113) is configured to receive results of instructions in the order that the instructions are executed. Results in the reorder buffer (113) can be moved out of the reorder buffer (113) for submission into a register file of the processor (e.g., 181 in Figure 4 the reorder buffer (113) in a hierarchical order that is consistent with the program order of the instructions. That is, the execution results of instructions that are to be executed earlier in the program order will be moved out of the reorder buffer (113) earlier. When a result of an instruction that is programmed before the instruction in the program order is ready to be moved out of the reorder buffer (113) for submission, the result of the instruction can be moved out of the reorder buffer (113) for submission. In some examples, some instructions can be executed in parallel units, threads, or pipelines; and the hierarchical order (retirement order or submission order) from the reorder buffer (113) maintains order consistency. Generally, order consistency requires that any executed result is the same as the result of the instruction executed in the order that it is program specified. Submission to a register can be referred to as a write to a register. Thus, a result can be submitted to a register by a processor configured to write the result to the register.

[0021] ​The capacity of the reorder buffer (113) determines the depth of the sequence of instructions that can be executed out-of-order before results can be retired from the reorder buffer (113). The same set of instructions executed using a reorder buffer (e.g., 113) of different capacities can have different result buffering timing in the reorder buffer (113). Thus, changing the capacity of the reorder buffer (113) can change the pattern of out-of-order execution. Randomizing the changes to the capacity of the reorder buffer (113) can introduce randomness in the timing of data in the reorder buffer (113), and thus remove the predictability of the timing in the reorder buffer (113), and prevent or thwart timing-based security attacks against the reorder buffer (113).

[0022] In some examples, the reorder buffer (113) has a predetermined full capacity. The buffer controller (115) identifies an available capacity of the reorder buffer (113) for ordering input results (111) provided in the order of actual execution / completion of instructions. When the available capacity identified by the buffer controller (115) is reached, preventing out-of-order execution of instructions of the instruction set for each reorder buffer (113) that can buffer results thereof until some results in the reorder buffer are retired from the reorder buffer (113).

[0023] The available capacity of the reorder buffer (113) can be a random portion of the predetermined full capacity of the reorder buffer (113). The randomness in the available capacity of the reorder buffer (113) can break or weaken the predictability of the timing of the reorder buffer (113), thereby preventing timing-based security attacks against the reorder buffer (113).

[0024] In some examples, the reorder buffer (113) can have a dynamically allocated capacity for ordering results in the execution order (111) into results in the retirement order (117). The buffer controller (115) controls the dynamic allocation of the capacity of the reorder buffer (113) (e.g., based on an output of a random number generator).

[0025] In some examples, multiple processing cores can each have multiple reorder buffers (e.g., 113). The buffer controller (115) can dynamically reallocate shared buffer capacity for the multiple reorder buffers (e.g., 113). For example, rather than dividing the shared buffer capacity evenly among the multiple reorder buffers (e.g., 113), the buffer controller (115) can randomize the ratio of the allocation of capacity among the multiple reorder buffers (e.g., 113) to induce randomness in the timing.

[0026] In some examples, the buffer controller (115) reconfigures the available capacity of the reorder buffer (113) periodically at regular, predetermined time intervals. Alternatively, the available capacity of the reorder buffer (113) can be configured for operation for a random period of time; and after this random period of time of operation, the available capacity of the reorder buffer (113) can be reconfigured for operation for another random period of time. The periods of operation can be referred to as, for example, a first period of time and a second period of time after the first period of time. The randomness in the length of the two or more constant available capacity periods of operation can also reduce or defeat timing predictability in the reorder buffer (113).

[0027] Figure 2 Reorder execution according to one embodiment is shown as being controlled by the buffer capacity controller (114). For example, the buffer capacity controller (114) of Figure 2 may be implemented with a random number generator (116) to randomize the reorder execution of instructions. Figure 1 The buffer controller (115) of may be implemented to randomize the reorder execution of instructions. The random number generator (116) can be configured to prevent an attacker from detecting a sequence of outputs generated from the random number generator (116) and / or its algorithm for generating randomized outputs. For example, statistical random noise on a computer bus can be used in the random number generator (116) to prevent an attacker from accurately predicting the output of the random number generator (116). Electrical noise is generally not accurately modelable. Such a random process is theoretically completely unpredictable; and the theory as to the unpredictability is subject to experimental verification. In general, any technique for preventing attacks on the random number generator (116) can be used. Thus, the present disclosure is not limited to any particular implementation of a random number generator.

[0028] Figure 2 In Figure 4 , instructions (101) fetched according to program order of the instructions are buffered in an instruction buffer (103). The instructions (101) can be fetched from a cache memory of the processor, from a memory of the computer system, and / or from a storage device of the computer system (e.g., as shown in

[0029] When data / operands (107) of the instructions are available to the functional units, the instructions in the instruction buffer (103) can be executed in the functional units (109) of the processor.

[0030] In general, the data / operands (107) of the instructions can be fetched from a cache memory of the processor, from a memory of the computer system, and / or from a storage device of the computer system (e.g., as shown in Figure 4Some data operands (107) of the instruction are loaded (107) as shown. Other data operands (107) of the instruction can be the result of execution of other instructions. Such results can be obtained in the processor's registers / register file and / or in the reorder buffer (113).

[0031] Loading certain data items (e.g., from cache, main memory or storage) can take a longer time period than processing one or more data ready instructions. The functional unit (109) can use the data / operands (107) of the data ready instructions for a short time period. Therefore, such data ready instructions in the instruction buffer (103) can be issued to the functional unit (109) for execution in a data order that is different from the program order.

[0032] The functional unit (109) generates results (111) in the order of execution / completion of the instructions; and the results (111) are temporarily stored in the reorder buffer (113) for their staging. When the results of instructions that precede the respective instruction are in the reorder buffer (113) and ready for staging, or have already been staged from the reorder buffer (113), the results of each respective instruction can be staged / retired / committed from the reorder buffer (113).

[0033] The results (117) in the staging order that is consistent with the program order of their instructions (101) can be moved out of the reorder buffer (113) for commitment into the registers (register file, cache / main memory and / or storage) (119).

[0034] When the capacity of the reorder buffer (113) is fixed, a security attack can predict, determine and / or exploit the timing of the results (111) in the reorder buffer (113) for a given instruction set to obtain unauthorized knowledge about the execution of the instructions and / or their data.

[0035] To disrupt, reduce or weaken the predictability of the timing of the results (111) entering the reorder buffer (113) and / or the results (117) leaving the reorder buffer (113), the buffer capacity controller (114) can inject randomness in the timing by randomizing the available capacity of the reorder buffer (113) when ordering the results (111 / 117).

[0036] For example, the buffer capacity controller (114) can include or be coupled to a random number generator (116). The output of the random number generator (116) can be used in the buffer capacity controller (114) to determine the limit of the available portion of the reorder buffer (113) when ordering the results (111 / 117).

[0037] For example, the buffer capacity controller (114) can determine an adjustment to the available portion of the reorder buffer (113) as results (111 / 117) are ordered. The adjustment can be made by adding a dummy result to the reorder buffer (113), or deleting a dummy result that was previously added to the reorder buffer (113). Dummy results that have been added to the front or back (or another position) of the queue in the reorder buffer (113) effectively reduce the available portion of the reorder buffer (113) for ordering results (111 / 117).

[0038] For example, the output of the random number generator (116) can be converted to a count of dummy results to save in the reorder buffer (113) for the next operational time period of the reorder buffer. The count of dummy results corresponds to a small fraction of the full capacity of the reorder buffer (113). If the current count of dummy results in the reorder buffer (113) is greater than the desired count converted from the output of the random number generator (116), the buffer capacity controller (114) deletes one or more dummy results from the reorder buffer (113) as if the dummy results were to be ordered from the reorder buffer (113). If the current count of dummy results in the reorder buffer (113) is less than the desired count converted from the output of the random number generator (116), the buffer capacity controller (114) adds one or more dummy results to the reorder buffer (113) (e.g., in a slot vacated by a most recently ordered result (117) from the reorder buffer (113)) as if the dummy results were generated by the functional unit (109) as a result of executing a dummy instruction.

[0039] Alternatively, the buffer capacity controller (114) can be configured to adjust one or more boundaries of the reorder buffer (113) that define the capacity of the buffer capacity controller (114) in accordance with the random number generator (116).

[0040] In some examples, the output of the random number generator (115) controls when the buffer capacity controller (114) adjusts the available capacity of the reorder buffer (113).

[0041] For example, the output of the random number generator (115) can be used to set a threshold count of operational periods of the reorder buffer between two successive adjustments. After the threshold count of operational periods after a previous adjustment, the buffer capacity controller (114) can again adjust the capacity of the reorder buffer (113).

[0042] In one embodiment, the operational periods of the reorder buffer can be counted based on a predetermined number of instruction cycles (or clock cycles) of the processor.

[0043] Alternatively, the operational cycle can be counted as between two successive stages of the result set (117) from the reorder buffer (113). In this case, the length of the cycle can not be constant with respect to clock cycles and / or instruction cycles.

[0044] Figure 3 A method of preventing a timing-based security attack against a reorder buffer is shown according to one embodiment. For example, the method of Figure 1 the buffer controller (115) or Figure 2 the buffer capacity controller (114) can be implemented. Figure 3 the method of

[0045] At block 131, a processor (e.g., 181 in FIG. 1) executes instructions in an order different from the program order in which the instructions are programmed. Figure 4

[0046] For example, the processor can execute the instructions according to a data order in which data / operands of the instructions are ready for processing in the processor.

[0047] At block 133, the processor buffers results (111) of the instructions in a reorder buffer (113).

[0048] For example, the results (111) of the instructions can enter the reorder buffer (113) in an order different from the program order of the instructions. For example, a first instruction can be programmed to be processed earlier than a second instruction; due to out-of-order execution, a result of the second instruction can arrive in the reorder buffer (113) earlier than a result of the first instruction; and in this case, the result of the second instruction can wait in the reorder buffer (113) until the result of the first instruction arrives in the reorder buffer (113), so that the results of the first and second instructions can be provided from the reorder buffer (113) according to the program order of the instructions.

[0049] At block 135, the reorder buffer (113) outputs the results of the instructions according to the order in which the instructions are programmed.

[0050] At block 137, a controller (e.g., 115 or 114) determines whether to adjust a capacity of the reorder buffer (113).

[0051] For example, the controller (e.g., 115 or 114) can determine whether to adjust the capacity of the reorder buffer (113) at regular time intervals.

[0052] ​For example, the controller (e.g., 115 or 114) can determine whether to adjust the capacity of the reorder buffer (113) when more than a threshold number of results can be moved out of the reorder buffer (113) to be staged in program order.

[0053] For example, the controller (e.g., 115 or 114) can determine whether to adjust the capacity of the reorder buffer (113) when more than a threshold number of results can be moved out of the reorder buffer (113) to be staged in program order.

[0054] For example, the controller (e.g., 115 or 114) can determine whether to adjust the capacity of the reorder buffer (113) when more than a threshold number of batches of results have been moved out of the reorder buffer (113) to be staged in program order.

[0055] At block 139, if the controller (e.g., 115 or 114) decides to adjust the capacity of the reorder buffer (113), the controller (e.g., 115 or 114) determines the adjustment to the capacity of the reorder buffer (113) according to the output of the random number generator (116).

[0056] For example, the controller (e.g., 115 or 114) can decide to increase or decrease the capacity of the reorder buffer (113) by a random amount calculated based on the output of the random number generator (116).

[0057] In some examples, the controller (e.g., 115 or 114) can decide to increase or decrease the capacity of the reorder buffer (113) (e.g., by a predetermined amount) at a randomized time controlled by the random number generator (116).

[0058] Optionally, the controller (e.g., 115 or 114) can decide to increase or decrease the capacity of the reorder buffer (113) at a random time controlled by the random amount.

[0059] At block 141, the controller (e.g., 115 or 114) implements the randomized adjustment to the capacity of the reorder buffer (113).

[0060] For example, the controller (e.g., 115 or 114) can adjust the number of dummy results inserted into the reorder buffer (113) to control the useful capacity of the reorder buffer (113) in ordering results.

[0061] For example, the controller (e.g., 115 or 114) can adjust the boundaries of the reorder buffer (113) to control the useful capacity of the reorder buffer (113) in ordering results.

[0062] For example, a controller (e.g., 115 or 114) can subdivide a set of memory units configured for multiple reorder buffers (e.g., 113) to adjust their capacities, including the capacity of reorder buffer (113).

[0063] Figure 4 A computing system in which methods Figure 3 may be implemented is shown.

[0064] Figure 4 A computing system can include a processor (181) with an internal cache (191), a storage device (187), an external cache (193), and a storage device (189) connected to the processor (181) and / or memory (187) via an interconnect (185).

[0065] For example, the processor (181) can have a functional unit (109) to execute instructions. The processor (181) can further include a register (153) to contain memory addresses, data / operands of instructions to be executed in the functional unit (109), and / or execution results of instructions.

[0066] For example, the register (153) can include a program counter and a memory address register to load execution instructions. When an instruction is executed in the processor (181), the memory address stored in the memory address register can be used to load operands of the instruction, and / or store a computation result generated by the execution instruction.

[0067] The processor (181) can execute instructions out of program order and use a reorder buffer (113) to make results of the instructions available in program order.

[0068] The processor (181) has a controller (151) configured to cause randomness in timing of results entering and / or leaving the reorder buffer (113). For example, the randomness can be achieved via randomized adjustment of the useful capacity of the reorder buffer (113) using any of the techniques discussed above in connection with Figures 1 to 3 For example, the controller (151) can be configured as a buffer controller (115) of Figure 1 or a buffer capacity controller (114) of Figure 2 to randomize data timing in the reorder buffer (113) using the methods of Figure 3

[0069] ​The randomization techniques discussed above can make the use of the reorder buffer (113) different for each execution of the same program. One of the results of using these techniques is that the execution time of a program can vary for multiple executions of the same program with the same data set under exactly the same computing conditions (same number of users, same amount of physical memory, etc.). In many cases, this arrangement is highly secure against timing attacks on its own.

[0070] For example, one of the more common security attacks is to determine a cryptographic key based on timing. When the timing of execution instances differs by only one or two cycles, a large number of such attacks can become useless on a computer system with a reorder buffer configured in the manner discussed in this disclosure.

[0071] For example, when data / operands for instructions are available in the internal cache (191), registers (153), and / or reorder buffer (113), the processor (181) can issue instructions from the internal cache (191) (e.g., instruction buffer (103)) to the functional units (109). The processor (181) buffers the results of execution of instructions generated by the functional units (109) so as to be staged in program order according to the instructions. The processor (181) can move results from the reorder buffer (113) to registers (153), internal cache memory (191), external cache memory (193), memory devices (187), and / or storage devices (189) in program order.

[0072] In some examples, the addresses used by the registers of the processor (181) are virtual memory addresses; and a memory management unit (MMU) (183) can translate the virtual memory addresses to physical memory addresses to access the external cache (193), memory devices (187), and / or storage devices (189).

[0073] For example, data in the memory devices (187) can be cached in the external cache (193) of the processor (181) and / or the internal cache (191) of the processor (181).

[0074] For example, data in the external cache (193) can be cached in the internal cache (191).

[0075] For example, data in the storage devices (189) can be cached in the storage devices (187), the external cache (193), and / or the internal cache (191).

[0076] In some examples, a memory management unit (MMU) (183) controls the movement of data between internal cache (191), external cache (193), and memory device (187).

[0077] The technology disclosed herein can be applied at least to computer systems in which a processor is separate from memory and the processor communicates with the memory and storage devices via a communication bus and / or computer network. Further, the technology disclosed herein can be applied to computer systems in which processing capability is integrated within the memory / storage devices. For example, processing circuitry including execution units and / or registers of a typical processor can be implemented within an integrated circuit package of an integrated circuit and / or memory media to perform processing within the memory device. Thus, the processor (e.g., 181) discussed above and shown in the figures is not necessarily a central processing unit in a von Neumann architecture. The processor can be a unit integrated within the memory to overcome the von Neumann bottleneck that limits computing performance due to latency in moving data between the central processing unit and memory separately configured according to a von Neumann architecture.

[0078] The description of the present disclosure and the accompanying drawings are illustrative, and should not be construed as limiting the present disclosure. Numerous specific details are described to provide a thorough understanding. However, in certain instances, well-known or conventional details are not described in order to avoid obscuring the description. References to one or an embodiment in the present disclosure are not necessarily references to the same embodiment; and, such references mean at least one.

[0079] In the foregoing specification, the disclosure has been described with reference to specific exemplary embodiments thereof. It is evident, however, that various modifications can be made to the disclosure without departing from the broader spirit and scope of the claims that are set forth in the following claims. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive.

Claims

1. A method for processor operation, comprising: The instructions are executed in the processor in an order different from the order in which the instructions of the application are programmed. The result of the instruction executed in the processor is buffered in the processor's reordering buffer; The result of outputting the instructions from the reordering buffer according to the programmed order of the instructions; While buffering the results, the processor adjusts the capacity of the reordering buffer; A random number is generated to determine the adjusted capacity, wherein the random number is configured to indicate a random portion of the full capacity of the reordering buffer as the current capacity for buffering the results; and The results are written from the reordering buffer to the register according to the programmed order of the instructions of the application.

2. The method of claim 1, wherein the capacity of the reordering buffer is adjusted from a predetermined full capacity to a first adjusted capacity, wherein during the operation time period of the reordering buffer, the first adjusted capacity limits the amount of results that can be buffered in the reordering buffer.

3. The method according to claim 1, further comprising: The reordering buffer is operated with the adjusted capacity during the first time period; Determine the further adjusted capacity for the second time period following the first time period; as well as The reordering buffer is operated with the further adjusted capacity during the second time period.

4. The method according to claim 3, wherein the second time period and the first time period have different lengths.

5. The method of claim 1, further comprising: The instructions are obtained in the order in which they are programmed. The instruction is buffered in the instruction buffer; as well as The instruction is issued to the functional unit in the order in which the operands of the instruction become available in the functional unit of the processor.

6. A processor comprising: One or more functional units configured to execute instructions for an application; A reordering buffer, configured to buffer the results of instructions executed in one or more functional units out of order relative to the programmed order of the instructions of the application. A controller configured to periodically and dynamically adjust the capacity of the reordering buffer; A register, wherein the processor is configured to write the results from the reordering buffer into the register according to the programmed order of the instructions of the application; as well as A random number generator, wherein the controller is configured to determine the capacity based on the output of the random number generator, and wherein the output of the random number generator indicates a random portion of the full capacity of the reordering buffer as the current capacity for buffering the result.

7. The processor of claim 6, wherein the controller is configured to periodically update the random portion to control the current use of the reordering buffer.

8. The processor of claim 6, wherein the controller is configured to update the random portion after a random time period to control the current use of the reordering buffer.

9. The processor of claim 6, wherein the controller is configured to change the timing pattern of the results generated by a set of instructions and stored in the reordering buffer by adjusting the capacity available for reordering the results.

10. The processor of claim 9, further comprising: An instruction buffer, wherein the processor is configured to fetch instructions into the instruction buffer in the order they are programmed to be fetched, and to issue instructions from the instruction buffer to the one or more functional units in the order in which the operands of the instructions in the instruction buffer are ready.

11. A non-transitory computer-readable medium storing instructions that, when executed in a processor, cause the processor to perform the method according to any one of claims 1 to 5.

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