Signal Development Caching in a Memory Device

Abstract

This application is directed to developing a cache for signals in a memory device. In one example, a memory device according to the described techniques may include a memory array, a sense amplifier array, and a signal-developing cache configured to store signals (e.g., cache signals, signal states) associated with logical states (e.g., memory states) that may be stored at the memory array (e.g., in accordance with various read or write operations). In various examples, accessing the memory device may include accessing information from the signal-developing cache or the memory array or both based on various mappings or operations of the memory device.

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 067829, filed Dec. 20, 2019, by Yudanov et al. entitled “SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICE”, which claims priority to U.S. Provisional Patent Application No. 62 / 783,388, filed Dec. 21, 2018, by Yudanov et al. entitled “MULTIPLEXED SIGNAL DEVELOPMENT IN A MEMORY DEVICE”, each of which is assigned to the assignee of the present invention and each of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to signal development caching in memory devices. BACKGROUND

[0004] The following generally relates to memory systems and, more particularly, to signal development caching in memory devices.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary memory devices have two logical states typically represented by a logic “1” or a logic “0”. In other memory devices, more than two logical states may be stored. To access the stored information, components of the electronic device may read or sense the stored logical states in the memory device. To store information, components of the electronic device may write or program the logical states into the memory device.

[0006] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), spin transfer torque memory, chalcogenide memory technologies, and other memories. Memory cells may be volatile or non-volatile. SUMMARY

[0007] Describe an apparatus. The apparatus may comprise: a memory array having a plurality of memory cells, each of the plurality of memory cells being associated with one of a plurality of access lines of the memory array; a signal development cache having a plurality of storage elements different from the plurality of memory cells of the memory array; a sense amplifier array having a plurality of sense amplifiers, each of the plurality of sense amplifiers being configured to output a logic state based at least in part on sensing signaling from the signal development cache; a first selection component operable to selectively couple the plurality of access lines of the memory array to the signal development cache; and a second selection component operable to selectively couple the signal development cache to the plurality of sense amplifiers of the sense amplifier array.

[0008] Describe a method. The method may comprise coupling a plurality of access lines of a memory array to a signal development cache, wherein each of the plurality of access lines corresponds to a respective one of a set of memory cells of the memory array. The method may involve storing, at each of a plurality of cache elements of the signal development cache and based on coupling the plurality of access lines to the signal development cache, a cache signal state corresponding to a logic state stored by the respective one of the set of memory cells. The method may comprise coupling the plurality of cache elements of the signal development cache to a sense amplifier array based on the storing. The method may involve sensing, at each of a plurality of sense amplifiers of the sense amplifier array, a respective logic signal based at least in part on the stored respective signal state and the coupling of the plurality of cache elements to the sense amplifier array.

[0009] Describe a method. The method may include receiving a write command at a memory device including a memory array, the write command including a plurality of logical states for writing to a plurality of memory cells of the memory array. The method may involve determining, at least in part based on the write command, to store corresponding cache signals for each of the plurality of logical states at corresponding storage elements of a plurality of storage elements of a signal development cache. The method may include coupling a plurality of sense amplifiers of a sense amplifier array to the plurality of storage elements of the signal development cache based on the determination to store the corresponding cache signals for each of the plurality of logical states at the corresponding storage elements. The method may involve coupling the plurality of storage elements to the plurality of memory cells after storing the corresponding cache signals for each of the plurality of logical states at the corresponding storage elements. The method may include writing the plurality of logical states to the plurality of memory cells based on coupling the plurality of storage elements to the plurality of memory cells of the memory array.

[0010] Describe a device. The device may include: a memory array including a plurality of memory cells; a signal development cache including a plurality of cache elements different from a set of memory cells; a sense amplifier including a plurality of sense amplifiers; and a controller operable to: couple a plurality of access lines of the memory array to the signal development cache, wherein each of the plurality of access lines corresponds to a corresponding one of the plurality of memory cells; store a signal state corresponding to a logical state stored by a corresponding one of the plurality of memory cells at each of the plurality of cache elements, at least in part based on coupling the plurality of access lines to the signal development cache; couple the plurality of cache elements to a sense amplifier array based on the storage; and sense a corresponding logic signal at each of the plurality of sense amplifiers based on the corresponding signal state and coupling the plurality of cache elements to the sense amplifier array.

[0011] Describe an apparatus. The apparatus may include: a memory array including a plurality of memory cells; a signal development cache including a plurality of cache elements different from a set of memory cells; sense amplifiers including a plurality of sense amplifiers; and a controller operable to: receive a write command including a plurality of logical states for writing to the plurality of memory cells; determine, at least in part based on the write command, to store a respective cache signal for each of the plurality of logical states at a respective one of the plurality of cache elements; couple the plurality of sense amplifiers to the plurality of cache elements based on the determination to store the respective cache signal for each of the plurality of logical states to the respective cache element; after storing the respective cache signal for each of the plurality of logical states to the respective cache element, couple the plurality of cache elements to the plurality of memory cells; and write the plurality of logical states to the plurality of memory cells based on coupling the plurality of cache elements to the plurality of memory cells.

[0012] Describe an apparatus. The apparatus may include: a memory array having a plurality of memory cells, each memory cell of the plurality of memory cells being associated with one of a plurality of access lines of the memory array; a signal development cache having a plurality of cache elements different from the plurality of memory cells of the memory array; a sense amplifier array having a plurality of sense amplifiers, each sense amplifier of the plurality of sense amplifiers being configured to output a logical state based on latching signaling from the signal development cache; and a selection circuitry operable to: selectively couple the plurality of access lines of the memory array to the signal development cache; selectively couple the signal development cache to the plurality of sense amplifiers of the sense amplifier array; selectively couple the plurality of access lines of the memory array to the plurality of sense amplifiers of the sense amplifier array; or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Illustrate an exemplary memory device supporting signal development caching in accordance with an example disclosed herein.

[0014] Figure 2 Illustrate an exemplary circuit supporting signal development caching in a memory device in accordance with an example disclosed herein.

[0015] Figure 3Illustrate an example circuit for caching signals in a support memory device according to an example disclosed herein.

[0016] Figure 4A And 4B Illustrate an example of a read operation for caching signals in a support memory device according to an example disclosed herein.

[0017] Figure 5A And 5B Illustrate an example of a write operation for caching signals in a support memory device according to an example disclosed herein.

[0018] Figure 6 Illustrate an example of a signal development component for caching signals in a support memory device according to an example disclosed herein.

[0019] Figure 7 Illustrate an example of a sense amplifier for caching signals in a support memory device according to an example disclosed herein.

[0020] Figure 8A , 8B And 8C show a block diagram of a system for caching signals in a support memory device according to an example disclosed herein.

[0021] Figure 9 Show a system diagram of a system for caching signals in a support memory device according to an example disclosed herein.

[0022] Figure 10 Show a block diagram of a memory device for caching signals in a support memory device according to an example disclosed herein.

[0023] Figure 11 And 12 Show a flowchart illustrating a method for caching signals in a support memory device according to an example disclosed herein. Detailed Description

[0024] Different latencies associated with different components used in a memory access operation or otherwise associated with portions of a memory access operation can cause delays when performing the memory access operation. For example, when the duration of the latency associated with developing a signal based on accessing a memory cell (e.g., including the operation of coupling the memory cell to a signal development component) is longer than the latency associated with generating an output signal at a sense amplifier (e.g., a sense or latch operation at the sense amplifier), the memory device may be able to generate the output signal more quickly compared to when the memory device performs the underlying signal development operation, where the output signal is based on the underlying signal development operation. For a memory device having a single signal development component for each sense amplifier (e.g., a 1:1 mapping of the signal development component to the sense amplifier), the throughput of the memory device may thus be limited by the latency or cycle duration associated with the signal development component or signal development operation, which can affect latency-sensitive applications.

[0025] According to an example disclosed herein, a memory device may include a signal development cache having a set of cache elements (e.g., signal storage elements) that can be selectively coupled and decoupled from sense amplifiers of the memory device. For example, a sense amplifier array may be coupled to a selection component (e.g., a multiplexer (MUX), a transistor network, a transistor array, a switch network, a switch array), and the selection component may be coupled to a set of signal development cache elements that can each be associated with one or more memory cells of the memory device. In some examples, a unit access signal (e.g., a unit read signal, a unit write signal) may be developed (e.g., at least partially based on coupling to the corresponding memory cell or other access to the corresponding memory cell) at each of the signal development cache elements independently of the other signal development cache elements. As used herein, a “set” may include one or more elements (e.g., one element, two elements, three elements, etc.).

[0026] In some instances (e.g., during a read operation), the signal development cache memory elements may each be coupled to a respective memory cell or access line during overlapping time intervals such that multiple cell access signals (e.g., multiple cell read signals associated with the respective memory cell or access line of each of the respective signal development components) may be generated during the overlapping time intervals. The signal development cache memory elements may then be coupled to a sense amplifier via a selection component to generate a sense or latch signal (e.g., an output signal of the sense amplifier, based on the respective cell access signal), which may be associated with a particular logic state stored by the respective memory cell (e.g., associated with the respective cell access signal). In instances where cell access signals have been developed at multiple signal development cache memory elements, the multiple signal development cache memory elements may be coupled to the sense amplifier in a sequential manner to generate the sense or latch signals in a sequential manner.

[0027] According to an example disclosed herein, signal development caching may utilize storage elements (e.g., cache memory elements) different from the storage elements (e.g., memory elements) of a memory array to support various pipelinings of information, including pipelinings associated with read operations, write operations, transfer operations, and others. In some instances, the storage elements in the signal development cache memory may utilize a storage technology different from that of the memory cells of the memory array, or may store signal states (e.g., cache memory states) in a manner different from how the associated memory array stores logic states.

[0028] Reference Figures 1 to 3 The features of the disclosure introduced above are further described in the context of a memory array and memory circuitry that support signal development caching in a memory device. Then reference Figures 4A to 5B describes specific examples, Figures 4A to 5B illustrates specific read and write operations that support signal development caching in a memory device. Reference Figures 6 to 9 describes other examples of circuits, components, and arrangements that may support the described operations. Further with respect to Figures 10 to 12 describes these and other features of the present disclosure, Figures 10 to 12 illustrates block diagrams and flowcharts that support signal development caching in a memory device.

[0029] Figure 1FIG. illustrates an exemplary memory device 100 for developing a cache based on support signals according to an example disclosed herein. The memory device 100 may also be referred to as an electronic memory device. The memory device 100 may include memory cells 105 that are programmable to store different states (e.g., memory states, which may be referred to herein as logical states). In some cases, the memory cells 105 may be programmable to store two logical states represented as logical 0 and logical 1. In some cases, the memory cells 105 may be programmable to store more than two logical states. Additionally or alternatively, the memory cells 105 may be programmable to store memory states based on analog or stochastic operations (e.g., related to neural networks), where the memory states correspond to information other than logical 0 or logical 1. In some examples, the memory cells 105 may include capacitive memory elements, ferroelectric memory elements, material memory elements, resistive elements, spin memory elements, thresholding memory elements, or any combination thereof.

[0030] A group of memory cells 105 may be part of a memory bank 110 of the memory device 100 (e.g., including an array of memory cells 105), where in some examples, the memory bank 110 may refer to a contiguous block of memory cells 105 (e.g., a set of contiguous elements of a semiconductor chip). In some examples, the memory bank 110 may refer to the smallest group of memory cells 105 that can be biased in an access operation, or the smallest group of memory cells 105 that share a common node (e.g., a common plate line, a set of plate lines biased to a common voltage). Although a single memory bank 110 of the memory device 100 is shown, various examples of memory devices according to the examples disclosed herein may have a set of memory banks 110. In one illustrative example, the memory device 100 or a sub-section thereof (e.g., a core of a multi-core memory device 100, a chip of a multi-chip memory device) may include 32 "banks" and each bank may include 32 sections. Thus, according to the illustrative example, the memory device 100 or a sub-section thereof may include 1,024 memory banks 110.

[0031] In some instances, the memory cell 105 may store charge representing a programmable logic state (e.g., storing charge in a capacitor, a capacitive memory element, a capacitive storage element). In one instance, a charged and an uncharged capacitor may represent two logic states, respectively. In another instance, a positively charged and a negatively charged capacitor may represent two logic states, respectively. A DRAM or FeRAM architecture may use such a design, and the capacitor employed may include a dielectric material having linear or paraelectric polarization properties as an insulator. In some instances, different charge levels of the capacitor may represent different logic states (e.g., supporting more than two logic states in the corresponding memory cell 105). In some instances such as a FeRAM architecture, the memory cell 105 may include a ferroelectric capacitor having a ferroelectric material as an insulating (e.g., non-conductive) layer between the terminals of the capacitor. Different polarization levels of the ferroelectric capacitor may represent different logic states (e.g., supporting two or more than two logic states in the corresponding memory cell 105). In some instances, the ferroelectric material has non-linear polarization properties.

[0032] In some instances, the memory cell 105 may include a material portion that may be referred to as a memory element, a memory storage element, a select memory element, or a select memory storage element. The material portion may have a variable and configurable resistance or other characteristics representing different logic states. For example, a material that can take the form of a crystalline atomic configuration or an amorphous atomic configuration (e.g., capable of maintaining a crystalline or amorphous state within the ambient operating temperature range of the memory device 100) may have different resistances depending on the atomic configuration. A more crystalline state of the material (e.g., a single crystal, a collection of relatively large grains that may be substantially crystalline) may have a relatively low resistance and may alternatively be referred to as the “set” logic state. A more amorphous state of the material (e.g., a completely amorphous state, a certain distribution of relatively small grains that may be substantially amorphous) may have a relatively high resistance and may alternatively be referred to as the “reset” logic state. Thus, depending on whether the material portion of the memory cell 105 is in a more crystalline state or a more amorphous state, a voltage applied to this memory cell 105 may cause different currents. Accordingly, the magnitude of the current resulting from applying a read voltage to the memory cell 105 may be used to determine the logic state stored by the memory cell 105.

[0033] In some instances, a memory element may be configured with various ratios of crystalline and amorphous regions (e.g., different degrees of atomic order and disorder) that can give rise to an intermediate resistance, which can represent different logic states (e.g., support two or more than two logic states in a corresponding memory cell 105). Additionally, in some instances, the material or memory element may have more than two atomic configurations, such as an amorphous configuration and two different crystalline configurations. Although described herein with reference to the resistance of different atomic configurations, the memory device may use some other property of the memory element to determine the stored logic state corresponding to an atomic configuration or combination of atomic configurations.

[0034] In some cases, a memory element in a more amorphous state may be associated with a threshold voltage. In some instances, when a voltage greater than the threshold voltage is applied across the memory element in a more amorphous state, current may flow through the memory element. In some instances, when a voltage less than the threshold voltage is applied across the memory element in a more amorphous state, current may not flow through the memory element. In some cases, a memory element in a more crystalline state may not be associated with a threshold voltage (e.g., may be associated with a zero threshold voltage). In some instances, current may flow through the memory element in response to a non-zero voltage applied across the memory element in a more crystalline state.

[0035] In some cases, materials in both a more amorphous state and a more crystalline state may be associated with a threshold voltage. For example, a select or thresholded memory may be based on the difference in the threshold voltage of a memory cell (e.g., through different compositional distributions) between different programmed states. The logic state of a memory cell 105 having such a memory element may be set by biasing or heating the memory element over time to a temperature profile that supports the formation of a particular atomic configuration or combination of atomic configurations.

[0036] Memory device 100 may include a three-dimensional (3D) memory array in which multiple two-dimensional (2D) memory arrays (e.g., planes, levels) are formed on top of each other. In various instances, such arrays may be divided into a set of memory segments 110, where each memory segment 110 may be arranged within a single plane or level, distributed across multiple planes or levels, or arranged in any combination thereof. Such an arrangement may increase the number of memory cells 105 that can be placed or formed on a single die or substrate compared to a 2D array, which in turn may reduce the production cost of memory device 100 or improve the performance of memory device 100 or achieve both. The planes or levels may be separated by an electrically insulating material. Each plane or level may be aligned or positioned such that the memory cells 105 are generally aligned with each other across each plane, thereby forming a stack of memory cells 105.

[0037] In an example of the memory device 100, each row of the memory cells 105 of the memory bank 110 may be coupled to one of a set of first access lines 120 (e.g., word lines (WL), such as WL1 to WL M among them), and each column of the memory cells 105 may be coupled to one of a set of second access lines 130 (e.g., digit lines (DL), such as DL1 to DL N among them). In some examples, rows of the memory cells 105 of different memory banks 110 (not shown) may be coupled to one of a different plurality of first access lines 120 (e.g., word lines different from WL1 to WL M ), and columns of the memory cells 105 of different memory banks 110 may be coupled to one of a different plurality of second access lines 130 (e.g., digit lines different from DL1 to DL N ). In some instances, the first access lines 120 and the second access lines 130 may be substantially perpendicular to each other in the memory device 100 (e.g., as shown in Figure 1 when viewing a plane of a layer of the memory device 100). Without loss of understanding or operation, references to word lines and bit lines or their equivalents are interchangeable.

[0038] Generally, a memory cell 105 may be located at an intersection of a first access line 120 and a second access line 130 (e.g., coupled to the first access line 120 and the second access line 130, coupled between the first access line 120 and the second access line 130). This intersection or an indication of this intersection may be referred to as the address of the memory cell 105. A target or selected memory cell 105 may be a memory cell 105 located at an intersection of a first access line 120 that is powered or otherwise selected and a second access line 130 that is powered or otherwise selected. In other words, the first access line 120 and the second access line 130 may be powered or otherwise selected to access (e.g., read, write, rewrite, refresh) the memory cell 105 at their intersection. Other memory cells 105 that communicate electronically (e.g., are connected to the same first access line 120 or second access line 130) with the same first access line 120 or second access line 130 may be referred to as non-target or non-selected memory cells 105.

[0039] In some architectures, the logic storage component of the memory cell 105 (e.g., a capacitive memory element, a ferroelectric memory element, a resistive memory element, other memory elements) can be electrically isolated from the second access line 130 by a cell selection component (which in some instances can be referred to as a switching component or a selector device). The first access line 120 can be coupled to the cell selection component (e.g., via a control node or terminal of the cell selection component), and can control the cell selection component of the memory cell 105 or the cell selection component associated with the memory cell 105. For example, the cell selection component can be a transistor and the first access line 120 can be coupled to the gate of the transistor (e.g., where the gate node of the transistor can be the control node of the transistor). Activating the first access line 120 of the memory cell 105 can result in an electrical connection or a closed circuit between the logic storage component of the memory cell 105 and its corresponding second access line 130. Then the second access line 130 can be accessed to read from or write to the memory cell 105.

[0040] In some instances, the memory cell 105 of the memory bank 110 can also be coupled to one of a plurality of third access lines 140 (e.g., a plate line (PL), such as one of PL1 to PL N ). Although illustrated as separate lines, in some instances, the plurality of third access lines 140 can represent or be functionally equivalent to the following: a common plate line, a common plate, or other common nodes of the memory bank 110 (e.g., nodes common to each of the memory cells 105 in the memory bank 110), or other common nodes of the memory device 100. In some instances, the plurality of third access lines 140 can couple the memory cell 105 to one or more voltage sources for various sensing and / or writing operations, including those described herein. For example, when the memory cell 105 uses a capacitor to store a logic state, the second access line 130 can provide access to the first terminal or first plate of the capacitor, and the third access line 140 can provide access to the second terminal or second plate of the capacitor (e.g., a terminal associated with the opposite plate of the capacitor that is opposite to the first terminal of the capacitor, a terminal otherwise located on the side of the capacitor opposite to the first terminal of the capacitor). In some instances, the memory cells 105 of different memory banks 110 (not shown) can be coupled to one of different pluralities of third access lines 140 (e.g., a set of plate lines different from PL1 to PL N , different common plate lines, different common plates, different common nodes), and the different pluralities of third access lines 140 can be electrically isolated from the illustrated third access lines 140 (e.g., plate lines PL1 to PL N ).

[0041] A plurality of third access lines 140 may be coupled to a board assembly 145 that may control various operations, such as activating one or more of the plurality of third access lines 140 or selectively coupling one or more of the plurality of third access lines 140 to a voltage source or other circuit elements. Although the plurality of third access lines 140 of the memory device 100 are shown as being substantially parallel to the plurality of second access lines 130, in other instances, the plurality of third access lines 140 may be substantially parallel to the plurality of first access lines 120 or in any other configuration.

[0042] Although the access lines described with reference Figure 1 are shown as straight lines between the memory cells 105 and the coupled components, the access lines may be associated with other circuit elements such as capacitors, resistors, transistors, amplifiers, voltage sources, switch components, select components, and other elements that may be used to support access operations, including those described herein. In some instances, an electrode may be coupled to the memory cell 105 and the first access line 120 (e.g., coupled between the memory cell 105 and the first access line 120), or to the memory cell 105 and the second access line 130 (e.g., coupled between the memory cell 105 and the second access line 130). The term electrode may refer to an electrical conductor or other electrical interface between components and, in some cases, may be employed as an electrical contact to the memory cell 105. Electrodes may include traces, wires, conductive lines, conductive layers, conductive pads, etc. that provide a conductive path between elements or components of the memory device 100.

[0043] Access operations such as read, write, rewrite, and refresh may be performed on the memory cell 105 by activating or selecting the first access line 120, the second access line 130, and / or the third access line 140 coupled to the memory cell 105, which may include applying a voltage, charge, or current to the respective access line. The first access line 120, the second access line 130, and the third access line 140 may be made of a conductive material such as a metal (e.g., copper (Cu), silver (Ag), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, or other conductive or semiconductive material, alloy, or compound. After selecting the memory cell 105, the resulting signal (e.g., a cell access signal, a cell read signal) may immediately be used to determine the logic state stored by the memory cell 105. For example, a memory cell 105 having a capacitive memory element storing a logic state may be selected, and the resulting charge flow through the access line and / or the resulting voltage of the access line may be detected, converted, or amplified to determine the programmed logic state stored by the memory cell 105.

[0044] Access to memory cells 105 can be controlled by a row component 125 (e.g., a row decoder), a column component 135 (e.g., a column decoder), or a board component 145 (e.g., a board driver), or a combination thereof. For example, the row component 125 can receive a row address from the memory controller 170 and select or activate an appropriate first access line 120 based on the received row address. Similarly, the column component 135 can receive a column address from the memory controller 170 and select or activate an appropriate second access line 130. Thus, in some instances, access to the memory cells 105 can be achieved by selecting or activating the first access line 120 and the second access line 130. In some instances, these access operations can be accompanied by the board component 145 biasing one or more of the third access lines 140 (e.g., biasing one of the third access lines 140 of the memory section 110, biasing all of the third access lines 140 of the memory section, biasing a common board line of the memory section 110 or the memory device 100, biasing a common node of the memory section 110 or the memory device 100), which can be referred to as "board movement" of the memory cells 105, the memory section 110, or the memory device 100. In various instances, any one or more of the row component 125, the column component 135, or the board component 145 can be referred to as or otherwise include an access line driver or an access line decoder.

[0045] In some instances, the memory controller 170 can control the operations (e.g., read operations, write operations, rewrite operations, refresh operations, discharge operations, dissipation operations, equalization operations) of the memory cells 105 through various components (e.g., the row component 125, the column component 135, the board component 145, the sense component 150). In some cases, one or more of the row component 125, the column component 135, the board component 145, and the sense component 150 can be co-located with the memory controller 170 or otherwise included together. In some instances, any one or more of the row component 125, the column component 135, or the board component 145 can also be referred to as a memory controller or a circuit for performing access operations of the memory device 100. In some instances, any one or more of the row component 125, the column component 135, or the board component 145 can be described as controlling or performing operations for accessing the memory device 100, or controlling or performing operations for accessing the memory section 110 of the memory device 100.

[0046] The memory controller 170 may generate row and column address signals to activate the desired first access line 120 and second access line 130. The memory controller 170 may also generate or control various voltages or currents used during the operation of the memory device 100. Although a single memory controller 170 is shown, the memory device 100 may have more than one memory controller 170 (e.g., a memory controller 170 for each of a set of memory segments 110 of the memory device 100, a memory controller 170 for each of several subgroups of the memory segments 110 of the memory device 100, a memory controller 170 for each of a set of chips of the multi-chip memory device 100, a memory controller 170 for each of a set of banks of the multi-bank memory device 100, a memory controller 170 for each core of the multi-core memory device 100, or any combination thereof), where different memory controllers 170 may perform the same functions and / or different functions.

[0047] Although the memory device 100 is illustrated as including a single row component 125, a single column component 135, and a single board component 145, other examples of the memory device 100 may include different configurations to accommodate the memory segment 110 or a set of memory segments 110. For example, in various memory devices 100, the row component 125 may be shared among a set of memory segments 110 (e.g., having sub-components common to all memory segments in the set of memory segments 110, having sub-components dedicated to the corresponding memory segments in the set of memory segments 110), or the row component 125 may be dedicated to one memory segment 110 in a set of memory segments 110. Similarly, in various memory devices 100, the column component 135 may be shared among a set of memory segments 110 (e.g., having sub-components common to all memory segments in the set of memory segments 110, having sub-components dedicated to the corresponding memory segments in the set of memory segments 110), or the column component 135 may be dedicated to one memory segment 110 in a set of memory segments 110. Additionally, in various memory devices 100, the board component 145 may be shared among a set of memory segments 110 (e.g., having sub-components common to all memory segments in the set of memory segments 110, having sub-components dedicated to the corresponding memory segments in the set of memory segments 110), or the board component 145 may be dedicated to one memory segment 110 in a set of memory segments 110.

[0048] Generally, the amplitude, shape, or duration of the applied voltage, current, or charge can be adjusted or changed and can be different for the various operations discussed in operating the memory device 100. Additionally, one, more, or all of the memory cells 105 within the memory device 100 can be accessed simultaneously. For example, during a reset operation in which all of the memory cells 105 or a group of memory cells 105 (e.g., the memory cells 105 of a memory section 110) are set to a single logical state, multiple or all of the memory cells 105 of the memory device 100 can be accessed simultaneously.

[0049] The sense component 150 can read (e.g., sense) the memory cell 105 when accessing (e.g., in cooperation with the memory controller 170) the memory cell 105 to determine the logical state stored by the memory cell 105. For example, the sense component 150 can be configured to sense a current or charge passing through the memory cell 105 or a voltage generated due to coupling the memory cell 105 with the sense component 150 or other intervening components (e.g., a signal development component between the memory cell 105 and the sense component 150) in response to a read operation. The sense component 150 can provide an output signal indicative (e.g., at least partially based) of the logical state stored by the memory cell 105 to one or more components (e.g., the column component 135, the input / output component 160, the memory controller 170). In various memory devices 100, the sense component 150 can be shared among groups or banks of memory sections 110 (e.g., having subcomponents common to all memory sections in the group or bank of memory sections 110, having subcomponents dedicated to respective memory sections in the group or bank of memory sections 110), or the sense component 150 can be dedicated to one memory section 110 of a group or bank of memory sections 110.

[0050] In some instances, during or after accessing memory cell 105, the logical storage portion of memory cell 105 may discharge or otherwise permit charge or current to flow through its corresponding first access line 120, second access line 130, or third access line 140. This charge or current may be generated by biasing memory cell 105 or applying a voltage from one or more voltage sources or supplies (not shown) of memory device 100 to memory cell 105, where these voltage sources or supplies may be part of row component 125, column component 135, board component 145, sense component 150, memory controller 170, or some other component (e.g., a biasing component). In some instances, the discharging of memory cell 105 may cause a change in the voltage of second access line 130, and sense component 150 may compare the voltage to a reference voltage to determine the stored state of memory cell 105. In some instances, a voltage may be applied to memory cell 105 (e.g., using corresponding first access line 120 and second access line 130), and the presence or magnitude of the resulting current may depend on the applied voltage and the resistance state of the memory element of memory cell 105, and sense component 150 may use the applied voltage and the resistance state to determine the stored state of memory cell 105.

[0051] In some instances, when a read signal (e.g., a read pulse, read current, read voltage) is applied across memory cell 105 having a material memory element storing a first logic state (e.g., a set state associated with a more crystalline atomic configuration), memory cell 105 conducts current because the read pulse exceeds the threshold voltage of memory cell 105. In response to or at least partially based on this, as part of determining the logic state stored by memory cell 105, sense component 150 may thus detect a current passing through memory cell 105. When a read pulse is applied to memory cell 105 having a memory element storing a second logic state (e.g., a reset state associated with a more amorphous atomic configuration) (this may occur before or after applying a read pulse across memory cell 105 having a memory element storing a first logic state), memory cell 105 may not conduct current because the read pulse does not exceed the threshold voltage of memory cell 105. As part of determining the stored logic state, sense component 150 may thus detect very little current passing through memory cell 105 or may not detect a current passing through memory cell 105.

[0052] In some instances, a threshold current may be defined for sensing the logic state stored by memory cell 105. The threshold current may be set to be higher than the current that can pass through memory cell 105 when memory cell 105 does not reach the threshold in response to a read pulse, but equal to or lower than the expected current passing through memory cell 105 when memory cell 105 reaches the threshold in response to a read pulse. For example, the threshold current may be higher than the leakage current of the associated first access line 120, second access line 130, or third access line 140. In some instances, the logic state stored by memory cell 105 may be determined at least in part based on the voltage generated due to the current driven by the read pulse (e.g., across a shunt resistor). For example, the generated voltage may be compared to a reference voltage, where a generated voltage less than the reference voltage corresponds to a first logic state and a generated voltage greater than the reference voltage corresponds to a second logic state.

[0053] In some instances, more than one voltage may be applied when reading memory cell 105 (e.g., multiple voltages may be applied during portions of the read operation). For example, if the applied read voltage does not cause a current, one or more other read voltages may be applied (e.g., until a current is detected by sense component 150). The stored logic state of memory cell 105 may be determined at least in part based on the access of the read voltage that causes a current. In some cases, the read voltage may be ramped (e.g., smoothly increased to a higher magnitude) until a current or other condition is detected by sense component 150. In other cases, a predetermined read voltage (e.g., a predetermined sequence of read voltages that increase in a stepwise manner to a higher magnitude) may be applied until a current is detected. Similarly, a read current may be applied to memory cell 105 and the magnitude of the voltage used to form the read current may depend on the resistance or total threshold voltage of memory cell 105.

[0054] The sensing component 150 may include various switch components, selection components, multiplexers, transistors, amplifiers, capacitors, resistors, voltage sources, or other components for detecting, converting, or amplifying a difference in a sensed signal (e.g., a difference between a read voltage and a reference voltage, a difference between a read current and a reference current, a difference between a read charge and a reference charge) (which may be referred to as sensing or latching or generating a sensing or latching signal in some instances). In some instances, the sensing component 150 may include a set of components (e.g., circuit elements, circuitry) that are repeated for each of a set of second access lines 130 connected to the sensing component 150. For example, the sensing component 150 may include a separate sensing circuit or circuitry (e.g., a separate sense amplifier, a separate signal development component) for each of a set of second access lines 130 coupled to the sensing component 150 such that the logic state can be detected individually for a corresponding memory cell 105 coupled to the corresponding access line in the set of second access lines 130. In some instances, a reference signal source (e.g., a reference component) or a generated reference signal may be shared among components of the memory device 100 (e.g., shared among one or more sensing components 150, shared among separate sensing circuits of the sensing component 150, shared among the first access lines 120, second access lines 130, or third access lines 140 of the memory section 110).

[0055] The sensing component 150 may be included in a device that includes the memory device 100. For example, the sensing component 150 may be included together with other read and write circuitry, decoding circuitry, or register circuitry of the memory that may be coupled to or coupled with the memory device 100. In some instances, the detected logic state of the memory cell 105 may be output as an output through the column component 135 or the input / output component 160. In some instances, the sensing component 150 may be part of the column component 135, the row component 125, or the memory controller 170. In some instances, the sensing component 150 may be connected to the column component 135, the row component 125, or the memory controller 170 or otherwise electronically communicate with the column component 135, the row component 125, or the memory controller 170.

[0056] Although a single sensing component 150 is shown, the memory device 100 (e.g., the memory section 110 of the memory device 100) may include more than one sensing component 150. For example, a first sensing component 150 may be coupled to a first subgroup of the second access lines 130 and a second sensing component 150 may be coupled to a second subgroup of the second access lines 130 (e.g., different from the first subgroup of the second access lines 130). In some instances, this partitioning of the sensing components 150 may support parallel (e.g., simultaneous) operation of multiple sensing components 150. In some instances, this partitioning of the sensing components 150 may support matching sensing components 150 having different configurations or characteristics to specific subgroups of the memory cells 105 of the memory device (e.g., support different types of memory cells 105, support different characteristics of subgroups of memory cells 105, support different characteristics of subgroups of the second access lines 130).

[0057] Additionally or alternatively, two or more sensing components 150 may be coupled (e.g., selectively coupled) to the same set of second access lines 130 (e.g., to achieve component redundancy). In some instances, this configuration may support maintaining functionality that overcomes the failure of one of the redundant sensing components 150 or otherwise performs poorly or degrades. In some instances, this configuration may support the ability to select one of the redundant sensing components 150 for specific operational characteristics (e.g., related to power consumption characteristics, related to access speed characteristics of a specific sensing operation, related to operating the memory cells 105 in a volatile or non-volatile mode).

[0058] In some memory architectures, accessing a memory cell 105 may degrade or corrupt the logical state stored by one or more memory cells 105 of a memory bank 110 and may perform a rewrite or refresh operation to return the original logical state to the memory cell 105. In DRAM or FeRAM, for example, the capacitor of the memory cell 105 may be partially or fully discharged or depolarized during a sense operation, thereby destroying the logical state stored in the memory cell 105. In PCM, for example, a sense operation may cause a change in the atomic configuration of the memory cell 105, thereby changing the resistance state of the memory cell 105. Thus, in some instances, the logical state stored in the memory cell 105 may be rewritten after an access operation. Additionally, activating a single first access line 120, second access line 130, or third access line 140 may cause all memory cells 105 coupled to the activated first access line 120, second access line 130, or third access line 140 to be discharged. Thus, several or all of the memory cells 105 (e.g., all cells of an accessed row, all cells of an accessed column) coupled to the first access line 120, second access line 130, or third access line 140 associated with the access operation may be rewritten after the access operation.

[0059] In some instances, reading a memory cell 105 may be non-destructive. That is, it may not be necessary to rewrite the logical state of the memory cell 105 after reading the memory cell 105. For example, in a non-volatile memory such as PCM, accessing the memory cell 105 may not corrupt the logical state, and thus, the memory cell 105 may not need to be rewritten after access. However, in some instances, it may be necessary or not necessary to refresh the logical state of the memory cell 105 in the absence or presence of other access operations. For example, the logical state stored by the memory cell 105 may be refreshed at periodic intervals by applying appropriate write, refresh, or equalization pulses or biases to maintain the stored logical state. Refreshing the memory cell 105 may reduce or eliminate read disturbance errors or logical state corruption (due to charge leakage or change in the atomic configuration of the memory elements over time).

[0060] The memory cell 105 can be set, written, or refreshed by activating the relevant first access line 120, second access line 130, and / or third access line 140 (e.g., via the memory controller 170). In other words, a logical state can be stored in the memory cell 105 (e.g., via a cell access signal, via a cell write signal). The row component 125, column component 135, or bank component 145 can receive data to be written to the memory cell 105, for example, via the input / output component 160. In some instances, the write operation can be performed at least in part by the sense component 150, or the write operation can be configured to bypass the sense component 150.

[0061] In the case of a capacitive memory element, the memory cell 105 can be written by applying a voltage to the capacitor and then isolating the capacitor (e.g., isolating the capacitor from the voltage source used to write to the memory cell 105, such that the capacitor floats) to store the charge associated with the desired logical state in the capacitor. In the case of a ferroelectric memory, the ferroelectric memory element (e.g., a ferroelectric capacitor) of the memory cell 105 can be written by applying a voltage (e.g., applying a saturation voltage) having a magnitude high enough to polarize the ferroelectric memory element with a polarization associated with the desired logical state, and the ferroelectric memory element can be isolated (e.g., floated), or a zero net voltage or bias (e.g., grounded, virtual grounded, or equalizing the voltage across the ferroelectric memory element) can be applied across the ferroelectric memory element. In the case of PCM, the memory element can be written by applying a current having a distribution curve that causes the memory element to form an atomic configuration associated with the desired logical state (e.g., by heating and cooling).

[0062] The sense component 150 can include a plurality of signal development components that can be selectively coupled and decoupled to respective ones of a group of sense amplifiers. For example, the sense amplifiers of the sense component 150 can be coupled to a selection component of the sense component 150, and the selection component can be coupled to a group of signal development components of the sense component 150, which can be associated with one or more memory cells 105 or one or more access lines (e.g., one or more second access lines 130) of the memory device 100. In some instances, the cell access signal can be developed at each of the signal development components independently of the other signal development components.

[0063] In some instances, the signal development components of the sensing component 150 may each be coupled to a respective memory cell during overlapping time intervals such that multiple cell access signals (e.g., cell read signals, cell write signals, each associated with a respective memory cell of each of the respective signal development components) may be generated during the overlapping time intervals. In instances where cell access signals have been developed at multiple signal development components (e.g., during a read operation of multiple memory cells 105, during a multi-cell read operation), the multiple signal development components may be coupled to a sense amplifier (e.g., in a sequential manner, in a stepped manner) to generate a sense or latch signal of the sense amplifier (e.g., in a sequential manner, in a stepped manner) at least in part based on the cell access signals. In instances where a sequence of sense or latch signals is associated with writing to or rewriting a set of memory cells 105 (e.g., during a write or refresh operation of multiple memory cells 105, during a multi-cell write or refresh operation), the multiple signal development components may be coupled to a sense amplifier (e.g., in a sequential manner, in a stepped manner) to generate multiple cell access signals (e.g., in a sequential manner, in a stepped manner) at least in part based on the sense or latch signal of the sense amplifier. In some instances, the multiplexed signal development component of the sensing component 150 may compensate for portions of the signal development components or portions of the access operations associated with different latencies, which may reduce the impact of access serialization.

[0064] Figure 2 Illustrates an example circuit 200 supporting signal development caching in a memory device according to an example as disclosed herein. Circuit 200 may include memory cells 105-a and a sensing component 150-a, which may be examples of the memory cells 105 and sensing component 150 described in reference Figure 1 Therein. Circuit 200 may also include a word line 205, digit lines 210, and a plate line 215, which in some instances may correspond to the first access line 120, second access line 130, and third access line 140 (e.g., of memory section 110) described in reference Figure 1 Therein. In some instances, the plate line 215 may illustrate a common plate line, common plate, or another common node for the memory cells 105-a and another memory cell 105 (not shown) of the same memory section 110. Circuit 200 illustrates a circuit system that may support the described techniques for signal development caching in a memory device.

[0065] The sensing component 150-a may include a sense amplifier 290 (e.g., an amplifier component, an input / output amplifier, a "latch"), and the sense amplifier 290 may include a first node 291 and a second node 292. In various examples, the first node 291 and the second node 292 may be coupled to different access lines of the circuit (e.g., the signal line 285 and the reference line 275 of the circuit 200 respectively), or may be coupled to a common access line of different circuits (not shown). In some examples, the first node 291 may be referred to as a signal node, and the second node 292 may be referred to as a reference node. The sense amplifier 290 may be associated with (e.g., coupled to, coupled to) one or more input / output (I / O) lines (e.g., I / O line 295), and the one or more input / output (I / O) lines may include access lines coupled to the column component 135 via the input / output component 160 described above. Although the sense amplifier 290 is illustrated as having a single I / O line 295, a sense amplifier according to an example disclosed herein may have more than one I / O line 295 (e.g., two I / O lines 295). In various examples, according to the examples disclosed herein, other configurations and naming for access lines and / or reference lines are possible. Figure 1 The access lines coupled to the column component 135 via the input / output component 160 described above. Although the sense amplifier 290 is illustrated as having a single I / O line 295, a sense amplifier according to an example disclosed herein may have more than one I / O line 295 (e.g., two I / O lines 295). In various examples, according to the examples disclosed herein, other configurations and naming for access lines and / or reference lines are possible.

[0066] The memory cell 105-a may include a logic storage component (e.g., a memory element, a storage element, a memory storage element), such as a capacitor 220 having a first plate (cell plate) 221 and a second plate (cell bottom) 222. The cell plate 221 and the cell bottom 222 may be capacitively coupled through a dielectric material positioned therebetween (e.g., in DRAM applications), or may be capacitively coupled through a ferroelectric material positioned therebetween (e.g., in FeRAM applications). The cell plate 221 may be associated with a voltage V plate and the cell bottom 222 may be associated with a voltage V bottom as illustrated in the circuit 200. Without changing the operation of the memory cell 105-a, the orientations of the cell plate 221 and the cell bottom 222 may be different (e.g., flipped). The cell plate 221 may be accessed via the plate line 215 and the cell bottom 222 may be accessed via the digit line 210. As described herein, various logic states may be stored by charging, discharging, or polarizing the capacitor 220.

[0067] The capacitor 220 can communicate electronically with the digital line 210, and the stored logic state of the capacitor 220 can be read or sensed by operating various components represented in the operation circuit 200. For example, the memory cell 105-a may also include a cell selection component 225, which in some instances may be referred to as a switching component or selector device coupled to or coupled between the access line (e.g., digital line 210) and the capacitor 220. In some instances, the cell selection component 225 may be considered outside the illustrative boundary of the memory cell 105-a, and the cell selection component 225 may be referred to as a switching component or selector device coupled to or coupled between the access line (e.g., digital line 210) and the memory cell 105-a.

[0068] When the cell selection component 225 is activated (e.g., by activating a logic signal or voltage), the capacitor 220 can be selectively coupled to the digital line 210, and when the cell selection component 225 is deactivated (e.g., by deactivating a logic signal or voltage), the capacitor 220 can be selectively isolated or decoupled from the digital line 210. A logic signal or other selection signal or voltage can be applied to the control node 226 of the cell selection component 225 (e.g., control node, control terminal, selection node, selection terminal) (e.g., via the word line 205). In other words, the cell selection component 225 can be configured to selectively couple or decouple the capacitor 220 (e.g., logic storage component) to the digital line 210 based on the logic signal or voltage applied to the control node 226 via the word line 205.

[0069] Activating the cell selection component 225 can be referred to as selecting the memory cell 105-a in some instances, and deactivating the cell selection component 225 can be referred to as deselecting the memory cell 105-a in some instances. In some instances, the cell selection component 225 is a transistor (e.g., an n-type transistor) and its operation can be controlled by applying an activation or selection voltage to the transistor gate (e.g., control or selection node or terminal). The voltage used to activate the transistor (e.g., the voltage between the transistor gate terminal and the transistor source terminal) can be a voltage greater than the threshold voltage magnitude of the transistor (e.g., a positive activation or selection voltage). The voltage used to deactivate the transistor can be a voltage less than the threshold voltage magnitude of the transistor (e.g., ground or a negative deactivation or deselection voltage).

[0070] A word line 205 (e.g., by a row component 125) can be used to activate or deactivate the cell selection component 225. For example, a select voltage applied to the word line 205 (e.g., a word line logic signal or a word line voltage) can be applied to the gate of the transistor of the cell selection component 225, which can selectively connect or couple the capacitor 220 to the digit line 210 (e.g., provide a conductive path between the capacitor 220 and the digit line 210). A deselect or deactivate voltage applied to the word line 205 can be applied to the gate of the transistor of the cell selection component 225, which can selectively disconnect, decouple, or isolate the capacitor 220 from the digit line 210. In some instances, activating the cell selection component 225 can be referred to as selectively coupling the memory cell 105-a to the digit line 210, and deactivating the cell selection component 225 can be referred to as selectively decoupling or isolating the memory cell 105-a from the digit line 210.

[0071] In other instances, the positions of the cell selection component 225 and the capacitor 220 in the memory cell 105-a can be swapped such that the cell selection component 225 can be coupled to the plate line 215 and the cell plate 221 or coupled between the plate line 215 and the cell plate 221, and the capacitor 220 can be coupled to the digit line 210 and the other terminal of the cell selection component 225 or coupled between the digit line 210 and the other terminal of the cell selection component 225. In this instance, the cell selection component 225 can remain connected (e.g., in electronic communication) to the digit line 210 through the capacitor 220. This configuration can be associated with alternative timings and biases for access operations.

[0072] In instances employing a ferroelectric capacitor, the capacitor 220 may or may not be fully discharged immediately after being connected to or coupled with the digit line 210. In various scenarios, to sense the logic state stored by the ferroelectric capacitor, a voltage can be applied to the plate line 215 and / or the digit line 210, and the word line 205 can be biased (e.g., by activating the word line 205) to select the memory cell 105-a. In some cases, before activating the word line 205, the plate line 215 and / or the digit line 210 can be made to be at virtual ground and then isolated from the virtual ground, which can be referred to as a floating condition, an idle condition, or a standby condition.

[0073] Operating the memory cell 105-a by varying the voltage of the cell plate 221 (e.g., via the plate line 215) may be referred to as "shifting the cell plate". Biasing the plate line 215 and / or the digit line 210 may result in a voltage difference across the capacitor 220 (e.g., the voltage of the digit line 210 minus the voltage of the plate line 215). This voltage difference may be accompanied by a change in the stored charge on the capacitor 220, where the magnitude of the change in the stored charge may depend on the initial state of the capacitor 220 (e.g., whether the initial logic state stores a logic 1 or a logic 0). In some scenarios, the change in the stored charge on the capacitor 220 or a portion of this charge may be used by the sense component 150-a to determine the logic state stored by the memory cell 105-a (e.g., in a charge transfer sensing scheme). In some scenarios, the change in the stored charge on the capacitor 220 may result in a change in the voltage of the digit line 210, which change may be used by the sense component 150-a to determine the logic state stored by the memory cell 105-a. A cell access signal may refer to a signal generated when a memory cell 105-a is selected or activated (e.g., when coupled to a signal development component), which signal may include a cell read signal in a read operation of the memory cell 105-a, or a cell write signal in a write operation, rewrite operation, or refresh operation of the memory cell 105-a. In various instances, the cell access signal may be referred to as a cell coupling signal or a cell charge sharing signal.

[0074] In some instances, the digit line 210 may be coupled to additional memory cells 105 (not shown), each of which may be coupled to a different word line 205 (not shown). In other words, in some instances, different memory cells 105 coupled to the digit line 210 may be selected or activated based at least in part on different word line logic signals.

[0075] The digit line 210 may have properties that give rise to an intrinsic capacitance 230 (e.g., on the order of a few picofarads (pF), which may be non-negligible in some cases), and the intrinsic capacitance 230 may couple the digit line 210 to a voltage source 240-a having a voltage V0. The voltage source 240-a may represent a common ground or virtual ground voltage, or the voltage of a neighboring access line (not shown) of the circuit 200. Although illustrated as a separate element in Figure 2 the figure, the intrinsic capacitance 230 may be associated with properties distributed throughout the digit line 210 or another portion of the circuit 200.

[0076] In some instances, the intrinsic capacitance 230 can depend on the physical characteristics of the digit line 210, including the conductor dimensions of the digit line 210 (e.g., length, width, thickness). The intrinsic capacitance 230 can also depend on the characteristics of neighboring access lines or circuit components, the proximity to such neighboring access lines or circuit components, or the insulation characteristics between the digit line 210 and such access lines or circuit components. Thus, the change in the voltage of the digit line 210 after selecting or activating the memory cell 105-a can depend on the net capacitance of the digit line 210 (e.g., the net capacitance associated with the digit line 210). In other words, when charge flows along the digit line 210 (e.g., flows onto the digit line 210, flows from the digit line 210), a certain finite charge can be stored along the digit line 210 (e.g., stored in the intrinsic capacitance 230, stored in another capacitance coupled to the digit line 210), and the resulting voltage of the digit line 210 can depend on the net capacitance of the digit line 210.

[0077] The circuit 200 (e.g., the sensing component 150-a) can include a signal development component 250, and the signal development component 250 can be an example of a signal development component or a signal development circuit coupled to or coupled between the memory cell 105-a and the sense amplifier 290. In some instances, the access line associated with the signal development component 250 (e.g., the access line coupled to the input / output of the signal development component 250, the access line coupled to or coupled between the signal development component 250 and the sense amplifier 290) can be referred to as a signal development line (SDL) (e.g., the signal development line 255, the "cache line" (CL)). The signal development component 250 can amplify or otherwise transform the signals of the digit line 210 and the signal development line 255 (e.g., the cell access signal). For example, for a read operation, the signal development component 250 can at least partially generate a cell read signal based on being coupled to the capacitor 220 (e.g., before the sensing operation of the sense amplifier 290) or otherwise and at least partially associated with generating the cell read signal based on being coupled to the capacitor 220, which can include charge sharing between the signal development component 250 and the capacitor 220. In another example, for a write operation, a rewrite operation, or a refresh operation, the signal development component 250 can generate a cell write signal for the capacitor 220 (e.g., at least partially based on being coupled to the sense amplifier 290, in response to a write command, a refresh command, a rewrite command, or a read command) or otherwise associated with generating the cell write signal for the capacitor 220, which can include charge sharing between the signal development component 250 and the capacitor 220.

[0078] In some instances, the signal development component 250 may include a signal storage element, such as a capacitor (e.g., a signal development cache memory element, an integrating capacitor, an amplifier capacitor (AMPCap), which may alternatively be referred to as a “fast capacitor” in some cases) or another type of charge storage element configured to store a signal or a signal state different from the logic state stored at the memory cell 105 (e.g., different from the logic state stored at the memory cell 105-a). Additionally or alternatively, the signal development component 250 may include a transistor, an amplifier, a gate-cathode amplifier, or any other charge or voltage conversion or amplification component. For example, the signal development component 250 may include a charge transfer sense amplifier (CTSA), which in some instances may include a transistor having a gate terminal coupled to a voltage source).

[0079] Although the sense component 150-a is illustrated as having a single signal development component 250, according to the examples disclosed herein, the sense component 150-a may include one or more additional signal development components 250 (not shown) to form a set of signal development components 250 (e.g., a signal development cache memory). Each signal development component in the set of signal development components 250 of the sense component 150-a may be associated with one or more memory cells 105 or one or more digital lines 210 (e.g., configured to selectively couple or decouple with one or more memory cells 105 or one or more digital lines 210, configured to develop a cell access signal for one or more memory cells 105 or one or more digital lines 210), and one or more memory cells 105 or one or more digital lines 210 may or may not include the memory cell 105-a or the digital line 210. For example, each signal development component 250 in the set of signal development components 250 may be selectively coupled or decoupled with one or more digital lines 210 of a memory section 110 of a memory array. In instances where a respective one of the signal development components 250 is coupled to more than one memory cell 105 or more than one digital line 210, any one of the memory cells 105 or digital lines 210 may be selectively coupled or decoupled with the respective signal development component 250 through a selection component (e.g., a digital line selection component, a multiplexer, a transistor network, a transistor array, a switch network, a switch array, not shown) between the associated memory cell 105 or digital line 210 and the respective signal development component 250).

[0080] The sensing component 150-a may also include a selection component 280 (e.g., a signal development component selection component, a multiplexer, a transistor network, a transistor array, a switch network, a switch array) coupled to or coupled between a set of signal development components 250 (e.g., a set of signal development lines 255) and a sensing amplifier 290. The selection component 280 may be configured to selectively couple or decouple any signal development component or signal development line in the signal development component 250 or the set of signal development lines 255 to the sensing amplifier 290. The selection component 280 may be associated with an access line (e.g., signal line 285) for transporting signals (e.g., voltage, charge, current) between the selection component 280 and the sensing amplifier 290. For example, the output of the selection component 280 (e.g., in a read operation) may be an output signal (e.g., a signal transported via the signal line 285) that is at least partially based on an input signal (e.g., a signal transported from the selected signal development component 250 of the selection component 280, a signal transported by the selected signal development line 255 of the selection component 280). In some instances, the output signal of the selection component 280 may be equal to or substantially equal to the input signal of the selection component 280 (e.g., where V sig = V SDL ). Although described in the context of an input signal via the signal development line 255 and an output signal via the signal line 285, the interpretation of input and output may be reversed in a particular access operation employing the circuit 200 (e.g., in a write operation, a rewrite operation, a refresh operation).

[0081] In a read operation, the sensing component 150-b may compare the voltage of the signal line 285 (e.g., a cell read signal after coupling the memory cell 105-a or the digital line 210 to the signal development component 250, after selecting the signal development component 250 at the selection component 280) with a reference (e.g., the voltage of the reference line 275) to determine the logical state stored in the memory cell 105-a (e.g., to generate a sense or latch signal). In some instances, the voltage of the reference line 275 may be provided by a reference component 270. In other instances, the reference component 270 may be omitted and the reference voltage may be provided, for example, by accessing the memory cell 105-a or the digital line 210 to generate the reference voltage (e.g., in a self-reference access operation). Other operations may be used to support the selection and / or sensing of the memory cell 105-a.

[0082] In some instances, circuit 200 may include a bypass line 260 that may permit bypassing (e.g., selectively bypassing) a signal development component 250 or some other portion of the circuit between memory cell 105-a and sense amplifier 290. In some instances, bypass line 260 may be selectively enabled or disabled via a switch component 265. In other words, when switch component 265 is activated, digital line 210 may be coupled (e.g., coupling memory cell 105-a and selection component 280 or some other portion of the circuit between the memory cell and sense amplifier 290) to signal development line 255 or selection component 280 via bypass line 260.

[0083] In some instances, when switch component 265 is activated, signal development component 250 may be selectively isolated or decoupled (e.g., via another switch component or selection component, not shown) from one or both of digital line 210 or signal development line 255. When switch component 265 is deactivated, digital line 210 may be selectively coupled to signal development line 255 or selection component 280 via signal development component 250. In other instances, one or more additional selection components (not shown) may be used to selectively couple memory cell 105-a (e.g., digital line 210) to either signal development component 250 (e.g., via signal development line 255) or bypass line 260.

[0084] Additionally or alternatively, in some instances, a switch or selection component may be used to selectively couple selection component 280 to either signal development component 250 (e.g., via signal development line 255) or bypass line 260. In some instances, bypass line 260 may be selected to support generation of a cell access signal (e.g., a cell read signal) for detecting a logical state of memory cell 105-a by using signal development component 250, and generation of a cell access signal (e.g., a cell write signal) to write a logical state to memory cell 105-a by bypassing signal development component 250.

[0085] Some instances of memory devices that support multiplexed signal development may share a common access line (not shown) between memory cell 105 and sense amplifier 290 to support generation of a sense signal and a reference signal from the same memory cell 105. In one instance, the common access line between signal development component 250 and sense amplifier 290 may be referred to as a “common line,” and the common access line may replace signal line 285 and reference line 275 illustrated in circuit 200.

[0086] In such instances, the common access line can be connected to the sense amplifier 290 at two different nodes (e.g., a first node 291 and a second node 292, as described herein). In some instances, the common access line can permit a self-referenced read operation to share components that may exist between the sense amplifier 290 and the accessed memory cell 105 in both signal generation operations and reference generation operations. This configuration can reduce the sensitivity of the sense amplifier 290 to operational variations of various components in the memory device, such as memory cells 105, access lines (e.g., word lines 205, digit lines 210, plate lines 215), signal development circuits (e.g., signal development component 250), transistors, voltage sources 293 and 294, and others.

[0087] Although the digit line 210, the signal development line 255, and the signal line 285 are identified as separate lines, in accordance with the examples disclosed herein, the digit line 210, the signal development line 255, the signal line 285, and any other lines connecting the memory cell 105 to the sense amplifier 290 can be referred to as a single access line. Constituents of this access line can be separately identified for purposes of illustrating intervening components and intervening signals in various exemplary configurations.

[0088] The sense amplifier 290 can include various transistors or amplifiers to detect, convert, or amplify the difference in signals, which can include or otherwise be referred to as generating a sense signal or a latch signal. For example, the sense amplifier 290 can include circuit elements that receive a sense signal voltage (e.g., a cell read signal, V sig ) at a first node 291 and a reference signal voltage (e.g., V ref ) at a second node 292 and compare the sense signal voltage with the reference signal voltage. Based on the comparison at the sense amplifier 290, the output of the sense amplifier 290 (e.g., a sense or latch signal) can be driven to a higher voltage (e.g., a positive voltage) or a lower voltage (e.g., a negative voltage, a ground voltage).

[0089] For example, if the first node 291 has a lower voltage than the second node 292, the output of the sense amplifier 290 can be driven to a relatively lower voltage of the low voltage source 293 (e.g., the voltage of V L , which can be a ground voltage or a negative voltage that is substantially equal to V0). The sense component 150 including the sense amplifier 290 or the I / O component 160 coupled to this sense component 150 can latch the output of the sense amplifier 290 to determine the logical state stored in the memory cell 105-a (e.g., detecting a logical 0 when the first node 291 has a voltage lower than the second node 292).

[0090] If the first node 291 has a voltage higher than that of the second node 292, then the output of the sense amplifier 290 can be driven to the voltage of the high voltage source 294 (e.g., the voltage of V H ). The sense component 150 including the sense amplifier 290 or the I / O component 160 coupled to this sense component 150 can latch the output of the sense amplifier 290 to determine the logical state stored in the memory cell 105-a (e.g., when the first node 291 has a voltage higher than that of the second node 292, a logical 1 is detected). Then, the latched output of the sense amplifier 290 corresponding to the detected logical state of the memory cell 105-a can be output via one or more input / output (I / O) lines (e.g., I / O line 295).

[0091] To perform a write operation, a rewrite operation, or a refresh operation on the memory cell 105-a, a voltage (e.g., a cell write signal) can be applied across the capacitor 220. Various methods can be used. In one example, the cell selection component 225 can be selected or activated (e.g., by selecting or activating the word line 205) through the word line 205 to electrically connect the capacitor 220 to the digit line 210. A voltage can be applied across the capacitor 220 by controlling the voltages of the cell plate 221 (e.g., through the plate line 215) and the cell bottom 222 (e.g., through the digit line 210). In some examples, the write operation, the rewrite operation, or the refresh operation can be at least partially based on the sense or latch signal at the sense amplifier 290, and the sense or latch signal can be based on the signal received via the I / O line 295 (e.g., a write signal, a refresh signal) or on the signal generated at the sense amplifier 290 (e.g., a rewrite signal).

[0092] For example, to write a logical 0, the cell plate 221 can be taken as high (e.g., a positive voltage is applied to the plate line 215), and the cell bottom 222 can be taken as low (e.g., the digit line 210 is grounded, the digit line 210 is virtually grounded, a negative voltage is applied to the digit line 210). The reverse process can be performed to write a logical 1, where the cell plate 221 is taken as low and the cell bottom 222 is taken as high. In some cases, the voltage applied across the capacitor 220 during the write operation can have a magnitude equal to or greater than the saturation voltage of the ferroelectric material in the capacitor 220, such that the capacitor 220 is polarized and thus maintains the charge even when the magnitude of the applied voltage is reduced or when a zero net voltage is applied across the capacitor 220. In some examples, the sense amplifier 290 or the signal development component 250 can be used to perform the write operation, which can include coupling the low voltage source 293 or the high voltage source 294 to the digit line. When the sense amplifier 290 is used to perform the write operation, the signal development component 250 can be bypassed or not bypassed (e.g., by applying a write signal via the bypass line 260).

[0093] The circuit 200 including the sensing component 150-a, the cell selection component 225, the signal development component 250, the switch component 265, the reference component 270, the selection component 280, or the sense amplifier 290 may include various types of transistors. For example, the circuit 200 may include n-type transistors, where applying a relatively positive voltage higher than the threshold voltage of the n-type transistor (e.g., an applied voltage having a positive magnitude relative to the source terminal that is greater than the threshold voltage) to the gate of the n-type transistor will achieve a conduction path between the other terminals of the n-type transistor (e.g., the source terminal and the drain terminal).

[0094] In some instances, the n-type transistor may act as a switch component, where the applied voltage is a logic signal that is used to selectively enable conductivity through the transistor by applying a relatively high logic signal voltage (e.g., a voltage corresponding to a logic 1 state, which may be associated with a positive logic signal voltage supply), or to selectively disable conductivity through the transistor by applying a relatively low logic signal voltage (e.g., a voltage corresponding to a logic 0 state, which may be associated with a ground or virtual ground voltage or a negative voltage). In some instances where an n-type transistor is used as a switch component, the voltage of the logic signal applied to the gate terminal may be selected to operate the transistor at a particular operating point (e.g., in the saturation region or in the active region).

[0095] In some instances, the behavior of the n-type transistor may be different from a logic switch (e.g., more complex than the logic switch), and the selective conductivity across the transistor may also vary with changing source and drain voltages. For example, the applied voltage at the gate terminal may have a specific voltage level (e.g., a clamped voltage, a control voltage) that is used to achieve conductivity between the source terminal and the drain terminal when the source terminal voltage is below a specific level (e.g., below the gate terminal voltage minus the threshold voltage). When the source terminal voltage or the drain terminal voltage rises above the specific level, the n-type transistor may be deactivated such that the conduction path between the source terminal and the drain terminal is disconnected.

[0096] Additionally or alternatively, the circuit 200 may include p-type transistors, where applying a relatively negative voltage higher than the threshold voltage of the p-type transistor (e.g., an applied voltage having a negative magnitude relative to the source terminal that is greater than the threshold voltage) to the gate of the p-type transistor will achieve a conduction path between the other terminals of the p-type transistor (e.g., the source terminal and the drain terminal).

[0097] In some instances, a p-type transistor can act as a switching component where the applied voltage is a logic signal that is used to selectively enable conductivity by applying a relatively low logic signal voltage (e.g., a voltage corresponding to a logic “1” state that can be associated with a negative logic signal voltage supply), or to selectively disable conductivity by applying a relatively high logic signal voltage (e.g., a voltage corresponding to a logic “0” state that can be associated with a ground or virtual ground voltage or a positive voltage). In some instances where a p-type transistor is used as a switching component, the voltage of the logic signal applied to the gate terminal can be selected to operate the transistor at a particular operating point (e.g., in the saturation region or in the active region).

[0098] In some instances, the behavior of a p-type transistor can be different from a logic switch by a gate voltage (e.g., more complex than the logic switch), and the selective conductivity across the transistor can also vary with varying source and drain voltages. For example, the applied voltage at the gate terminal can have a particular voltage level that is used to achieve conductivity between the source terminal and the drain terminal as long as the source terminal voltage is higher than a particular level (e.g., higher than the gate terminal voltage plus the threshold voltage). When the source terminal voltage drops below the particular level, the p-type transistor can be deactivated such that the conduction path between the source terminal and the drain terminal is disconnected.

[0099] The transistors of circuit 200 can be field effect transistors (FETs), including metal oxide semiconductor FETs, which can be referred to as MOSFETs. These and other types of transistors can be formed from doped material regions on a substrate. In some instances, the transistors can be formed on a substrate dedicated to a particular component of circuit 200 (e.g., a substrate for sense amplifier 290, a substrate for signal development component 250, a substrate for memory cell 105-a), or the transistors can be formed on a substrate common to particular components of circuit 200 (e.g., a substrate common to sense amplifier 290, signal development component 250, and memory cell 105-a). Some FETs can have a metal portion that includes aluminum or other metals, but some FETs can implement other non-metal materials such as polysilicon, including those FETs that can be referred to as MOSFETs. Additionally, although an oxide portion can be used as the dielectric portion of an FET, other non-oxide materials can be used in the dielectric material in FETs (including those FETs that can be referred to as MOSFETs).

[0100] In some instances, different portions of circuit 200 or different operations that use portions of circuit 200 may be associated with different latency times. For example, in one portion of an access operation (e.g., a first sub-operation, a first set of sub-operations), a cell access signal may be developed by coupling memory cell 105-a to signal development component 250 (e.g., at least in part based on activating or selecting cell selection component 225, at least in part based on activating another switching component, isolation component, or selection component between memory cell 105-a and signal development component 250). In some instances, the cell access signal may be developed at least in part based on charge sharing between memory cell 105-a (e.g., capacitor 220) and signal development component 250 (e.g., charge flowing from capacitor 220 to signal development component 250, charge flowing from signal development component 250 to capacitor 220), or the cell access signal may be otherwise associated with the charge sharing. In some instances (e.g., in a read operation), the developed cell access signal (e.g., cell read signal) or charge sharing may be at least in part based on the logic state stored by memory cell 105-a. In some instances (e.g., in a write operation, rewrite operation, refresh operation), the developed cell access signal (e.g., cell write signal) or charge sharing may be at least in part based on the developed sense or latch signal (e.g., at sense amplifier 290, at signal line 285). As disclosed herein, charge sharing between memory cell 105-a and signal development component 250 may be associated with a voltage change on digital line 210 or a voltage change on signal development line 255 or both.

[0101] The development of a cell access signal for an access operation may be associated with a latency time, which may refer to the amount of time (e.g., duration) used to develop the cell access signal, the delay between the start of the cell access signal development operation and the cell access signal reaching a threshold level suitable for a subsequent portion of the access operation (e.g., in a read operation), or the delay between the start of the cell access signal development operation and writing a logical value to memory cell 105 (e.g., in a write operation, rewrite operation, or refresh operation). In some instances (e.g., in a read operation), the duration or latency time may be referred to as a "row-to-column address delay", and in some instances (e.g., in a write operation), the duration or latency time may be referred to as a "row precharge delay", which may be longer or shorter than the row-to-column address delay.

[0102] In some instances, charge sharing between memory cell 105-a, digital line 210 (e.g., intrinsic capacitance 230), and signal development component 250 may be associated with a time constant behavior (e.g., the time constant behavior of a change in voltage V DL of, the time constant behavior of a change in voltage V SDLassociated with, or otherwise include, logarithmic or exponential behavior in the changed time constant behavior). The duration or latency used to develop the cell access signal may refer to the duration between a coupling or activation operation (e.g., selection or activation of the cell selection component 225, selection or activation of another component configured to selectively couple the memory cell 105-a to the signal development component 250) and the digital line 210 or the signal development line 255 reaching a steady-state voltage or a threshold ratio of the steady-state voltage (e.g., 95% of the steady-state voltage, 99% of the steady-state voltage).

[0103] In some instances, the duration or latency used to develop the cell access signal may be expressed as a time constant (e.g., the duration to reach 63% of the change between an initial voltage and a steady-state voltage), or as multiple time constants. For example, the duration or latency used to develop the cell access signal may be expressed as the duration of 3 time constants, or otherwise associated with a duration within 5% of the steady-state value of the cell access signal. In another instance, the duration or latency used to develop the cell access signal may be expressed as the duration of 5 time constants, or otherwise associated with a duration within 1% of the steady-state value of the cell access signal.

[0104] In some instances, the charge sharing behavior and associated time constant or other latency may be at least partially based on the capacitance of the memory cell 105-a, the capacitance of the signal development component 250, or other capacitance between the memory cell 105-a and the signal development component 250 (e.g., an intrinsic capacitance, such as the intrinsic capacitance 230). For example, a relatively high capacitance of the digital line 210 (e.g., a relatively high intrinsic capacitance 230) may be associated with a relatively high latency (e.g., a relatively long duration to develop a cell read signal), and a relatively low capacitance of the digital line 210 may be associated with a relatively low latency (e.g., a relatively short duration to develop a cell read signal). In another instance, a relatively high capacitance of the memory cell 105-a (e.g., the capacitor 220) may be associated with a relatively low latency (e.g., a relatively short duration to develop a cell read signal), and a relatively low capacitance of the memory cell 105-a may be associated with a relatively high latency (e.g., a relatively long duration to develop a cell read signal).

[0105] Although described with reference to time-constant behavior, the duration or latency associated with developing a cell access signal may additionally or alternatively include other behaviors, such as ramp, step, or oscillatory (e.g., underdamped) behavior. In some instances, the cell access signal may include a set of operations, such as a set of coupling, isolation, activation, deactivation, selection, or deselection operations, and the duration or latency associated with developing the cell access signal may include the associated circuit behavior of each of the set of operations. For example, the cell access signal may include activating a switch or select component along digital line 210 or signal development line 255, activating a switch or select component between the digital line or signal development line and another component (e.g., selectively coupling a voltage source (not shown) to digital line 210 or signal development line 255), or other operations or combinations of operations.

[0106] In another portion of the access operation (e.g., a second sub-operation, a second set of sub-operations), a sense signal (e.g., a latch signal, an output signal, an input / output signal) may be developed by activating sense amplifier 290 (e.g., at least partially based on selectively coupling signal development component 250 to sense amplifier 290, at least partially based on selectively coupling the sense amplifier to one or both of low voltage source 293 or high voltage source 294). In some instances, the sense signal may be developed at least partially based on charge sharing between signal development component 250 and sense amplifier 290, or the sense signal may otherwise be associated with the charge sharing. In some instances (e.g., in a read operation), the sense signal or charge sharing may be at least partially based on the developed cell access signal (e.g., at signal development component 250, at signal development line 255). As described herein, the charge sharing between signal development component 250 and sense amplifier 290 may be associated with a voltage change on I / O line 295, which voltage change may be at least partially based on a comparison between voltage V sig and voltage V ref . (e.g., an output of V sig when V ref is less than V L , an output of V sig when V ref is greater than V H ).

[0107] Developing a sense or latch signal for an access operation may also be associated with a latency, which may refer to the amount of time for developing the sense or latch signal, or the delay between initiating a sense or latch signal generation operation and the sense or latch signal reaching a threshold level suitable for a subsequent part of the access operation (e.g., an output indicating a logical state stored by memory cell 105-a). For example, charge sharing between signal development component 250 and sense amplifier 290 may also be associated with a time constant behavior (e.g., the time constant behavior of the voltage change of I / O line 295) or other logarithmic or exponential behavior. The duration or latency for developing a sense or latch signal may refer to a coupling or activation operation (e.g., selection or activation of a switch component of selection component 280 or a selection component configured to selectively couple signal development component 250 with sense amplifier 290, coupling of sense amplifier 290 with one or both of low voltage source 293 or high voltage source 294) and the duration between I / O line 295 reaching a steady state voltage or a threshold proportion of the steady state voltage of I / O line 295 (e.g., 90% of the steady state voltage, 95% of the steady state voltage).

[0108] The duration or latency for developing a sense or latch signal may also be expressed as a time constant, or as a plurality of time constants. Although described with reference to time constant behavior, the duration or latency associated with developing a sense or latch signal may additionally or alternatively include other behaviors, such as ramp, step, or oscillatory (e.g., underdamped) behavior. In some instances, developing a sense or latch signal may include a set of operations, such as a set of coupling, isolation, activation, deactivation, selection, or deselection operations, and the duration or latency associated with developing the sense or latch signal may include the associated circuit behavior of each of the set of operations.

[0109] In some instances of circuit 200, the duration of the latency associated with developing a cell access signal may be longer than the latency associated with generating a sense or latch signal. For example, charge sharing between signal development component 250 and memory cell 105-a may be associated with a different amount of charge or a slower charge transfer than charge sharing between signal development component 250 and sense amplifier 290. In other words, signal development component 250 or memory cell 105-a may be associated with a relatively high latency part of circuit 200 or otherwise be considered a relatively high latency part of circuit 200, and sense amplifier 290 may be associated with a relatively low latency part of circuit 200 or be considered a relatively low latency part of circuit 200. In such instances, circuit 200 may support performing input or output operations more quickly than performing signal development operations.

[0110] According to an example disclosed herein, a memory device 100 that includes a circuit 200 may couple each of a set of signal development components 250 to a respective memory cell 105 during overlapping time intervals such that multiple cell access signals (e.g., associated with respective memory cells 105 of each of the signal development components 250) may be generated during the overlapping time intervals. Each signal development component in the set of signal development components 250 may be selectively coupled (e.g., in a sequential order) to a sense amplifier 290 via a selection component 280 to generate a sequence of sense or latch signals at the sense amplifier 290, or vice versa. For example, in a read operation or a set of read operations, the sequence of sense or latch signals generated at the sense amplifier 290 may be based on respective cell access signals (e.g., cell read signals) developed at the set of signal development components 250 during overlapping time intervals, where the cell access signals may be associated with a particular logic state stored by a respective memory cell 105. Thus, as disclosed herein, the memory device 100 that includes the circuit 200 may include signal development components 250 multiplexed via a selection component 280, which in some examples may compensate for portions of access operations associated with different latencies.

[0111] Figure 3 Illustrated is an exemplary circuit 300 that supports signal development caching in a memory device according to an example disclosed herein. It should be understood that the circuit 300 is merely an illustrative example, and many implementations including other specific circuits and topologies are possible while following the principles and techniques disclosed herein, as would be understood by a person of ordinary skill in the art.

[0112] The circuit 300 includes a set of memory cells 105-b (e.g., memory cells 105-b-111 to 105-b-srm) and a sensing component 150-b. Although the memory cells 105-b are illustrated as including capacitors and cell selection components, the memory cells 105-b according to an example disclosed herein may include various configurations (e.g., with or without cell selection components) and various types of logic storage elements (e.g., capacitive memory elements, ferroelectric memory elements, material memory elements, resistive memory elements, thresholded memory elements, other memory elements) to support various types of memory devices (e.g., DRAM memory devices, FeRAM memory devices, PCM devices, chalcogenide memory devices). The circuit 300 illustrates a circuitry that may support the described techniques for signal development caching in a memory device.

[0113] The sensing component 150-b may include a set of signal development components 250-a (e.g., signal development components 250-a-1 to 250-a-s), each associated with one or more of the memory cells 105-b. The sensing component 150-b may also include a selection component 280-a (e.g., a signal development component selection component, a MUX, a transistor network, a transistor array, a switch network, a switch array) coupled to the set of signal development components 250-a (e.g., via signal development lines 255-a-1 to 255-a-s). The selection component 280-a may be configured to selectively couple a selected one of the signal development components 250-a (e.g., a selected one of the signal development lines 255-a) to the sense amplifier 290-a of the sensing component 150-b (e.g., via a signal line 285-a, in response to a logic or selection signal, such as a signal development component multiplexing (SDCM) signal). The sense amplifier 290-a may exchange (e.g., transfer, receive, transmit) input or output signals with other components of the memory device (e.g., the input / output component 160) via the I / O line 295-a.

[0114] In an instance of the circuit 300, the memory cells 105-b may be arranged according to a set of domains 310-a (e.g., domains 310-a-1 to 310-a-s). In other words, the circuit 300 may illustrate an instance of a set of memory cells 105-b partitioned across or otherwise associated with s domains. In an instance of the circuit 300, each of the domains 310-a may be associated with (e.g., coupled to) one of the signal development components 250-a (e.g., domain 310-a-1 is associated with signal development component 250-a-1). However, in various instances of circuit systems supporting the described techniques, a domain 310 may be associated with more than one signal development component 250, or a signal development component 250 may be associated with more than one domain 310, or both.

[0115] Although the exemplary domains 310-a of the circuit 300 are described with reference to specific characteristics, alternative domain definitions or organizations may also be utilized to support the described techniques. As one such instance, the memory cells 105 or access lines (e.g., word lines 205, digit lines 210, plate lines 215) of a domain may be organized or subdivided in a manner different from the domains 310-a illustrated in the circuit 300, or a domain may be defined in a manner different from the domains 310-a illustrated in the circuit 300 (e.g., the components are included within the illustrative boundaries of the domain), or a domain may be coupled to the signal development components 250 or the sense amplifier 290 in a manner different from the domains 310-a illustrated in the circuit 300 (e.g., using a different multiplexing organization or scheme, a different selection component).

[0116] In an example of circuit 300, each of domains 310-a may include a memory cell 105-b coupled to or coupled between one of a group of digital lines 210-a and one of a group of plate lines 215-a. For example, for domain 310-a-1, each memory cell in the group of memory cells 105-b (e.g., each of memory cells 105-b-111 to 105-b-1rm) may be coupled to one of digital lines 210-a-11 to 210-a-1r and may be coupled to one of plate lines 215-a-11 to 215-a-1r. In other words, domain 310-a may illustrate an arrangement of memory cells 105-b divided across or otherwise associated with r digital lines 210-a or "columns". Although the exemplary circuit 300 is illustrated as having separate plate lines 215-a, in some examples, a group of plate lines 215-a (e.g., a group of two or more of plate lines 215-a-11 to 215-a-1r) may represent or otherwise be functionally equivalent to a common plate line for domain 310-a (e.g., domain 310-a-1), or may represent or otherwise be functionally equivalent to a common plate line for a portion (e.g., a "sub-domain") of domain 310-a, or a different group of plate lines 215-a (e.g., a group of two or more of plate lines 215-a-11 to 215-a-sr) may represent or otherwise be functionally equivalent to a common plate line for a group of domains 310-a (e.g., a group of domains 310-a-1 to 310-a-s).

[0117] Domain 310-a may also illustrate an arrangement of memory cells 105-b divided across or otherwise associated with m word lines 205-a or "rows". For example, domain 310-a-1 may include a corresponding group of m memory cells 105-b (e.g., a group of memory cells 105-b-111 to 105-b-11m coupled to or coupled between digital line 210-a-11 and plate line 215-a-11) coupled to each of the digital lines 210-a of domain 310-a and each of the plate lines 215-a of the domain. For a group of memory cells 105-b coupled to the same digital line 210-a and the same plate line 215-a, it may be at least partially based on the associated logic signal WL (e.g., for domain 310-a, logic signal WL 11 to WL 1mselect or access each memory cell in the group individually (e.g., one of the ones in). Although illustrated as sharing a common set of word lines 205-a in the shared domain 310-a (e.g., word lines 205-a-11 to 205-a-1m shared by each column in the columns spanning domain 310-a-1), other instances of the memory device may have different arrangements of word lines 205 in domain 310.

[0118] In an example of circuit 300, each of the domains 310-a may also include a selection component 320-a (e.g., digital line selection component, MUX, transistor network, transistor array, switch network, switch array) coupled to each digital line in the set of digital lines 210-a of domain 310-a or otherwise associated with the selection component 320-a. For example, domain 310-a-1 may include a selection component 320-a-1 coupled to each of digital lines 210-a-11 to 210-a-1r. For example, the selection component 320-a-1 may be configured to selectively couple a selected one of digital lines 210-a-11 to 210-a-1r or one of the memory cells 105-b-111 to 105-b-11m to the signal development component 250-a-1 (e.g., in response to a logic or selection signal, such as a digital line multiplexing (DLM) signal DLM1). Thus, each of the selection components 320-a-1 to 320-a-s may be associated with a corresponding one of the signal development components 250-a-1 to 250-a-s.

[0119] In an example of circuit 300, each of the signal development components 250-a may be associated with a corresponding set of memory cells 105-b or a corresponding set of digital lines 210-a. In some examples, the selection components 320-a-1 to 320-a-s may be instances of a plurality of second selection components, where each second selection component of the plurality of second selection components is associated with a corresponding signal development component 250 and is configured to selectively couple any one of the memory cells 105-b or digital lines 210-a in the set to the corresponding signal development component 250.

[0120] In an illustrative example, each of the domains 310-a may include 1,048,576 memory cells 105-b arranged as 1,024 uniquely addressable rows and 1,024 columns (e.g., where m = 1,024 and r = 1,024). According to an illustrative example of the circuit 300, one signal development component 250-a may be mapped to a particular domain 310-a, but in other examples, a group of more than one signal development component 250-a may be mapped to a particular domain 310-a (e.g., to the corresponding group of digit lines 210-a of the domain 310-a). In some examples, this mapping may be fixed (e.g., where the corresponding group of digit lines 210-a is mapped to the corresponding signal development component 250-a within each domain 310-a), which in some examples may reduce multiplexing or selection circuit complexity. In various other examples (not shown), the signal development component 250 may be mapped to more than one domain 310, (e.g., more than one group of digit lines 210 of a domain) or other configurations. Additionally or alternatively, a domain 310 or a group of digit lines 210 may be mapped to more than one signal development component 250. In other words, the memory device may include various configurations of the signal development component 250 to support the examples of multiplexed signal development described herein.

[0121] In an example of the circuit 300, each of the digit lines 210-a is associated with a single one of the signal development components (e.g., configured to be selectively coupled with a single one of the signal development components) (e.g., via a respective one of the selection components 320-a-1). For example, the digit line 210-a-11 may be associated with the signal development component 250-a-1 rather than the signal development component 250-a-s. However, in various examples of circuitry that supports the described techniques for signal development caching in a memory device, a particular digit line 210-a may be associated with more than one signal development component 250-a (e.g., configured to be selectively coupled with more than one signal development component 250-a), and the signal development component 250-a may include selection components different from the group of selection components 320-a-1 to 320-a-s illustrated in the circuit 300. For example, the digit line 210-a-11 may be associated with the signal development component 250-a-1 or the signal development component 250-a-s or any other signal development component 250-a of the circuit 300 (e.g., configured to be selectively coupled with the signal development component 250-a-1 or the signal development component 250-a-s or any other signal development component 250-a of the circuit 300).

[0122] In another illustrative example that supports the described techniques for multiplexed signal development, another circuit may include a number of domains each having 1,048,576 memory cells 105 arranged in 1,024 uniquely addressable rows and 1,024 columns, which may refer to a different component organization than circuit 300. Each of the domains of the other circuit may be arranged such that m = 1,024 and r = 1,024, and the digital lines 210 of the corresponding domains of this other circuit may be collectively mapped to an array of 64 signal development components 250 (e.g., according to a many-to-one mapping, according to a many-to-many mapping). In one example of the other circuit, each of the signal development components 250 may be mapped to a corresponding subgroup of the digital lines 210 of the domain (e.g., one signal development component 250 may be mapped to 1,024 / 64 = 16 digital lines 210 within each domain). In some instances, this mapping may be fixed (e.g., where a group or subgroup of 16 digital lines 210 is mapped to the corresponding signal development component 250 within each domain), and in some instances, this may reduce multiplexing or selection circuit complexity.

[0123] In this other example, the rows of 1,024 memory cells 105 (e.g., across one domain of the other circuit) may be selected by a single word line 205 in each domain. In other words, with 64 signal development components 250 per domain and r = 1,024, the activation of a word line in one domain and the activation of another word line in another domain (e.g., including other independent word lines in other domains) may select the memory cells 105 associated with the corresponding rows. With 64 signal development components 250 per domain in this circuit, 64 memory cells out of a group of 1,024 memory cells 105 may be accessed at a time in each domain (e.g., by selectively coupling the corresponding digital lines 210 to each of the 64 signal development components 250 via the corresponding selection components). During this access, the other digital lines 210 may be selectively isolated from the corresponding signal development components 250 and other signal development components 250 that interface the same domain. Additionally, the other digital lines 210 may be shunted or shielded from other digital lines 210, as described herein.

[0124] Thus, examples in accordance with the techniques disclosed herein may include examples in which the word lines 205 within a domain or the word lines 205 spanning multiple domains or some combination thereof are independent (e.g., selectively independent from each other). Examples in accordance with the techniques disclosed herein may also include examples in which the word lines 205 within a domain or the word lines 205 spanning multiple domains or some combination thereof are locked (e.g., hardwired) to be selected jointly (collectively). It should be understood that in examples in which the word lines 205 are independently selectable, these word lines 205 may still be operated simultaneously at least at a particular time or under particular conditions (e.g., even when locked). Additionally, examples in accordance with the techniques disclosed herein may include examples in which a number of digit lines 210 map to a number of signal development components 250 within a domain, and examples in which a number of digit lines 210 map to one signal development component 250 within a domain (e.g., the selection component 280 may have many-to-one or many-to-many functionality). Aspects of these and other exemplary variations are described throughout this disclosure, including reference Figure 8A , 8B and 8C).

[0125] In some examples, operations associated with word line selection may be time-limited to prevent data loss or corruption, which may involve waiting for an operation in progress on the accessed cell to complete. For example, when switching from a first word line 205-a in domain 310-a to a second word line 205-a in the same domain 310-a, this switch may require waiting for the cell access signal development of domain 310-a (e.g., of signal development component 250-a) to complete before the switch occurs. In examples in which a word line 205-a is shared across a number of domains (e.g., word line 205-a shared between domains 310-a-1 and 310-a-s, where word line 205-a-11 is functionally equivalent to word line 205-a-s1), when switching from a first shared word line 205-a to a second shared word line 205-a, this switch may require waiting for the cell access signal development of each of domains 310-a-1 and 310-a-s (e.g., of each of signal development components 250-a-1 and 250-a-s) to complete before the switch occurs.

[0126] In an example of circuit 300, each of domains 310-a may also include a set of shunts 330-a (e.g., digital line shunts, digital-to-board shunts) or otherwise be associated with a set of shunts 330-a. For example, domain 310-a-1 may include a set of shunts 330-a-11 to 330-a-1r. Each of shunts 330-a may be coupled to digital line 210-a and board line 215-a or coupled between digital line 210-a and board line 215-a. For example, for domain 310-a-1, shunt 330-a-11 may be coupled to digital line 210-a-11 and board line 215-a-11 or coupled between digital line 210-a-11 and board line 215-a-11. For example, shunt 330-a-11 may be configured to selectively couple digital line 210-a-11 and board line 215-a-11 (e.g., in response to a logic or switch signal DLS 11 ). In some examples, shunts 330-a may be configured to selectively equalize a bias between digital line 210-a and board line 215-a, or equalize one or more memory cells 105-b coupled to or coupled between digital line 210-a and board line 215-a. In some examples, shunts 330-a may be configured to selectively discharge one or more memory cells 105-b coupled to or coupled between digital line 210-a and board line 215-a.

[0127] In some examples, circuit 300 may be operated in accordance with a shunt mask. For example, when multiplexing is performed on domain 310-a (e.g., using selection component 320-2), shunts 330-a of shielded digital lines 210-a (e.g., digital lines 210-a not associated with the access operation being performed) may support selective coupling to board line 215-a to prevent or reduce data loss (e.g., charge leakage) of memory cells 105-b associated with the shielded digital lines 210-a. In other words, shunts 330-a may turn off bit transfer on shielded digital lines 210-a not associated with the access operation being performed.

[0128] The selection component 280-a and the selection component 320-a can include various component configurations and can each be referred to as a multiplexer, a transistor network, a transistor array, a switch network, or a switch array. In one example, the selection component 280-a can include a set of transistors each coupled to a sense amplifier 290-a (e.g., each coupled to a signal line 285-a). Each transistor in the set of transistors can also be coupled to a corresponding one of the signal development components 250-a (e.g., a corresponding one of the signal development lines 255-a-1 to 255-a-s). Each transistor in the set of transistors can be configured to selectively couple a corresponding one of the signal development components 250-a to the sense amplifier 290-a in response to one of a set of switch or logic signals provided to the gate of the transistor.

[0129] In some examples, the selection component 280-a or the selection component 320-a can include a decoder or other logic or selection signal conversion component. For example, the decoder of the selection component 280-a can receive a logic or selection signal (e.g., the signal SDCM), which can be a digital signal received via a signal bus (e.g., a signal having or otherwise representing multiple bits). In some examples, the decoder can receive the digital signal as an input to generate a set of binary signals (e.g., switch or logic signals) that can be applied to the gates of a set of transistors configured as a switch arrangement. For example, the decoder of the selection component 280-a can receive the selection signal SDCM as a 4-bit digital input signal and generate 16 binary (e.g., on / off) switch signals, each of which is applied to the gate of one of a set of 16 transistors configured as a switch arrangement.

[0130] In various examples, the select component 280-a may be configured such that one of the signal development components 250-a-1 to 250-a-s is coupled (e.g., selectively coupled) to the sense amplifier 290-a at a time, and the other ones of the signal development components 250-a-1 to 250-a-s may be decoupled (e.g., selectively decoupled) from the sense amplifier 290-a at the time (e.g., the time when the one of the signal development components 250-a-1 to 250-a-s is selectively coupled to the sense amplifier 290-a). In some examples, the select component 280-a may also be configured to support an operation in which none of the signal development components 250-a-1 to 250-a-s is coupled to the sense amplifier 290-a at a particular time (e.g., where each of the signal development components 250-a-1 to 250-a-s is selectively isolated from the sense amplifier 290-a). In various examples of the circuit 300, the select component 320-a may include a similar feature or group of features as the select component 280-a, or the select component 320-a may include a different feature or group of features from the select component 280-a.

[0131] In some examples of the circuit 300, the signal development component 250-a or the memory cell 105-b may be associated with a relatively high latency portion of the circuit 300 or otherwise be considered a relatively high latency portion of the circuit 300, and the sense amplifier 290-a may be associated with a relatively low latency portion of the circuit 300 or be considered a relatively low latency portion of the circuit 300. According to examples disclosed herein, the sense component 150-b may illustrate an example of partitioning a memory cell access circuit system into a high latency portion (e.g., the signal development component 250-a) and a low latency portion (e.g., the sense amplifier 290-a) and coupling a group of high latency portions with a group of low latency portions through a multiplexer (e.g., the select component 280-a).

[0132] In an example of the circuit 300, the select component 280-a may provide a first degree of data pipelining, which may reduce the impact of data access serialization (due to row buffer conflicts). For example, the select component 280-a may support overlapping data transfers on different sets of digital lines 210-a (e.g., different domains 310-a). Thus, the sense amplifier 290-a may be free to support read, write, rewrite, or refresh operations (e.g., when coupled to one of the signal development components 250-a), which occur while other signal development components 250-a are involved in data transfers (e.g., while other signal development components 250-a are coupled to the digital lines 210-a or the memory cell 105-b).

[0133] The signal development component 250-a group can be regarded as a small, fast local cache memory (e.g., a signal development cache memory), where the corresponding signal development component 250-a can be configured to store signal states different from the logical states stored at the memory cell 105-b. This configuration can be used to support reducing the row buffer conflict rate, increasing the internal bandwidth, or achieving other benefits. In some instances, the selection component 320-a can provide additional gains by providing a second level of data pipelining via the multiplexed digital line 210-a. Thus, according to the examples disclosed herein, the memory device 100 including the circuit 300 can include the signal development component 250-a multiplexed via the selection component 280-a or the digital line 210-a multiplexed via one or more selection components 320-a, which can compensate for portions of the access operations associated with different latencies or portions of the access circuitry.

[0134] Various memory devices (e.g., the memory device 100) can include various arrangements of the circuit 300. For example, the memory device 100 can include a group of sense components 150-b, or the sense components 150 can otherwise include a group of sense amplifiers 290-a and a corresponding group of multiplexed signal development components 250-a. In one instance, the memory device 100 or a portion thereof can include 16 sense amplifiers 290-a multiplexed with 1024 digital lines 210-a (which can include or exclude multiplexing via the selection component 320-a). In some instances, a group of sense amplifiers 290-a can be included in a composite array, where the group of sense amplifiers 290-a is accessed as a single sense amplifier "row" of the composite array. In various instances, the multiplexed digital lines 210-a can be in the same domain 310-a or different domains 310. In some instances, each of the domains 310-a can be independently controllable and can be accessed via the same row component 125 or different row components 125.

[0135] Figure 4A Illustrates an example of a read operation 400 that supports signal development caching in a memory device according to an example disclosed herein. The read operation 400 can illustrate a portion (e.g., a time interval) of the access operation associated with generating a cell access signal (e.g., a cell read signal, a cell write signal) and a latch signal when accessing a memory cell 105. For example, the read operation 400 can be divided into a read signal development portion 410 (e.g., a cell read portion), a latch signal generation portion 420, and a rewrite signal development portion 430 (e.g., a cell rewrite portion). The read operation 400 can employ circuitry that supports multiplexed signal development, such as with reference to Figure 3The described circuit 300. As an illustrative example, read operation 400 is described with reference to reading the logical state stored in memory cell 105-b-111 of circuit 300, but read operation 400 can illustrate operations that can be performed on any one or more of the memory cells 105-b of circuit 300.

[0136] The read signal development section 410 can be associated with charge sharing among the memory cell 105-b-111 (e.g., the capacitive storage element, linear capacitor, or ferroelectric capacitor of the memory cell 105-b-111), the digital line 210-a-11 (e.g., the intrinsic capacitance 230), and the signal development component 250-a-1. The read signal development section 410 can be an example of developing a signal (e.g., a signal state, a cache signal) at the signal development component 250-a-1 based at least in part on selectively coupling the signal development component 250-a-1 with the memory cell 105-b-111. In some instances, developing the read signal at the signal development component 250-a-1 is associated with a first latency (e.g., a relatively high latency or long duration). During the read signal development section 410, the signal development component 250-a-1 can be selectively decoupled from the sense amplifier 290-a.

[0137] In some instances of the read signal development section 410, the access line (e.g., the signal development line 255-a-1) of the signal development component 250-a-1 can be biased with a relatively high voltage, which can be associated with storing a relatively high voltage charge at the signal development component 250-a-1 (e.g., stored in the signal storage component (e.g., an integrating capacitor) of the signal development component 250-a-1). In some instances, this biasing can be associated with a "plate low" read operation, where during the read signal development section 410, the plate line 215-a-11 associated with the memory cell 105-b-111 is biased with a voltage (e.g., a ground voltage) lower than the voltage of the digital line 210-a-11 associated with the accessed memory cell 105-b-111.

[0138] The read signal development section 410 may also include selectively coupling the memory cell 105-b-111 to the signal development component 250-a-1. In some instances, the read signal development section 410 may include activating the word line 205-a-11 associated with the memory cell 105-b-111 being read (e.g., activating the logic signal WL1), which may selectively couple the memory storage element (e.g., the capacitor 220) to the corresponding digit line 210-a-11 (e.g., via the cell selection component 225 of the memory cell 105-b-111). In some instances, the read signal development section 410 may include selectively coupling the corresponding digit line 210-a-11 to the signal development component 250-a-1 (e.g., via the selection component 320-a-1, based on the selection signal DLM1, or some other switching component). Charge may thus be shared between the memory cell 105-b-111 and the signal development component 250-a-1 and may stabilize after a certain time (e.g., according to a time constant behavior), where the voltage changes of the digit line 210-a-11 and the signal development line 255-a-1 are at least partially based on the logic state stored by the memory cell 105-b-111.

[0139] In some instances, the read signal development section 410 may include a delay (e.g., a delay portion, a delay duration) between developing the read signal (e.g., the read signal at the signal development component 250 reaches a steady state, the read signal reaches a maximum at the signal development component 250) and providing the developed read signal (e.g., maintained by the signal development component 250) to the sense amplifier 290. In other words, there may be a delay or an inactive period during the read signal development section 410 prior to the start latch signal generation section 420, which in some instances may include the decay of the developed read signal (e.g., the decay of the maintained read signal). In some instances, the circuit 300 may be configured such that the duration of this delay or inactive period or the amount of delay of the developed read signal can be tolerated while still reliably detecting the logic state stored by the memory cell 105. In some instances, this functionality of the circuit 300 may be supported by a refresh operation of the signal development component 250 that mitigates the delay of the developed read signal (e.g., maintaining the cache signal at the signal development component 250). These and other configurations may support the signal development component 250 in performing a caching function in the circuit 300 (e.g., caching the developed read signal or the cache signal for a certain amount of time).

[0140] In some instances, charge sharing in the read signal development section 410 may be associated with a destructive read operation (e.g., where the originally stored logic state of memory cell 105-b-111 is lost or otherwise degraded at memory cell 105-b-111), and may thus be followed by a rewrite operation (e.g., rewrite signal development section 430). In some instances, the rewrite operation may not immediately follow the read signal development section 410, such as when the stored data is transferred to the signal development component 250, where the stored data may be stored and further read, written, or modified. In various instances, the data may be transferred back to the same memory cell 105 or a different memory cell 105, which may be associated with an operation that makes the signal development component 250 available for other operations. In some instances, charge sharing in the read signal development section 410 may be associated with a non-destructive read operation (e.g., where the originally stored logic state of memory cell 105-b-111 is maintained at memory cell 105-b-111), and may thus not be followed by a rewrite operation (e.g., the rewrite signal development section 430 may be omitted).

[0141] Charge sharing in the read signal development section 410 may be associated with a delay or latency referred to as a row-to-column address delay. In DRAM applications, data may be stored as electrode charge at the memory cell 105 and may respond relatively quickly (e.g., with a relatively low latency). In FeRAM applications, data may be stored as a cell state in the form of dipole orientation or polarization at the memory cell 105. The dynamics of these dipoles may be relatively slow (e.g., with a relatively high latency), which may result in a longer sense time for FeRAM applications (e.g., longer than DRAM applications). Thus, in some instances (e.g., in FeRAM applications), the read signal development section 410 may be associated with a relatively high latency or long duration (e.g., compared to the latch signal generation section 420). In some FeRAM applications, for example, the latency associated with the operation of the read signal development section 410 may be approximately 50 nanoseconds.

[0142] In some instances of the read signal development section 410, shunts 330-a associated with other memory cells 105-b of the domain 310-a-1 may be selected or activated, such as shunts 330-a-12 (not shown, which may be associated with digital line 210-a-12 or board line 215-a-12) to 330-a-1r, which may equalize the bias across the unaccessed memory cells 105-b (e.g., equalize the bias between digital line 210-a-12 and board line 215-a-12, equalize the bias between digital line 210-a-1r and board line 215-a-1r, etc.). In a FeRAM application, for example, this bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cell 105-b-111 being accessed during the read signal development section 410.

[0143] The latch signal generation section 420 may be associated with charge sharing between the signal development component 250-a-1 and the sense amplifier 290-a. The latch signal generation section 420 may be an example of generating an output signal of the sense amplifier 290-a (e.g., an amplifier component) at least partially based on the developed signal (e.g., a cell read signal) at the signal development component 250-a-1. In some instances, generating the latch signal at the sense amplifier 290-a is associated with a second latency (e.g., a relatively low latency or short duration). Transitioning from the read signal development section 410 to the latch signal generation section 420 may include selectively coupling the signal development component 250-a-1 and the sense amplifier 290-a.

[0144] In some instances, selectively coupling the signal development component 250-a-1 and the sense amplifier 290-a may include selection via the selection component 280-a based on a logic selection signal SDCM. In some instances, selectively coupling the signal development component 250-a-1 and the sense amplifier 290-a may include selective coupling via some other switching component (e.g., an isolation switch component) between the signal development component 250-a-1 and the sense amplifier 290-a. In some instances, the charge sharing in the latch signal generation section 420 may be relatively rapid and may take a fraction of the amount of time involved in charge sharing between the memory cell 105-b-11 and the signal development component 250-a-1. In other words, the duration of the latch signal generation section 420 may be shorter than the read signal development section 410. In some FeRAM applications, for example, the latency associated with the operation of the latch signal generation section 420 may be approximately 5 nanoseconds to 10 nanoseconds.

[0145] In some instances, the latch signal generation section 420 may include a "firing" sense amplifier 290-a, which may include selectively coupling one or more voltage sources (e.g., low voltage source 293, high voltage source 294) to the sense amplifier 290-a. Accordingly, an output signal may be generated at the sense amplifier 290-a that is at least partially based on the cell read signal (e.g., at least partially based on the logic state stored by the memory cell 105-b-111). The output signal may be transferred from the sense amplifier 290-a via the I / O line 295 to another component of the memory device (e.g., the input / output component 160) to provide an indication of the data stored by the memory cell 105-b-111. In some instances, the output signal or some other signal associated with the generated latch signal may also be fed back to the signal development component 250-a-1 or otherwise shared with the signal development component 250-a-1, which in some instances may support a rewrite operation (e.g., after a destructive read operation). For example, as part of the latch signal generation section 420, based on the generated latch signal or output signal (e.g., based on whether the memory cell 105-b-111 stores a logic 0 or a logic 1), the signal development component 250-a-1 may transfer or otherwise share or generate a rewrite signal (e.g., via the signal development line 255-a-1). In some instances, the generated latch signal or output signal may be fed back to the signal development component 250-a-1 to reinforce a charge or other signal maintained at the signal development component 250-a-1, which may support a rewrite operation on the memory cell 105-b-111.

[0146] In some instances of the latch signal generation section 420, shunts 330-a associated with other memory cells 105-b of the domain 310-a-1 may be selected or activated, such as shunts 330-a-12 (not shown, which may be associated with the digit line 210-a-12 or the plate line 215-a-12) to 330-a-1r, which may equalize the bias across the unaccessed memory cells 105-b (e.g., equalize the bias between the digit line 210-a-12 and the plate line 215-a-12, equalize the bias between the digit line 210-a-1r and the plate line 215-a-1r, etc.). In a FeRAM application, for example, this bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cell 105-b-111 being accessed during the latch signal generation section 420.

[0147] The rewrite signal development section 430 may be associated with charge sharing between the memory cell 105-b-111, the digit line 210-a-11, and the signal development component 250-a-1. The rewrite signal development section 430 may be an instance of developing a cell access signal (e.g., a cell write signal, a cell rewrite signal) at or using the signal development component 250-a-1. In some cases, developing a cell access signal (e.g., a cell write signal, a cell rewrite signal) at or using the signal development component 250-a-1 may be at least partially based on the latch signal of the sense amplifier 290-a (e.g., generated during the latch signal generation section 420). In some instances, the cell access signal (e.g., a cell write signal, a cell rewrite signal) at or using the signal development component 250-a-1 may be based on the charge or voltage maintained at the signal development component 250-a-1 (e.g., at least partially based on the read signal development section 410), where the charge or voltage maintained at the signal development component 250-a-1 may indicate the logical state originally stored by the memory cell 105-b-111. In some instances, the charge or voltage maintained at the signal development component 250-a-1 may be independent of the latch signal at the sense amplifier 290-a, or may be enhanced by the latch signal at the sense amplifier 290-a (e.g., enhanced during the latch signal generation section 420).

[0148] In some instances, developing the rewrite signal at the signal development component 250-a-1 is associated with a third latency (e.g., a relatively high latency or long duration) that may or may not be equal to the first latency. The transition from the latch signal generation section 420 to the rewrite signal development section 430 may include selectively decoupling or isolating the signal development component 250-a-1 from the sense amplifier 290-a (e.g., via the selection component 280-a or the isolation switch component). Although the rewrite signal development section 430 may support rewriting the logical state to the memory cell 105 that has been discharged, depolarized, or otherwise damaged or degraded during a read operation, in instances of non-destructive read operations (e.g., when 105-b-111 maintains the stored logical state after the read signal development section 410), the rewrite signal development section 430 may be omitted, and the latch signal generation section 420 may be followed by another access operation (e.g., a read operation, a write operation, a refresh operation).

[0149] In various examples, the rewriting of memory cell 105-b-111 during rewrite signal development section 430 may be performed or modified based on whether the rewrite signal is generated or otherwise provided by sense amplifier 290-a or based on whether the rewrite signal is generated or otherwise provided by signal development component 250-a. For example, the rewrite operation of rewrite signal development section 430 may be performed without relying on the rewrite signal of sense amplifier 290-a, such as when signal development component 250-a is configured to locally maintain a charge or other state (e.g., cache state, signal state) associated with the originally stored logical state of memory cell 105-b-111 until it is written back to memory cell 105-b-111 (e.g., providing a local caching function related to the rewrite operation). In other words, depending on whether signal development component 250-a depends on the latch signal of sense amplifier 290-a to rewrite memory cell 105-b-111, read signal development section 410 or latch signal generation section 420 may be "destructive" or may not be "destructive" from the perspective of signal development component 250-a. In some examples (e.g., when signal development component 250-a is configured to maintain a charge or other state indicating the originally stored logical state of memory cell 105-b-111), the rewriting of memory cell 105-b-111 may occur after a certain delay period (e.g., in rewrite signal development section 430) depending on the duration for which signal development component 250-a-1 is configured to maintain this charge or other state or the type of control logic implementing the write-back (e.g., first-in-first-out (FIFO), least recently used (LRU), or others).

[0150] In some examples of the rewrite operation, circuit 300 may be configured to couple memory cell 105-b-111 to a high voltage source (e.g., high voltage rail, via signal development component 250-a-1), which may be a direct coupling via a pull-up or pull-down circuitry (e.g., transistors or other switching components of signal development component 250-a-1). In some examples, signal development component 250-a-1 may be configured with a capacitor or other charge storage component, and latch signal generation section 420 or rewrite signal development section 430 may include charging or refreshing the capacitor or other charge storage component with a charge sufficient to rewrite memory cell 105-b-111 (e.g., during rewrite signal development section 430). Thus, in various examples, signal development component 250-a-1 may rewrite a logical state to memory cell 105-b-111, which may be performed when signal development component 250-a-1 is selectively decoupled from sense amplifier 290-a such that sense amplifier 290-a is free to support operations regarding other signal development components 250-a.

[0151] Charge sharing in the rewrite signal development section 430 can be associated with a delay or latency referred to as row precharge delay, which can include rewriting, fully or in part, the logic state initially stored at the memory cell 105-b-111. For example, to rewrite a logic 0, the digit line 210-a-11 can be biased to a positive voltage (e.g., 1.5V) and the plate line 215-a-11 can be biased to ground or a negative voltage (e.g., 0V). To rewrite a logic 1, the digit line 210-a-11 can be biased to ground or a negative voltage (e.g., 0V) and the plate line 215-a-11 can be biased to a positive voltage (e.g., 1.5V). In some cases, the biasing of the digit line 210-a-11 and the plate line 215-a-11 can be at least partially based on the generated latch signal (e.g., before the sense amplifier 290-a and the signal development component 250-a-1 are selectively isolated). For example, during the rewrite signal development section 430, the signal development component 250-a-1 or the sense amplifier 290-a can bias the digit line 210-a-11 to a positive voltage or a ground voltage at least partially based on the latch signal. In some cases, this biasing can be based on the charge or other state maintained at the signal development component 250-a-1, which can be independent of the generated latch signal (e.g., generated using the sense amplifier 290-a).

[0152] In DRAM applications, data can be written as electrode charge at the memory cell 105 and can respond relatively quickly (e.g., relatively low latency). In FeRAM applications, data can be written as the cell state in the form of dipole orientation or polarization at the memory cell 105. The dynamics of these dipoles can be relatively slow (e.g., relatively high latency), which can result in a longer write time for FeRAM applications (e.g., longer than DRAM applications). Thus, in some instances (e.g., in FeRAM applications), the rewrite signal development section 430 can be associated with a relatively high latency or long duration (e.g., compared to the latch signal generation section 420). At the end of the rewrite signal development section 430, all digit lines 210-a-11 and all plate lines 215-a of the domain 310-a-1 can be biased to the ground voltage, effectively equalizing the bias across each of the memory cells 105-b in the domain 310-a-11, which can support maintaining the logic state stored by the memory cells 105-b over time.

[0153] In some instances, shunt 330-a associated with other memory cells 105-b of domain 310-a-1 may be selected or activated during rewrite signal development section 430, such as shunt 330-a-12 (not shown, which may be associated with digital line 210-a-12 or board line 215-a-12) to 330-a-1r, which may equalize the bias across unaccessed memory cells 105-b (e.g., equalize the bias between digital line 210-a-12 and board line 215-a-12, equalize the bias between digital line 210-a-1r and board line 215-a-1r, etc.). This bias equalization may prevent or reduce data loss (e.g., due to charge leakage) of memory cells 105-b other than memory cell 105-b-111 being rewritten during rewrite signal development section 430.

[0154] Read operation 400 may be associated with the reading of a single memory cell 105-b-11 having a total duration t A1 -t A0 and includes a read signal development section 410, a latch signal generation section 420, and a rewrite signal development section 430 for reading a single memory cell 105-b-111. In instances where read operation 400 does not employ multiplexed signal development techniques (e.g., a sequence of read operations 400 using the same signal development component 250), a subsequent read operation employing sense amplifier 290-a may follow rewrite signal development section 430. Thus, performing multiple read operations 400 (e.g., reading multiple memory cells 105-b) using the same signal development component 250 may involve a multiple of the duration t A1 -t A0 (e.g., at least 2*(t A1 -t A0 ) to read two memory cells 105-b). However, multiplexing signal development component 250-a (e.g., via selection component 280-a) may reduce the amount of time involved in sense amplifier 290-a reading multiple memory cells 105-b.

[0155] Figure 4BThe figure illustrates an example of a read operation 450 of a cache for signal development in a support memory device according to an example disclosed herein. The read operation 450 may illustrate a portion (e.g., a time interval) of an access operation (e.g., a multi-cell access operation) associated with generating cell access signals (e.g., cell read signals, cell write signals) and latch signals when accessing four memory cells 105 (e.g., via four signal development components 250). For example, the read operation 450 may be divided into a read signal development portion 410-a, a latch signal generation portion 420-a, and a rewrite signal development portion 430-a for each of a group of memory cells 105-b, which may be examples of the corresponding portions described in reference Figure 4A The described corresponding portions. The read operation 450 may employ a circuit system that supports multiplexed signal development, such as the circuit 300 described in reference Figure 3 The described circuit 300. The read operation 450 illustrates an example of separating signal development operations from input / output operations, which may increase data throughput in the memory device.

[0156] As an illustrative example, read operation 450 is described with reference to reading the logic states stored in four memory cells 105-b of four different domains 310-a, where each of the different domains is associated with a respective signal development component 250-a that is multiplexed with sense amplifier 290-a. For example, read signal development section 410-a-1, latch signal generation section 420-a-1, and rewrite signal development section 430-a-1 may refer to the read operation of memory cell 105-b-111 (e.g., of domain 310-a-1 associated with signal development component 250-a-1). For example, read signal development section 410-a-2, latch signal generation section 420-a-2, and rewrite signal development section 430-a-2 may refer to the read operation of memory cell 105-b-211 (e.g., of domain 310-a-2 (not shown) that may be associated with signal development component 250-a-2). For example, read signal development section 410-a-3, latch signal generation section 420-a-3, and rewrite signal development section 430-a-3 may refer to the read operation of memory cell 105-b-311 (e.g., of domain 310-a-3 (not shown) that may be associated with signal development component 250-a-3). For example, read signal development section 410-a-4, latch signal generation section 420-a-4, and rewrite signal development section 430-a-4 may refer to the read operation of memory cell 105-b-411 (e.g., of domain 310-a-4 (not shown) that may be associated with signal development component 250-a-4). Each of signal development components 250-a-1, 250-a-2, 250-a-3, and 250-a-4 may be selectively coupled to the same sense amplifier 290-a via selection component 280-a (e.g., based on logic selection signal SDCM).

[0157] Each of the read signal development portions 410-a may be associated with charge sharing (which may occur during overlapping time intervals) between a corresponding memory cell 105-b, a corresponding digit line 210-a, and a corresponding signal development component 250-a. The read signal development portion 410-a may be an instance of developing a signal (e.g., a cell read signal, a cache signal, a signal state) at the signal development component 250-a at least in part based on selectively coupling the signal development component 250-a among a plurality of signal development components 250-a with a memory cell 105-b among a plurality of memory cells 105-b. The read signal development portion 410-a-1 may be an instance of coupling a memory cell 105-b-111 (e.g., a first memory cell) to a signal development component 250-a-1 (e.g., a first signal development component) during a first time interval (e.g., and at least in part based on determining to access the memory cell 105-b-111) (e.g., via a selection component 280-a, via a selection component 320-a-1), and the read signal development portion 410-a-2 may be an instance of coupling a memory cell 105-b-211 (e.g., a second memory cell) to a signal development component 250-a-2 (e.g., a second signal development component) during a second time interval overlapping the first time interval (e.g., and at least in part based on determining to access the memory cell 105-b-211) (e.g., via a selection component 280-a, via a selection component 320-a-2).

[0158] Thus, charge may be shared between the memory cell 105-b-111 and the signal development component 250-a-1, between the memory cell 105-b-211 and the signal development component 250-a-2, between the memory cell 105-b-311 and the signal development component 250-a-3, and between the memory cell 105-b-411 and the signal development component 250-a-4. In other words, charge may be shared via the signal development components 250-a-1 to 250-a-4 during overlapping time intervals. In some instances, developing a cell read signal at the signal development components 250-a-1 to 250-a-4 is associated with a first latency (e.g., a relatively high latency or a long duration).

[0159] In some instances of the read signal development section 410-a, shunts 330-a associated with other memory cells 105-b of the corresponding domain 310-a may be selected or activated, which may equalize the bias across the unaccessed memory cells 105-b. For example, for domain 310-a-1, during the read signal development section 410-a-1, the bias between the digit line 210-a-12 and the plate line 215-a-12 may be equalized via the shunt 330-a-12, the bias between the digit line 210-a-13 and the plate line 215-a-13 may be equalized via the shunt 330-a-13, and so on. In a FeRAM application, for example, this bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cells 105-b being accessed during the corresponding read signal development section 410.

[0160] The latch signal generation section 420-a may be associated with charge sharing (which may occur in non-overlapping time intervals) between the signal development component 250-a-1 and the corresponding sense amplifier 290-a. The latch signal generation sections 420-a may each be an instance of generating an output signal of the sense amplifier 290-a based at least in part on the developed signal at the corresponding signal development component 250-a (e.g., based on a cell read signal, a cache signal, or a signal state). In some instances, generating a latch signal at the sense amplifier 290-a is associated with a second latency (e.g., a relatively low latency or short duration). Transitioning from the read signal development section 410 to the corresponding latch signal generation section 420-a may include selectively coupling the corresponding signal development component 250-a and the sense amplifier 290-a.

[0161] The latch signal generation section 420-a-1 may be an instance of coupling the signal development component 250-a-1 (e.g., the first signal development component) and the sense amplifier 290-a (e.g., via the selection component 280-a) during a third time interval following the first time interval. In some instances, the third time interval may at least partially overlap the second time interval, or the third time interval may be within the second time interval. The latch signal generation section 420-a-2 may be an instance of coupling the signal development component 250-a-2 (e.g., the second signal development component) and the sense amplifier 290-a (e.g., via the selection component 280-a) during a fourth time interval following the second time interval (e.g., and following the third time interval).

[0162] Latch signal generation parts 420-a-1 to 420-a-4 may be executed according to a sequence, which may be at least partially based on a sequence selected or otherwise indicated by a logic selection signal SDCM for a signal development component. In some examples, each of the latch signal generation parts 420-a may separate a gap or a delay period (e.g., a period between the latch signal generation part 420-a-1 and the latch signal generation part 420-a-2), and the gap or the delay period may be associated with: a gap or a delay for selecting the component 280-a, a gap or a delay associated with changing the value of the logic selection signal SDCM, or a period during which no signal development component 250-a is coupled to the sense amplifier 290-a. In other words, an access operation may include a gap or a delay period between when one signal development component 250-a is selectively decoupled from the sense amplifier 290-a and when another signal development component 250-a is selectively coupled to the sense amplifier 290-a. In other examples, this decoupling and coupling may be configured to occur simultaneously.

[0163] In some examples, the latch signal generation part 420-a may include "activating" the sense amplifier 290-a, which may include selectively coupling one or more voltage sources (e.g., a low voltage source 293, a high voltage source 294) to the sense amplifier 290-a. Accordingly, according to the sequence of the latch signal generation parts 420-a-1 to 420-a-4, an output signal sequence may be generated at the sense amplifier 290-a that is at least partially based on a corresponding unit read signal sequence (e.g., at least partially based on the logic states stored in the accessed memory cells 105-b-111 to 105-b-411 according to the sequence or the read signal development parts 410-a-1 to 410-a-4).

[0164] The output signal may be transferred from the sense amplifier 290-a to another component of the memory device (e.g., an input / output component 160) via the I / O line 295 to provide an indication of data stored in the memory cell 105-b. In some examples, the output signal or some other signal associated with the generated latch signal may also be fed back to the signal development components 250-a-1 to 250-a-4 or otherwise shared by the signal development components 250-a-1 to 250-a-4, which may support a rewrite operation (e.g., after a destructive read operation) in some examples. For example, as part of the latch signal generation part 420, based on the generated latch signal or output signal (e.g., based on whether the memory cell 105-b stores a logic 0 or a logic 1), a corresponding one of the signal development components 250-a-1 to 250-a-4 may be utilized to transfer or otherwise share a rewrite signal.

[0165] In some instances of the latch signal generation section 420-a, shunts 330-a associated with other memory cells 105-b of the corresponding domain 310-a may be selected or activated, which may equalize the bias across the unaccessed memory cells 105-b. For example, for domain 310-a-1, during the latch signal generation section 420-a-1, the bias between digital line 210-a-12 and board line 215-a-12 may be equalized via shunt 330-a-12, the bias between digital line 210-a-13 and board line 215-a-13 may be equalized via shunt 330-a-13, and so on. In a FeRAM application, for example, this bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cells 105-b being accessed during the corresponding latch signal generation section 420.

[0166] The rewrite signal development section 430-a may be associated with charge sharing between a respective one of the memory cells 105-b, a respective one of the digital lines 210-a, and a respective one of the signal development components 250-a. The rewrite signal development sections 430-a may each be an instance of developing a cell access signal (e.g., a cell write signal, a cell rewrite signal) at the signal development component 250-a based at least in part on the latch signal of the sense amplifier 290-a, or may be independent of the latch signal of the sense amplifier 290-a. In some instances, developing the rewrite signal at the signal development component 250-a-1 is associated with a third latency (e.g., a relatively high latency or long duration), which may or may not be equal to the first latency. Transitioning from the latch signal generation section 420-a to the corresponding rewrite signal development section 430-a may include selectively isolating the respective signal development component 250-a from the sense amplifier 290-a (e.g., via the selection component 280-a or another isolation switch component). Although the rewrite signal development section 430-a may support rewriting the logic state to a memory cell 105 that has been discharged, depolarized, or otherwise damaged or degraded during a read operation, in instances of non-destructive read operations, the rewrite signal development section 430-a may be omitted (e.g., associated with charge sharing between the signal development component and the memory cell).

[0167] In some instances of the rewrite signal development section 430-a, shunts 330-a associated with other memory cells 105-b of the corresponding domain 310-a may be selected or activated, which may equalize the bias across the unaccessed memory cells 105-b. For example, for domain 310-a-1, during the rewrite signal development section 430-a-1, the bias between the digital line 210-a-12 and the board line 215-a-12 may be equalized via the shunt 330-a-12, the bias between the digital line 210-a-13 and the board line 215-a-13 may be equalized via the shunt 330-a-13, and so on. This bias equalization may prevent or reduce data loss (e.g., due to charge leakage) of memory cells 105-b other than the memory cells 105-b being accessed during the rewrite signal development section 430-a.

[0168] Similar to the read operation 400, the read operation 450 may also be associated with the reading of a single memory cell 105 (e.g., via the sense amplifier 290-a) having a total duration of t A1 -t A0 and may include a read signal development section 410-a-1, a latch signal generation section 420-a-1, and a rewrite signal development section 430-a-1 for reading a single memory cell 105-b-111. However, by employing multiplexed signal development as disclosed herein, performing multiple read operations via the same sense amplifier 290-a may not take an integer multiple of the duration t A1 -t A0 (e.g., where the integer multiple may correspond to the number of memory cells 105-b accessed in parallel). Specifically, by generating cell access signals (e.g., cache signals, signal states) in overlapping time intervals (e.g., the time intervals of the read signal development section 410-a or the rewrite signal development section 430-a of the signal development component 250-a-1 that overlap with the time intervals of the read signal development section 410-a or the rewrite signal development section 430-a of the signal development component 250-a-2, etc.), multiple memory cells 105-b may be read in a time shorter than this integer multiple. In other words, according to the described techniques for multiplexed signal development, the sense amplifier 290-a may support reading four memory cells 105-b within a duration of t A3 -t A2 which may be shorter than 4*(t A1 -t A0 )(e.g., shorter than the corresponding integer multiple of the duration for reading a single memory cell 105-b).

[0169] In one example, the first set of read rewrite signal development portions 430-a-1, 430-a-2, 430-a-3, and 430-a-4 may be respectively followed by a second set of read read signal development portions 410-a-5, 410-a-6, 410-a-7, and 410-a-8. The first set of reads may be associated with a first digital thread index (e.g., a value of "1" as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4), and the second set of reads may be associated with a second digital thread index (e.g., a value of "2" as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4). Alternatively, more generally, the first set of reads and the second set of reads may differ at least in part based on a selected digital line 210-a of the read operation.

[0170] In some examples (e.g., where the selection component 320-a across domain 310-a is independently controllable and the logic select signal DLM across domain 310-a is independently controllable), upon completion of the rewrite signal development portion 430 for the signal development component 250, a new digital line 210-a may be selected for the same signal development component 250 (e.g., via the selection component 320-a). In other words, as illustrated in the example of the read operation 450, for the signal development component 250-a multiplexed with the same sense amplifier 290-a, the rewrite signal development portion 430-a of the first set of reads may overlap in time with the read signal development portion 410-a of the second set of reads (e.g., read signal development portion 410-a-5 overlaps with rewrite signal development portion 430-a-4). Thus, in an example of the read operation 450 where domains 310-a-1 to 310-a-4 are independently controllable, the period for reading four memory cells 105 may be represented by time t A3 -t A2 as illustrated, time t A3 -t A2 In some examples may be equal to or approximately equal to time t A1 -t A0 , or t A1 -t A0 plus some delay or gap period (e.g., associated with selecting a new digital line 210-a via the selection component 320-a), or some other duration based on: the overall duration associated with the read operation (e.g., t A1 -t A0 ), the respective latencies of the sub-operations (e.g., the relative durations of the read signal development portion 410, the latch signal generation portion 420, the rewrite signal development portion 430), and the degree of multiplexing (e.g., the number of signal development components 250-a multiplexed with the sense amplifier 290-a).

[0171] In some instances, a subsequent read may be performed on memory cell 105-b, which is coupled to a different digit line 210-a than the previous read operation but to the same activated word line 205-a (this may reduce latency). For example, maintaining the selected word line 205-a may eliminate the word line deselection operation and the subsequent word line selection operation. Such instances may be accompanied by shunting the digit line 210-a associated with the earlier read operation (e.g., a digit line 210-a that was not previously shunted), and not shunting the digit line 210-a associated with the later read operation (e.g., a digit line 210-a that was shunted during an earlier write operation).

[0172] In another example (not shown), a first set of reads may be associated with a first common word line (e.g., where logical word lines WL 11 、WL 21 、WL 31 and WL 41 are simultaneously activated), and a second set of reads may be associated with a second common word line (e.g., where logical word lines WL 12 、WL 22 、WL 32 and WL 42 are simultaneously activated). Alternatively, more generally, the first set of reads and the second set of reads may differ at least in part based on the selected common word line 205-a of the read operation. In some instances (e.g., where the word lines 205-a across domain 310-a are not independently controllable), a new word line 205-a may be selected as soon as the latch signal generation section 420 or the rewrite signal development section 430 is completed for all multiplexing signal development components 250-a (e.g., associated with sense amplifier 290-a or other groups of domains 310-a that are not independently controllable). In other words, in some instances, the latch signal generation section 420 or the rewrite signal development section 430 of the first set of reads may not overlap in time with the read signal development section 410 of the second set of reads for the multiplexing signal development components multiplexed with the same sense amplifier 290-a.

[0173] For example, when the word line 205-a spans domains 310-a-1 to 310-a-4 and is not independently controllable, the read signal development section 410-a-5 can follow or otherwise trail the rewrite signal development section 430-a-4. Thus, in instances where domain 310-a is not independently controllable, the period for reading four memory cells 105 can be equal to or nearly equal to the combined time of one read signal development section 410-a, each of the latch signal generation sections 420-a-1 to 420-a-4 of the multiplexed signal development components 250-a-1 to 250-a-4, and one rewrite signal development section 430-a, plus any associated delays or gap periods (e.g., associated with selecting a new word line 205-a or a new signal development component 250-a via the selection component 280-a). Thus, in some instances, this period where domain 310-a is not independently controllable can be longer than the period illustrated by A2 -t A0 the illustration.

[0174] Accordingly, in accordance with various examples disclosed herein, the advantages provided by the described signal development multiplexing (e.g., reduced latency when accessing multiple memory cells 105-b in parallel) can scale with the relative latency differences (e.g., durations) of the read signal development section 410, the latch signal generation section 420, and the rewrite signal development section 430. The advantages provided by the described signal development multiplexing can also depend on whether domain 310-a is configured to be independently controllable or is controlled via a common access line or a common logic signal.

[0175] Although the techniques of read operation 450 are described with reference to a single sense amplifier 290-a, the techniques of read operation 450 may be repeated for each sense amplifier 290 of a sense amplifier array, including various operations being performed concurrently (e.g., using simultaneous or offset start or trigger in parallel) to support further pipelining of read operations in memory device 100. For example, read operation 450 or another read operation performed concurrently or with an offset relative to read operation 450 may include signal development operations that include read signal development portions 410-b-1, 410-b-2, 410-b-3, and 410-b-4 (not shown) associated with different sense amplifiers 290 (e.g., of the same sense amplifier array). In some instances, read signal development portion 410-b-1 may be started simultaneously with or otherwise performed concurrently or with an offset relative to read signal development portion 410-a-1 (e.g., according to simultaneous access of multiple memory cells of a row, region, or sub-region, according to concurrent signal exchange with a cache line). Similarly, read signal development portion 410-b-2 may be started simultaneously with or otherwise performed concurrently or with an offset relative to read signal development portion 410-a-2, and so on.

[0176] In addition, read operation 450 or another read operation performed concurrently with read operation 450 may include input / output operations that include latch signal generation portions 420-b-1, 420-b-2, 420-b-3, and 420-b-4 (not shown) associated with different sense amplifiers 290 (e.g., of the same sense amplifier array). In some instances, latch signal generation portion 420-b-1 may be started simultaneously with or otherwise performed concurrently or with an offset relative to latch signal generation portion 420-a-1 (e.g., according to simultaneous sensing at the sense amplifier array, according to simultaneous latching at a set of latches of a sensing component or I / O component, according to concurrent signal exchange with a cache line). Similarly, latch signal generation portion 420-b-2 may be started simultaneously with or otherwise performed concurrently or with an offset relative to latch signal generation portion 420-a-2, and so on. Although described in the context of two parallel reads associated with two different sense amplifiers 290, the described techniques may be applied to any number of parallel reads. For example, to support a 64-bit information transfer scheme, 64 parallel reads may be performed using 64 sense amplifiers 290 as disclosed herein.

[0177] Figure 5AThe figure illustrates an example of a write operation 500 for caching signals in a support memory device according to an example disclosed herein. The write operation 500 may illustrate a portion (e.g., a time interval) of an access operation associated with generating a latch signal and a cell access signal (e.g., a cell write signal) when accessing a memory cell 105. For example, the write operation 500 may be divided into a latch signal generation portion 510 and a write signal development portion 520 (e.g., a cell write portion). The write operation 500 may employ a circuit system that supports multiplexed signal development, such as the circuit 300 described with reference to Figure 3 As an illustrative example, the write operation 500 is described with reference to writing a logical state to the memory cell 105-b-111 of the circuit 300, but the write operation 500 may illustrate an operation that can be performed on any one or more of the memory cells 105-b of the circuit 300.

[0178] The latch signal generation portion 510 may be associated with charge sharing between the signal development component 250-a-1 and the sense amplifier 290-a. The latch signal generation portion 510 may be an example of generating a latch signal (e.g., a cache memory signal, a signal state) at the sense amplifier 290-a or the signal development component 250-a-1 at least partially based on a write command or a write signal (e.g., from the input / output component 160 or the memory controller 170) received via the I / O line 295-a. In some examples, generating the latch signal at the sense amplifier 290-a or the signal development component 250-a-1 is associated with a fourth latency (e.g., a relatively low latency or a short duration), which may be the same as or different from the second latency of the latch signal generation portion 420 described with reference to the read operations 400 and 450.

[0179] The latch signal generation portion 510 may include selectively coupling the signal development component 250-a-1 and the sense amplifier 290-a (e.g., at the start of the latch signal generation portion 510, or at another time after other operations of the latch signal generation portion 510 (e.g., after receiving a write command or a write signal via the I / O line 295-a)). In some examples, selectively coupling the signal development component 250-a-1 and the sense amplifier 290-a may include selection via the selection component 280-a based on a logic selection signal SDCM. In some examples, selectively coupling the signal development component 250-a-1 and the sense amplifier 290-a may include selective coupling via some other switching component (e.g., an isolation switch component) between the signal development component 250-a-1 and the sense amplifier 290-a.

[0180] In some instances, the latch signal generation section 510 may include an "activate" sense amplifier 290-a, which may include selectively coupling one or more voltage sources (e.g., low voltage source 293, high voltage source 294) to the sense amplifier 290-a. Accordingly, a latch signal may be generated at the sense amplifier 290-a that is at least partially based on a write command or write signal (e.g., received via I / O line 295-a). The generated latch signal or some other signal associated with the generated latch signal may be passed to or otherwise shared with the signal development component 250-a-1 (e.g., storing a cache signal or signal state at a cache element of the signal development component 250-a-1) to support the writing of the memory cell 105-b-111. For example, as part of the latch signal generation section 510, based on the generated latch signal (e.g., based on whether the memory cell 105-b-111 will store a logic 0 or a logic 1), a write signal may be passed or otherwise shared or generated by the signal development component 250-a-1 (e.g., via signal development line 255-a-1).

[0181] The write signal development section 520 may be associated with charge sharing among the memory cell 105-b-111, the digit line 210-a-11, and the signal development component 250-a-1. The write signal development section 520 may be an instance where a cell access signal (e.g., a cell write signal) is developed at or using the signal development component 250-a-1 that is at least partially based on the latch signal of the sense amplifier 290-a. In some instances, developing the write signal at the signal development component 250-a-1 is associated with a fifth latency (e.g., a relatively high latency or long duration), which may or may not be equal to the third latency of the rewrite signal development section 430 described with reference to the read operations 400 and 450. Transitioning from the latch signal generation section 510 to the write signal development section 520 may include selectively decoupling or isolating the signal development component 250-a-1 from the sense amplifier 290-a (e.g., via a selection component 280-a or an isolation switch component).

[0182] In some instances of the write operation, circuit 300 may be configured to couple memory cell 105-b-111 to a high voltage source (e.g., a high voltage rail, via signal development component 250-a-1), which may be a direct coupling via pull-up or pull-down circuitry (e.g., transistors or other switching components of signal development component 250-a-1). In some instances, signal development component 250-a-1 may be configured with a capacitor or other charge storage component, and the latch signal generation section 510 or the write signal development section 520 may include charging or refreshing the capacitor or other charge storage component with charge sufficient to rewrite memory cell 105-b-111 (e.g., during write signal development section 520). Thus, in various instances, signal development component 250-a-1 may write a logic state to memory cell 105-b-111, which may be performed when signal development component 250-a-1 is selectively decoupled from sense amplifier 290-a such that sense amplifier 290-a is free to support operations regarding other signal development components 250-a).

[0183] Charge sharing in write signal development section 520 may also be associated with a delay or latency referred to as row precharge delay, which may include writing a logic state to memory cell 105-b-111 based on a write command. For example, to write a logic 0, digit line 210-a-11 may be biased to a positive voltage (e.g., 1.5V) and plate line 215-a-11 may be biased to ground or a negative voltage (e.g., 0V). To write a logic 1, digit line 210-a-11 may be biased to ground or a negative voltage (e.g., 0V) and plate line 215-a-11 may be biased to a positive voltage (e.g., 1.5V). The biasing of digit line 210-a-11 and plate line 215-a-11 may be at least partially based on the generated latch signal (e.g., before sense amplifier 290-a is selectively isolated from signal development component 250-a-1). For example, during write signal development section 520, signal development component 250-a-1 may bias digit line 210-a-11 to a positive voltage or ground voltage at least partially based on the latch signal (e.g., at least partially based on the write command). At the end of write signal development section 520, all digit lines 210-a-11 and all plate lines 215-a of domain 310-a-1 may be biased to ground voltage, effectively equalizing the bias across each of the memory cells 105-b in domain 310-a-11, which may support maintaining the logic state stored by memory cells 105-b over time.

[0184] In some instances, shunts 330-a associated with other memory cells 105-b of domain 310-a-1 may be selected or activated during write signal development section 520, such as shunts 330-a-12 to 330-a-1r, which may equalize the bias across unaccessed memory cells 105-b (e.g., equalize the bias between digit line 210-a-12 and plate line 215-a-12, equalize the bias between digit line 210-a-1r and plate line 215-a-1r, etc.). This bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cell 105-b-111 being written during write signal development section 520.

[0185] Write operation 500 may be associated with writing to a single memory cell 105-b-11 having a total duration t B1 -t B0 and includes a latch signal generation section 510 and a write signal development section 520 for writing to a single memory cell 105-b-111. In instances where write operation 500 does not employ multiplexed signal development techniques (e.g., a sequence of write operations 500 using the same signal development component 250), a subsequent write operation using sense amplifier 290-a may follow write signal development section 520. Thus, performing multiple write operations 500 (e.g., writing to multiple memory cells 105-b) using the same signal development component 250 may involve an integer multiple of the duration t B1 -t B0 (e.g., at least 2*(t B1 –t B0 ) to read two memory cells 105-b). However, multiplexing signal development component 250-a (e.g., via selection component 280-a) may reduce the amount of time involved in writing to multiple memory cells 105-b using sense amplifier 290-a.

[0186] Figure 5B Illustrates an example of a write operation 550 supporting signal development caching in a memory device according to an example disclosed herein. Write operation 550 may illustrate a portion (e.g., a time interval) of an access operation (e.g., a multi-cell access operation) associated with generating a latch signal and a cell access signal (e.g., a cell write signal) when accessing four memory cells 105 (e.g., via four signal development components 250). For example, write operation 550 may be divided into a latch signal generation section 510-a and a write signal development section 520-a for each of a group of memory cells 105-b, which may be a reference Figure 5AAn example of the corresponding part described. The write operation 550 may employ a circuit system that supports multiplexed signal development, such as the circuit 300 described with reference to Figure 3 The circuit 300. The write operation 550 illustrates an example of separating the signal development operation from the input / output operation, which can improve data throughput in a memory device.

[0187] As an illustrative example, the write operation 550 is described with reference to writing logic states to four memory cells 105-b in four different domains 310-a, where each of the different domains is associated with a corresponding signal development component 250-a that is multiplexed with a sense amplifier 290-a. For example, the latch signal generation part 510-a-1 and the write signal development part 520-a-1 may refer to the write operation of the memory cell 105-b-111 (e.g., of the domain 310-a-1 associated with the signal development component 250-a-1). For example, the latch signal generation part 510-a-2 and the write signal development part 520-a-2 may refer to the write operation of the memory cell 105-b-211 (e.g., of the domain 310-a-2 (not shown) associated with the signal development component 250-a-2). For example, the latch signal generation part 510-a-3 and the write signal development part 520-a-3 may refer to the write operation of the memory cell 105-b-311 (e.g., of the domain 310-a-3 (not shown) associated with the signal development component 250-a-3). For example, the latch signal generation part 510-a-4 and the write signal development part 520-a-4 may refer to the write operation of the memory cell 105-b-411 (e.g., of the domain 310-a-4 (not shown) associated with the signal development component 250-a-4). Each of the signal development components 250-a-1, 250-a-2, 250-a-3, and 250-a-4 may be selectively coupled to the same sense amplifier 290-a via a selection component 280-a (e.g., based on a logic selection signal SDCM).

[0188] Each of the latch signal generation parts 510-a may be associated with charge sharing (which may occur in non-overlapping time intervals) between the corresponding one of the signal development component 250-a and the sense amplifier 290-a. The latch signal generation parts 510-a may each be an example of generating a signal (e.g., a cache signal, a signal state) at the signal development component 250-a at least in part based on selectively coupling the signal development component 250-a to the sense amplifier 290-a (e.g., an amplifier component). In some examples, this signal may be generated at least in part based on a write command or a write signal. In some examples, generating the latch signal, the cache signal, or the signal state is associated with a fourth latency (e.g., a relatively low latency or a short duration).

[0189] The latch signal generation section 510-a-1 can be an example of coupling a signal development component 250-a-1 (e.g., a first signal development component) to a sense amplifier 290-a (e.g., an amplifier component) (e.g., via a selection component 280-a) during a first time interval and at least partially based on determining to access a memory cell 105-b-111 (e.g., a first memory cell). The latch signal generation section 510-a-2 can be an example of coupling a signal development component 250-a-2 (e.g., a second signal development component) to the sense amplifier 290-a (e.g., via the selection component 280-a) during a second time interval following the first time interval and at least partially based on determining to access a memory cell 105-b-211 (e.g., a second memory cell).

[0190] The latch signal generation sections 510-a-1 to 510-a-4 can be executed according to a sequence that can be at least partially based on a memory cell write command or signal sequence (e.g., received via the I / O line 295-a). This sequence can also correspond to a sequence selected or otherwise indicated by a logic selection signal SDCM for the signal development component 250-a. In some instances, each of the latch signal generation sections 510-a can separate a gap or delay period (e.g., the period between the latch signal generation section 510-a-1 and the latch signal generation section 510-a-2), which can be associated with: a gap or delay of the selection component 280-a, a gap or delay associated with changing the value of the logic selection signal SDCM, or a period during which no signal development component 250-a is coupled to the sense amplifier 290-a. In other words, an access operation can include a gap or delay period between when one signal development component 250-a is selectively decoupled from the sense amplifier 290-a and when another signal development component 250-a is selectively coupled to the sense amplifier 290-a. In other instances, this decoupling and coupling can be configured to occur simultaneously.

[0191] In some instances, the latch signal generation section 510-a can include "activating" the sense amplifier 290-a, which can include selectively coupling one or more voltage sources (e.g., a low voltage source 293, a high voltage source 294) to the sense amplifier 290-a. Thus, according to the sequence of the latch signal generation sections 510-a-1 to 510-a-4, a signal sequence can be generated at the sense amplifier 290-a or the signal development component 250-a that is at least partially based on the corresponding write command or signal sequence.

[0192] As part of or in conjunction with a write operation, one or more signals may be transmitted between sense amplifier 290 and signal development component 250. For example, the generated latch signal may also be fed back to signal development components 250-a-1 through 250-a-4 or otherwise utilized by signal development components 250-a-1 through 250-a-4 to support the corresponding write operation. For example, as part of latch signal generation section 510-a, based on the generated latch signal (e.g., based on whether memory cell 105-b will store a logic 0 or a logic 1), a corresponding one of signal development components 250-a-1 through 250-a-4 may be utilized to transfer or otherwise share the write signal.

[0193] Write signal development section 520-a may be associated with charge sharing between a corresponding one of memory cells 105-b, a corresponding one of digit lines 210-a, and a corresponding one of signal development components 250-a. Each write signal development section 520-a may be an instance of developing a cell access signal (e.g., a cell write signal) at signal development component 250-a, at least partially based on a latch signal of sense amplifier 290-a. The transition from latch signal generation section 510 to the corresponding write signal development section 520-a may include selectively isolating the corresponding signal development component 250-a from sense amplifier 290-a (e.g., via selection component 280-a or another isolation switch component). Write signal development section 520-a-1 may be an instance of coupling signal development component 250-a-1 (e.g., the first signal development component) to memory cell 105-b-111 (e.g., the first memory cell) during a third time interval following the first time interval. In some instances, the second time interval is within the third time interval or at least partially overlaps with the third time interval. Write signal development section 520-a-2 may be an instance of coupling signal development component 250-a-2 (e.g., the second signal development component) to memory cell 105-b-211 (e.g., the second memory cell) during a fourth time interval following the second time interval that overlaps with the third time interval.

[0194] In some instances of the write signal development section 520-a, shunts 330-a associated with other memory cells 105-b of the corresponding domain 310-a may be selected or activated, which may equalize the bias across the unaccessed memory cells 105-b. For example, for domain 310-a-1, during the write signal development section 520-a-1, the bias between the digital line 210-a-12 and the board line 215-a-12 may be equalized via the shunt 330-a-12, the bias between the digital line 210-a-13 and the board line 215-a-13 may be equalized via the shunt 330-a-13, and so on. This bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cells 105-b being accessed during the write signal development section 520-a.

[0195] Similar to the write operation 500, the write operation 550 may also be associated with the writing (e.g., via the sense amplifier 290-a) of a single memory cell 105 having a total duration t B1 -t B0 and may include a latch signal generation section 510-a-1 and a write signal development section 520-a-1 for writing to a single memory cell 105-b-111. However, by employing multiplexed signal development according to the examples disclosed herein, performing multiple write operations via the same sense amplifier 290-a may not take an integer multiple of the duration t B1 -t B0 (e.g., where the integer multiple may correspond to the number of memory cells 105-b written in parallel). Specifically, by generating cell access signals in overlapping time intervals (e.g., the time interval of the write signal development section 520-a of the signal development component 250-a-1 that overlaps with the time interval of the write signal development section 520-a of the signal development component 250-a-2, etc.), multiple memory cells 105-b may be written in a time shorter than this integer multiple. In other words, according to the described techniques for multiplexed signal development, the sense amplifier 290-a may support writing four memory cells 105-b in a duration of t B2 -t B0 that may be shorter than 4*(t B1– t B0 )(e.g., shorter than the corresponding integer multiple of the duration for writing to a single memory cell 105-b).

[0196] In one example, the write signal development portions 520-a-1, 520-a-2, 520-a-3, and 520-a-4 of the first set of writes may be followed by the latch signal generation portions 510-a-5, 510-a-6, 510-a-7, and 510-a-8 of the second set of writes, respectively. The first set of writes may be associated with a first digital thread index (e.g., a value of "1" as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4), and the second set of writes may be associated with a second digital thread index (e.g., a value of "2" as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4). Or, more generally, the first set of writes and the second set of writes may differ at least in part based on the selected digital line 210-a of the write operation. In some examples (e.g., where the selection component 320-a across the domain 310-a is independently controllable and where the logic select signal DLM across the domain 310-a is independently controllable), upon completion of the write signal development portion 520-a for the signal development component 250, a new digital line 210-a may be selected for the same signal development component 250 (e.g., via the selection component 320-a). In other words, as illustrated in the example of operation 550, for the signal development component 250-a multiplexed with the same sense amplifier 290-a, the write signal development portion 520-a of the first set of writes may overlap in time with the latch signal generation portion 510-a of the second set of writes (e.g., latch signal generation portion 510-a-5 overlaps with write signal development portion 520-a-4). Thus, in the example of operation 550 where the domains 310-a-1 to 310-a-4 are independently controllable, the period for writing to the four memory cells 105 may be represented by the time t B2 -t B0 as illustrated, where the time t B2 -t B0 may be based on the overall duration associated with the write operation (e.g., t B1 -t B0 ), the respective latency of the sub-operations (e.g., the relative durations of the latch signal generation portion 510-a and the write signal development portion 520-a), and the degree of multiplexing (e.g., the number of signal development components 250-a multiplexed with the sense amplifier 290-a).

[0197] In some instances, a subsequent write may be performed on memory cell 105-b, which is coupled to a digit line 210-a different from the previous write operation but to the same activated word line 205-a (this can reduce latency). For example, maintaining the selected word line 205-a can eliminate the word line deselection operation and the subsequent word line selection operation. Such instances can be achieved by shunting the digit line 210-a associated with the earlier write operation (e.g., the previously unshunted digit line 210-a) and not shunting the digit line 210-a associated with the later write operation (e.g., the digit line 210-a shunted during the earlier write operation).

[0198] In another instance, not shown, a set of writes may be associated with a first common word line (e.g., where logical word lines WL 11 、WL 21 、WL 31 and WL 41 ) of different domains are simultaneously activated), and a second set of writes may be associated with a second common word line (e.g., where logical word lines WL 12 、WL 22 、WL 32 and WL 42 ) of different domains are simultaneously activated). Or, more generally, the first set of writes and the second set of writes may be different at least in part based on the selected common word line 205-a of the write operation. In some instances (e.g., where the word lines 205-a across domain 310-a are not independently controllable), a new word line 205-a can be selected as soon as the write signal development portion 520 of the write signal development component 250-a (e.g., associated with the sense amplifier 290-a or another group of domain 310-a that is not independently controllable) for all multiplexed signals is completed. In other words, in some instances, for the signal development component 250 multiplexed with the same sense amplifier 290-a, the write signal development portion 520 of the first set of writes may not overlap in time with the latch signal generation portion 510 of the second set of writes.

[0199] For example, when the word line 205-a spans domains 310-a-1 to 310-a-4 and is not independently controllable, the latch signal generation section 510-a-5 can follow or otherwise trail the write signal development section 520-a-4. Thus, in instances where domain 310-a is not independently controllable, the period for writing to the four memory cells 105 can be equal to or approximately equal to the combined time of each of the latch signal generation sections 510-a-1 to 510-a-4 for multiplexing signal development components 250-a-1 to 250-a-4 and one of the write signal development sections 520-a. Thus, in some instances, this period where domain 310-a is not independently controllable can be longer than the period illustrated by time t B2 -t B0 illustrated.

[0200] Thus, according to the various examples disclosed herein, the advantages provided by the described signal development multiplexing (e.g., reduced latency when accessing multiple memory cells 105-b in parallel) can scale with the relative latency difference (e.g., duration) between the latch signal generation section 510 and the write signal development section 520. The advantages of the described signal development multiplexing can also depend on whether domain 310-a is configured to be independently controllable or is controlled via a common access line or common logic signal.

[0201] Although the techniques of the write operation 550 are described with reference to a single sense amplifier 290-a, the techniques of the write operation 550 can be repeated for each sense amplifier 290 of the sense amplifier array, including various operations being performed concurrently (e.g., using simultaneous or offset start or trigger in parallel) to support further pipelining of the write operation in the memory device 100. For example, the write operation 550 or another write operation performed concurrently with the write operation 550 can include input / output operations that include latch signal generation sections 510-b-1, 510-b-2, 510-b-3, and 510-b-4 (not shown) associated with different sense amplifiers (e.g., of the same sense amplifier array). In some instances, the latch signal generation section 510-b-1 can be started simultaneously with the latch signal generation section 510-a-1 or otherwise performed concurrently or with an offset (e.g., according to simultaneous sensing at the sense amplifier array, according to simultaneous latching at a set of latches of the sense component or I / O component, according to concurrent signal exchange with the cache line). Similarly, the latch signal generation section 510-b-2 can be started simultaneously with the latch signal generation section 510-a-2 or otherwise performed concurrently or with an offset, and so on.

[0202] In addition, a write operation 550 or another write operation performed concurrently or offset from the write operation 550 may include a signal development operation that includes write signal development portions 520-b-1, 520-b-2, 520-b-3, and 520-b-4 (not shown) associated with different sense amplifiers (e.g., of the same sense amplifier array). In some instances, the write signal development portion 520-b-1 may be initiated simultaneously with or otherwise concurrently or offset from the write signal development portion 520-a-1 (e.g., according to simultaneous access of multiple memory cells of a row, field, or subfield, according to concurrent signal exchange with a cache line). Similarly, the write signal development portion 520-b-2 may be initiated simultaneously with or otherwise concurrently or offset from the write signal development portion 520-a-2, and so on. Although described in the context of two parallel writes associated with two different sense amplifiers 290, the described techniques may be applied to any number of parallel writes. For example, to support a 64-bit information transfer scheme, 64 parallel writes may be performed using 64 sense amplifiers 290 according to the examples disclosed herein.

[0203] Figure 6 Illustrates an example of a signal development component 250-b that supports signal development caching in a memory device according to an example disclosed herein. The signal development component 250-b may be an example of the signal development component 250 referred to Figure 1 to 5. The signal development component 250-b may be coupled to or coupled between the digital line 210-b and the signal development line 255-b. The signal development component 250-b may include a capacitor 610 (e.g., an integrating capacitor, a storage element, a cache element, a cache storage element) and a transistor 620 that may be configured in an amplifier configuration (e.g., as a charge transfer sense amplifier, as a gate-cathode amplifier).

[0204] The capacitor 610 can be an instance of a signal storage component or a charge storage component of the signal development component 250-b. In an instance of the signal development component 250-b, the capacitor 610 can be coupled to a line of the signal development component 250-b (e.g., the signal development line 255-b) and a voltage source 615 (e.g., a ground voltage source, a voltage source having a reference voltage for the capacitor 610), or be coupled between the line of the signal development component 250-b and the voltage source 615. Although illustrated as including the capacitor 610, according to the instances disclosed herein, the signal development component 250 can additionally or alternatively include or otherwise employ transistors, diodes, or other components that can provide the functionality of the signal storage component or the charge storage component in the signal development component 250 in a particular state. In some instances, a set of signal development components 250-b can include a set of capacitors 610, which can provide a high-speed cache in a fast local memory (e.g., a signal development cache) in a device including the set of signal development components 250-b.

[0205] In some instances, a memory device including the signal development component 250-b can include memory cells 105 that employ logic storage elements, the logic storage elements including capacitive elements (e.g., linear capacitors in DRAM applications, ferroelectric capacitors in FeRAM applications). In various instances, the capacitor 610 can include the same capacitive element or technology as the logic storage element (e.g., the capacitor 610 can be a linear capacitor in a DRAM application, the capacitor 610 can be a ferroelectric capacitor in a FeRAM application), or a different capacitive element or technology from the logic storage element (e.g., the capacitor 610 can be a linear capacitor in a FeRAM application, a PCM application, or a chalcogenide memory application).

[0206] The transistor 620 can be an instance of an amplifier or a voltage regulator of the signal development component 250-b, and can be configured to transfer charge between the signal development line 255-b and the digital line 210-b based at least in part on one or both of the voltage of the signal development line 255-b (e.g., the first access line) and the voltage of the digital line 210-b (e.g., the second access line). For example, the gate node of the transistor 620 can be coupled to the voltage source 625, and charge can be transferred across the transistor based at least in part on the relationship between the voltage of the voltage source 625 (e.g., V2) and the voltage of the digital line 210-b. In various instances, the transistor 620 can be associated with one or more digital lines 210 (e.g., a multiplexed digital line 210), and can be located outside the illustrative boundary of the signal development component 250-b (e.g., in an instance of a memory device that includes a transistor 620 for each of a set of multiplexed digital lines 210).

[0207] The transistor 620 may provide signal conversion between the digital line 210-b and the signal development line 255-b. For example, the transistor 620 may permit a charge flow (e.g., current) from the signal development line 255-b (e.g., from the capacitor 610) to the digital line 210-b immediately after the voltage of the digital line 210-b has decreased (e.g., after selecting the memory cell 105 via the selection component 320 and selecting the digital line 210), as fed or enabled by the voltage source 625. A relatively small charge flow to the digital line 210-b may be associated with a relatively small voltage change of the signal development line 255-b, whereas a relatively large charge flow to the digital line 210-b may be associated with a relatively large voltage change of the signal development line 255-b. Depending on the net capacitance of the signal development line 255-b (e.g., including the capacitor 610), for example, the signal development line 255-b may experience a relatively small voltage change or a relatively large voltage change depending on the charge flow across the transistor 620 after selecting the memory cell 105. In some instances, the transistor 620 or the signal development component 250-b may be isolated from the digital line 210-b by a switching component or a selection component (e.g., the selection component 320). The transistor 620 may also be referred to as a "voltage regulator" or a "biasing component", which is related to how the transistor 620 regulates the charge flow in response to the voltage of the digital line 210-b.

[0208] In some instances, the signal development component 250-b may include circuitry configured to support a selective coupling (e.g., of the signal development line 255-b) to a relatively high voltage (e.g., the voltage source 635). For example, the signal development component 250-b may include a switching component 630 that may operate based on a logic signal SW1. In some instances, the voltage source 645 may be coupled to a relatively high voltage rail or supply, which may support charging the capacitor 610 (e.g., for developing a cell access signal).

[0209] In some instances, the signal development component 250-b may include circuitry configured to support a selective coupling (e.g., of the digital line 210-b) to a reference voltage (e.g., the voltage source 645). For example, the signal development component 250-b may include a switching component 640 that may operate based on a logic signal SW2. In some instances, the voltage source 645 may be coupled to a ground or virtual ground rail or supply. In some instances, the voltage source 645 may be coupled to the same rail or supply as the voltage source 615 (e.g., V1 may be equal to V4).

[0210] In some instances, the signal development component 250-b may include circuitry configured to support selective coupling (e.g., of the signal development line 255-b, the signal development component 250-b) to another component (e.g., the selection component 280, the sense amplifier 290). For example, the signal development component 250-b may include a switch component 650, which may be referred to as an isolation switch component and may be operable based on a logic signal ISO. Additionally or alternatively, according to an example disclosed herein, the isolation switch component may be included in the sense amplifier 290.

[0211] Figure 7 Illustrates an example of a sense amplifier 290-b that supports signal development caching in a memory device according to an example disclosed herein. The sense amplifier 290-b may be an example of the sense amplifier 290 described with reference Figure 1 to 5. The sense amplifier 290-b may be coupled to the signal line 285-b and the reference line 275-b or coupled between the signal line 285-b and the reference line 275-b. The sense amplifier 290-b may also be associated with (e.g., coupled to) the I / O lines 295-b and 295-c. In some instances, the sense amplifier 290-b may be referred to as an amplifier component of the memory device.

[0212] The sense amplifier 290-b may include a pair of opposing amplifiers 710-a and 710-b. Although illustrated as amplifiers, the sense amplifier 290-b may alternatively or equivalently include a number of cross-coupled transistors (e.g., a pair of cross-coupled p-type transistors and a pair of cross-coupled n-type transistors).

[0213] In some instances, the sense amplifier 290-b may include circuitry configured to support selective coupling (e.g., of the opposing amplifiers 710-a and 710-b) to sense amplifier low and high voltage sources (e.g., voltage sources 293-b and 294-b). For example, the sense amplifier 290-b may include switch components 730-a and 730-b that are respectively operable based on logic signals SW3 and SW4. In some instances, activating or selecting the logic signals SW3 and SW4 may be referred to as activating or latching the sense amplifier 290-b.

[0214] In some instances, sense amplifier 290-b may include circuitry configured to support selective coupling or decoupling with another component (e.g., signal development component 250, selection component 280, reference component 270). For example, sense amplifier 290-b may include switch components 720-a and 720-b, which may be referred to as isolation switch components and may be operable based on logic signals ISO1 and ISO2. Additionally or alternatively, according to the examples disclosed herein, the isolation switch components may be included in signal development component 250 or selection component 280.

[0215] In some instances (e.g., supporting a read operation), sense amplifier 290-b may generate an output signal based at least in part on a cell read signal. For example, signal development component 250 (e.g., a selected one of a set of signal development components 250) may transfer a cell access signal via signal line 285-b or otherwise share charge based at least in part on the cell access signal with sense amplifier 290-b. Reference component 270 may transfer a reference signal via reference line 275-b or otherwise share charge based at least in part on the reference signal with sense amplifier 290-b. When signal line 285-b has a higher voltage than reference line 275-b, output signal may be generated using I / O line 295-b having a relatively high voltage (e.g., V H ) and I / O line 295-c having a relatively low voltage (e.g., V L ). When reference line 275-b has a higher voltage than signal line 285-b, output signal may be generated using I / O line 295-c having a relatively high voltage (e.g., V H ) and I / O line 295-b having a relatively low voltage (e.g., V L ). In some instances, switch components 720-a and 720-b may be closed to receive a cell read signal or a cell reference signal and then opened when sense amplifier 290-b is activated (e.g., “latched”).

[0216] In some instances, the generated sense or latch signal or other output signal generated may be shared with or otherwise associated with a write or rewrite signal that is transmitted via signal line 285-b to a selected signal development component 250 (e.g., after closing switch component 720-a). In some instances, a write command or write signal may be received at sense amplifier 290-b (e.g., from input / output component 160 via I / O lines 295-b and 295-c), and the received write command or write signal may be latched, shared (e.g., via signal line 285-b), or otherwise associated with a cell write signal generated by selected signal development component 250. In some instances, the write command or write signal associated with sense amplifier 290-b may bypass signal development component 250 (e.g., via bypass line 260).

[0217] Figure 8A FIG. 4 shows a block diagram of a system 800 supporting signal development cache according to an example disclosed herein. System 800 may include a memory array 805, a selection component 815, an array of signal development components 825, a selection component 835, and an array of sense amplifiers 845. In some instances, these and other components may be included in data path 860 of system 800.

[0218] Memory array 805 may include a set of memory cells 105, which may be associated with access lines such as those described with reference to Figures 1 to 3 access lines (e.g., word lines 205, digit lines 210, plate lines 215). In some instances, the memory array may be associated with A rows (e.g., A independently addressable word lines 205) and B columns (e.g., B independently addressable digit lines 210). In one example, memory array 805 may be associated with 1,048,576 memory cells 105 arranged according to 1,024 word lines 205 and 1,024 digit lines 210. Each of memory cells 105 may be configured to store a corresponding logic state alternatively referred to as a memory state.

[0219] In some instances, memory array 805 may be arranged in a set of domains, which may be similar to domains 310 described with reference to Figure 3 reference. In one example, memory array 805 may be split among four domains, and each of the four domains may have four independent zones with board control (e.g., each domain of memory array 805 may have four zones of plate lines 215 with common or individual biasing, which may be examples of sub-domains). In such examples, memory array 805 may be arranged according to 16 control zones, which may be associated with selecting 64 bits of data.

[0220] The signal development component array 825 may include a set of signal development components 250, which may include aspects of the signal development component 250 described with reference to Figures 2 to 7 each of the signal development components 250. The signal development component array 825 or its components (e.g., the cache memory elements of the signal development component array 825) may be an example of a signal development cache memory according to the examples disclosed herein. In some examples, the signal development components 250 of the signal development component array 825 or its cache memory elements may be arranged in a grid having C columns and D rows. In some examples, each of the D rows may be associated with a cache memory block, and each of the C columns may be associated with a position in the corresponding cache memory block. In one example, the signal development component array 825 may be associated with 8 cache memory blocks each having 64 positions. Each position in each of the cache memory blocks may correspond to a single signal development component 250 or a cache memory element of the signal development component 250.

[0221] The selection component 815 may include various components that support mapping the memory cells 105 of the memory array 805 to the signal development components 250 of the signal development component array 825. For example, the selection component 815 may provide selective coupling and decoupling of the individual digit lines 210 of the memory array 805 to the individual signal development components 250 of the signal development component array 825 to support various examples of multiplexed signal development described herein.

[0222] The selection component 815 may be coupled to the memory array 805 via a bus 810 having N signal paths, and the selection component 815 may be coupled to the signal development component array 825 via a bus 820 having M signal paths. In some examples, the selection component 815 may be coupled to each of the digit lines 210 of the memory array 805 (e.g., where N = B). In some examples, the bus 820 may have fewer signal paths than the bus 810, where M is associated with the size of the cache memory blocks of the signal development component array (e.g., the number of storage elements per cache memory line of the cache memory block). For example, the bus 810 may have N = 1,024 signal paths, and the bus 820 may have M = 64 signal paths or some other number of signal paths.

[0223] In various examples, each digit line 210 of the memory array 805 can be configured to selectively couple to a particular one of the signal development components 250 of the signal development component array 825, a particular group of signal development components 250 of the signal development component array 825, or can be configured to selectively couple to any one of the signal development components 250 of the signal development component array. Additionally or alternatively, the signal development components 250 of the signal development component array 825 can be configured to selectively couple to a particular one of the digit lines 210 of the memory array 805, a particular group of digit lines 210 of the memory array, or can be configured to selectively couple to any one of the digit lines 210 of the memory array 805. In other words, the mapping between the digit lines 210 and the signal development components 250 according to the described techniques can include a one-to-many mapping, a many-to-one mapping, or a many-to-many mapping.

[0224] The sense amplifier array 845 can include a set of sense amplifiers 290, which can include reference Figures 2 to 7 Aspects of the described sense amplifiers 290. In some examples, the sense amplifiers of the sense amplifier array 845 can be arranged in strips or other grouped arrangements. The selection component 835 can be coupled between the signal development component array 825 (e.g., via bus 830) and the sense amplifier array 845 (e.g., via bus 840) to support various mappings between the signal development components 250 and the sense amplifiers 290. In various examples, the sense amplifiers 290 (e.g., of the sense amplifier array 845) can be integrated between cache memory blocks (e.g., of the signal development component array 825) or can be external to the signal development component cache memory region (e.g., external to the signal development component array 825). In some examples, the sense amplifier array 845 can be coupled to a bus 850, which can support information transfer with I / O components (not shown) that can be considered within or outside the illustrative boundaries of the data path 860.

[0225] In some instances, the signal development component array 825 may be coupled to a strip or other group of sense amplifiers 290 (e.g., of the sense amplifier array 845), each of the sense amplifiers 290 also being independently addressable. For example, each sense amplifier in the strip of sense amplifiers 290 may be configured to selectively couple to a particular one of the signal development components 250 of the signal development component array 825, a particular group of signal development components 250 of the signal development component array 825, or may be configured to selectively couple to any one of the signal development components 250 of the signal development component array. Additionally or alternatively, the signal development components 250 of the signal development component array 825 may be configured to selectively couple to a particular one of the sense amplifiers 290 of the sense amplifier strip, a particular group of sense amplifiers of the sense amplifier strip, or may be configured to selectively couple to any one of the sense amplifiers 290 of the sense amplifier strip. In other words, the mapping (e.g., via the selection component 835) between the signal development components 250 of the signal development component array 825 and the sense amplifiers 290 of the sense amplifier array 845 according to the described techniques may include a one-to-many mapping, a many-to-one mapping, or a many-to-many mapping.

[0226] In an illustrative example where the memory array 805 is associated with 1,024 digital lines 210, each of the 1,024 digital lines 210 may be coupled to a multiplexer (e.g., of the selection component 815), where the digital lines may be reduced to 64×4 = 256 digital lines. This may support the transmission of signals for 4 groups of 64 digital lines that overlap in time (e.g., participating in simultaneous transmission between the memory cells 105 and the signal development components 250). In some instances, each of these 4 groups may be routed to any one of 8 cache blocks (e.g., of the signal development component array 825), where each cache block may include 8 lines by 64 bits. In other words, the total cache size associated with this signal development component array 825 may be 64×64 bits. According to this example of array routing, any 64-bit sub-row from the memory array may be routed to any one of the 64-bit signal development component cache lines.

[0227] In another illustrative example, system 800 may include (e.g., of memory array 805) several domains, each of which has 1,048,576 memory cells 105 arranged in 1,024 uniquely addressable rows and 1,024 columns. Each of the domains of system 800 may be mapped (e.g., via selection component 815) to 64 signal development components (e.g., of signal development component array 825). In other words, 64 signal development components may be mapped to 1,024 digital lines 210 within each domain. In some instances, a particular signal development component 250 may be mapped to 16 digital lines 210 within each domain (e.g., 1,024 digital lines 210 divided by 64 signal development components 250). In some instances, this mapping may be fixed (e.g., where a group of 16 digital lines 210 is mapped to a corresponding signal development component 250 within each domain), which in some instances may reduce multiplexing or selection circuit complexity. In various other instances, signal development component 250 may be mapped to more than one domain, more than one set of digital lines 210 (e.g., of a domain), or other configurations. Additionally or alternatively, a digital line 210 domain or group may be mapped to more than one signal development component 250. In other words, the memory device may include various configurations of signal development components 250 to support the examples of multiplexed signal development described herein.

[0228] In this illustrative example, a row of 1,024 memory cells 105 (e.g., across a domain 310) may be selected by a single word line 205 in each domain. With 64 signal development components 250 per domain, 64 memory cells out of a group of 1,024 memory cells 105 may be accessed at a time in each domain (e.g., by selectively coupling the corresponding digital lines 210 to each of the 64 signal development components 250-a via selection component 815). During this access, other digital lines 210 may be selectively isolated from the signal development components 250 that interface the same domain. Additionally, other digital lines 210 may be shunted or masked from other digital lines 210 as described herein.

[0229] In some instances, the operation of one or more components of system 800 may be controlled by a memory controller (e.g., memory controller 870). Memory controller 870 may be as described with reference to Figure 1The example of the memory controller 170 described or otherwise associated with performing the operations of the memory controller 170. The memory controller 870 may represent a controller or other circuitry configured to control various components or operations of the system 800. For example, the system 800 may include various components or circuitry of the data path 860, which may include the memory array 805, the selection component 815, the signal development component array 825, the selection component 835, and the sense amplifier array 845, as well as other components (e.g., the row component 125, the column component 135, the board component 145, the I / O component 160, and other components) along the information transfer path in the system 800. In various examples, the memory controller 870 may communicate with any one or more of the components of the data path 860 to control the associated components or operations.

[0230] The memory controller 870 may be configured (e.g., by one or more commands received from a host device) to perform one or more write operations, read operations, eviction operations, or bypass operations, as well as other examples of memory operations of the system 800. In various examples of these operations, the memory controller 870 may be configured to transfer data between one or more portions of the memory array 805, one or more portions of the signal development component array 825 (e.g., the cache blocks of the signal development component array 825), or one or more portions of the sense amplifier array 845 according to one or more memory operations.

[0231] In some examples, the memory controller 870 may be configured to perform a read operation, which may include transferring data from the signal development component array 825 to the sense amplifier array 845 (e.g., when the requested data is stored in the signal development component array 825). In some examples, the memory controller 870 may be configured to transfer data from the memory array 805 to the signal development component array 825 (e.g., when the requested data does not exist in the signal development component array 825). Additionally or alternatively, the memory controller 870 may be configured to perform an eviction operation. The eviction operation may include transferring the data stored in the signal development component array 825 to the memory array 805 before transferring other data (e.g., data associated with a read operation) from the memory array 805 to the signal development component array 825. In some examples, the memory controller 870 may be configured to perform a cache bypass operation, which may include transferring data directly from the memory array 805 to the sense amplifier array 845. As an example, this may facilitate a streaming read operation (e.g., performing multiple read operations in parallel).

[0232] In some instances, the memory controller may be configured to perform a write-back operation, which may include transferring data from the sense amplifier array 845 to the signal development component array 825 (e.g., after performing a read operation). Additionally or alternatively, the memory controller 870 may be configured to perform a write-through operation. The write-through operation may include transferring data directly from the sense amplifier array 845 to the memory array 805 according to a write command based on determining that the data is stored at the signal development component array 825. In some instances, the memory controller 870 may be configured to perform a bypass operation. For example, the bypass operation may include transferring data directly from the sense amplifier array 845 to the memory array 805 according to a write command based on determining that the data is not stored in the signal development cache. These instances of the bypass operation may facilitate streaming write operations (e.g., performing multiple write operations in parallel). In some cases, one or more of the write operations described herein may include an eviction operation. For example, the memory controller 870 may transfer data stored in the signal development component array 825 to the memory array 805 based on determining that the data corresponding to a write command (e.g., a write-back command) is not currently stored in the signal development component array 825.

[0233] Although the system 800 in the instance of Figure 8A is illustrated such that the selection component 815 is operable to selectively couple the memory array 805 and the signal development component array 825 and the selection component 835 is operable to selectively couple the signal development component array 825 and the sense amplifier array 845, other configurations for supporting memory access are possible. For example, in some cases, the memory array 805 may be selectively coupled to the sense amplifier array 845 in a manner that bypasses the signal development component array 825 or its components. In some instances, the coupling between the memory array 805 and the sense amplifier array 845 may be supported by one or more bypass lines (e.g., the bypass line 260 described with reference to Figure 2 .

[0234] Figure 8B FIG. shows a block diagram of a system 800-a that supports signal development caching according to an example disclosed herein. The system 800-a may include a memory array 805-a, a bus 810-a, a bus 820-a, a signal development component array 825-a, a bus 840-a, a sense amplifier array 845-a, a bus 850-a, and a memory controller 870-a, each of which may be a reference to Figure 8Ainstances of the corresponding components described. Memory array 805-a, bus 810-a, bus 820-a, signal development component array 825-a, bus 840-a, and sense amplifier array 845-a may be part of data path 860-a, and memory controller 870-a may be coupled to any one or more of these and other components of data path 860-a to support the techniques disclosed herein.

[0235] In some instances, a system such as system 800-a may include a selection component 875 that may be operable to selectively couple memory array 805-a and sense amplifier array 845-a (e.g., bypass signal development component array 825-a or its components), selectively couple memory array 805-a and signal development component array 825-a, or selectively couple signal development component array 825-a and sense amplifier array 845-a. In some cases, selection component 875 may be operable to selectively couple memory array 805-a, sense amplifier array 845-a, and signal development component array 825-a to each other concurrently. Selection component 875 may thus include or otherwise support the functionality of one or more of the switch components 265, reference Figure 2 described elsewhere herein and attributed to reference Figure 2 and 3 the selection component 280, reference Figure 3 the selection component 320, reference Figure 8A the selection component 815, or reference Figure 8A the selection component 835 described elsewhere herein, as well as other features or functions.

[0236] An instance of system 800-a may in some cases be referred to as a "T" configuration, where each of memory array 805, signal development component array 825, and sense amplifier array 845 may be coupled to a common selection component 875 (e.g., a central switch network). In this instance, each of memory array 805-a, signal development component array 825-a, and sense amplifier array 845-a may be coupled to selection component 875 according to the number of signal paths in the corresponding system component, and the common selection component 875 may be configured or operable to perform the techniques described for signal development caching according to various degrees of multiplexing or other arrangements with the corresponding system components.

[0237] More generally, the selection component 875 can include various switch components, selection components, or other circuitry operable to selectively couple either the memory array 805-a or its components (e.g., multiple access lines of the memory array 805-a), the signal development component array 825-a or its components (e.g., cache memory elements of the signal development cache), or the sense amplifier array 845-a or its components (e.g., multiple sense amplifiers 290 of the sense amplifier array 845-a) concurrently and selectively with any one or both of the other arrays. The selection component 875 can thereby support various access techniques in accordance with the examples disclosed herein. For example, in some cases, each of the memory array 805-a or its components, the signal development component array 825-a or its components, and the sense amplifier array 845-a or its components can be coupled to each other, and the sense amplifier array 845-a can strengthen signals transmitted in either direction between the signal development component array 825-a and the memory array 805-a (e.g., to support writing of logical states from the signal development component array 825-a to the memory array 805-a or to support writing of logical states from the memory array 805-a to the signal development component array 825-a).

[0238] In some examples, the bus 850-a can support information transfer using I / O components (not shown) that can be considered either within or external to the illustrative boundaries of the data path 860. In some cases, the bus 850-a can be coupled to the selection component 875, as illustrated in the example of the system 800-a. In other cases, the bus 850-a can be coupled to the sense amplifier array 845-a, as illustrated in the example of the system 800. In various examples, the operation of the selection component 875 can be coordinated (e.g., by the memory controller 870-a) to avoid signaling conflicts in the data path 860-a, including coordinating to avoid or mitigate conflicts that can inadvertently corrupt or degrade information (e.g., logical states, signal states) intended to be maintained at components of the data path 860-a.

[0239] In some cases, a system in accordance with the described techniques for signal development caching can be arranged in a "T" configuration, where each of the memory array 805, the signal development component array 825, and the sense amplifier array 845 can be coupled to a common central node (e.g., a common bus node, a central node of each signal path in a set of signal paths of a common bus). Figure 8CFIG. 800-b is a block diagram of a system for developing a cache based on support signals according to this example. The system 800-b may include a memory array 805-b, a bus 810-b, a bus 820-b, a signal development component array 825-b, a bus 840-b, a sense amplifier array 845-b, a bus 850-b, and a memory controller 870-b, each of which may be an example of a corresponding component described in reference Figure 8A and 8B The memory array 805-b, the bus 810-b, the bus 820-b, the signal development component array 825-b, the bus 840-b, and the sense amplifier array 845-b may be part of a data path 860-b, and the memory controller 870-b may be coupled to any one or more of these and other components of the data path 860-b to support the techniques disclosed herein.

[0240] In addition, the system 800-b may include a central node 880. Each of the memory array 805, the signal development component array 825, and the sense amplifier array 845 may be selectively coupled to the central node 880 through a corresponding selection component 885-a, 885-b, or 885-c. Each corresponding selection component 885-a, 885-b, 885-c may have a first coupling to the common central node according to the number of signal paths of the common bus and a second coupling to the corresponding system component (e.g., the memory array 805, the signal development component array 825, or the sense amplifier array 845) according to the number of signal paths in the corresponding system component, the degree of multiplexing of the corresponding system component, or other arrangements. Thus, although the central node 880 is illustrated as a single point, the central node 880 may be illustrated as having a common bus connection with a corresponding common node for each signal path in a set of signal paths coupled to the central node 880. In some cases, the central node 880 and the corresponding selection components 885-a, 885-b, or 885-c may include aspects attributed to the common selection component 875 described in reference Figure 8B and support its functions in other ways. In various examples, the operations of the selection components 885-a, 885-b, and 885-c may be coordinated (e.g., by the memory controller 870-b) to avoid conflicts at the central node 880, including coordinating to avoid or mitigate conflicts that may inadvertently corrupt or degrade information (e.g., logical state, signal state) intended to be maintained at components of the data path 860-b.

[0241] Figure 9A block diagram showing a system 900 for developing a cache based on support signals according to an example disclosed herein. The system 900 may include a memory array 805-c, a bus 810-c, a selection component 815-c, a bus 820-c, an array of signal development components 825-c, a bus 830-c, a selection component 835-c, a bus 840-c, a sense amplifier array 845-c, and a controller 870-c, each of which may be an example of a corresponding component described in references Figure 8A , 8B and 8C.

[0242] The memory array 805-c may be arranged according to various numbers of memory cells 105, word lines 205, digit lines 210, and plate lines 215 or other plate nodes. In one example, the memory array 805-c may be arranged according to 1,024 word lines (e.g., A = 1,024) and 1,024 digit lines (e.g., B = N = 1,024) or some other organization of a 1,024×1,024 array of memory cells 105.

[0243] In some examples, the memory array 805-c may be arranged according to the number of domains 310-b, each of which may include an equal number of digit lines 210 or columns. For example, the system 900 illustrates an example of a memory array 805-c that includes four domains 310-b (e.g., domains 310-b-1, 310-b-2, 310-b-3, and 310-b-4). In one example, each of the domains 310-b may include 256 digit lines 210. Each of the domains 310-b may have word lines 205 that can be independently controlled, and each word line 205 may select a defined number of sub-rows 908 or stripe them that may or may not be aligned across the memory array 805-c. For example, in an example of the system 900, one word line 205 may select 4 sub-rows 908 (e.g., one sub-row per domain 310-b) or stripe them. In some cases, one or more of the sub-rows 908 in a given word line 205 may be activated while the remaining sub-rows 908 of the word line 205 may not be activated. For example, the sub-rows of domains 310-b-1 and 310-b-3 associated with a given word line 205 may be activated, but the sub-rows of domains 310-b-2 and 310-b-4 may not be activated. In some examples, sub-rows 908 associated with different word lines 205 may be activated concurrently in different domains 310-b. For example, in an example of the system 900, sub-rows 908-a and 908-b may be associated with different word lines 205 but may be activated concurrently.

[0244] In some instances, each domain 310-b may be arranged according to a defined number of control zones 907. In an instance of system 900, each domain 310-b may include four control zones 907 such that the memory array 805-c may include a total of sixteen control zones 907. It should be understood that all specific numbers included herein are non-limiting examples used only for clarity in explaining the concepts herein, and the claims are not limited in any way thereby. In an instance where domain 310-b includes 256 digit lines 210, each of the control zones 907 may include (e.g., span) 64 digit lines 210. In some instances, each of the control zones 907 may support independent bank control. Independent bank control may refer to the ability of the bank lines 215 within a control zone 907 to be activated simultaneously (e.g., with the same bias, through the same independently controllable bank node) with other bank lines within the control zone 907 but independently of the bank lines 215 in other control zones 907. In various instances, each of the control zones 907 may be associated with a common bank or bank node (e.g., common to all memory cells 105 of the control zone), or each of the control zones 907 may be associated with bank lines 215 that may be individually biased or activated from one another.

[0245] In some instances, the word lines 205 may be further striped within the bank line region of domain 310-b (e.g., each control zone 907) to provide additional access granularity within domain 310-b. In one instance, for two sub-rows 908 within domain 310-b, a first row of memory cells 105 may be activated for a first set of control zones 907 within domain 310-b and a second row of memory cells 105 may be activated for a second set of control zones 907 within domain 310-b. More generally, for a domain 310-b having a set of sub-rows 908 or control zones 907, a row of memory cells 105 may be activated for some or each of a set of sub-rows or control zones 907 within domain 310-b.

[0246] In some instances, a set of digit lines 210, a set of memory cells 105, or both, spanned by a sub-row 908 or control zone 907 may be referred to as a sub-domain. In some instances, partitioning the access of domain 310-b into sub-domains may be supported by including multiple contacts from a common driver (e.g., word line driver) at the top of the word line transistor gates (e.g., relative to the substrate). The contacts may be gated by additional transistors such that word line charge can be deposited on the word line transistor gates. As such, striped word lines 205 and charge-locked pull-up gated transistors may be used to create sub-domains. Sub-domains may provide the functionality of forming bit lines from multiple word lines 205 accessed simultaneously on the same domain 310-b, which may extend the access pattern or reduce row buffer conflicts and achieve other benefits.

[0247] Memory controller 870-c may support various biasing or activation of word lines in memory array 805-c. In some instances, memory controller 870-c may be configured or operable to concurrently couple a word line driver to a first segment of a first word line 205 (e.g., first sub-row 908) within a given domain 310-b and to a second segment of a second word line 205 (e.g., second sub-row 908) within the given domain 310-b. In some instances, memory controller 870-c may be configured or operable to concurrently couple another word line driver to a second segment of a first word line 205 (e.g., third sub-row 908) within a given domain 310-b and to a first segment of a second word line 205 (e.g., fourth sub-row 908) within the given domain 310-b.

[0248] In an instance of system 900, each digit line 210 of memory array 805-c may be coupled (e.g., into multiplexer (MUX) 917) to selection component 815-c via bus 810-c. In some instances, digit lines 210 of domain 310-b may be grouped according to corresponding sub-buses 912 of bus 810-c, where each sub-bus 912-a may be associated with a certain number of signal paths. For example, digit lines of domain 310-b-1 may be coupled via sub-bus 912-a, digit lines of domain 310-b-2 may be coupled via sub-bus 912-b, digit lines of domain 310-b-3 may be coupled via sub-bus 912-c, and digit lines of domain 310-b-4 may be coupled via sub-bus 912-d. An instance of system 900 may include four sub-buses 912, and each sub-bus 912 may include 256 signal paths. Thus, bus 810-c may in total include 1024 digit lines 210 or otherwise be associated therewith.

[0249] In some instances, each sub-bus 912 may be mapped via a MUX 917 to an intermediate sub-bus 919 that may include a different number of signal paths (e.g., where the number of signal paths of the sub-bus 912 is an integer multiple of the intermediate sub-bus 919). For example, for a 4:1 multiplexing ratio, each sub-bus 912 may include 256 signal paths, and each intermediate sub-bus 919 may include 64 signal paths. In some instances, this multiplexing may include a mapping between the signal paths of the intermediate sub-bus 919 and the digitally activated or otherwise selected digital lines 210 of a given domain 310-b, and these digitally activated or selected digital lines 210 may be unshunted (e.g., associated with a deactivated shunt 330). In some instances, the remaining digital lines 210 that are not activated or selected may be shunted (e.g., associated with an activated shunt 330), which may mitigate charge leakage or other degradation of the logic states stored by non-target memory cells 105. In some cases, the logic state may alternatively be referred to as a memory state. In an instance of system 900 supported by a 4:1 multiplexing ratio (e.g., at MUX 917), four groups of 64 bits may be transmitted simultaneously or concurrently (e.g., temporally overlapping) via bus 810-c and selection component 815-c, where each group corresponds to a different domain 310-b.

[0250] In an instance of system 900, each intermediate sub-bus 919 may be coupled to a MUX 918 (e.g., a routing wiring MUX), where MUX 918 may be part of selection component 815-c. MUX 918 may be operable to couple a selected group of digital lines 210 to a corresponding group of storage elements or cache elements in a respective cache block 926 of the signal development component array 825-c (e.g., via a respective sub-bus 922 of bus 820-c). An instance of system 900 may include four sub-buses 922 (e.g., sub-buses 922-a, 922-b, 922-c, and 922-d) between MUX 918 and the signal development component array 825-c, and each sub-bus 922 may include 64 signal paths. In an instance of system 900, any of the illustrated or logical positions of sub-bus 922 may be mapped to any of the illustrated or logical positions of intermediate sub-bus 919. For example, intermediate sub-bus 919-a may be mapped to any of sub-buses 922-a, 922-b, 922-c, or 922-d, etc. Thus, any of the intermediate sub-buses 919 may be mapped to any of the cache blocks 926. In another instance, bus 820-c may include a separate sub-bus 922 (not shown) for each of the cache blocks 926, which may be another configuration to support mapping any of the intermediate sub-buses 919 to any of the cache blocks 926 (e.g., via MUX 918).

[0251] The signal development component array 825-c can be arranged according to cache memory blocks 926, each of which can be associated with a certain number of cache memory lines respectively coupled to corresponding groups of storage elements (e.g., cache memory elements). Each of the storage elements can be configured to maintain a signal state (e.g., cache memory signal, cache memory state) corresponding to a logical state when the corresponding storage element is isolated from one or both of the memory array 805-c or the sense amplifier array 845-c. In an example of the system 900, the signal development component array 825-c can include eight cache memory blocks 926, where each cache memory block 926 includes eight cache memory lines, and each cache memory line includes 64 cache memory elements. Thus, the total cache memory size of the signal development component array 825-c can be 64×64 bits (e.g., 4,096 bits). In some examples, the signal development component array 825-c (e.g., cache memory block 926) can include another select component (not shown) that can be operative to select or activate a target cache memory line of the corresponding cache memory block 926 (e.g., couple the target cache memory line to the sub-bus 922).

[0252] In some examples, the number of signal paths of the corresponding sub-bus 922 can be equal to the number of storage elements in the cache memory lines or rows of the signal development component array 825-c. Thus, the number of storage elements coupled to a cache memory line can be proportional to (e.g., equal to, an integer multiple of) the number of digital lines 210 in the control zone 907 or sub-domain. For example, if the control zone 907 is associated with 64 digital lines 210, then the cache memory line can be associated with 64n (where n = 1, 2, 3, …) storage elements. In some examples, the number of signal paths of the sub-bus 922 or the number of signal paths of the intermediate sub-bus 919 or the number of storage elements of the cache memory line can be equal to the number of data bits of a read command or the number of data bits of a write command (e.g., where 64 storage elements in a given cache memory line or 64 signal paths of a given sub-bus 922 or intermediate sub-bus 919 can correspond to a 64-bit data transfer scheme).

[0253] In various examples, the select component 815-c may be operable to couple more than one memory cell 105 to a given storage element of the cache block 926, to couple the memory cell 105 to more than one storage element of the cache block 926, or to do both. For example, where the memory cells 105 of the memory array 805-c are operable to store one of a set of more than two logic states, the select component 815-c may be operable to selectively couple one of the digital lines 210 of the sub-bus 912 to two or more than two of the set of storage elements of the cache block 926. In another example, where the storage elements of the cache block 926 are operable to store one of a set of more than two signal states, the select component 815-c may be operable to selectively couple one of the storage elements of the cache block to two or more than two digital lines 210 or to the memory cells 105 of the memory array 805-c.

[0254] In some cases, data may be provided from the signal development component array 825-c to the requesting device. Retrieving the data may include outputting the data (e.g., information stored as signal states, cache states) from the cache block 926 to the respective MUX 932 via the respective sub-bus 929 of the bus 830-c. An example of the system 900 may include four sub-buses 929 (e.g., sub-buses 929-a, 929-b, 929-c, and 929-d), where each sub-bus 929 may include one information transfer signal path bit (e.g., 64 signal paths for a 64-bit information transfer scheme). The MUX 932 may be operable to select a set of bits or signal states from the cache block 926. In one example, if the cache block is configured to output 64 bits, the MUX 932 may be operable to select eight of the 64 bits for transfer to the sense amplifier sub-array 937. In another example, if the cache block is configured to output 64 bits, the MUX 932 may be operable to select 64 bits from a particular location (e.g., a particular cache block 926 or its cache line) of the signal development component array 825-c. In an example of the system 900, various selection operations may be supported by a select component 835-c that includes four MUXes 932 (e.g., MUXes 932-a, 932-b, 932-c, and 932-d). In some examples, the system 900 may multiplex multiple sense amplifier sub-arrays 937 and the signal development component array 825-c to increase device bandwidth.

[0255] In some instances, MUX 932 may output select bits to corresponding sense amplifier sub-arrays 937 via respective sub-buses 934 of bus 840-c. An example of system 900 may include four sub-buses 934 (e.g., sub-buses 934-a, 934-b, 934-c, and 934-d), and each sub-bus 934 may have one signal path per bit (e.g., 8 signal paths for 8 bits, 64 signal paths for 64 bits) that is passed between the corresponding MUX 932 and the corresponding sense amplifier sub-array 937. Each sense amplifier sub-array 937 may include a set of sense amplifiers 290 operable to compare the signaling to one or more reference voltages and provide an indication of the associated logic state. In an example of system 900, the sense amplifier array may include four sense amplifier sub-arrays 937-a (e.g., sense amplifier sub-arrays 937-a-1, 937-a-2, 937-a-3, and 937-a-4). Although the sense amplifier sub-arrays 937-a of system 900 are depicted as being external to the signal development component array 825-c, in some systems, the sense amplifier sub-arrays 937-a may be integrated between cache blocks 926. For example, each of the cache blocks 926 may include 64 integrated sense amplifiers to support a 64-bit information transfer scheme.

[0256] In various instances, selection component 815-c and selection component 835-c may be configured to operate for or otherwise based on different latencies or bandwidths. For example, selection component 835-c may be configured for signal exchange between a set of storage elements of signal development component array 825-c and the sense amplifier array 845-c having a first latency, and selection component 815-c may be configured for signal exchange between a set of memory cells and the set of storage elements of signal development component array 825-c having a second latency that is greater than the first latency (e.g., considering that signal development in memory array 805-c may be relatively slower than signal development in sense amplifier array 845-c).

[0257] One or more of the memory array 805-c, the selection component 815-c, the signal development component array 825-c, the selection component 835-c, and the sense amplifier array 845-c may be coupled to the memory controller 870-c to support various operations of the system 900. In some cases, the memory controller 870-c may include a content addressable memory (CAM) that supports mapping between the addresses of the memory array 805-c and the signal development component array 825-c, and this mapping may be used to perform various selective couplings via the selection component 815-c or the selection component 835-c. In some instances, a separate CAM may be coupled to each cache block 926 of the signal development component array 825-c or each MUX 932-d of the selection component 835-c. In some instances, the system 900 may support various associativity techniques, where the addresses in the signal development component array 825-c may be associated with or mapped to the addresses in the memory array 805-c. In some cases, the memory controller 870-c may be configured to manage a refresh procedure to maintain the cache signals stored by the set of storage elements of the signal development component array 825-c.

[0258] In some instances, the system 900 may be operated to provide requested data (e.g., in response to a read command). For example, a memory device including the system 900 may receive one or more commands (e.g., from a requesting device) to perform reads on multiple memory locations of the memory array 805-c. In an illustrative example, the memory device may activate subrows 908-a of domain 310-b-1, subrows 908-b of domain 310-b-2, subrows 908-c of domain 310-b-3, and subrows 908-d of domain 310-b-4, which may activate the word line terminals of the first, second, third, and fourth memory locations, respectively. The memory device may also activate the control zones 907 within each of the domains 310-b corresponding to the first, second, third, and fourth memory locations, which may include activating the plate line terminals of these locations. In an instance where each control zone 907 is associated with 64 digital lines, 64 of the 256 total digital lines 210 associated with each sub-bus 912 may be activated. It should be noted that there may be instances where different portions of the word line, different sub-domains, or various other patterning techniques may be used to activate the digital lines 210.

[0259] Continuing with the illustrative example, the MUX 917 can select 64 signal paths of each sub-bus 912, and the signal paths are activated to reduce the total number of coupled signal paths from 1024 signal paths going to the MUX 917 to 256 signal paths output from the MUX 917 (e.g., 64 signal paths via the intermediate sub-bus 919-a, 64 signal paths via the intermediate sub-bus 919-b, 64 signal paths via the intermediate sub-bus 919-c, and 64 signal paths via the intermediate sub-bus 919-d). The 256 total signal paths can be input to the MUX 918, which can route and distribute the first set of 64 signal paths to the first sub-bus 922-a, the second set of 64 signal paths to the second sub-bus 922-b, the third set of 64 signal paths to the third sub-bus 922-c, and the fourth set of 64 signal paths to the fourth sub-bus 922-d. It should be noted that the sorting can be different without departing from the scope of the present disclosure.

[0260] Continuing with the illustrative example, the 64 signal paths carried by each of the sub-buses 922-a, 922-b, 922-c, and 922-d can be coupled to corresponding cache blocks 926 (e.g., corresponding cache lines), where the corresponding cache blocks can support the signal development described with reference to FIG. 4 (e.g., according to the read signal development section 410). Based on this signal development, the storage elements of the corresponding cache blocks can store signal states (e.g., cache states) associated with the logic states stored by the coupled memory cells 105 of the memory array 805-c.

[0261] After developing or storing the corresponding signals or signal states at the signal development component array 825-c, the corresponding cache blocks 926 can each output 64 signals to the sub-buses 929-a, 929-b, 929-c, and 929-d. The 64 signals of each of the sub-buses 929-a, 929-b, 929-c, and 929-d can then be coupled to the sense amplifier array 845-c via the selection component 835-c according to various multiplexing techniques, where the corresponding sense amplifier 290 can sense the logic state at least partially based on the signals provided by the cache block 926, and the logic state can be latched by the sense amplifier 290 or other latching components. For example, the sense amplifier sub-array 937-a can output the logic state and the data can be read out to the requesting device. If the sense amplifier sub-array 937-a is not integrated with a latch, then a latch or SRAM cache can be implemented such that the sense amplifier 290 can be between the signal development component array 825-c and the latch or SRAM cache.

[0262] In some cases, information data can be directly read from the signal development component array 825-c. For example, the memory array 805-c may not be accessed and the selection component 815-c may not be operated, but the remaining steps as described herein may occur (e.g., when the relevant signal states are stored at the signal development component array 825-c before receiving an access command). Additionally or alternatively, the MUX 917 may support various operations on the information passed to the MUX 917. For example, the MUX 917 may shuffle bits according to a pattern or may flip bits (e.g., from 0 to 1, from 1 to 0). To enable the MUX 917 to perform these operations, the MUX 917 may integrate additional signal development components with reactance components (e.g., transistors) or may have capacitive or inductive features that enable charge sharing or charge transfer to maintain its integrity. In these cases, the selection component 815-c in conjunction with the signal development component array 825-c may be referred to as a hierarchical signal development component device (e.g., partly in the MUX 917 or 918 and partly in the signal development component array 825-c).

[0263] In some instances, the system 900 may be operated to store data (e.g., in response to a write command). For example, a memory device including the system 900 may receive one or more commands (e.g., from a requesting device) to perform writes to multiple memory locations of the memory array 805-c. In an illustrative example, data may be provided to the sense amplifier sub-array 937, where each sense amplifier 290 of the sense amplifier sub-array 937 may be configured to receive a target logic state of the write command and generate a write signal based on the target logic state. For example, the sense amplifier sub-arrays 937-a, 937-b, 937-c, and 937-d may receive different sets of data and may each output 8 bits or 64 bits (e.g., 8 write signals or 64 write signals) to the MUXes 932-a, 932-b, 932-c, and 932-d via the sub-buses 934-a, 934-b, 934-c, and 934-d, respectively. The MUXes 932-a, 932-b, 932-c, and 932-d may each select 8 signal paths out of 64 signal paths of the sub-buses 929-a, 929-b, 929-c, and 929-d, and may output the corresponding signals to the signal paths of each sub-bus 929. The signals provided via the coupled signal paths may be stored in the corresponding cache blocks 926 (e.g., according to the latch signal generation section 510), and the process may be repeated until bits have been output from the MUXes 932-a, 932-b, 932-c, and 932-d for each of the 64 lines of each sub-bus 929.

[0264] Continuing with the illustrative example, once 64 bits have been stored in a cache block 926 (e.g., a cache line) coupled to one of the sub-buses 929, the corresponding cache block 926 can output 64 write signals to the corresponding sub-bus 922. For example, the cache block 926 coupled to sub-bus 929-a can provide 64 write signals via sub-bus 922-a, the cache block 926 coupled to sub-bus 929-b can provide 64 write signals via sub-bus 922-b, the cache block 926 coupled to sub-bus 929-c can provide 64 write signals via sub-bus 922-c, and the cache block 926 coupled to sub-bus 929-d can provide 64 write signals via sub-bus 922-d. Each sub-bus 922 can be routed via MUX 918 to the corresponding intermediate sub-bus 919 and MUX 917, which can couple the signal path of the intermediate sub-bus 919 to a selected subset of the signal paths of sub-bus 912 (e.g., a subset of the digital lines 210 corresponding to the respective domain 310-b).

[0265] In some examples, the 64 digital lines 210 along which the 64-bit output of each sub-bus 912 travels (e.g., selected by MUX 917) can be associated with the respective control zones 907 of different domains 310-b. To store the 64 bits in a particular memory location, a sub-row 908 containing the memory cells in which the 64 bits are to be stored can be activated. For example, sub-row 908-a can be activated to store the 64-bit output on sub-bus 912-a in a first memory location (e.g., in the memory cells coupled to sub-row 908-a); sub-row 908-b can be activated to store the 64-bit output on sub-bus 912-b in a second memory location (e.g., in the memory cells coupled to sub-row 908-b); sub-row 908-c can be activated to store the 64-bit output on sub-bus 912-c in a third memory location (e.g., in the memory cells coupled to sub-row 908-c); and sub-row 908-d can be activated to store the 64-bit output on sub-bus 912-d in a fourth memory location (e.g., in the memory cells coupled to sub-row 908-d). In some examples, these operations can be included in the write signal generation section 520.

[0266] In various examples, the routing or multiplexing supported by system 900 (e.g., selection component 815-c) may be capable of routing between 64-bit sub-rows from memory array 805-c and one of each potential 64-bit cache line of signal development component array 825-c. As such, system 900 may be configured (e.g., via a CAM, via cache associativity) to provide signal caching with various set associativities depending on the application in which system 900 is used. The cache controller that deploys system 900 to operate according to this configuration (e.g., memory controller 870-c may be microcode-driven. As such, a memory device incorporating system 900 may be capable of performing a dynamic change in associativity when microcode is sent from an operating system (OS) to the controller via a control signal.

[0267] The described techniques for signal development caching and multiplexing may support clustering of signal development components 250 (e.g., of signal development component array 825-c) that are mixed with a memory array (e.g., memory array 805-c) and may act as an in-memory cache with various set associativities. For example, row address or tag matching may be used to monitor which rows of memory array 805-c may have had information stored (e.g., as signal state, as cache state) in signal development component array 825-c. In some examples, a local CAM may be used to make signal development component array 825-c fully associative. Write-back and write-through strategies or operations (e.g., in combination or not) may be supported and may include one or more reconfigurable options to vary them.

[0268] In some examples, system 900 may support rank-level and chip-level parallelization. For example, multiple chips may have the same timing specifications or operations and may be timed simultaneously to scale the bandwidth for one or more devices (e.g., DIMM, attached PCIe). In some cases, simultaneous write-read may be performed by precharging one set of multiplexed digital lines 210 from the same row while activating another set of digital lines 210 from the same row on the same domain 310 or in a sub-domain. In some cases, the data paths for the two transfers may be isolated (e.g., due to not biasing the corresponding board). The latency of the read data path, the write data path, or both may be balanced, which may achieve higher efficiency compared to the latency when the read data path, the write data path, or both are not balanced.

[0269] To enable a memory device to configure a cache configuration with an optionally signal enabled via the BIOS, dynamic bandwidth amplification can be performed via the OS or a memory controller (e.g., memory controller 870). For example, a dynamic adjustment of the multiplexing rate can occur. In some cases, the signal development component array 825-c can be integrated with an OS page map. For example, physical pages can be at the granularity of rows, which can support integration with the OS page table or pagetable walk or other operations in memory with distributed hardware acceleration.

[0270] In some instances, system 900 can support computational operations at the signal development component array 825. For example, if values are stored such that they fit a multiplexing structure, their bit accesses can be overlapped in time, which can be referred to as pipelined-multiplexed in-memory computing. Sub-domain computing using interleaved charge sharing waves can also be supported. Additionally, the use of sub-domains can provide functionality for interleaved activation. For example, an activation wave can be directed towards the signal development component array 825 such that multiple memory cells 105 can be charge shared on the same digital line 210, providing charge-sharing-based analog computing. This computational wave can be used to perform mathematical operations or other divisions in a wave-like or synchronous pattern on the digital line 210 that encodes an access pattern configured by one or more hierarchical components of system 900 to activate domains 310, sub-domains, board lines, or zones. In this computational wave, sense logic close to along the wave can provide a latency gradient for the wave and can help improve the computational speed.

[0271] In some instances, a storage page migration system can be supported where the page cache does not have a backing store but instead has a byte-addressable storage extension. This system can be associated with values in a persistent memory (e.g., persistent FeRAM). Additionally, the extended capacity can improve the efficiency of a relatively slow multi-level cell architecture (e.g., a quad-level cell (QLC) architecture) by extending the page cache memory size.

[0272] In some instances, the signal development component storage element may not maintain a signal strong enough to write to the memory cell 105, in which case strengthening can be supported. For example, charge pumping of the signal development component 250 can be performed, and the sense amplifier 290 can be used to amplify or generate a write signal to both the signal development component storage element and the memory cell 105.

[0273] In some instances, system 900 may implement a T-connection where the bottom of the T-connection may be coupled to the sense amplifier array 845 and the sides of the T-connection may be coupled to the memory array 805 and the signal development component array 825, respectively. Thus, there may be a three-state connector where each node of the T-connection is connected to at least one other node, which may support enhanced flexibility for signal strengthening. The T-connection may enable signal strengthening when charge coupling may be insufficient during a write operation. The three-state connection may be able to connect the memory array 805 to the signal development component array 825, connect the signal development component array to the sense amplifier array 845, connect the sense amplifier array 845 to the memory array 805, or connect all three arrays together.

[0274] In some cases (e.g., when implementing a write-through cache policy), the signal development component array 825 and the main memory connection may act on the same physical line by enabling select components (e.g., select component 815, select component 835), which may support writing information concurrently to the signal development component array 825 and the memory array 805. In these cases, the information may be used in the signal development component array 825 for subsequent reads. However, isolating the main memory connection from the signal development component array 825 may enable streaming writes. This isolation may depend on whether the information to be written to a memory address is also maintained in the signal development component array 825.

[0275] Techniques for signal development caching according to the examples disclosed herein may be supported by various physical configurations of a memory device or its components. In some instances, the signal development cache (e.g., cache element array, signal development component array 825) and the memory array 805 may be formed on the same die (e.g., the same or different levels, the same or different layers of a memory die or chip, at a similar or overlapping distance from the substrate of the memory die or chip). In some instances, the signal development cache and the memory array 805 may utilize a similar memory architecture (e.g., a capacitive memory architecture), and may be modified during the manufacturing process to selectively form different memory architectures in the same component (e.g., in the same die, to form ferroelectric capacitors for the memory cells of the memory array 805 and linear capacitors for the cache elements of the signal development cache). In various instances, the sense amplifier 290 (e.g., or sense amplifier array 245) may be formed on the same, different, or overlapping levels or layers (e.g., relative to the substrate, of the same memory die or chip) as the cache elements or memory elements.

[0276] In some instances, when a memory device includes multiple tiers or levels, one tier or level may include the memory array 805 and another tier or level may include a signal development cache. In various instances, the sense amplifier array 845, the memory controller 870, or both may be included in a different (e.g., third) tier or level that is above or below the tier or level that includes the memory array 805 or the signal development cache (e.g., relative to the substrate).

[0277] In some instances, the memory array 805 and the signal development cache (e.g., the signal development component array 825) may be formed on different memory dies or chips, and these different dies or chips may be coupled to each other (e.g., using bonding techniques, using through-silicon vias). In various instances, the sense amplifier array 845 or the memory controller 870 may be included on the same or different memory dies or chips. Multiple memory dies or chips, or a stack thereof, may be included in the same memory device package. In any of the described instances, various physical or logical arrangements of the described components, or combinations thereof, may be used to support the described techniques for signal development caching, including but not limited to the arrangements described with reference to Figure 1 , 2 , 3, 6, 7, 8A, 8B, 8C, and 9.

[0278] Figure 10 FIG. 1000 shows a block diagram of a memory device 1005 that supports signal development caching in a memory device according to an example disclosed herein. The memory device 1005 may be an example of aspects of a memory device as described with reference to Figures 1 to 9 . The memory device 1005 may include a memory SDC coupling component 1010, a signal state storage component 1015, an SDC SA coupling component 1020, a sensing component 1025, a command receiver 1030, a word line activation component 1035, a board node biasing component 1040, a storage determination component 1045, and a logical state write component 1050. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0279] The memory SDC coupling component 1010 can perform various coupling operations between the memory array and the signal development cache memory. In some instances, the memory SDC coupling component 1010 can couple a set of access lines of the memory array to the signal development cache memory, where each of the set of access lines can correspond to a respective one of a set of memory cells of the memory array. In some instances, the memory SDC coupling component 1010 can couple a first access line of the set of access lines to a first cache memory element of a set of cache memory elements during a first time interval. In some instances, the memory SDC coupling component 1010 can couple a second access line of the set of access lines to a second cache memory element of the set of cache memory elements during a second time interval that at least partially overlaps with the first time interval.

[0280] In some instances, the memory SDC coupling component 1010 can couple a set of storage elements to the set of memory cells after storing respective cache memory signals for each of a set of logic states into respective storage elements. In some instances, the memory SDC coupling component 1010 can couple a first storage element of the set of storage elements to a first memory cell of the set of memory cells during a third time interval. In some instances, the memory SDC coupling component 1010 can couple a second storage element of the set of storage elements to a second memory cell of the set of memory cells during a fourth time interval that overlaps with the third time interval.

[0281] The signal state storage component 1015 can store a signal state (e.g., a cache memory signal) corresponding to a logic state stored by a respective one of the set of memory cells (e.g., corresponding to a signal developed based on the coupling) at each of a set of cache memory elements of the signal development cache memory and based on coupling the set of access lines to the signal development cache memory.

[0282] The SDC sense amplifier (SA) coupling component 1020 can perform various coupling operations between the signal development cache and the sense amplifier array. In some instances, the SDC SA coupling component 1020 can couple the set of cache elements of the signal development cache to the sense amplifier array based on the storage (e.g., after the storage, concurrently with the storage). In some instances, the SDC SA coupling component 1020 can couple the first cache element in the set of cache elements to the first sense amplifier of the sense amplifier array during a third time interval. In some instances, the SDC SA coupling component 1020 can couple the second cache element in the set of cache elements to the first sense amplifier of the sense amplifier array during a fourth time interval following the third time interval. In some instances, the SDC SA coupling component 1020 can couple the first cache element in the set of cache elements to the first sense amplifier of the sense amplifier array during a third time interval. In some instances, the SDC SA coupling component 1020 can couple the second cache element in the set of cache elements to the second sense amplifier of the sense amplifier array during a fourth time interval that at least partially overlaps with the third time interval.

[0283] In some instances, the SDC SA coupling component 1020 can couple a set of sense amplifiers of the sense amplifier array to the set of storage elements of the signal development cache based on the determination to store the corresponding cache signals for each of the set of logic states in the corresponding storage elements. In some instances, the SDC SA coupling component 1020 can couple the first sense amplifier of the sense amplifier array to the first storage element in the set of storage elements during a first time interval. In some instances, the SDC SA coupling component 1020 can couple the first sense amplifier of the sense amplifier array to the second storage element in the set of storage elements during a second time interval following the first time interval.

[0284] The sensing component 1025 can sense (e.g., capture, latch, or strengthen) the corresponding logic signals at each of a set of sense amplifiers of the sense amplifier array based on the stored corresponding signal states and the coupling of the set of cache elements to the sense amplifier array.

[0285] The command receiver 1030 can receive various commands from a requesting device. In some instances, the command receiver 1030 can receive a write command that includes a set of logical states for writing to a set of memory cells of the memory array. In some instances, the command receiver 1030 can receive a read command from a requesting device (e.g., a host device, another device different from the memory device), and coupling the set of access lines of the memory array to the signal development cache can be based on the read command. In some instances, the command receiver 1030 can receive a read command from a requesting device (e.g., a host device, another device different from the memory device) after or during storing the corresponding cache signal or cache signal state at each of the set of cache elements of the signal development cache, and coupling the signal development cache to the sense amplifier array can be based on the read command.

[0286] In some instances, the memory array can include multiple domains each associated with a corresponding subgroup of a plurality of word lines, and the word line activation component 1035 can activate the word lines of the first domain of the set of domains to couple the first subgroup of the set of memory cells to the first subgroup of the set of access lines. In some instances, the word line activation component 1035 can activate the word lines of the second domain of the set of domains to couple the second subgroup of the set of memory cells to the second subgroup of the set of access lines.

[0287] In some instances, each of the multiple domains of the memory array can be associated with one or more of a plurality of plate nodes that can be operated to be biased independently of other plate nodes of the plurality of plate nodes. In some instances, the plate node biasing component 1040 can bias the plate nodes of the first domain, wherein the cache signal storing the logical state corresponding to that stored by the first subgroup of memory cells is based on biasing the plate nodes of the first domain. In some instances, the plate node biasing component 1040 can bias the plate nodes of the second domain, wherein the cache signal storing the logical state corresponding to that stored by the second subgroup of memory cells is based on biasing the plate nodes of the second domain.

[0288] The storage determination component 1045 can determine, based on the write command, to store the corresponding cache signal (e.g., signal state) for each of the set of logical states at the corresponding storage element of a set of storage elements of the signal development cache.

[0289] The logical state writing component 1050 can write the set of logical states to the set of memory cells based on coupling the set of storage elements to the set of memory cells of the memory array.

[0290] Figure 11 The flowchart shows an illustration of one or more methods 1100 for developing a cache in a support memory device according to an example as disclosed herein. The operations of method 1100 may be implemented by a memory device or its components as described with reference to Figures 1 to 9 as described. For example, the operations of method 1100 may be performed by a memory device as described with reference to Figure 10 as described. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0291] At 1105, the memory device may couple a set of access lines of a memory array to a signal development cache, where each of the set of access lines corresponds to a respective one of a set of memory cells of the memory array. The operation of 1105 may be performed according to techniques as described with reference to Figures 1 to 9 as described. In some examples, aspects of the operation of 1105 may be performed by a memory SDC coupling component as described with reference to Figure 10 as described.

[0292] At 1110, the memory device may store, at each of a set of cache elements of the signal development cache and based on coupling the set of access lines to the signal development cache, a signal state (e.g., a cache signal) corresponding to a logic state stored by a respective one of the set of memory cells (e.g., corresponding to a signal developed based on the coupling). The operation of 1110 may be performed according to techniques as described with reference to Figures 1 to 9 as described. In some examples, aspects of the operation of 1110 may be performed by a signal state storage component as described with reference to Figure 10 as described.

[0293] At 1115, the memory device may couple the set of cache elements of the signal development cache to a sense amplifier array based on the storing (e.g., after the storing, concurrently with the storing). The operation of 1115 may be performed according to techniques as described with reference to Figures 1 to 9 as described. In some examples, aspects of the operation of 1115 may be performed by an SDC SA coupling component as described with reference to Figure 10 as described.

[0294] At 1120, the memory device may sense (e.g., capture, latch, or strengthen) a corresponding logic signal at each of a set of sense amplifiers in the sense amplifier array based on a corresponding stored signal state and the coupling of the set of cache elements to the sense amplifier array. The operation of 1120 may be performed according to techniques as described with reference to Figures 1 to 9 The techniques described. In some instances, aspects of the operation of 1120 may be performed by a sense component as described with reference to Figure 10 The techniques described.

[0295] In some instances, a device as described herein may perform a method or methods, such as method 1100. The device may include features, circuitry, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: coupling a set of access lines of a memory array to a signal development cache, wherein each of the set of access lines corresponds to a respective one of a set of memory cells of the memory array; storing, at each of a set of cache elements of the signal development cache and based on coupling the set of access lines to the signal development cache, a signal state (e.g., a cache signal) corresponding to a logic state stored by the respective one of the set of memory cells (e.g., corresponding to a signal developed based on the coupling); coupling the set of cache elements of the signal development cache to a sense amplifier array based on the storing (e.g., after the storing, concurrently with the storing); and sensing (e.g., capturing, latching, or strengthening) a corresponding logic signal at each of a set of sense amplifiers in the sense amplifier array based on the respective stored signal state and the coupling of the set of cache elements to the sense amplifier array.

[0296] In some instances of method 1100 and the device described herein, coupling the set of access lines of the memory array to the signal development cache may include operations, features, circuitry, components, or instructions for: coupling a first access line of the set of access lines to a first cache element of the set of cache elements during a first time interval; and coupling a second access line of the set of access lines to a second cache element of the set of cache elements during a second time interval that at least partially overlaps the first time interval.

[0297] In some examples of method 1100 and the devices described herein, coupling the signal exploitation cache memory to the sense amplifier array can include operations, features, circuitry, components, or instructions for: coupling the first cache memory element of the set of cache memory elements to a first sense amplifier of the sense amplifier array during a third time interval; and coupling the second cache memory element of the set of cache memory elements to the first sense amplifier of the sense amplifier array during a fourth time interval subsequent to the third time interval.

[0298] In some examples of method 1100 and the devices described herein, coupling the signal exploitation cache memory to the sense amplifier array can include operations, features, circuitry, components, or instructions for: coupling the first cache memory element of the set of cache memory elements to a first sense amplifier of the sense amplifier array during a third time interval; and coupling the second cache memory element of the set of cache memory elements to a second sense amplifier of the sense amplifier array during a fourth time interval that at least partially overlaps with the third time interval.

[0299] Some examples of method 1100 and the devices described herein can further include operations, features, circuitry, components, or instructions for receiving a read command from a requesting device (e.g., a host device, another device different from the memory device), wherein coupling the set of access lines of the memory array to the signal exploitation cache memory can be based on the read command.

[0300] Some examples of method 1100 and the devices described herein can further include operations, features, circuitry, components, or instructions for: receiving a read command at the memory device from a requesting device (e.g., a host device, another device different from the memory device) after or during storing the respective cache memory signal or cache memory signal state at each of the set of cache memory elements of the signal exploitation cache memory, wherein coupling the signal exploitation cache memory to the sense amplifier array can be based on the read command.

[0301] In some examples of method 1100 and the devices described herein, the memory array may include a set of domains, each associated with a respective subgroup of the set of word lines, and method 1100 or the device may include operations, features, circuitry, components, or instructions for: activating the word lines of a first domain of the set of domains to couple a first subgroup of the set of memory cells to a first subgroup of the set of access lines, and activating the word lines of a second domain of the set of domains to couple a second subgroup of the set of memory cells to a second subgroup of the set of access lines.

[0302] In some examples of method 1100 and the devices described herein, each of the set of domains may be associated with one or more of a set of plate nodes, each of the one or more of the set of plate nodes being operable to be biased independently of other plate nodes of the set of plate nodes, and method 1100 or the device may further include operations, features, circuitry, components, or instructions for: biasing the plate nodes of the first domain, wherein the cache signal storing the logic state corresponding to that stored by the first subgroup of memory cells may be based on biasing the plate nodes of the first domain; and biasing the plate nodes of the second domain, wherein the cache signal storing the logic state corresponding to that stored by the second subgroup of memory cells may be based on biasing the plate nodes of the second domain.

[0303] Figure 12 FIG. illustrates a flowchart of one or more methods 1200 for developing a cache for signals in a memory device in accordance with an example as described with reference to Figures 1 to 9 The operations of method 1200 may be implemented by a memory device or components thereof as described with reference to Figures 1 to 9 For example, the operations of method 1200 may be performed by a memory device as described with reference to Figure 10 In some examples, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0304] At 1205, the memory device may receive a write command that includes a set of logic states for writing to a set of memory cells of the memory array. The operation of 1205 may be performed in accordance with techniques as described with reference to Figures 1 to 9 In some examples, aspects of the operation of 1205 may be performed by a command receiver as described with reference to Figure 10 In some examples, aspects of the operation of 1205 may be performed by a command receiver as described with reference to

[0305] At 1210, the memory device may determine, based on the write command, to store corresponding cache signals (e.g., signal states) for each of the group of logical states at corresponding storage elements of a group of storage elements of the signal development cache. The operation of 1210 may be performed according to techniques as described in reference Figures 1 to 9 as described. In some instances, aspects of the operation of 1210 may be performed by a storage determination component as described in reference Figure 10 as described.

[0306] At 1215, the memory device may couple a group of sense amplifiers of the sense amplifier array to the group of storage elements of the signal development cache based on the determination to store the corresponding cache signals for each of the group of logical states to the corresponding storage elements. The operation of 1215 may be performed according to techniques as described in reference Figures 1 to 9 as described. In some instances, aspects of the operation of 1215 may be performed by an SDC SA coupling component as described in reference Figure 10 as described.

[0307] At 1220, the memory device may couple the group of storage elements to the group of memory cells after storing the corresponding cache signals for each of the group of logical states to the corresponding storage elements. The operation of 1220 may be performed according to techniques as described in reference Figures 1 to 9 as described. In some instances, aspects of the operation of 1220 may be performed by a memory SDC coupling component as described in reference Figure 10 as described.

[0308] At 1225, the memory device may write the group of logical states to the group of memory cells based on coupling the group of storage elements to the group of memory cells of the memory array. The operation of 1225 may be performed according to techniques as described in reference Figures 1 to 9 as described. In some instances, aspects of the operation of 1225 may be performed by a logical state write component as described in reference Figure 10 as described.

[0309] In some instances, a device as described herein may execute one or several methods, such as method 1200. The device may include features, circuitry, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following: receiving a write command at a memory device including a memory array, the write command including a set of logical states for writing to a set of memory cells of the memory array; determining, based on the write command, that corresponding cache signals (e.g., signal states) for each of the set of logical states are to be stored at corresponding storage elements of a set of storage elements of a signal development cache; coupling, based on the determination, a set of sense amplifiers of a sense amplifier array to the set of storage elements of the signal development cache to store the corresponding cache signals for each of the set of logical states to the corresponding storage elements; after storing the corresponding cache signals for each of the set of logical states to the corresponding storage elements, coupling the set of storage elements to the set of memory cells; and writing the set of logical states to the set of memory cells based on coupling the set of storage elements to the set of memory cells of the memory array.

[0310] In some instances of method 1200 and the device described herein, storing the corresponding cache signals for each of the set of logical states at the corresponding storage elements of the signal development cache may include operations, features, circuitry, components, or instructions for performing the following: coupling a first sense amplifier of the sense amplifier array to a first storage element of the set of storage elements during a first time interval; and coupling the first sense amplifier of the sense amplifier array to a second storage element of the set of storage elements during a second time interval following the first time interval.

[0311] In some instances of method 1200 and the device described herein, coupling the set of storage elements to the set of memory cells may include operations, features, circuitry, components, or instructions for performing the following: coupling a first storage element of the set of storage elements to a first memory cell of the set of memory cells during a third time interval; and coupling a second storage element of the set of storage elements to a second memory cell of the set of memory cells during a fourth time interval overlapping the third time interval.

[0312] Note that the methods described herein are possible implementations, and the operations and steps may be rearranged or otherwise modified and other implementations are possible. Additionally, parts from two or more of the methods may be combined.

[0313] Describe a device. The device may include: a memory array having a set of memory cells, each memory cell in the set of memory cells being associated with one of a set of access lines of the memory array; a signal development cache having a set of storage elements different from the set of memory cells of the memory array; a sense amplifier array having a set of sense amplifiers, each sense amplifier in the set of sense amplifiers being configured to output a logic state based on sensing, capturing, or latching signaling from the signal development cache; a first selection component operable to selectively couple the set of access lines of the memory array to the signal development cache; and a second selection component operable to selectively couple the signal development cache to the set of sense amplifiers of the sense amplifier array.

[0314] Some examples of the device may include a third selection component operable to selectively couple the set of access lines of the memory array to the set of sense amplifiers of the sense amplifier array.

[0315] In some examples, the memory array includes a set of domains, each of the domains being associated with a corresponding subgroup of the set of access lines of the memory array, and each of the domains being associated with a corresponding set of second access lines to selectively couple the memory cells of the memory array to the corresponding subgroup of the set of access lines.

[0316] In some examples, the device may be operable to concurrently select one or more of the corresponding set of second access lines of the first of the set of domains and one or more of the corresponding set of second access lines of the second of the set of domains.

[0317] In some examples, each of the domains includes a corresponding set of subdomains, each of the subdomains being associated with a corresponding group within the subgroup of the set of access lines corresponding to the corresponding domain.

[0318] In some examples, each of the subdomains may be associated with an independently controllable board node.

[0319] In some examples, each of the domains includes a corresponding segment of the second access lines within the domain, and each of the subdomains is associated with a corresponding group within the subgroup of the set of access lines corresponding to the corresponding domain.

[0320] In some instances, the second access line may include word lines, and for a given domain, the device may be operable to concurrently couple a first word line driver to a first segment of a first word line within the given domain and to a second segment of a second word line within the given domain, and to concurrently couple a second word line driver to a second segment of the first word line within the given domain and to a first segment of the second word line within the given domain.

[0321] In some instances, the signal development cache may be associated with a set of cache lines, each of the cache lines being coupled to a corresponding subgroup of the set of storage elements.

[0322] In some instances, the number of the corresponding subgroups of the set of storage elements of each of the cache lines may be proportional (e.g., equal, an integer multiple) to the number of the corresponding groups within the subgroup of the set of access lines corresponding to a respective domain.

[0323] In some instances, an integer multiple of the number of the corresponding subgroups of the set of storage elements of each of the cache lines may be equal to the number of data bits of a read command, the number of data bits of a write command, or both.

[0324] In some instances, the first selection component may be configured for signal exchange with a first latency between the set of memory cells and the set of storage elements of the signal development cache, and the second selection component may be configured for signal exchange with a second latency between the set of storage elements of the signal development cache and the set of sense amplifiers, the second latency being less than the first latency.

[0325] In some instances, the first selection component may be operable to concurrently couple each access line in a subgroup of the set of access lines of the memory array to a corresponding one of the set of storage elements in a subgroup of the set of storage elements of the signal development cache.

[0326] In some instances, the second selection component may be operable to couple each storage element in a subgroup of the set of storage elements of the signal development cache to a corresponding one of the set of sense amplifiers of the sense amplifier array.

[0327] In some instances, each storage element in the set of storage elements may be configured to maintain a signal state (e.g., cache signal, cache state) corresponding to a logical state when the corresponding storage element is isolated from one or both of the memory array or the sense amplifier array.

[0328] In some instances, each sense amplifier of the group of sense amplifiers may be configured to receive a target logic state of a write command and generate a write signal based on the target logic state.

[0329] In some instances, to write the target logic state to a target memory cell, the device may be configured to transport the write signal from a corresponding one of the group of sense amplifiers to one of the group of storage elements of the signal de...

Claims

1. An apparatus, comprising: A memory array having a plurality of memory cells, each of the plurality of memory cells being associated with one of a plurality of access lines of the memory array; A signal development cache having a plurality of storage elements different from the plurality of memory cells of the memory array, the signal development cache being between an output node of a first selection component and an input node of a second selection component; A sense amplifier array having a plurality of sense amplifiers, each of the plurality of sense amplifiers being configured to output a logic state based at least in part on sensing signaling from the signal development cache; The first selection component, coupled to the plurality of access lines and the input node of the signal development cache and operable to selectively couple the plurality of access lines of the memory array to the input node of the signal development cache; And The second selection component, coupled to the output node of the signal development cache and the input node of the sense amplifier array and operable to selectively couple the signal development cache to the input node of the sense amplifier array.

2. The apparatus of claim 1, further comprising: A third selection component operable to selectively couple the plurality of access lines of the memory array to the plurality of sense amplifiers of the sense amplifier array.

3. The apparatus of claim 1, wherein the memory array includes domains, each of the domains being associated with a corresponding subgroup of the plurality of access lines of the memory array, and each of the domains being associated with a corresponding plurality of second access lines to selectively couple the memory cells of the memory array to the corresponding subgroup of the plurality of access lines.

4. The apparatus of claim 3, wherein the apparatus is operable to concurrently select one or more of the corresponding plurality of second access lines of a first domain of the domains and one or more of the corresponding plurality of second access lines of a second domain of the domains.

5. The apparatus of claim 3, wherein each of the domains includes a corresponding set of sub-domains, each of the sub-domains being associated with a corresponding group within the subgroup of the plurality of access lines corresponding to the respective domain.

6. The apparatus of claim 5, wherein each sub-domain is associated with an independently controllable board node.

7. The apparatus of claim 5, wherein each sub-domain includes a corresponding segment of the second access lines within the domain, and wherein each of the sub-domains is associated with a corresponding group within the subgroup of the plurality of access lines corresponding to the respective domain.

8. The apparatus of claim 5, wherein the corresponding plurality of second access lines includes word lines, and for a given domain, the apparatus is operable to: Concurrently couple a first word line driver to a first segment of a first word line within the given domain and to a second segment of a second word line within the given domain; and Couple a second word line driver to a second segment of the first word line within the given domain and concurrently to a first segment of the second word line within the given domain.

9. The apparatus of claim 5, wherein the signal development cache is associated with cache lines, each of the cache lines being coupled to a corresponding subgroup of the plurality of memory elements.

10. The apparatus of claim 9, wherein the number of the corresponding subgroups of the plurality of memory elements of each of the cache lines is proportional to the number of the corresponding groups within the subgroup of the plurality of access lines corresponding to a respective domain.

11. The apparatus of claim 10, wherein an integer multiple of the number of the corresponding subgroups of the plurality of memory elements of each of the cache lines is equal to the number of data bits of a read command, the number of data bits of a write command, or both.

12. The apparatus of claim 1, wherein: the first selection component is configured for signal exchange with a first latency between the plurality of memory cells and the plurality of memory elements of the signal development cache; and the second selection component is configured for signal exchange with a second latency between the plurality of memory elements of the signal development cache and the plurality of sense amplifiers, the second latency being less than the first latency.

13. The apparatus of claim 1, wherein the first selection component is operable to concurrently couple each access line of a subgroup of the plurality of access lines of the memory array to a corresponding one of the plurality of memory elements of a subgroup of the signal development cache.

14. The apparatus of claim 1, wherein the second selection component is operable to couple each of the plurality of memory elements of a subgroup of the signal development cache to a corresponding one of the plurality of sense amplifiers of the sense amplifier array.

15. The apparatus of claim 1, wherein each of the plurality of memory elements is configured to maintain a signal state corresponding to a logical state when the corresponding memory element is isolated from one or both of the memory array or the sense amplifier array.

16. The apparatus of claim 1, wherein each of the plurality of sense amplifiers is configured to receive a target logical state of a write command and generate a write signal at least in part based on the target logical state.

17. The apparatus according to claim 16, wherein, To write the target logical state to a target memory cell, the apparatus is configured to: transport the write signal from a corresponding one of the plurality of sense amplifiers to one of the plurality of memory elements of the signal development cache via the second selection component; and Transporting a second write signal from one of the plurality of storage elements of the signal development cache memory to the target memory cell via the first selection component, the second write signal being at least partially based on transporting the write signal to one of the plurality of storage elements of the signal development cache memory.

18. The apparatus according to claim 16, wherein, To write the target logic state to the target memory cell, the device is configured to: Isolate the plurality of storage elements of the signal development cache memory from the write signal; And Transport the write signal to the target memory cell via the first selection component and the second selection component.

19. The device according to claim 1, wherein each memory cell of the plurality of memory cells includes a corresponding storage element having an architecture different from that of the plurality of storage elements of the signal development cache memory.

20. The device according to claim 19, wherein the corresponding storage element of each memory cell of the plurality of memory cells includes a ferroelectric cell.

21. The device according to claim 19, wherein the corresponding storage element of each memory cell of the plurality of memory cells includes a material memory element.

22. The device according to claim 19, wherein each storage element of the plurality of storage elements of the signal development cache memory includes a linear capacitor.

23. The device according to claim 1, further comprising: A controller configured to manage a refresh process to maintain cache memory signals stored by the plurality of storage elements of the signal development cache memory.

24. The device according to claim 1, wherein: Each memory cell of the plurality of memory cells is operable to store one of a set of more than two logic states; and The first selection component is operable to selectively couple one of the plurality of access lines of the memory array to two or more of the plurality of storage elements of the signal development cache memory.

25. The device according to claim 1, wherein: Each storage element of the signal development cache memory is operable to store one of a set of more than two cache memory signal states; and The first selection component is operable to selectively couple one of the plurality of storage elements of the signal development cache memory to two or more of the plurality of access lines of the memory array.

26. The device according to claim 1, wherein: Each storage element of the signal development cache memory is operable to store one of a set of more than two cache memory signal states; and The first selection component is operable to selectively couple one of the plurality of storage elements of the signal development cache memory to two or more of the plurality of memory cells.

27. A method, comprising: Couple a set of access lines of a memory array to a signal-developing cache, wherein each of the set of access lines corresponds to a respective one of a set of memory cells of the memory array, and wherein coupling the set of access lines of the memory array to the signal-developing cache includes: During a first time interval, couple a first access line of the set of access lines to a first cache element of a plurality of cache elements; and During a second time interval that at least partially overlaps the first time interval, couple a second access line of the set of access lines to a second cache element of the plurality of cache elements; At each of the plurality of cache elements of the signal-developing cache and at least partially based on coupling the set of access lines to the signal-developing cache, store a cache signal state corresponding to a logic state stored by a respective one of the set of memory cells; At least partially based on the storing, couple the plurality of cache elements of the signal-developing cache to a sense amplifier array; and At each of a plurality of sense amplifiers of the sense amplifier array, sense a respective logic signal at least partially based on the stored respective signal state and the coupling of the plurality of cache elements to the sense amplifier array.

28. The method of claim 27, wherein coupling the signal-developing cache to the sense amplifier array includes: During a third time interval, couple the first cache element of the plurality of cache elements to a first sense amplifier of the sense amplifier array; And During a fourth time interval subsequent to the third time interval, couple the second cache element of the plurality of cache elements to the first sense amplifier of the sense amplifier array.

29. The method of claim 27, wherein coupling the signal-developing cache to the sense amplifier array includes: During a third time interval, couple the first cache element of the plurality of cache elements to a first sense amplifier of the sense amplifier array; And During a fourth time interval that at least partially overlaps the third time interval, couple the second cache element of the plurality of cache elements to a second sense amplifier of the sense amplifier array.

30. The method of claim 27, further comprising: Receive a read command from a requesting device at a memory device, wherein coupling the set of access lines of the memory array to the signal-developing cache is at least partially based on the read command.

31. The method of claim 27, further comprising: After storing the corresponding cache memory signal state at each of the plurality of cache memory elements of the signal development cache memory, a read command is received at the memory device from a requesting device, wherein coupling the signal development cache memory to the sense amplifier array is at least partially based on the read command.

32. The method according to claim 27, wherein the memory array includes a plurality of domains each associated with a corresponding subgroup of a plurality of word lines, the method further comprising: Activating the word lines of a first domain of the plurality of domains to couple a first subgroup of the set of memory cells to a first subgroup of the set of access lines; And Activating the word lines of a second domain of the plurality of domains to couple a second subgroup of the set of memory cells to a second subgroup of the set of access lines.

33. The method according to claim 32, wherein each of the plurality of domains is associated with one or more of a plurality of plate nodes, each of the plurality of plate nodes being operable to be biased independently of other plate nodes of the plurality of plate nodes, the method further comprising: Biasing the plate nodes of the first domain, wherein storing the cache memory signal state corresponding to the logic state stored by the first subgroup of the set of memory cells is at least partially based on biasing the plate nodes of the first domain; And Biasing the plate nodes of the second domain, wherein storing the cache memory signal state corresponding to the logic state stored by the second subgroup of the set of memory cells is at least partially based on biasing the plate nodes of the second domain.

34. A method, comprising: Receiving a write command at a memory device including a memory array, the write command including a plurality of logic states for writing to a plurality of memory cells of the memory array; Determining, at least partially based on the write command, to store a corresponding cache memory signal for each of the plurality of logic states at a corresponding storage element of a plurality of storage elements of a signal development cache memory; Coupling a plurality of sense amplifiers of a sense amplifier array to the plurality of storage elements of the signal development cache memory, at least partially based on the determination, to store the corresponding cache memory signal for each of the plurality of logic states to the corresponding storage element, wherein storing the corresponding cache memory signal for each of the plurality of logic states at the corresponding storage element of the signal development cache memory includes: Coupling a first sense amplifier of the sense amplifier array to a first storage element of the plurality of storage elements during a first time interval; and Coupling the first sense amplifier of the sense amplifier array to a second storage element of the plurality of storage elements during a second time interval subsequent to the first time interval; After storing the corresponding cache memory signal for each of the plurality of logic states to the corresponding storage element, coupling the plurality of storage elements to the plurality of memory cells; and Writing the plurality of logical states to the plurality of memory cells is at least partially based on coupling the plurality of storage elements to the plurality of memory cells of the memory array.

35. The method of claim 34, wherein coupling the plurality of storage elements to the plurality of memory cells comprises: coupling a first one of the plurality of storage elements to a first one of the plurality of memory cells during a third time interval; and coupling a second one of the plurality of storage elements to a second one of the plurality of memory cells during a fourth time interval overlapping the third time interval.

36. An apparatus comprising: a memory array including a plurality of memory cells; a signal development cache including a plurality of cache elements different from the plurality of memory cells; a sense amplifier array including a plurality of sense amplifiers; and a controller operable to: couple a plurality of access lines of the memory array to the signal development cache, wherein each of the plurality of access lines corresponds to a respective one of the plurality of memory cells, and wherein coupling the plurality of access lines of the memory array to the signal development cache comprises: coupling a first access line of the plurality of access lines to a first cache element of the plurality of cache elements during a first time interval; and coupling a second access line of the plurality of access lines to a second cache element of the plurality of cache elements during a second time interval at least partially overlapping the first time interval; storing, at each of the plurality of cache elements, a signal state corresponding to a logical state stored by a respective one of the plurality of memory cells at least partially based on coupling the plurality of access lines to the signal development cache; coupling the plurality of cache elements to the sense amplifier array at least partially based on the storing; and sensing a respective logic signal at each of the plurality of sense amplifiers at least partially based on the respective signal state and coupling the plurality of cache elements to the sense amplifier array.

37. An apparatus comprising: a memory array including a plurality of memory cells; a signal development cache including a plurality of cache elements different from the plurality of memory cells; a sense amplifier array including a plurality of sense amplifiers; and a controller operable to: receive a write command including a plurality of logical states for writing to the plurality of memory cells; determine, at least partially based on the write command, that a respective cache signal for each of the plurality of logical states is to be stored at a respective cache element of the plurality of cache elements; Couple the plurality of sense amplifiers to the plurality of cache memory elements based at least in part on the determination to store the respective cache memory signals for each of the plurality of logic states to the respective cache memory elements, wherein storing the respective cache memory signals for each of the plurality of logic states at the respective cache memory elements of the signal development cache memory includes: Couple a first sense amplifier of the sense amplifier array to a first cache memory element of the plurality of cache memory elements during a first time interval; and Couple the first sense amplifier of the sense amplifier array to a second cache memory element of the plurality of cache memory elements during a second time interval subsequent to the first time interval; After storing the respective cache memory signals for each of the plurality of logic states to the respective cache memory elements, couple the plurality of cache memory elements to the plurality of memory cells; and Write the plurality of logic states to the plurality of memory cells based at least in part on coupling the plurality of cache memory elements to the plurality of memory cells.

38. An apparatus comprising: A memory array having a plurality of memory cells, each memory cell of the plurality of memory cells being associated with one of a plurality of access lines of the memory array; A signal development cache memory having a plurality of cache memory elements different from the plurality of memory cells of the memory array; A sense amplifier array having a plurality of sense amplifiers, each sense amplifier of the plurality of sense amplifiers being configured to output a logic state based at least in part on latching signaling from the signal development cache memory; And A selection circuitry comprising: A first selection element coupled to the plurality of access lines and an input node of the signal development cache memory and operable to Selectively couple the plurality of access lines of the memory array to the input node of the signal development cache memory; And A second selection component coupled to an output node of the signal development cache memory and an input node of the sense amplifier array and operable to selectively couple the signal development cache memory to the input node of the sense amplifier array.

39. The apparatus of claim 38, wherein the selection circuitry is operable to support concurrent coupling of the plurality of access lines of the memory array, the signal development cache memory, and the plurality of sense amplifiers of the sense amplifier array.

40. The apparatus of claim 38, wherein the selection circuitry is operable to support concurrent coupling of one of the plurality of access lines of the memory array, one of the plurality of cache memory elements of the signal development cache memory, and one of the plurality of sense amplifiers of the sense amplifier array.

41. The apparatus of claim 38, wherein the select circuitry is reconfigurable to support changes between policies for writing information back to the memory array.

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