Systems and techniques for concurrently accessing multiple memory units

Abstract

This application relates to systems and techniques for concurrently accessing multiple memory cells. A memory tile can include a plurality of self-selecting memory cells addressable using a row decoder and a column decoder. A memory controller can access a first self-selecting memory cell of the memory tile using a first pulse having a first polarity. The memory controller can also concurrently access a second self-selecting memory cell of the memory tile using a second pulse having a second polarity different from the first polarity. The memory controller can determine characteristics of the pulses to mitigate interference to unselected self-selecting memory cells of the memory tile.

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT / US2019 / 066202, filed by Pio on December 13, 2019, entitled "Systems and Techniques for Accessing Multiple Memory Cells Concurrently," which claims priority to U.S. Patent Application No. 16 / 712,682, filed by Pio on December 12, 2019, also entitled "Systems and Techniques for Accessing Multiple Memory Cells Concurrently," and U.S. Patent Application No. 16 / 712,682, filed by Pio on December 19, 2018, also entitled "Systems and Techniques for Accessing Multiple Memory Cells Concurrently." The priority of U.S. Provisional Patent Application No. 62 / 782,015, entitled “CONCURRENTLY”, is assigned to its assignee, and each of the claims is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to systems and techniques for concurrently accessing multiple memory cells. Background Technology

[0004] The following text generally deals with programming enhancements in memory cells, and more specifically with programming enhancements in custom memory.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by logic '1' or logic '0'. In other systems, more than two states can be stored. To access stored information, components of the electronic device can read or sense the stored states in the memory device. To store information, components of the electronic device can write or program states into the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), read-only memory (ROM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. Even in the absence of external power, non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time. Volatile memory devices, such as DRAM, may lose their stored state over time unless they are periodically refreshed by an external power supply. Improvements to memory devices may include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption or manufacturing costs, and other metrics.

[0007] Some memory devices may include multiple memory blocks comprising arrays of memory cells. Each memory block may include a single row decoder and a single column decoder, which can be used to access the memory cells of the memory block. In some memory blocks, only a single memory cell may be accessed during an access operation. Summary of the Invention

[0008] Describe a method. The method may include: identifying a first memory cell of a memory block for reading; identifying a second memory cell of the memory block for reading; selecting a first polarity of a first read pulse to read the first memory cell and selecting a second polarity of a second read pulse to read the second memory cell; using the first read pulse to read the first memory cell; and using the second read pulse concurrently with reading the first memory cell, based at least in part on selecting the first polarity and the second polarity.

[0009] Another method is described. The method may include: identifying a first memory cell of a memory block for programming using a write operation; identifying a second memory cell of the memory block for access using a write operation or a read operation; determining that concurrent access to the second memory cell on the memory block is permitted during the access operation duration, in addition to programming the first memory cell; programming the first memory cell of the memory block during the access operation duration; and at least in part based on the determination that concurrent access to the second memory cell of the memory block is permitted, in addition to programming the first memory cell during the access operation duration.

[0010] Describe an apparatus. The apparatus may include: a memory cell; a digital line coupled to the memory cell; a first sensing component coupled to the digital line, the first sensing component being configured to identify a logic state stored in the memory cell based at least in part on a first read pulse having a first polarity; and a second sensing component coupled to the digital line, the second sensing component being configured to identify the logic state stored in the memory cell based at least in part on a second read pulse having a second polarity different from the first polarity.

[0011] Describe a method. The method may include: identifying a first memory cell in a first segment of a memory block for reading, wherein the memory cell in the first segment of the memory block is configured to read in response to the application of a first read pulse having a first polarity; identifying a second memory cell in a second segment of the memory block for reading, wherein the memory cell in the second segment of the memory block is configured to read in response to the application of a second read pulse having a second polarity different from the first polarity; reading the first memory cell; and reading the second memory cell concurrently with reading the first memory cell, at least in part based on identifying the first memory cell in the first segment and the second memory cell in the second segment.

[0012] Describe an apparatus. The apparatus may include: a memory block having a first segment of memory cells and a second segment of memory cells, wherein the memory cells of the first segment are configured to be read in response to the application of a first read pulse having a first polarity and the memory cells of the second segment are configured to be read in response to the application of a second read pulse having a second polarity different from the first polarity; a first sensing component coupled to the first segment of the memory cells of the memory block and configured to identify a logical state of a memory cell of the first segment of the memory cells based at least partially on the first read pulse having the first polarity; and a second sensing component coupled to the second segment of the memory cells of the memory block and configured to identify the logical state of a memory cell of the second segment of the memory cells based at least partially on the second read pulse having the second polarity. Attached Figure Description

[0013] Figure 1 This disclosure describes various examples of memory arrays that support systems and techniques for concurrent access to multiple memory cells, based on different embodiments of the present disclosure.

[0014] Figure 2This disclosure describes various examples of memory arrays that support systems and techniques for concurrent access to multiple memory cells, based on different embodiments of the present disclosure.

[0015] Figure 3 Examples of diagrams illustrating various embodiments of the present disclosure that support systems and techniques for concurrent access to multiple memory cells.

[0016] Figure 4 Examples of memory blocks illustrating various embodiments of the present disclosure that support systems and techniques for concurrent access to multiple memory cells.

[0017] Figure 5 Examples of diagrams illustrating various embodiments of the present disclosure that support systems and techniques for concurrent access to multiple memory cells.

[0018] Figure 6 Examples of memory blocks illustrating various embodiments of the present disclosure that support systems and techniques for concurrent access to multiple memory cells.

[0019] Figure 7 Examples of diagrams illustrating various embodiments of the present disclosure that support systems and techniques for concurrent access to multiple memory cells.

[0020] Figure 8 Examples of diagrams illustrating various embodiments of the present disclosure that support systems and techniques for concurrent access to multiple memory cells.

[0021] Figure 9 Examples of circuits supporting systems and techniques for concurrently accessing multiple memory cells are illustrated according to various embodiments of this disclosure.

[0022] Figure 10 Examples of memory blocks illustrating various embodiments of the present disclosure that support systems and techniques for concurrent access to multiple memory cells.

[0023] Figure 11 Examples of memory devices that support systems and techniques for concurrent access to multiple memory cells, according to various embodiments of this disclosure.

[0024] Figures 12 to 17 This invention describes a system and technique for concurrently accessing multiple memory cells according to embodiments of the present disclosure. Detailed Implementation

[0025] Some memory cells can be formed from chalcogenide materials, which, when a voltage is applied, cause ions to migrate or aggregate toward one side of the chalcogenide material. These memory cells, sometimes called auto-memory cells, can utilize ion migration or aggregation to store logical states (e.g., logic '0' or logic '1') on the memory cell. Due to the properties of chalcogenide materials, auto-memory cells can be programmed using programming pulses of different polarities and read using read pulses of different polarities. In many memory blocks, only a single memory cell can be addressed at a time, which leads to drawbacks and limitations. Using different polarities in the access pulses can provide some advantages in terms of the functionality of memory devices containing auto-memory cells.

[0026] A technique is provided for concurrently accessing multiple memory cells of a memory block. The memory block may contain multiple selectable memory cells addressable using row decoders and column decoders. To access a first selectable memory cell of the memory block, a memory controller may apply a first pulse having a first polarity to the first selectable memory cell. The memory controller may also concurrently access a second selectable memory cell of the memory block using a second pulse having a second polarity different from the first polarity. The memory controller may determine the characteristics of the first and second pulses to mitigate interference with unselected selectable memory cells of the memory block. In such a memory block, two selectable memory cells may be read concurrently, two selectable memory cells may be programmed concurrently, or one selectable memory cell may be read concurrently while another selectable memory cell is programmed concurrently.

[0027] Figure 1 Examples of memory blocks 100 supporting systems and techniques for concurrent access to multiple memory cells according to various embodiments of this disclosure are described. A memory device may include multiple memory blocks 100. Each memory block 100 includes memory cells 105 programmable to store different states. Each memory cell 105 may be programmable to store two states, represented as logic '0' and logic '1'. In some cases, memory cells 105 are configured to store more than two logic states.

[0028] Memory block 100 may represent a block of memory cells that can be addressed during an access operation. Memory block 100 may include row decoders 120 and column decoders 130 for addressing selected memory cells of memory block 100 during an access operation. In some memory technologies, only a single memory cell 105 of memory block 100 can be accessed at a time. This is due to potential interference to unselected memory cells that may occur when multiple access lines (e.g., word lines 110 and / or digital lines 115) are biased during the same access operation. Systems and techniques for concurrently accessing two or more memory cells 105 of the same memory block 100 during the same access operation duration are provided herein.

[0029] Memory block 100 can be a three-dimensional (3D) memory array, wherein two-dimensional (2D) memory arrays are formed by stacking them one on top of the other. Compared to 2D arrays, this can increase the number of memory cells that can be formed on a single die or substrate, which in turn can reduce manufacturing costs or improve the performance of the memory array, or both. Figure 1 In the example depicted, memory block 100 contains two levels of memory cells 105 and can therefore be considered a three-dimensional memory array; however, the number of levels is not limited to two. Each level can be aligned or positioned such that the memory cells 105 can be substantially aligned with each other across each level, thereby forming a memory cell stack 145.

[0030] Each row of memory cells 105 is connected to access lines 110 and 115. Access lines 110 may also be referred to as word lines 110 and digital lines 115, respectively. Digital lines 115 may also be referred to as digital lines 115. References to word lines and digital lines, or the like, are interchangeable without loss of understanding or operation. Word lines 110 and digital lines 115 may be substantially perpendicular to each other to create an array. Two memory cells 105 in the memory cell stack 145 may share a common conductive line, such as digital line 115. That is, digital line 115 may be electrically connected to the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. Other configurations are possible; for example, memory cells 105 may be asymmetrical in shape, such as referenced in [reference needed]. Figure 3 The memory cell 105-c.

[0031] Generally, a memory cell 105 may be located at the intersection of two conductive lines (e.g., word line 110 and digital line 115). This intersection may be referred to as the address of the memory cell. A target memory cell 105 (i.e., a selected memory cell) may be the memory cell 105 located at the intersection of an energized word line 110 and a digital line 115; that is, the word line 110 and digital line 115 may be energized to read or write to the memory cell 105 at their intersection. Other memory cells 105 electrically connected to the same word line 110 or digital line 115 (e.g., connected to the same word line 110 or digital line 115) may be referred to as non-target memory cells 105. In some memory blocks, due to possible interference on other non-target memory cells 105 of the memory block 100, only a single memory cell 105 may be targeted during an access operation. In this disclosure, systems and techniques for targeting two or more memory cells of a memory block 100 during the duration of a single access operation are discussed.

[0032] As discussed above, electrodes may be coupled to memory cell 105 and word line 110 or digital line 115. The term electrode may refer to an electrical conductor and, in some cases, may serve as an electrical contact with memory cell 105. Electrodes may include traces, leads, conductive lines, conductive layers, etc., that provide conductive paths between elements or components of memory block 100.

[0033] Memory cell 105 can be operated on, for example, by activating or selecting word line 110 and digital line 115. This may involve applying voltage or current to the respective lines (e.g., a read pulse). Word line 110 and digital line 115 may be made of conductive materials, such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti), etc.), metal alloys, carbon, conductive doped semiconductors, or other conductive materials, alloys, or compounds. After selecting memory cell 105, the logic state of the cell may be set using, for example, the migration of selenium (Se) ions. Alternatively or alternatively, ions of other conductive materials may migrate in addition to or in place of selenium (Se) ions.

[0034] For example, a memory cell 105, which may contain a selenium-containing memory storage element, can be programmed by providing an electrical pulse (e.g., a programming pulse) to it. The programming pulse can be provided, for example, via a first access line (e.g., word line 110) or a second access line (e.g., digital line 115). After the programming pulse is provided, ions can migrate within the memory storage element, depending on the polarity of the programming pulse and / or the current state of the memory cell 105. Therefore, the concentration of ions and / or selenium relative to a first or second side of the memory storage element can be based at least in part on the polarity and / or magnitude of the voltages applied to the memory storage element by the first and second access lines. In some cases, the memory storage element may have an asymmetrical shape. This asymmetrical shape can cause ions to accumulate more in one portion of the memory storage element than in another portion.

[0035] To read the cell, a voltage (e.g., a read pulse) can be applied across memory cell 105, and the resulting current or a threshold voltage under which current begins to flow can represent a logic '1' or logic '0' state. The accumulation of selenium ions at one or the other end of the memory storage element can affect resistivity and / or threshold voltage, resulting in a greater difference in cell response between logic states.

[0036] Access to memory cell 105 can be controlled via row decoder 120 and column decoder 130. For example, row decoder 120 can receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, column decoder 130 receives a column address from memory controller 140 and activates the appropriate digital line 115. Thus, memory cell 105 can be accessed by activating word line 110 and digital line 115.

[0037] Following access, sensing component 125 can read or sense memory cell 105. For example, sensing component 125 can be configured to determine the stored logic state of memory cell 105 based on a signal generated by accessing memory cell 105. The signal may include voltage or current, and sensing component 125 may include a voltage-sensing amplifier, a current-sensing amplifier, or both. For example, a voltage may be applied to memory cell 105 (using corresponding word lines 110 and digital lines 115), and the magnitude of the resulting current may depend on the resistance of memory cell 105. Similarly, a current may be applied to memory cell 105, and the magnitude of the voltage used to generate the current may depend on the resistance of memory cell 105. Sensing component 125 may include various transistors or amplifiers to detect and amplify the signal; this may be referred to as latching. The detected logic state of memory cell 105 can then be output as input / output 135. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, the sensing component 125 may be connected to or electrically communicated with the column decoder 130 or the row decoder 120.

[0038] Memory cell 105 can be programmed or written to by similarly activating the associated word line 110 and digital line 115—that is, logical values ​​can be stored in memory cell 105. Column decoder 130 or row decoder 120 can accept data, such as input / output 135, to be written to memory cell 105. In the case of auto-memory, memory cell 105 can be written to (or programmed) by passing current through the memory storage element. Depending on the logical state written to memory cell 105 (e.g., logic '1' or logic '0'), selenium ions may accumulate at or near a specific electrode in contact with the memory storage element. For example, based on the polarity of memory cell 105, ion accumulation at or near a first electrode may result in a first threshold voltage representing a logic '1' state, and ion accumulation at or near a second electrode may result in a second threshold voltage representing a logic '0' state, different from the first threshold voltage. The difference between the first and second threshold voltages may be more pronounced in asymmetric memory storage elements, including references. Figure 3 The memory storage elements described.

[0039] In some memory architectures, accessing memory cell 105 may degrade or corrupt the stored logical state and may perform a rewrite or refresh operation to return the original logical state to memory cell 105. For example, in DRAM, logic storage capacitors may partially or completely discharge during a sensing operation, thereby corrupting the stored logical state. Therefore, the logical state may be rewritten after the sensing operation. Additionally, activating a single word line 110 may cause all memory cells in the row to discharge; therefore, it may be necessary to rewrite all memory cells 105 in the row. However, in non-volatile memory such as PCM and / or auto-select memory, accessing memory cell 105 may not corrupt the logical state, and therefore, memory cell 105 may not need to be rewritten after access.

[0040] Some memory architectures, including DRAM, may lose their stored state over time unless periodically refreshed by an external power source. For example, charged capacitors may discharge over time through leakage current, leading to the loss of stored information. These so-called volatile memory devices can have relatively high refresh rates, such as tens of refresh operations per second for DRAM, which can result in significant power consumption. As memory arrays become larger, the increased power consumption can inhibit the deployment or operation of memory arrays (e.g., power supply, heat generation, material limitations, etc.), especially for mobile devices that rely on limited power sources (e.g., batteries). As discussed below, non-volatile PCM and / or self-select memory cells can have beneficial properties that lead to improved performance relative to other memory architectures. For example, PCM and / or self-select memories can provide read / write speeds comparable to DRAM, but can be non-volatile and allow for increased cell density.

[0041] The memory controller 140 can control the operation (read, write, rewrite, refresh, discharge, etc.) of memory cells 105 through various components (e.g., row decoder 120, column decoder 130, and sensing component 125). In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 can generate row and column address signals to activate the desired word line 110 and digital line 115. The memory controller 140 can also generate and control various voltages or currents used during the operation of the memory block 100. For example, it can apply a discharge voltage to the word line 110 or digital line 115 after accessing one or more memory cells 105.

[0042] Generally, the amplitude, shape, polarity, or duration of the applied voltage or current discussed herein may be adjusted or altered and may differ for the various operations discussed when operating memory block 100. Furthermore, one, more, or all memory cells 105 within memory block 100 may be accessed simultaneously; for example, more or all cells of memory block 100 may be accessed simultaneously during a reset operation in which all memory cells 105 or groups of memory cells 105 are set to a single logic state.

[0043] Figure 2 This description illustrates an example memory array 200, which supports systems and techniques for concurrently accessing multiple memory cells according to various embodiments of this disclosure. Memory array 200 may be used as a reference. Figure 1 An example of the described memory block 100.

[0044] The memory array 200 may include multiple memory cells 105-a, 105-b, multiple word lines 110-a, 110-b, and multiple digital lines 115-a, 115-b, etc., which can be used as a reference. Figure 1 Examples of the described memory cell 105, word line 110, and digital line 115. Memory cell 105-a may include a top electrode 210, a bottom electrode 215, and a memory storage element 205, which may be referred to as a chalcogenide memory assembly. In some cases, memory cell 105-a may be an example of a self-selecting memory cell.

[0045] The architecture of memory array 200 can be called a cross-point architecture. It can also be called a pillar structure. For example, as... Figure 2 As shown, the pillar can contact a first conductive line (e.g., an access line of word line 110-a) and a second conductive line (e.g., an access line of digital line 115-a). The pillar may include a memory cell 105-a, wherein the memory cell 105-a includes a first electrode (e.g., a top electrode 210), a memory storage element 205, and a second electrode (e.g., a bottom electrode 215). The memory storage element 205 may be asymmetrical in shape. Depending on the polarity of the memory cell 105-a, this asymmetrical shape may cause ion accumulation at the top electrode 210 or the bottom electrode 215. Ion accumulation at the top electrode 210 or the bottom electrode 215 may allow for more accurate sensing of the memory cell 105-a, as described above.

[0046] Compared to other memory architectures, Figure 2 The cross-point or pillar architecture described herein can provide relatively high-density data storage at a lower production cost. For example, compared to other architectures, the cross-point architecture can have memory cells with a reduced area and therefore increased memory cell density. For example, compared to architectures with 6F... 2Compared to other architectures with different memory cell areas (such as those with three-terminal selection), this architecture can have 4F. 2 The memory cell area, where F is the minimum feature size. For example, DRAM can use transistors (which are three-terminal devices) as the optional component for each memory cell and can have a larger memory cell area compared to a strut architecture.

[0047] In some cases, the memory storage element 205 may be connected in series between the first conductive line and the second conductive line, for example, between word line 110-a and digital line 115-a. The memory storage element 205 may be located between the top electrode 210 and the bottom electrode 215; therefore, the memory storage element 205 may be positioned in series between digital line 115-a and word line 110-a. Other configurations are possible.

[0048] Memory storage element 205 may comprise a chalcogenide material, which may be referred to as a chalcogenide memory assembly. The chalcogenide memory assembly may be configured to use a non-uniform distribution of ions to indicate the logic state stored in memory cell 105-a. The threshold voltage of the chalcogenide memory assembly may vary based on the polarity of the pulse used to program memory cell 105-a. For example, a self-selected memory cell programmed with a first polarity pulse (e.g., positive polarity) may have certain resistance and / or electrical properties and therefore a first threshold voltage, while a self-selected memory cell programmed with a second polarity pulse (e.g., negative polarity) may have different resistance and / or electrical properties and therefore a second threshold voltage. These electrical characteristics of the chalcogenide material may be caused by differences in ion migration based on the characteristics of the programming pulse (including the polarity, magnitude, and / or shape of the programming pulse).

[0049] For example, depending on the polarity of the programming pulse applied to a given memory cell, ions can migrate toward a specific electrode. The logic state stored in the memory cell can be based on the distribution of ions in the chalcogenide memory assembly.

[0050] Unit programming can utilize the structural structure or atomic configuration of a chalcogenide memory component to achieve different logical states. For example, materials with crystalline or amorphous atomic configurations can exhibit different electrical properties based on differences in the programming pulses applied to the material. A chalcogenide memory component can have at least two states.

[0051] In some cases, the chalcogenide memory assembly can be in a set state and a reset state. The set state may exhibit low resistance and may be referred to as a crystalline state in some cases. The reset state may exhibit high resistance and may be referred to as an amorphous state. Therefore, a voltage (e.g., a programming pulse) applied to the memory cell 105-a may cause the memory storage element 205 to enter or maintain a certain state (e.g., a set state or a reset state). The magnitude and polarity of the applied voltage (e.g., a programming pulse) may affect the distribution of ions and thus may affect the logic state stored in the memory cell 105-a containing the memory storage element 205 formed using a chalcogenide material.

[0052] Each state of memory storage element 205 may have an associated threshold voltage—that is, current flows after the threshold voltage is exceeded. Therefore, if the applied voltage is less than the threshold voltage, current cannot flow through memory storage element 205. In some cases, one of the states of memory storage element 205 may not have a threshold voltage (i.e., the threshold voltage is zero), and therefore current may flow in response to the applied voltage. In some cases, memory storage element 205 may have two or more states that could result in multiple different resistances and multiple threshold voltages. In such cases, memory cell 105-a may be configured to have three or more states and may be configured to store more than one bit of digital logic data.

[0053] In some cases, the memory storage element 205 may be configured in an asymmetrical shape to facilitate ion accumulation at or near the top electrode 210 or the bottom electrode 215. For example, the memory storage element 205 may be in the shape of a trapezoidal prism and the cross-section of the memory storage element 205 may include a trapezoid. Alternatively, the memory storage element 205 may be a frustum. As used herein, a frustum includes a shape or similar to a portion of a cone or pyramid with the upper portion removed, or a shape or similar to a portion of a cone or pyramid that cuts off below the top between a first plane of the cone or pyramid and a second plane at or above the bottom. The memory storage element 205 may be arranged in series between the first access line 110-a and the second access line 115-a. The memory storage element 205 may comprise a first chalcogenide glass including selenium. In some examples, the memory storage element 205 comprises a composition of at least one of selenium, arsenic (As), tellurium (Te), silicon (Si), germanium (Ge), or antimony (Sb). When a voltage is applied across memory storage element 205, or when a voltage difference exists between the top electrode 210 and the bottom electrode 215, ions can migrate toward one or the other electrode. For example, Te and Se ions can migrate toward the positive electrode, and Ge and As ions can migrate toward the negative electrode. Memory storage element 205 can also be used as a selector device. This type of memory architecture is an example of self-selecting memory technology.

[0054] Figure 3 This illustration shows examples of a system and technique for concurrent access to multiple memory cells, according to various embodiments of this disclosure. Block 300 may illustrate the effect of programming pulses and read pulses of different polarities on a memory cell 105-e comprising a chalcogenide material. The memory cell 105-e may include a memory storage element 205-a, a top electrode 210-a, and a bottom electrode 215-a. The memory cell 105-e may be coupled to word lines 110-e and digital lines 115-e.

[0055] Figure 300-a illustrates the effect of programming pulses with different polarities on memory cell 105-e. If a first programming pulse 305 with positive polarity (e.g., a total voltage across memory cell 105-e greater than zero) is applied to memory cell 105-e, ions in memory storage element 205-a may accumulate near the interface between memory storage element 205-a and top electrode 210-a. The first programming pulse 305 can generate a non-uniform distribution of elements (e.g., ions or selenium or selenium ions) in memory storage element 205-a, with element enrichment near top electrode 210-a. To generate the first programming pulse 305 with positive polarity, a first voltage can be applied to digital line 115-e, and a second voltage less than the first voltage can be applied to word line 110-e.

[0056] If a negative programming pulse 310 (e.g., a total voltage across memory cell 105-e less than zero) is applied to memory cell 105-e, ions in memory storage element 205-a may accumulate near the interface between memory storage element 205-a and bottom electrode 215-a. The second programming pulse 310 can generate a non-uniform distribution of elements (e.g., ions or selenium or selenium ions) in memory storage element 205-a, with element enrichment near the bottom electrode 215-a. To generate the negative programming pulse 310, a first voltage can be applied to word line 110-e, and a second voltage less than the first voltage can be applied to digital line 115-e.

[0057] Figure 300-b illustrates the effect of read pulses with different polarities on memory cell 105-e. When reading memory cell 105-e, the logic state identified by the memory controller as stored in memory cell 105-e can be based on the distribution of elements in memory storage element 205-a and the polarity of the read pulse applied during the read operation.

[0058] For example, as part of a read operation, the memory controller may apply a first read pulse 315 with positive polarity (e.g., the total voltage across memory cell 105-e is greater than zero) to memory cell 105-e. The logic state identified by the memory controller as stored in memory cell 105-e may be based on the distribution of ions in the memory cell. If memory cell 105-e is programmed with a positive polarity programming pulse (e.g., first programming pulse 305), the memory controller may determine that logic '1' has been stored in memory cell 105-e. However, if memory cell 105-e is programmed with a negative polarity programming pulse (e.g., second programming pulse 310), the memory controller may determine that logic '0' has been stored in memory cell 105-e.

[0059] This phenomenon may occur due to the distribution of ions in the memory storage element 205-a and the manner in which they interact with the applied pulse. If a positive voltage of the read pulse is applied to the electrode closest to the ion-rich region (e.g., top electrode 210 or bottom electrode 215), the memory controller can detect a large amount of charge or high resistivity. The memory controller can recognize a large amount of charge as logic '1'. If a positive voltage of the read pulse is applied to the electrode furthest from the ion-rich region (e.g., top electrode 210 or bottom electrode 215), the memory controller can detect a small amount of charge or low resistivity. The memory controller can recognize a small amount of charge as logic state '0'.

[0060] The same principle applies when a second read pulse 320 with negative polarity (e.g., the total voltage across memory cell 105-e is less than zero) is applied to memory cell 105-e as part of a read operation. The logic state identified by the memory controller as stored in memory cell 105-e can be based on the distribution of ions in the memory cell. If memory cell 105-e is programmed with a positive polarity programming pulse (e.g., a first programming pulse 305), the memory controller can determine that logic '0' has been stored in memory cell 105-e. However, if memory cell 105-e is programmed with a negative polarity programming pulse (e.g., a second programming pulse 310), the memory controller can determine that logic '1' has been stored in memory cell 105-e.

[0061] In some cases, the memory controller can be configured to invert data before outputting it to the host device. To correctly identify the logical state stored in the auto-memory cell, the memory controller may need to know the distribution of ions in the memory storage element. One way to identify the distribution of ions is to know the polarity of the programming pulse used to program the auto-memory cell. In some examples, the memory controller can identify the polarity of both the programming pulse used to program the auto-memory cell and the read pulse used to read the auto-memory cell. The memory controller can identify the logical state stored in the auto-memory cell based on both the polarity of the programming pulse and the polarity of the read pulse. In some examples, the polarity of the pulse applied to a specific memory cell of a memory block can be configured statically or semi-statically. If the polarity of the pulse applied to a specific memory cell is configured dynamically, the memory controller can perform additional operations to identify the polarity.

[0062] The memory controller can be configured to concurrently access memory cells on the same memory block simultaneously using the ability to access select memory cells using pulses of multiple polarities. During the duration of a single access operation, the voltage applied to the access line for each memory cell access can be configured such that the voltage applied to the unselected memory cells of the memory block does not exceed a programming threshold, a read threshold, or some other interference threshold for the unselected memory cells. In practice, voltages applied to different access lines during an access operation can be configured such that they negatively interfere with each of the unselected cells, but constructively interfere with each of the selected memory cells on the memory block.

[0063] Figure 4 This describes examples of memory block 400 that support systems and techniques for concurrent access to multiple memory units, according to various embodiments of this disclosure. Specifically, Figure 4 This describes using the same type of access operation to concurrently access two memory cells on memory block 400 during the same access operation duration. For example, any two memory cells in memory block 400 can be read concurrently or programmed concurrently.

[0064] Memory block 400 includes a plurality of memory cells 405, 410, a plurality of word lines 110-f, and a plurality of digital lines 115-f. Memory block 400 illustrates a mode in which a first selected memory cell 405-a can be accessed (e.g., read or written) using a first pulse having a first polarity, and a mode in which a second selected memory cell 405-b can be accessed (e.g., read or written) using a second pulse having a second polarity different from the first polarity, wherein the selected memory cells 405 are accessed (e.g., read or written) concurrently. Memory block 400 may also include a plurality of unselected memory cells 410. Memory cells 405, 410 may be referenced. Figures 1 to 3 An example of the described memory cell 105.

[0065] A memory controller (not shown) associated with memory block 400 can identify first selected memory cell 405-a and second selected memory cell 405-b for concurrent access using read or write operations during a single access operation duration. In many memory architectures, only a single memory cell can be accessed during a single access operation duration.

[0066] The memory controller can select the polarity of the pulses (e.g., two read pulses or two programming pulses) to be applied to selected memory cells 405. The specific polarity of the pulse for each selected memory cell can be selected based on a variety of factors, including the location of the selected memory cell 405, the distribution of ions in the selected memory cell 405, the characteristics of the programming pulses used to program the selected memory cells 405, 405-b (e.g., polarity and other characteristics), or combinations thereof. The memory controller can determine that pulses of different polarities will be used to access (e.g., read or write) each selected memory cell 405, 405-b. For example, if a first selected memory cell 405-a is to be read with a positive polarity read pulse, then the memory controller can determine that a second selected memory cell 405-b will be read with a negative polarity read pulse. In another example, if a first selected memory cell 405-a is to be programmed with a positive polarity programming pulse, then the memory controller can determine that a second selected memory cell 405-b will be programmed with a negative polarity programming pulse.

[0067] The memory controller can control the biasing of word lines 110-f and digital lines 115-f to achieve pulses with selected polarity and magnitude. For example, a positive pulse may have a magnitude and polarity of +Va (e.g., +Vr for a read pulse or +Vp for a program pulse, where Vr and Vp are different) and a negative pulse may have a magnitude and polarity of -Va (e.g., –Vr for a read pulse or –Vp for a program pulse, where Vr and Vp are different). Va may represent the total voltage difference across the selected memory cell during an access operation (e.g., a read operation or a write operation). The memory controller can control the voltages on the respective word lines 110-f and digital lines 115-f such that the voltage difference across the selected memory cell is of the desired polarity and / or magnitude. In some cases, the memory controller may hold one of the access lines of the first selected memory cell 405 at zero volts and bias the other access line to the full value of Va. This operation will cause the selected memory cell 405 to be accessed (e.g., read or write), but it may also interfere with the unselected memory cell 410 coupled to the access line biased to Va. The unselected memory cell 410 may be interfered with when the voltage difference across the memory cell exceeds a programming threshold, a read threshold, or some other interference threshold associated with the unselected memory cell 410.

[0068] The memory controller can divide a pulse (e.g., Va) into a first voltage (e.g., +Va / 2) applied to a first access line and a second voltage (e.g., -Va / 2) applied to a second access line. The combination of the first and second voltages will result in a full voltage difference of Va being applied to the selected memory cell 405. The memory controller can identify the magnitude, polarity, shape, or combination thereof of the first and second voltages to achieve the full voltage difference across the selected memory cell 405.

[0069] The memory controller can determine the polarity of each voltage based on the polarity of the pulse applied to the selected memory cell 405. For example, if the pulse (e.g., a read pulse or a programming pulse) is a positive polarity pulse, then the memory controller can apply a positive polarity voltage of +Va / 2 to the digital line 115-f of the selected memory cell 405 and a negative polarity voltage of -Va / 2 to the word line 110-f of the selected memory cell 405.

[0070] In some cases, the memory controller may divide the pulse (Va) magnitude equally between the two access lines (e.g., 50%-50% division, where Va / 2 is applied to both access lines). In other cases, the memory controller may divide the pulse unequally between the two access lines (e.g., 51%-49% division, 60%-40% division, 66%-33% division, 75%-25% division). The percentage divisions shown herein are for illustrative purposes only and are not limited to this disclosure.

[0071] Dividing the pulse into a first voltage and a second voltage reduces the likelihood that the voltage difference across the unselected memory cell 410 exceeds the programming threshold, read threshold, or some other interference threshold of the unselected memory cell 410. In this way, the memory controller can reduce the likelihood that the unselected memory cell 410 in memory block 400 is interfered with. For example, memory block 400 illustrates how the voltage difference across each memory cell 405, 410 can be seen based on biasing some access lines to access the selected memory cell 405 (e.g., read or write).

[0072] As shown in memory block 400, the voltages applied to the access lines can be configured to mutually reinforce each other at selected memory cells 405. Thus, the first selected memory cell 405-a experiences a positive polarity pulse during the access operation duration, and the second selected memory cell 405-b experiences a negative polarity pulse during the access operation. The voltages applied to the access lines are configured to cooperate to concurrently access the first selected memory cell 405-a and the second selected memory cell 405-b.

[0073] As shown in memory block 400, the voltages applied to the access lines can also be configured to interfere with each other cancelingly at some unselected memory cells 410. For example, some unselected memory cells 410 may see a zero-volt voltage difference, even if the access line of that unselected memory cell is biased to a certain value for an access operation (e.g., a read operation or a write operation). By configuring the voltages (e.g., the first voltage and the second voltage) in such a way that they interfere with each other constructively and / or cancelingly, the likelihood of unselected memory cells 410 sharing access lines with selected memory cells 405 being interfered with by access operations is reduced.

[0074] The voltage applied to the access line can also be configured such that if no constructive or destructive interference occurs in the memory block, the voltage difference seen across the unselected memory cell 410 will not meet an interference threshold (e.g., a programming threshold or a read threshold).

[0075] In some cases, if pulses of the same polarity are used to access two selected memory cells 405 of memory block 400, some unselected memory cells 410 may also be accessed unintentionally. For example, if a positive pulse is used to access both the first selected memory cell 405-a and the second selected memory cell 405-b, unselected memory cells 410-a and 410-b may also be accessed unintentionally. In such cases, the voltage applied to the access lines may mutually reinforce each other at four memory cells instead of the two selected memory cells.

[0076] In some cases, selected memory cells 405 configured for concurrent access cannot share a common access line. This means that the first selected memory cell 405-a cannot be coupled to the same digital line 115-f or word line 110-f as the second selected memory cell 405-b. This condition may increase the likelihood that one or more unselected memory cells 410 will be interfered with during access operations.

[0077] The memory controller may be configured to identify a selected memory cell 405 for concurrent access operations based at least in part on the location of the memory cell, the access line of the selected memory cell 405, or whether the selected memory cell 405 shares an access line. In some cases, the memory controller may be configured to determine whether the memory cell shares a common access line after the selected memory cell 405 has been selected. If the memory controller determines that the selected memory cell 405 shares a common access line, then the memory controller may cancel the access operation to one of the selected memory cells 405. In such cases, the access operation performed during the duration of a single access operation can be used to access only a single memory cell.

[0078] In some cases, any combination of memory cells can be accessed concurrently. In such cases, the memory controller can be configured to dynamically select the memory cells to be accessed during the duration of a single access operation based on commands received from the host device. To reduce the latency for executing read or write commands received from the host device, the memory device can concurrently access two or more memory cells 405 in the same memory block 400. In some cases, this concurrent access can reduce the total time spent by the memory device executing the read or write command to the host device after receiving the command.

[0079] The principles described regarding concurrent access to two memory cells of memory block 400 using the same type of access operations (e.g., two read operations or two write operations) are also more generally applicable to any combination of access operations. For example, the memory controller can be configured to use, as... Figure 4 A similar principle to that described in the text is used to concurrently write to the first memory cell and read from the second memory cell on the same tile.

[0080] Figure 5This describes an example of a block 500 in a memory block that shows an access pulse at an unselected memory cell in a system and technology supporting concurrent access to multiple memory cells, according to various embodiments of this disclosure. In some situations, the memory controller may want to use two access pulses that would interfere with the unselected memory cell to access two memory cells in the memory block. To prevent interference with the unselected memory cell while still accessing two selected memory cells during the duration of a single access operation, the memory controller may delay one of the access pulses.

[0081] The features of tile 500 can be found in the reference. Figure 4 The memory is implemented in the described memory block 400. The access pulses described with reference to block 500 can be instances of two read pulses or two program pulses.

[0082] Block 500-a illustrates voltages 505-a and 510-a as seen by an unselected memory cell (e.g., unselected memory cell 410 of memory block 400) during an access operation. In block 500-a, voltages 505-a and 510-a may interfere with each other in a “canceling” manner to prevent interference to the unselected memory cell. For example, a first voltage 505-a may have a first polarity and a first magnitude (e.g., +Va / 2), and voltage 510 may have the same polarity and, in some cases, the same magnitude (e.g., +Va / 2). The combination of these two voltages 505-a and 510-a may result in a voltage difference 515 that fails to meet an interference threshold (e.g., a programming threshold, a read threshold, or some other threshold) for the unselected memory cell. In some cases, the magnitudes and / or polarities of the two voltages 505-a and 510-a may differ, but the resulting voltage difference may still fail to meet the interference threshold.

[0083] Block 500-b illustrates voltages 505-b and 510-b as seen by an unselected memory cell of a memory block (e.g., unselected memory cell 410 of memory block 400) during an access operation. In block 500-b, voltages 505-b and 510-b may mutually interfere with each other so that the unselected memory cell is disturbed during an access operation (e.g., a read operation or a write operation). For example, a first voltage 505-b may have a first polarity and a first magnitude (e.g., +Va / 2), and voltage 510-b may have a different polarity and, in some cases, the same magnitude (e.g., -Va / 2). The combination of these two voltages 505-b and 510-b may result in a voltage difference 520 that satisfies an interference threshold (e.g., a programming threshold, a read threshold, or some other threshold) for the unselected memory cell. In some cases, the magnitudes and / or polarities of the two voltages 505 and 510 may be different, but the resulting voltage difference may still satisfy the interference threshold.

[0084] The memory controller can identify when two access pulses (e.g., read-read, program-program, or program-read pulses) for two selected memory cells in a memory block might interfere with one or more unselected memory cells. The memory controller can use various methods to identify this situation. In some cases, the memory controller can compare the voltage of the access pulses with a predefined list of prohibited voltage combinations. In some cases, the memory controller can compare the memory cell location, the magnitude of the access pulses, and / or the polarity with a predefined list of prohibited combinations. In some cases, the memory controller can dynamically determine the interaction of each memory cell to identify whether unselected memory cells might be interfered with.

[0085] The memory controller can be configured to delay one of the access pulses of a selected memory cell in a memory block based on the likelihood that the unselected memory cell may be interfered with. Block 500-c illustrates an example in which the memory controller delays the second voltage 510-c so that it occurs at a certain time after the first voltage 505-c. Block 500-d illustrates an example in which the memory controller delays the first voltage 505-d so that it occurs at a certain time after the second voltage 510-d. By staggering the access pulses in this way, the memory controller can be configured to prevent the voltage difference 520 seen across the unselected memory cell from meeting an interference threshold.

[0086] In some cases, the delayed pulse may occur after the initial pulse has fully completed. In some cases, the initial pulse and the delayed pulse may at least partially overlap. The memory controller may select which pulse is delayed based on the memory cell location, the pulse polarity, the pulse magnitude, the pulse shape, or a combination thereof. For example, based on its corresponding magnitude and / or shape, the first type of pulse overlap is less likely to cause interference to unselected memory cells compared to the second type of pulse overlap.

[0087] In some cases, programming operations may be accompanied by prefetching operations. In such cases, if two units are programmed concurrently, only a portion of the programming and prefetching operations may be delayed. For example, the prefetching operation may occur immediately, but one of the programming pulses may be delayed.

[0088] Figure 6 This describes examples of memory block 600 that support systems and techniques for concurrent access to multiple memory cells, according to various embodiments of this disclosure. Specifically, Figure 6This describes using different types of access operations (e.g., read and write operations) to concurrently access two memory cells on memory block 600 during the same access operation duration. For example, a first selected memory cell 605-a can be programmed during the access operation duration and a second selected memory cell 605-b can be read during the access operation duration, or vice versa.

[0089] Memory block 600 includes multiple memory cells 605, 610, multiple word lines 110-g, and multiple digital lines 115-g. Memory block 600 illustrates a method for programming a first selected memory cell 605-a using a programming pulse of a first polarity and a method for reading a second selected memory cell 605-b using a read pulse of a second polarity different from the first polarity, wherein the selected memory cells 605 are accessed concurrently. Memory block 600 illustrates the principle of concurrently using two different types of pulses. Memory block 600 may also include multiple unselected memory cells 610. Memory block 600 may be used as a reference. Figure 1 and 4 Examples of memory blocks 100 and 400 are described. Memory cells 605 and 610 may be used as references. Figures 1 to 4 Examples of the described memory cells 105, 405, and 410.

[0090] The memory controller (not shown) associated with memory block 600 may operate similarly to the memory controller used for memory block 400. For example, the memory controller may select the memory cell to be accessed (e.g., selected memory cell 605), select the characteristics (e.g., magnitude, polarity, or shape) of the pulse applied to the selected memory cell 605, determine the voltage to be applied to the access line based on the identified pulse, perform operations to ensure that the unselected memory cell 610 is not disturbed, perform other operations and functions, or combinations thereof.

[0091] When different access operations are performed on the same memory block during the same access duration, differences between different types of pulses may cause interference to the unselected memory cell 610. For example, a programming pulse may have one or more characteristics that differ from those of a read pulse. In some cases, the magnitude of the programming pulse may be greater than that of the read pulse. Furthermore, differences in the shapes of the programming and read pulses may increase the likelihood of interference to the unselected memory cell 610 during at least a portion of the access operation duration, wherein both write and read operations are performed on different memory cells of the same memory block 600.

[0092] The memory controller can be configured to select pulse characteristics and divide the pulses in a certain way into voltages for the access lines to reduce the possibility of interference with unselected memory cell 610. Figures 700 and 800 illustrate the problems and solutions regarding the interaction between programming pulses and read pulses in memory blocks.

[0093] Figure 7 This description illustrates examples of block 700, according to various embodiments of the present disclosure, showing access pulses seen at unselected memory cells in a memory block within a memory block supporting systems and techniques for concurrent access to multiple memory cells. In some cases, the memory controller may want to concurrently access a first memory cell of the same memory block as a second memory cell of the memory block. In some cases, performing two operations concurrently may interfere with unselected memory cells in the memory block. To prevent interference with unselected memory cells during the duration of a single access operation while still accessing two selected memory cells, the memory controller may perform various mitigation operations.

[0094] The features of tile 700 can be found in the reference. Figure 6 The memory is implemented in the described memory block 600. The access pulses described with reference to block 700 can be examples of read pulses and program pulses.

[0095] Block 700 illustrates multiple voltages 705, 710 applied to access lines during multiple access operation durations 715, as seen by an unselected memory cell (e.g., unselected memory cell 610). Voltages 705, 710 may be portions of programming and read pulses. For example, during a first access operation duration 715-a, a first programming voltage 705-a may be applied to a first access line (e.g., word line 110-g or digital line 115-g) coupled to an unselected memory cell of the memory block, and a first read voltage 710-a may be applied to a second access line (e.g., word line 110-g or digital line 115-g) coupled to an unselected memory cell of the memory block. A first read voltage 710-a may be applied concurrently with the first programming voltage 705-a during the first access operation duration 715-a.

[0096] During the first access operation duration 715-a, the voltage difference 720 seen by the unselected memory cell may fail to meet the interference threshold (e.g., programming threshold, read threshold, or other threshold) of the unselected memory cell. In fact, the first programming voltage 705-a and the first read voltage 710-a can "cancel each other out" and prevent the unselected memory cell from being disturbed.

[0097] In the comparative example, during the third access operation duration 715-c, the voltage difference 725 seen by the unselected memory cell satisfies an interference threshold (e.g., a programming threshold, a read threshold, or other threshold) for the unselected memory cell. The third programming voltage 705-c may have a first polarity and a first magnitude, which cooperates with the second polarity (different from the first polarity) and a second magnitude of the third read voltage 710-c to produce a voltage difference 725 that satisfies the interference threshold. In effect, the third programming voltage 705-c and the third read voltage 710-c can mutually "complementarily" interfere with each other, causing the unselected memory cell to be disturbed.

[0098] The memory controller may perform one or more mitigation operations to prevent interference to unselected memory cells in scenarios such as those described in the third access operation duration 715-c. In some cases, during the access operation duration in which unselected memory cells may be interfered with, the memory controller may cancel a programming or read operation. In some cases, the memory controller may divide the programming pulse into several voltages, which will reduce the likelihood of interference to unselected memory cells or prevent interference to unselected memory cells. Because the programming pulse and the read pulse may have different magnitudes and / or shapes, the memory controller may divide the magnitudes of these two pulses in this way to mitigate the risk of interference to unselected memory cells. In some cases, the memory controller may delay the reference... Figure 5 The voltage described is one of the voltages similar to the voltage described above.

[0099] In some cases, the memory controller may divide the pulses into unequal segments (e.g., not 50 / 50). In some cases, each pulse and / or voltage may have a specific shape. For example, the third programming voltage 705-c may have a stepped or ramp shape, and the third read voltage 710-c may have a stepped or ramp shape. In such examples, the memory controller may cause ramp or step overlap so that the voltage difference seen at unselected memory cells does not meet the interference threshold. For example, during the third access operation duration 715-c, the third programming voltage 705-c may be an increasing ramp shape, and the third read voltage 710-c may be a decreasing ramp shape.

[0100] In some cases, the memory controller may select the polarity of the programming pulse, the read pulse, and / or the polarity of the divided voltage generated by those pulses to mitigate interference to unselected memory cells. In some cases, the memory controller may cause the two voltages applied to the unselected memory cell to have different polarities (e.g., one negative and one positive).

[0101] Figure 8This illustration describes an example of block 800, according to various embodiments of the present disclosure, showing access pulses seen at unselected memory cells in a memory block within a system and technology supporting concurrent access to multiple memory cells. The illustration demonstrates a process by which a memory controller mitigates interference to unselected memory cells when programming a first selected memory cell is performed concurrently with reading a second selected memory cell on the same memory block. Features of block 800 can be found in reference to... Figure 6 The memory is implemented in the described memory block 600. The access pulses described with reference to block 800 can be examples of read pulses and program pulses.

[0102] The diagram illustrates an example where a memory controller selects the polarity of the read pulse (and, more broadly, the read voltage) applied to the access lines of a memory block based on the polarity of the programming pulse. By selecting the polarity of the read pulse based on the polarity of the programming pulse, the memory controller can mitigate the possibility of interference from unselected memory cells in the memory block. In some cases, the memory controller may select the polarity of the programming pulse based on the polarity of the read pulse.

[0103] The memory controller can identify the polarity of the programming pulse used for a selected memory cell. This identification can be based on the current state of the selected memory cell (e.g., the current ion distribution of the selected memory cell). The memory controller can then select the polarity of the read pulse to be opposite to the polarity of the programming pulse to minimize the possibility that unselected memory cells in the memory patch will be interfered with by simultaneous writes and reads to two memory cells on the memory patch.

[0104] For example, block 800 illustrates multiple voltages 805, 810 applied to access lines during multiple access operation durations 815, as seen by an unselected memory cell (e.g., unselected memory cell 610). Voltages 805, 810 may be portions of programming pulses and read pulses. During each access operation duration 815, the memory controller may identify the polarity of the programming voltage 805 applied to a first access line (e.g., word line 110-g or digital line 115-g) coupled to an unselected memory cell of the memory block. The memory controller may also select the polarity of the read voltage 810 based on the identified polarity of the programming pulse.

[0105] For example, the memory controller can recognize that the first programming voltage 805-a has a positive polarity during the first access operation duration 815-a. The memory controller can select the first read voltage 810-a to have a negative polarity based on the positive polarity of the programming pulse. In practice, the memory controller can switch the polarity of the read pulse based on the polarity of the programming pulse used to program new data on a selected memory cell. In some cases, the memory controller can be configured to switch the polarity of the programming pulse based on the polarity of the read pulse.

[0106] Figure 9 Examples of circuitry 900 supporting systems and techniques for concurrent access to multiple memory cells are described according to various embodiments of this disclosure. Circuitry 900 describes components for dynamically modifying the polarity of programming pulses and / or read pulses during access operations.

[0107] Circuit 900 may include memory cell 905, word line 110-h, and digital line 115-h. Positive voltage source 910 and negative voltage source 915 may be selectively coupled to the access lines (e.g., word line 110-h or digital line 115-h). Switching component 920 may be configured to selectively couple one or more of the various voltage sources 910, 915 to the corresponding access lines. Memory cell 905 may be a reference. Figures 1 to 8 Examples of the described memory cells 105, 405, and 605.

[0108] Voltage sources 910 and 915 can be configured to bias their respective access lines to voltage values ​​associated with the voltage source. In some cases, each voltage source 910 and 915 is configured to output multiple voltage values. For example, a positive voltage source 910 can be configured to output a first voltage value associated with a programming pulse, a second voltage value associated with a read pulse, and / or multiple voltage values ​​associated with pulses of different shapes. In some cases, each voltage source 910 and 915 is configured to output a single voltage value and a single polarity. In such cases, a switching component 920 can be used to selectively couple access lines (e.g., word line 110-h and digital line 115-h) to two or more voltage sources 910 and 915.

[0109] For example, word line 110-h can be configured to couple to a positive voltage source for programming pulses, a positive voltage source for reading pulses, a negative voltage source for programming pulses, a negative voltage source for reading pulses, or a combination thereof. In some cases, a single voltage source can be configured to generate all pulses (e.g., magnitude, polarity, and shape) for accessing memory cell 905. In such cases, circuitry 900 may not include switching component 920. The memory controller can also be configured to isolate / decouple voltage sources 910, 915 from the access lines during access operations.

[0110] The switching component 920 may be one or more transistors positioned between voltage sources 910, 915 and their respective access lines. The memory controller may be configured to select various voltage sources 910, 915 by controlling the gate voltages of the transistors. In some cases, the switching component 920 may include a p-type transistor for one voltage source and an n-type transistor for another voltage source. In such cases, the gates of the transistors may be bonded together such that only one voltage source can be coupled to the access line at a time. In some cases, the two transistors may be of the same type, and their gates may be bonded together, but one of the gates may also include an inverter. In some cases, the switching component 920 may be configured to switch between different components. For example, the switching component 920 may couple an access line to a positive voltage source 910 or a negative voltage source 915.

[0111] Circuit 900 may further include a first sensing element 925 and a second sensing element 930 (sometimes referred to as a sensing amplifier) ​​selectively coupled to digital line 115-h using a switching element 935. The first sensing element 925 may be configured to sense the state of memory cell 905 when a positive polarity read pulse is used during an access operation. The second sensing element 930 may be configured to sense the state of memory cell 905 when a negative polarity read pulse is used during an access operation.

[0112] The memory controller can be configured to selectively couple digital line 115-h to one of the sensing components 925, 930 based on the polarity of the read pulse applied to memory cell 905. The memory controller can also be configured to isolate / decouple the digital line from one of the sensing components 925, 930 during access operations. In some cases, a single sensing component can be configured to sense using both positive and negative polarity read pulses. In such cases, circuit 900 may not include switching component 935. The sensing component may be a reference. Figure 1 An example of the described sensing component 125.

[0113] The switching component 935 may be one or more transistors positioned between the sensing components 925, 930 and their digital access lines 115-h. The memory controller may be configured to select various sensing components 925, 930 by controlling the gate voltage of the transistors.

[0114] In some cases, switching component 935 may include a p-type transistor for one sensing component and an n-type transistor for another sensing component. In such cases, the gates of the transistors may be tied together such that only one sensing component can be coupled to the access line at a time. In some cases, the two transistors may be of the same type, and their gates may be tied together, but one of the gates may also include an inverter. In some cases, switching component 935 may be configured to switch between different components. For example, switching component 935 may couple an access line to either sensing component 925 or 930.

[0115] In one embodiment, the memory device may include a memory cell 905, a digital line 115-h coupled to the memory cell 905, a first sensing component 925 coupled to the digital line 115-h, the first sensing component 925 being configured to identify a logical state stored on the memory cell based at least in part on a first read pulse having a first polarity, and a second sensing component 930 coupled to the digital line 115-h, the second sensing component 930 being configured to identify a logical state stored on the memory cell based at least in part on a second read pulse having a second polarity different from the first polarity.

[0116] In some examples of the memory device described above, a first voltage source 910 is coupled to a digital line 115-h, and the first voltage source 910 is configured to supply at least a portion of a first read pulse having a first polarity. In some examples of the device or system described above, a second voltage source 915 is coupled to a digital line 115-h, and the second voltage source 915 is configured to supply at least a portion of a second read pulse having a second polarity.

[0117] In some examples of the memory devices described above, the switching component 920 is configured to selectively couple digital line 115-h to a first voltage source 910 or a second voltage source 915 during access operations.

[0118] In some instances of the memory device described above, the switching component 935 is configured to selectively output a signal from either the first sensing component 925 or the second sensing component 930 during a read operation, based at least in part on the type of read pulse applied to the memory cell 905.

[0119] In some examples of the memory devices described above, memory cell 905 includes a chalcogenide material configured to indicate logic states using a non-uniform distribution of ions. In some examples of the memory devices described above, memory cell 905 may be a self-selected memory cell.

[0120] Figure 10This description illustrates examples of a memory block 1000 that supports systems and techniques for concurrently accessing multiple memory cells, according to various embodiments of this disclosure. The memory block 1000 may include half-blocks 1005 and 1010 configured statically or semi-statically. Half-blocks 1005 and 1010 can be used to implement techniques for concurrently accessing two memory cells of the memory block 1000. The memory block 1000 may be used as a reference. Figure 1 , 4 Examples of memory blocks 100, 400, and 600 described in section 6.

[0121] A memory block containing multiple selectable memory cells can be configured to concurrently access virtually any pair of memory cells. However, using various combinations of pulses to dynamically access memory cells can increase the processing load on the memory controller. To reduce the processing required to perform concurrent access operations on two memory cells within the same memory block, memory block 1000 may include a first half-block 1005 and a second half-block 1010.

[0122] The first half-block 1005 may include a plurality of memory cells 1015 configured to be read using a positive polarity read pulse. The second half-block 1010 may include a plurality of memory cells 1020 configured to be read using a negative polarity read pulse. The memory blocks may include a plurality of word lines 110-i and a plurality of digital lines 115-i. This configuration reduces the processing required to perform read operations because the same read pulse is used each time for a given half-block. In addition, this configuration reduces the number of components required to operate the memory block 1000 (e.g., the number of sensing components, switching components, voltage sources, or combinations thereof may be reduced).

[0123] The memory block 1000 can be divided into different half blocks in any way. In some cases, memory block 1000-a may contain half blocks grouped by word lines 110-i. The first half block 1005-a contains memory cells 1015-a electrically connected to the first group of word lines 110-i, and the second half block 1010-a contains memory cells 1020-a electrically connected to a second group of word lines 110-i, different from the first group. In some cases, memory block 1000-b may contain half blocks grouped by digital lines 115-i. The first half block 1005-b contains memory cells 1015-b electrically connected to the first group of digital lines 115-i, and the second half block 1010-b contains memory cells 1020-b electrically connected to a second group of digital lines 115-i, different from the first group.

[0124] Even though memory cells 1015 and 1020 of memory block 1000 are configured to be read by read pulses of a specific polarity, each memory cell 1015 and 1020 of the memory block can also be configured to be programmed by both positive and negative polarity programming pulses. This capability may be needed to change the distribution of ions in any given memory cell.

[0125] The access operation duration, including the read operation of the first memory cell and the read operation of the second memory cell, can be referenced as follows. Figure 4 and 5 It is performed as described. The memory controller can select memory cell 1015 in the first half-block 1005 and memory cell 1020 in the second half-block 1010 for reading during a single access operation duration. In a half-block configuration, due to the way the half-blocks are configured, it may be impossible to read two memory cells coupled to the same access line.

[0126] For example, in memory block 1000-a, word line 110-i for the first half-block 1005-a can be configured to have a negative polarity voltage during a read operation, and word line 110-i for the second half-block 1010-a can also be configured to have a negative polarity voltage during a read operation. To read a memory cell, the corresponding digital line 115-i for each half-block 1005-a, 1010-a can be biased to a voltage with the opposite polarity to its associated word line 110-i. Because it is impossible to bias a single digital line 115-i to both a positive and a negative polarity voltage at the same time, if two memory cells configured as half-blocks are read during the same access operation duration, they cannot share a common digital line 115-i or a common word line 110-i. In some cases, any two memory cells of memory block 1000 can be read concurrently, as long as the two memory cells do not share a common access line (common word line or common digital line).

[0127] In the half-block configuration of memory block 1000, the polarity of the read pulse is statically configured for each half-block. For example, a positive polarity read pulse can be used to read memory cell 1015 of the first half-block 1005 and a negative polarity read pulse can be used to read memory cell 1020 of the second half-block 1010, or vice versa. Due to this static configuration of the read pulses, the memory controller can be configured to select the polarity of the programming pulse based on which half-block the memory cell is in, the desired logic state of the memory cell, the current state of the memory cell, or the polarity of the read pulse to be used to read the memory cell, or a combination thereof.

[0128] For example, in a first half-block 1005 of memory cell 1015 where a positive polarity read pulse is used to read the memory cell 1015, if a positive polarity programming pulse is applied to the memory cell 1015, a first distribution of ions may appear on the memory cell 1015, which the positive polarity read pulse can interpret as logic '1'. Similarly, if a negative polarity programming pulse is applied to the memory cell 1015, a second distribution of ions different from the first distribution may appear on the memory cell 1015, which the positive polarity read pulse can interpret as logic '0'.

[0129] Conversely, in the second half-block 1010 where a negative polarity read pulse is used to read memory cell 1020, if a positive polarity programming pulse is applied to memory cell 1020, a first distribution of ions may appear on memory cell 1020, which the negative polarity read pulse can interpret as logic '0'. Similarly, if a negative polarity programming pulse is applied to memory cell 1020, a second distribution of ions may appear on memory cell 1020, which the negative polarity read pulse can interpret as logic '1'. In such cases, programming pulses of different polarities are used to write logic '1' to memory cells in different half-blocks. For example, a positive polarity programming pulse is used to store logic '1' on the first half-block 1005 and a negative polarity programming pulse is used to store logic '1' on the second half-block 1010. In some cases, the memory controller may be configured to invert the sensed logic state before outputting the sensed logic state. In such cases, programming pulses of the same polarity can be used to store logic '1' in both half-blocks.

[0130] In some cases, the memory controller may not apply a programming pulse during a write operation. For example, if a memory cell already stores a logic '1' and the write command indicates that the next desired logic state is logic '1', the memory controller may take no action during the write operation and instruct the desired value to be written to the memory cell.

[0131] In a half-block configuration of memory block 1000, various combinations of programming pulses, read pulses, bit transitions, or combinations thereof may interfere with unselected memory cells of memory block 1000. This may occur because the static configuration of read pulses reduces some flexibility in access operations. The memory controller may be configured to identify “prohibited” combinations of access operations that may occur concurrently in memory block 1000 with half-blocks 1005, 1010. Prohibited combinations of access operations may occur when unselected memory cells of memory block 1000 see a voltage difference that meets an interference threshold (e.g., a programming threshold or a read threshold).

[0132] Table 1 illustrates the voltage differences that may occur across unselected memory cells in memory block 1000 when two memory cells in memory block 1000 are programmed concurrently (e.g., programming a second memory cell 1020 in second half-block 1010 concurrently with programming a first memory cell 1015 in first half-block 1005). Table 1 indicates which programming bit transitions may cause unselected memory cells in memory block 1000 to see voltage differences that meet interference thresholds.

[0133] Table 1—Simultaneous Write Operations in Different Half-Patches

[0134]

[0135] In a half-block configuration, the memory controller can be configured to determine whether unselected memory cells in a memory block can be interfered with at the half-block level. This configuration can reduce processing for performing concurrent write operations and thereby reduce power consumption, processing time (e.g., latency), or a combination thereof. In some instances, the memory controller can identify bit transitions for each half-block during concurrent access operations and can determine whether unselected memory cells in a memory block will be interfered with based on the bit transitions. In such instances, the memory controller may not need to check for permissible combinations of write operations cell-by-cell, but rather can check half-block-by-block. In some cases, the memory controller can use a lookup table stored in memory to compare bit transitions.

[0136] After determining that one or more unselected memory cells may be disturbed by two concurrent write operations performed in the same memory block having half-blocks, the memory controller may perform one or more disturbance mitigation operations. For example, the memory controller may cancel one of the write operations and perform the write operation for a subsequent access operation duration other than the current duration. In some instances, the memory controller may delay one of the programming pulses within the same access operation duration. In some cases, the memory controller may modify the shape of one or more voltages applied to the memory cell during two concurrent write operations.

[0137] Table 2 illustrates the voltage differences that may occur across unselected memory cells in memory block 1000 when programming the first memory cell of memory block 1000 concurrently with reading the second memory cell of memory block 1000 (and programming the first memory cell 1015 of the first half-block 1005 concurrently with reading the second memory cell 1020 in the second half-block 1010). Table 2 indicates which programming pulse polarities, combined with the read pulse polarity, may cause unselected memory cells in memory block 1000 to see voltage differences that meet the interference threshold.

[0138] Table 2—Simultaneous Read-Write Operations in Different Half-Tile

[0139]

[0140] In Table 2, only positive polarity read pulses are shown for half-tile 1005 and only negative polarity read pulses are shown for half-tile 1010. This is because, by definition, only a single polarity read pulse is associated with each half-tile. In some cases, the polarity of the read pulses assigned to each half-tile may be reversed.

[0141] In a half-block configuration, the memory controller can be configured to determine whether unselected memory cells within the same memory block can be interfered with at the half-block level by concurrently performing read and write operations on memory block 1000. This half-block configuration can reduce the processing required to perform concurrent write and read operations, thereby reducing power consumption, processing time (e.g., latency), or a combination thereof. In some instances, the memory controller can identify the pulse polarity and / or bit transitions of each half-block during concurrent access operations and can determine whether unselected memory cells within the memory block will be interfered with based on the pulse polarity and / or bit transitions.

[0142] In such instances, the memory controller may not need to check each memory cell individually to determine if a combination of write and read operations is permissible; instead, it can check half-blocks at a time. In some cases, the memory controller can use a lookup table stored in memory to compare pulse polarities.

[0143] After determining that one or more unselected memory cells may be disturbed by two concurrent write operations performed in the same memory block with half-blocks, the memory controller may perform one or more disturbance mitigation operations. For example, the memory controller may cancel one of the access operations (read or write) and perform the access operation for the duration of a subsequent access operation, excluding the current duration. In some instances, the memory controller may delay one of the pulses (read pulse or program pulse) within the same access operation duration. In some cases, the memory controller may modify the shape of one or more voltages applied to the memory cell during two concurrent access operations.

[0144] In one embodiment, a memory device may include: a memory block 1000 having a first segment of memory cells (e.g., a first half-block 1005) and a second segment of memory cells (e.g., a second half-block 1010), wherein memory cells 1015 of the first segment are configured to be read in response to the application of a first read pulse having a first polarity and memory cells 1020 of the second segment are configured to be read in response to the application of a second read pulse having a second polarity different from the first polarity; a first sensing component (e.g., sensing component 1120 or 1155) coupled to the first segment of memory cells of the memory block 1000 and configured to identify the logical state of a memory cell of the first segment of the memory cells based at least in part on the first polarity of the first read pulse; and a second sensing component (e.g., sensing component 1120 or 1155) coupled to the second segment of memory cells of the memory block and configured to identify the logical state of a memory cell of the second segment of the memory cells based at least in part on the second read pulse having a second polarity.

[0145] In some examples of the memory device described above, a first voltage source (e.g., voltage source 910, 915) is coupled to a digital line 115 of a first portion, and the first voltage source (e.g., voltage source 910, 915) is configured to supply at least a portion of a first read pulse having a first polarity. In some examples of the device or system described above, a second voltage source (e.g., voltage source 910, 915) is coupled to a digital line of a second portion, and the second voltage source (e.g., voltage source 910, 915) is configured to supply at least a portion of a second read pulse having a second polarity.

[0146] In some examples of the memory devices described above, memory cells 1015, 1020 of memory block 1000 may be formed of a chalcogenide material configured to indicate logic states using a non-uniform distribution of ions. In some examples of the memory devices described above, one or more trimming parameters for a first portion of the memory cell may be independent of one or more trimming parameters for a second portion of the memory cell.

[0147] In some examples of the memory device described above, the first sensing component (e.g., sensing component 1120) and the second sensing component (e.g., sensing component 1120) may be positioned below an occupied area (e.g., occupied area 1170) of the memory block 1000. In some examples of the memory device described above, the memory block 1000 includes more than one layer of memory cells.

[0148] Figure 11Examples of a memory device 1100, which supports systems and techniques for concurrently accessing multiple memory cells according to various embodiments of this disclosure, are described. The memory device 1100 may comprise multiple memory blocks. Each memory block of the memory device may be divided into two or more half-blocks. The memory device 1100 describes components configured to concurrently perform access operations on at least two memory cells of a memory block.

[0149] The first memory device 1100-a may include a plurality of memory blocks 1105, each memory block 1105 being divided into a first half-block 1110 configured to be read by a positive polarity read pulse and a second memory block 1115 configured to be read by a negative polarity read pulse. Each memory block 1105 may include a sensing component 1120 coupled to each half-block 1110, 1115. The sensing component 1120 may be configured to identify the logic state of a memory cell based on the polarity of the read pulse associated with that half-block.

[0150] In memory block 1105, sensing component 1120 may be positioned outside the occupied area 1135 of the memory cell array. Memory block 1105 may include row decoder 1125 and column decoder 1130 configured to address memory cells of two half-blocks 1110, 1115. In memory block 1105, at least one or both of row decoder 1125 or column decoder 1130 may be positioned outside the occupied area 1135 of the memory cell array. In some cases, at least one or both of row decoder 1125 or column decoder 1130 may be positioned below and / or within the occupied area 1135 of the memory cell array.

[0151] The second memory device 1100-b may include a plurality of memory blocks 1140, each memory block 1140 being divided into a first half-block 1145 configured to be read by a positive polarity read pulse and a second memory block 1150 configured to be read by a negative polarity read pulse. Memory block 1140 may include a sensing component 1155 coupled to each half-block 1145, 1150. The sensing component 1155 may be configured to identify the logical state of a memory cell based on the polarity of the read pulse associated with that half-block. Within memory block 1140, the sensing component 1155 may be positioned within an occupied region 1170 of the memory cell array.

[0152] In this configuration, the sensing component 1155 may be positioned in a complementary metal-oxide-semiconductor (CMOS) array below the array. Memory block 1140 may include a row decoder 1160 and a column decoder 1165 configured to address memory cells of the two half-blocks 1145, 1150. In memory block 1140, at least one or both of the row decoder 1160 or column decoder 130 may be positioned below the memory cell array and / or within the occupied region 1170 of the memory cell array. In this configuration, at least one or both of the row decoder 1160 or column decoder 130 may be positioned in the CMOS array below the array. In some cases, at least one or both of the row decoder 1160 or column decoder 1165 may be positioned outside the occupied region 1170 of the memory cell array.

[0153] Memory blocks 1105 and 1140 of memory device 1100 may include components not shown. In some cases, memory blocks 1105 and 1140 may include one or more voltage sources and / or one or more switching components configured to selectively couple one or more voltage sources to their respective access lines. For example, memory blocks 1105 and 1140 may include references Figure 9 Some or all of the components described. In some cases where the sensing components are associated with the entire half-block, memory blocks 1105, 1140 may not contain switching components configured to selectively couple different sensing components to digital lines.

[0154] Figure 12 The flowchart illustrates a method 1200 for concurrently accessing multiple memory cells according to embodiments of the present disclosure. Operation of method 1200 may be implemented by a memory controller 140 or components thereof as described herein. In some instances, the memory controller 140 may execute a set of code to control functional elements of the memory device to perform the functions described below. Alternatively, the memory controller 140 may use dedicated hardware to perform portions of the functions described below.

[0155] At box 1205, memory controller 140 can identify the first memory cell of the memory block for reading. Operation of 1205 can be performed according to the method described herein.

[0156] At block 1210, memory controller 140 can identify a second memory cell of the memory block for reading. Operation of 1210 can be performed according to the method described herein.

[0157] At block 1215, memory controller 140 can select a first polarity of a first read pulse to read the first memory cell and select a second polarity of a second read pulse to read the second memory cell. The operation of 1215 can be performed according to the method described herein.

[0158] At block 1220, memory controller 140 may use the first read pulse to read the first memory cell. Operation of 1220 may be performed according to the method described herein.

[0159] At block 1225, memory controller 140 may, at least in part, use the second read pulse to read the second memory cell concurrently with reading the first memory cell, based on selecting the first polarity and the second polarity. The operation of 1225 may be performed according to the methods described herein.

[0160] An apparatus for performing method 1200 is described. The apparatus may include: means for identifying a first memory cell of a memory block for reading; means for identifying a second memory cell of the memory block for reading; means for selecting a first polarity of a first read pulse to read the first memory cell and selecting a second polarity of a second read pulse to read the second memory cell; means for using the first read pulse to read the first memory cell; and means for using the second read pulse concurrently with reading the first memory cell, at least in part based on selecting the first polarity and the second polarity, to read the second memory cell.

[0161] In some instances of the method 1200 and apparatus described above, the first polarity of the first read pulse may be opposite to the second polarity of the second read pulse. Some instances of the method 1200 and apparatus described above may further include processes, features, components, or instructions for concurrently applying voltages to access lines coupled to the first memory cell and the second memory cell, at least in part based on selecting the first and second polarities, wherein concurrently reading the second memory cell with the first memory cell may be at least in part based on applying the voltage to the access line.

[0162] Some examples of the method 1200 and apparatus described above may further include processes, features, components, or instructions for: dividing the first read pulse into a first voltage applied to a first access line and a second voltage applied to a second access line, the first access line and the second access line being coupled to the first memory cell. Some examples of the method 1200 and apparatus described above may further include processes, features, components, or instructions for: identifying the magnitude and polarity of the first voltage, at least in part based on the first polarity of the first read pulse. Some examples of the method 1200 and apparatus described above may further include processes, features, components, or instructions for: identifying the magnitude of a second voltage different from the magnitude of the first voltage and the polarity of the second voltage different from the polarity of the first voltage, at least in part based on the first polarity of the first read pulse and the first voltage, wherein applying the voltage may be at least in part based on the division and the identification.

[0163] Some examples of the method 1200 and apparatus described above may further include processes, features, components or instructions for: at least in part based on reading the second memory cell concurrently with reading the first memory cell, and identifying a first logical state stored on the first memory cell and a second logical state stored on the second memory cell.

[0164] Some examples of the method 1200 and apparatus described above may further include processes, features, components, or instructions for coupling the first memory cell to a first type of sensing component, at least in part based on the first read pulse having the first polarity. Some examples of the method 1200 and apparatus described above may further include processes, features, components, or instructions for coupling the second memory cell to a second type of sensing component, different from the first type, at least in part based on the second read pulse having the second polarity.

[0165] In some instances of the method 1200 and apparatus described above, the first polarity and the second polarity may be selected such that the voltage difference at the third memory cell of the memory block caused by the first read pulse or the second read pulse does not meet the programming threshold of the third memory cell.

[0166] Some examples of the method 1200 and apparatus described above may further include processes, features, components or instructions for determining that the first memory cell and the second memory cell are coupled to a common access line, wherein, at least in part based on the determination that the first memory cell and the second memory cell are coupled to the common access line, the first polarity and the second polarity may be the same.

[0167] Figure 13 The flowchart illustrates a method 1300 for concurrently accessing multiple memory cells according to embodiments of the present disclosure. Operation of method 1300 may be implemented by a memory controller 140 or components thereof as described herein. In some instances, the memory controller 140 may execute a set of code to control functional elements of the memory device to perform the functions described below. Alternatively, the memory controller 140 may use dedicated hardware to perform portions of the functions described below.

[0168] At box 1305, memory controller 140 can identify the first memory cell of the memory block for reading. Operation of 1305 can be performed according to the method described herein.

[0169] At block 1310, memory controller 140 can identify a second memory cell of the memory block for reading. Operation of 1310 can be performed according to the method described herein.

[0170] At block 1315, memory controller 140 can select a first polarity of a first read pulse to read the first memory cell and select a second polarity of a second read pulse to read the second memory cell. The operation of 1315 can be performed according to the method described herein.

[0171] At block 1320, memory controller 140 may concurrently apply voltages to access lines coupled to the first and second memory cells, at least in part, based on the selection of the first and second polarities. Operation of 1320 may be performed according to the methods described herein.

[0172] At block 1325, memory controller 140 may use the first read pulse to read the first memory cell. Operation of 1325 may be performed according to the method described herein.

[0173] At 1330, the memory controller 140 may, at least in part, use the second read pulse to read the second memory cell concurrently with reading the first memory cell, based on selecting the first polarity and the second polarity and applying the voltage to the access line. The operation of 1330 may be performed according to the methods described herein.

[0174] Figure 14 The illustration shows a flowchart of a method 1400 for concurrently accessing multiple memory cells according to embodiments of the present disclosure. Operation of method 1400 may be implemented by a memory controller 140 or components thereof as described herein. In some instances, the memory controller 140 may execute a set of code to control functional elements of the memory device to perform the functions described below. Alternatively, the memory controller 140 may use dedicated hardware to perform portions of the functions described below.

[0175] At box 1405, memory controller 140 can identify the first memory cell of the memory block for programming using a write operation. The operation of 1405 can be performed according to the method described herein.

[0176] At block 1410, memory controller 140 can identify a second memory cell of the memory block for access using a write operation or a read operation. Operation of 1410 can be performed according to the methods described herein.

[0177] At block 1415, memory controller 140 may determine that concurrent access to the second memory cell on the memory block is permitted during the duration of the access operation, in addition to programming the first memory cell. Operation 1415 may be performed according to the methods described herein.

[0178] At block 1420, memory controller 140 can program the first memory cell of the memory block during the duration of the access operation. Operation of 1420 can be performed according to the methods described herein.

[0179] At block 1425, memory controller 140 may, at least in part, determine that a second memory cell of the memory block is permitted to be accessed concurrently with the first memory cell during the access operation duration. Operation of 1425 may be performed according to the methods described herein.

[0180] An apparatus for performing method 1400 is described. The apparatus may include: means for identifying a first memory cell of a memory block for programming using a write operation; means for identifying a second memory cell of the memory block for access using a write operation or a read operation; means for determining that concurrent access to the second memory cell on the memory block is permitted during the access operation duration, in conjunction with programming the first memory cell; means for programming the first memory cell of the memory block during the access operation duration; and means for, at least in part, based on determining that concurrent access to the second memory cell of the memory block is permitted, concurrent access to the second memory cell on the memory block is permitted during the access operation duration, in conjunction with programming the first memory cell.

[0181] In some instances of the method 1400 and apparatus described above, concurrently accessing the second memory cell with programming the first memory cell may further include processes, features, components, or instructions for: programming the first memory cell using a first programming pulse during the duration of the access operation and concurrently programming the second memory cell with a second programming pulse during the duration of the access operation.

[0182] Some examples of the method 1400 and apparatus described above may further include processes, features, components, or instructions for: delaying the application of the first programming pulse or the second programming pulse during the access operation duration, at least in part based on a voltage applied to an unselected memory cell exceeding a programming threshold on the memory block during the access operation duration, wherein concurrent access to the second memory cell with programming the first memory cell during the access operation duration may be at least in part based on delaying the first programming pulse.

[0183] Some examples of the method 1400 and apparatus described above may further include procedures, features, components, or instructions for: identifying a first bit transition of the first memory cell during the write operation and identifying a second bit transition of the second memory cell during the write operation. Some examples of the method 1400 and apparatus described above may further include procedures, features, components, or instructions for: determining that a combination of the first bit transition and the second bit transition during the duration of the single access operation will cause a voltage applied to the unselected memory cell to exceed a programming threshold on the memory block, wherein delaying the application of the first programming pulse or the second programming pulse may be based at least in part on determining that the combination of the first bit transition and the second bit transition will cause the voltage applied to the unselected memory cell to exceed the programming threshold.

[0184] Some examples of the method 1400 and apparatus described above may further include processes, features, components or instructions for: applying a voltage exceeding a programming threshold of the unselected memory cell based at least in part on a combination of the first programming pulse and the second programming pulse, and avoiding the application of the first programming pulse and the second programming pulse during the duration of the single access operation.

[0185] Some examples of the method 1400 and apparatus described above may further include processes, features, components, or instructions for determining that the first memory cell can be coupled to a different access line with the second memory cell, wherein concurrent access to the second memory cell during the access operation duration is at least partially based on the determination that the first memory cell can be coupled to a different access line with the second memory cell.

[0186] In some instances of the method 1400 and apparatus described above, concurrently accessing the second memory cell with programming the first memory cell may further include processes, features, components, or instructions for: programming the first memory cell using programming pulses during the access operation duration and reading the second memory cell concurrently with programming the first memory cell during the access operation duration.

[0187] Some examples of the method 1400 and apparatus described above may further include processes, features, components or instructions for selecting the polarity of the read pulse applied to the second memory cell during the access operation duration, based at least in part on the characteristics of the programming pulse applied to the first memory cell during the access operation duration.

[0188] In some instances of the method 1400 and apparatus described above, the characteristics of the programming pulse may be the polarity of the programming pulse, the location to which the programming pulse may be applied, a bit transition associated with the programming pulse, or a combination thereof.

[0189] Some examples of the method 1400 and apparatus described above may further include procedures, features, components, or instructions for reversing data read from the second memory cell, at least in part based on the negative polarity of the read pulse. Some examples of the method 1400 and apparatus described above may further include procedures, features, components, or instructions for outputting the reversed data.

[0190] Some examples of the method 1400 and apparatus described above may further include processes, features, components, or instructions for: delaying the application of a programming pulse or a read pulse during the access operation duration, at least in part based on a voltage applied to an unselected memory cell exceeding a programming threshold on the memory block during the access operation duration, wherein concurrent access to the second memory cell with programming of the first memory cell during the access operation duration may be at least in part based on delaying the programming pulse or the read pulse.

[0191] Some examples of the method 1400 and apparatus described above may further include processes, features, components, or instructions for determining that a combination of the programming pulse and the read pulse will cause a voltage applied to an unselected memory cell during the duration of the access operation to exceed a programming threshold on the memory block, wherein delaying the programming pulse or the read pulse may be based at least in part on determining that the combination of the programming pulse and the read pulse will cause the voltage applied to the unselected memory cell to exceed the programming threshold.

[0192] Some examples of the method 1400 and apparatus described above may further include processes, features, components or instructions for: applying a voltage exceeding a programming threshold of the unselected memory cell based at least in part on the combination of the programming pulse and the read pulse, and avoiding the application of the programming pulse and the read pulse during the access operation duration.

[0193] Some examples of the method 1400 and apparatus described above may further include processes, features, components, or instructions for: determining that allowing concurrent access to the second memory cell with programming of the first memory cell may be at least partially based on the identification that the voltage does not meet the programming threshold.

[0194] Some examples of the method 1400 and apparatus described above may further include processes, features, components, or instructions for: determining that allowing concurrent access to the second memory cell with programming of the first memory cell may be at least partially based on the identification that the voltage does not meet the programming threshold.

[0195] Some examples of the method 1400 and apparatus described above may further include processes, features, components, or instructions for: determining that concurrent access to the second memory cell, which allows programming of the first memory cell, may be at least partially based on the comparison of the combination with the set.

[0196] Figure 15 The flowchart illustrates a method 1500 for concurrently accessing multiple memory cells according to embodiments of the present disclosure. Operation of method 1500 may be implemented by a memory controller 140 or components thereof as described herein. In some instances, the memory controller 140 may execute a set of code to control functional elements of the memory device to perform the functions described below. Alternatively, the memory controller 140 may use dedicated hardware to perform portions of the functions described below.

[0197] At block 1505, memory controller 140 can identify the first memory cell of the memory block for programming using a write operation. The operation of 1505 can be performed according to the method described herein.

[0198] At block 1510, memory controller 140 can identify a second memory cell of the memory block for access using a write operation or a read operation. Operation of 1510 can be performed according to the methods described herein.

[0199] At block 1515, memory controller 140 may determine that concurrent access to the second memory cell on the memory block is permitted during the duration of the access operation, in addition to programming the first memory cell. Operation of 1515 may be performed according to the methods described herein.

[0200] At block 1520, memory controller 140 may program the first memory cell of the memory block using a first programming pulse during the duration of the access operation. Operation of 1520 may be performed according to the methods described herein.

[0201] At block 1525, the memory controller 140 may, at least in part, program the second memory cell of the memory block concurrently with programming the first memory cell, using a second programming pulse concurrently with programming the first memory cell during the duration of the access operation, based on a determination that allows concurrent access to the memory block of the memory block of the first memory cell. Operation of 1525 may be performed according to the methods described herein.

[0202] Figure 16 The flowchart illustrates a method 1600 for concurrently accessing multiple memory cells according to embodiments of the present disclosure. Operation of method 1600 may be implemented by a memory controller 140 or components thereof as described herein. In some instances, the memory controller 140 may execute a set of code to control functional elements of the memory device to perform the functions described below. Alternatively, the memory controller 140 may use dedicated hardware to perform portions of the functions described below.

[0203] At box 1605, memory controller 140 can identify the first memory cell of the memory block for programming using a write operation. The operation of 1605 can be performed according to the method described herein.

[0204] At block 1610, memory controller 140 can identify a second memory cell of the memory block for access using a write operation or a read operation. Operation of 1610 can be performed according to the methods described herein.

[0205] At block 1615, memory controller 140 may determine that concurrent access to the second memory cell on the memory block is permitted during the duration of the access operation, in addition to programming the first memory cell. Operation 1615 may be performed according to the methods described herein.

[0206] At block 1620, memory controller 140 may use programming pulses to program the first memory cell of the memory block during the duration of the access operation. Operation of 1620 may be performed according to the methods described herein.

[0207] At block 1625, the memory controller 140 may select the polarity of the read pulse applied to the second memory cell during the access operation duration, at least in part, based on the characteristics of the programming pulse applied to the first memory cell during the access operation duration. Operation of 1625 may be performed according to the methods described herein.

[0208] At block 1630, memory controller 140 may, at least in part, read the second memory cell of the memory block concurrently with programming the first memory cell, using read pulses concurrently with programming the first memory cell during the duration of the access operation. Operation of 1630 may be performed according to the methods described herein.

[0209] Figure 17 The flowchart illustrates a method 1700 for concurrently accessing multiple memory cells according to embodiments of the present disclosure. Operation of method 1700 may be implemented by a memory controller 140 or components thereof as described herein. In some instances, the memory controller 140 may execute a set of code to control functional elements of the memory device to perform the functions described below. Alternatively, the memory controller 140 may use dedicated hardware to perform portions of the functions described below.

[0210] At block 1705, memory controller 140 can identify a first memory cell in a first segment of a memory block for reading, wherein the memory cell in the first segment of the memory block is configured to be read in response to the application of a first read pulse having a first polarity. Operation of 1705 can be performed according to the method described herein.

[0211] At block 1710, the memory controller 140 can identify a second memory cell in a second segment of the memory block for reading, wherein the memory cell in the second segment of the memory block is configured to be read in response to the application of a second read pulse having a second polarity different from the first polarity. Operation of 1710 can be performed according to the methods described herein.

[0212] At block 1715, memory controller 140 can read the first memory cell. Operation of 1715 can be performed according to the method described herein.

[0213] At block 1720, memory controller 140 may read the second memory cell concurrently with reading the first memory cell, based at least in part on identifying the first memory cell in the first segment and the second memory cell in the second segment. Operation of 1720 may be performed according to the methods described herein.

[0214] An apparatus for performing method 1700 is described. The apparatus may include: means for identifying a first memory cell in a first segment of a memory block for reading, wherein the memory cell in the first segment of the memory block is configured to be read in response to the application of a first read pulse having a first polarity; means for identifying a second memory cell in a second segment of the memory block for reading, wherein the memory cell in the second segment of the memory block is configured to be read in response to the application of a second read pulse having a second polarity different from the first polarity; means for reading the first memory cell; and means for reading the second memory cell concurrently with reading the first memory cell, at least in part based on identifying the first memory cell in the first segment and the second memory cell in the second segment.

[0215] Some examples of the method 1700 and apparatus described above may further include processes, features, components or instructions for determining that the first memory cell and the second memory cell are coupled to different access lines, wherein reading the second memory cell concurrently with reading the first memory cell may be based at least in part on determining that the first memory cell and the second memory cell are coupled to different access lines.

[0216] Some examples of the method 1700 and apparatus described above may further include processes, features, components, or instructions for: applying a first voltage having the first polarity to a first digital line coupled to the first memory cell, at least in part based on the first read pulse having the first polarity. Some examples of the method 1700 and apparatus described above may further include processes, features, components, or instructions for: applying a second voltage having the second polarity to a second digital line coupled to the second memory cell, at least in part based on the second read pulse having the second polarity.

[0217] Some examples of the method 1700 and apparatus described above may further include processes, features, components, or instructions for: applying a first voltage having a second polarity to a first digital line coupled to the first memory cell, at least in part based on the first read pulse having the first polarity. Some examples of the method 1700 and apparatus described above may further include processes, features, components, or instructions for: applying a second voltage having the first polarity to a second digital line coupled to the second memory cell, at least in part based on the second read pulse having the second polarity.

[0218] In some instances of the method 1700 and apparatus described above, the first polarity may be opposite to the second polarity such that the first segment of the memory cell may be configured to be read with a positive polarity read pulse and the second segment of the memory cell may be configured to be read with a negative polarity read pulse.

[0219] An electronic memory device is described. The device may include: a memory cell; a digital line coupled to the memory cell; a first sensing component coupled to the digital line, the first sensing component being configured to identify a logical state stored in the memory cell based at least in part on a first read pulse having a first polarity; and a second sensing component coupled to the digital line, the second sensing component being configured to identify the logical state stored in the memory cell based at least in part on a second read pulse having a second polarity different from the first polarity.

[0220] In some instances, the device may include: a first voltage source coupled to the digital line, the first voltage source being configured to supply at least a portion of the first read pulse having the first polarity; and a second voltage source coupled to the digital line, the second voltage source being configured to supply at least a portion of the second read pulse having the second polarity. In some instances, the device may include a switching component configured to selectively couple the digital line to either the first voltage source or the second voltage source during an access operation.

[0221] In some instances, the device may include a switching component configured to selectively output a signal from either the first sensing component or the second sensing component, at least in part based on the type of read pulse applied to the memory cell during a read operation. In some instances, the memory cell includes a chalcogenide material configured to use a non-uniform distribution of ions to indicate the logic state. In some instances, the memory cell is a self-selecting memory cell.

[0222] An electronic memory device is described. In some instances, the device may include: a memory block having a first segment of memory cells and a second segment of memory cells, wherein the memory cells of the first segment are configured to be read in response to the application of a first read pulse having a first polarity and the memory cells of the second segment are configured to be read in response to the application of a second read pulse having a second polarity different from the first polarity; a first sensing component coupled to the first segment of the memory cells of the memory block and configured to identify, at least partially, a logical state of a memory cell of the first segment of the memory cells based on the first polarity of the first read pulse; and a second sensing component coupled to the second segment of the memory cells of the memory block and configured to identify, at least partially, the logical state of a memory cell of the second segment of the memory cells based on the second polarity of the second read pulse.

[0223] In some instances, the device may include: a first voltage source coupled to the digital line of the first segment, the first voltage source being configured to supply at least a portion of the first read pulse having the first polarity; and a second voltage source coupled to the digital line of the second segment, the second voltage source being configured to supply at least a portion of the second read pulse having the second polarity. In some instances, the memory cells of the memory block are formed of a chalcogenide material configured to use a non-uniform distribution of ions to indicate the logic state.

[0224] In some instances, one or more trimming parameters for the first segment of the memory cell are independent of one or more trimming parameters for the second segment of the memory cell. In some instances, the first sensing component and the second sensing component are positioned below the occupied area of ​​the memory block. In some instances, the memory block comprises more than one layer of the memory cell.

[0225] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are also possible. Furthermore, embodiments from two or more methods can be combined.

[0226] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some figures may illustrate signals as single signals; however, those skilled in the art will understand that signals can represent signal buses, which may have various bit widths.

[0227] The terms "electrically connected" and "coupled" refer to the relationship between components that enables the flow of electrons between them. This can include direct connections between components or may include intermediate components. Components that are electrically connected or coupled to each other may be actively exchanging electrons or signals (e.g., in a powered circuit) or may not be actively exchanging electrons or signals (e.g., in a de-energized circuit) but can be configured and operable to exchange electrons or signals when the circuit is energized. For example, two components physically connected via a switch (e.g., a transistor) are electrically connected or coupled regardless of the state of the switch (i.e., open or closed).

[0228] The term "isolation" refers to the relationship between components in which electrons cannot currently flow; if there is an open circuit between the components, then they are isolated from each other. For example, when a switch is open, two components physically connected by the switch are isolated from each other.

[0229] As used herein, the term "short circuit" refers to a relationship between components in which a conductive path is established between the components in question by activating a single intermediate component between the two components. For example, when a switch between two components is closed, the first component shorted to the second component can exchange electrons with the second component. Thus, a short circuit can enable dynamic operation that allows charge flow between components (or lines) that are in an electrical connection.

[0230] The apparatus discussed herein, including memory blocks 100, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

[0231] Chalcogenide materials can be materials or alloys containing at least one of the elements sulfur (S), selenium (Se), and tellurium (Te). The phase change materials discussed in this article can be chalcogenide materials. Chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te -Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-B i-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. As used herein, hyphenated chemical composition symbols indicate elements contained in a particular compound or alloy and are intended to represent all stoichiometry involving the indicated element. For example, Ge-Te may contain Ge x Te y Where x and y can be any positive integers. Other examples of variable resistance materials may include binary metal oxide materials or mixed-valence oxides containing two or more metals, such as transition metals, alkaline earth metals, and / or rare earth metals. Embodiments are not limited to specific variable resistance materials or materials associated with memory elements of memory cells. For example, other examples of variable resistance materials may be used to form memory elements and may include chalcogenide materials, colossal magnetoresistance materials, or polymer-based materials, as well as other materials.

[0232] The transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include heavily doped, for example, degenerate semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to conduct. When a voltage greater than or equal to the transistor threshold voltage is applied to the transistor gate, the transistor may be “turned on” or “activated.” When a voltage less than the transistor threshold voltage is applied to the transistor gate, the transistor may be “turned off” or “deactivated.”

[0233] The descriptions set forth herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to other examples." The detailed descriptions include specific details for the purpose of providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, numerous well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0234] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by adding a dash after the reference label and a second label to differentiate similar components. When only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0235] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips described above can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0236] The various illustrative blocks and modules described in this disclosure can be implemented or performed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0237] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If the functionality described herein is implemented in software executed by a processor, then the functionality can be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including portions distributed such that the functionality is implemented in different physical locations. Moreover, as used herein (included in the claims), the word "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list such that, for example, a list of at least one of A, B, or C represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as a reference to a conditionally closed set. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0238] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave), then the definition of media includes coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave). As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0239] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will readily be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for operating an electronic memory device, comprising: Identify the first memory cell of the memory block for reading; The second memory cell of the memory block is identified for reading; Select the first polarity of the first read pulse to read the first memory cell and select the second polarity of the second read pulse to read the second memory cell; The first memory cell is read using the first read pulse; and At least in part, based on the selection of the first polarity and the second polarity, the second memory cell is read concurrently with the reading of the first memory cell using the second read pulse, wherein the first polarity of the first read pulse is different from the second polarity of the second read pulse, wherein the selection of the first polarity and the second polarity is such that the voltage difference at the third memory cell of the memory block caused by the first read pulse or the second read pulse does not meet the programming threshold of the third memory cell.

2. The method according to claim 1, wherein the first polarity of the first read pulse is opposite to the second polarity of the second read pulse.

3. The method according to claim 1, further comprising: Voltages are concurrently applied to access lines coupled to the first memory cell and the second memory cell, at least in part based on selecting the first polarity and the second polarity, wherein concurrent reading of the second memory cell with the first memory cell is at least in part based on applying the voltages to the access lines.

4. The method of claim 3, further comprising: The first read pulse is divided into a first voltage applied to a first access line and a second voltage applied to a second access line, wherein the first access line and the second access line are coupled to the first memory cell; The magnitude and polarity of the first voltage are identified, at least in part, based on the first polarity of the first read pulse; and Based at least in part on the first polarity and the first voltage of the first read pulse, the magnitude of a second voltage that is different from the magnitude of the first voltage and the polarity of the second voltage that is different from the polarity of the first voltage are identified, wherein the application of the voltage is based at least in part on the division and the identification.

5. The method of claim 1, further comprising: At least in part, based on reading the second memory cell concurrently with reading the first memory cell, the first logical state stored on the first memory cell and the second logical state stored on the second memory cell are identified.

6. The method of claim 1, further comprising: The first memory cell is coupled to a first type of sensing component, at least in part based on the fact that the first read pulse has the first polarity. and The second memory cell is coupled to a second type of sensing component, different from the first type, based at least in part on the second read pulse having the second polarity.

7. The method of claim 1, further comprising: It is determined that the first memory cell and the second memory cell are coupled to a common access line, wherein at least in part, it is determined that the first memory cell and the second memory cell are coupled to the common access line, and the first polarity and the second polarity are the same.

8. A method for operating an electronic storage device, comprising: A first memory cell in a first segment of a memory block is identified for reading, wherein the memory cell in the first segment of the memory block is configured to be read in response to the application of a first read pulse having a first polarity; A second memory cell in a second segment of the memory block is identified for reading, wherein the memory cell in the second segment of the memory block is configured to be read in response to the application of a second read pulse having a second polarity different from the first polarity; Read the first memory unit; and At least in part, based on identifying the first memory cell of the first segment and the second memory cell of the second segment, the second memory cell is read concurrently with the first memory cell, wherein the first polarity and the second polarity are selected such that the voltage difference at the third memory cell of the memory block caused by the first read pulse or the second read pulse does not meet the programming threshold of the third memory cell.

9. The method of claim 8, further comprising: It is determined that the first memory cell and the second memory cell are coupled to different access lines, wherein reading the second memory cell concurrently with reading the first memory cell is at least in part based on determining that the first memory cell and the second memory cell are coupled to different access lines.

10. The method of claim 8, further comprising: At least in part based on the fact that the first read pulse has the first polarity, a first voltage having the first polarity is applied to a first digital line coupled to the first memory cell; and At least in part based on the second read pulse having the second polarity, a second voltage having the second polarity is applied to a second digital line coupled to the second memory cell.

11. The method of claim 8, further comprising: At least in part based on the fact that the first read pulse has the first polarity, a first voltage having the second polarity is applied to a first digital line coupled to the first memory cell; and At least in part based on the second read pulse having the second polarity, a second voltage having the first polarity is applied to a second digital line coupled to the second memory cell.

12. The method of claim 8, wherein the first polarity is opposite to the second polarity such that the first segment of the memory cell is configured to be read with a positive polarity read pulse and the second segment of the memory cell is configured to be read with a negative polarity read pulse.

13. An electronic storage device comprising: A memory block having a first segment of memory cells and a second segment of memory cells, wherein the memory cells of the first segment are configured to be read in response to the application of a first read pulse having a first polarity and the memory cells of the second segment are configured to be read in response to the application of a second read pulse having a second polarity different from the first polarity, wherein the second memory cells of the second segment are configured to be read concurrently while the first memory cells of the first segment are being read; A first sensing component, coupled to the first segment of a memory cell of the memory block and configured to identify the memory cell at least in part based on the first polarity of the first read pulse. The logical state of the first memory cell in the first segment; and A second sensing component, coupled to the second segment of the memory cell of the memory block and configured to identify the memory cell at least in part based on the second polarity of the second read pulse. The logic state of the second memory cell in the second segment, wherein the first polarity and the second polarity are selected such that the voltage difference caused by the first read pulse or the second read pulse at the third memory cell of the memory block does not meet the programming threshold of the third memory cell.

14. The electronic memory device of claim 13, further comprising: A first voltage source coupled to the digital line of the first segment, the first voltage source being configured to supply at least a portion of the first read pulse having the first polarity; and A second voltage source coupled to the digital line of the second segment is configured to supply at least a portion of the second read pulse having the second polarity.

15. The electronic memory device of claim 13, wherein the memory cells of the memory block are formed of a chalcogenide material configured to indicate the logic state using a non-uniform distribution of ions.

16. The electronic memory device of claim 13, wherein one or more trimming parameters for the first segment of the memory cell are independent of one or more trimming parameters for the second segment of the memory cell.

17. The electronic memory device of claim 13, wherein the first sensing component and the second sensing component are positioned below the occupied area of ​​the memory tile.

18. The electronic memory device of claim 13, wherein the memory block comprises one or more layers of memory cells.

19. The electronic memory device of claim 13, wherein the first polarity is opposite to the second polarity, such that the first segment of the memory cell is configured to be read with a positive polarity read pulse and the second segment of the memory cell is configured to be read with a negative polarity read pulse.

20. An electronic storage device comprising: One or more memory arrays; and At least one controller coupled to and configured to: Identify the first memory cell of the memory block for reading; The second memory cell of the memory block is identified for reading; Select the first polarity of the first read pulse to read the first memory cell and select the second polarity of the second read pulse to read the second memory cell; The first memory cell is read using the first read pulse; and At least in part, based on the selection of the first polarity and the second polarity, the second memory cell is read concurrently with the reading of the first memory cell using the second read pulse, wherein the first polarity of the first read pulse is different from the second polarity of the second read pulse, wherein the selection of the first polarity and the second polarity is such that the voltage difference at the third memory cell of the memory block caused by the first read pulse or the second read pulse does not meet the programming threshold of the third memory cell.

21. The electronic memory device of claim 20, wherein the first polarity of the first read pulse is opposite to the second polarity of the second read pulse.

22. The electronic memory device of claim 20, wherein the at least one controller is further configured to: Voltages are concurrently applied to access lines coupled to the first memory cell and the second memory cell, at least in part based on the selection of the first polarity and the second polarity, wherein concurrent readings of the second memory cell and the first memory cell are at least in part based on the application of the voltages to the access lines.

23. The electronic memory device of claim 22, wherein the at least one controller is further configured to: The first read pulse is divided into a first voltage applied to a first access line and a second voltage applied to a second access line, wherein the first access line and the second access line are coupled to the first memory cell; The magnitude and polarity of the first voltage are identified at least in part based on the first polarity of the first read pulse; and The magnitude and polarity of the second voltage are identified at least in part based on the first polarity and the first voltage of the first read pulse, wherein the magnitude of the second voltage is different from the magnitude of the first voltage and the polarity of the second voltage is different from the polarity of the first voltage, wherein the voltage is applied at least in part based on the division and the identification.

24. The electronic memory device of claim 20, wherein the at least one controller is further configured to: At least in part, based on reading the second memory cell concurrently with reading the first memory cell, a first logical state stored on the first memory cell and a second logical state stored on the second memory cell are identified.

25. The electronic memory device of claim 20, wherein the at least one controller is further configured to: At least in part based on the first read pulse having the first polarity, the first memory cell is coupled to a first type of sensing component; and The second memory cell is coupled to a second type of sensing component, different from the first type, based at least in part on the second read pulse having the second polarity.

26. The electronic memory device of claim 20, wherein the at least one controller is further configured to: The first memory cell and the second memory cell are determined to be coupled to a common access line, wherein the first polarity and the second polarity are the same, at least in part based on the determination that the first memory cell and the second memory cell are coupled to the common access line.

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