Method and apparatus for full-cycle error correction of inductor current measurements

Abstract

The present disclosure relates to a method and apparatus for performing full-cycle error correction on an inductor current measurement of a switching regulator. Example embodiments include a method that generates a ramp-down compensation voltage based at least in part on an inductor voltage and a current sense voltage of an inductor at an inductor node; applies the ramp-down compensation voltage to the inductor node; and, based on a first determination that a valley current sense voltage is not equal to the inductor voltage, modifies a predetermined capacitance of a system capacitor operatively coupled to the inductor node to a first modified capacitance. Example embodiments also include an apparatus having a ramp-down compensator and a ramp-up compensator.

Description

[0001] Cross-references to Related Patent Applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 967,843, filed on January 30, 2020, entitled “FULL CYCLE INDUCTOR CURRENTMEASUREMENT TECHNIQUE FOR SWICHING REGULATOR,” the contents of which are hereby incorporated by reference in their entirety and for all purposes as if fully set forth herein. Technical Field

[0003] The present embodiments relate generally to power regulators, and more particularly to full-cycle error correction of inductor current measurements of switching regulators. Background Art

[0004] Accurate inductor current sensing is crucial for precise operation of voltage regulator systems. However, conventional systems may not be able to effectively correct errors in the inductor current sense signal across the full cycle of voltage regulator operation, resulting in reduced accuracy of the current sense signal or increased cost and complexity of the correction system. Therefore, a technical solution is needed for full-cycle error correction of inductor current measurements in switching regulators. Summary of the Invention

[0005] Example embodiments include a method of generating a ramp-down compensation voltage based at least in part on an inductor voltage and a current sense voltage of an inductor at an inductor node, applying the ramp-down compensation voltage to the inductor node, and modifying a predetermined capacitance of a system capacitor operably coupled to the inductor node to a first modified capacitance based on a first determination that the valley current sense voltage and the inductor voltage are unequal.

[0006] Example embodiments also include an apparatus having a ramp-down compensator and a ramp-up compensator, the ramp-down compensator operable to generate a ramp-down compensation voltage based at least in part on an inductor voltage and a current sense voltage of the inductor at an inductor node, and to apply the ramp-down compensation voltage to the inductor node; the ramp-up compensator including a system capacitor operably coupled to the inductor node, the ramp-up compensator operably coupled to the ramp-down compensator and operable to modify a predetermined capacitance of the system capacitor to a first modified capacitance based on a first determination regarding a valley current sense voltage if the inductor voltage and the inductor voltage are not equal.

[0007] Example embodiments also include a method that generates a ramp-down compensation voltage based at least in part on an inductor voltage and a current sensing voltage of an inductor at an inductor node, applies the ramp-down compensation voltage to the inductor node, reduces capacitance of a system capacitor operably coupled to the inductor node based on a first determination that a valley current sensing voltage is greater than the inductor voltage, and increases capacitance of the system capacitor based on a second determination that the valley current sensing voltage is less than the inductor voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] These and other aspects and features of the present embodiments will become apparent to those of ordinary skill in the art from a reading of the following description of the detailed embodiments in conjunction with the accompanying drawings.

[0009] Figure 1 An example system according to the present embodiment is illustrated.

[0010] Figure 2 An example device according to the present embodiment is illustrated.

[0011] Figure 3 A first example timing diagram according to the present embodiment is illustrated, including a reference corrected voltage waveform and an uncorrected voltage waveform.

[0012] Figure 4 A second example timing diagram according to the present embodiment is illustrated, the second example timing diagram including a first partially corrected voltage waveform and a second partially corrected voltage waveform.

[0013] Figure 5 The example shows the connection Figure 4 The third example timing diagram following the example timing diagram of FIG. 1 includes a third partially corrected voltage waveform and a corrected voltage waveform.

[0014] Figure 6 Another example system according to the present embodiment is illustrated.

[0015] Figure 7 An example method for full-cycle error correction of inductor current measurement of a switching regulator according to the present embodiment is illustrated.

[0016] Figure 8 The example shows the connection Figure 7 An example method for full-cycle error correction of inductor current measurement for a switching regulator is provided below. DETAILED DESCRIPTION

[0017] The present embodiment will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of the embodiments so that those skilled in the art can practice embodiments and alternatives that would be apparent to those skilled in the art. It is noteworthy that the following figures and examples are not intended to limit the scope of the present embodiment to a single embodiment, but rather that other embodiments may be implemented by interchanging some or all of the elements described or illustrated. Furthermore, where certain elements of the present embodiment can be partially or completely implemented using known components, only those portions of such known components necessary for understanding the present embodiment will be described, and detailed descriptions of the remaining portions of such known components will be omitted to avoid obscuring the present embodiment. Unless otherwise indicated herein, it will be apparent to those skilled in the art that embodiments described as being implemented in software are not limited thereto, but may include embodiments implemented in hardware or a combination of software and hardware, and vice versa. In this specification, embodiments showing a single component should not be considered restrictive; rather, unless otherwise expressly indicated herein, the present disclosure is intended to encompass other embodiments including multiple identical components, and vice versa. Furthermore, unless expressly provided, the applicant does not intend for any term in the specification or claims to have an uncommon or special meaning. Furthermore, the present embodiment encompasses current and future known equivalents of the known components mentioned herein by way of example.

[0018] It should be understood that accurate inductor current sensing is crucial for the precise operation of voltage regulator systems. Therefore, in some embodiments, accurate inductor current sensing is crucial for the operation of various control operations, including those of the voltage regulator, and for the current measurement operations that govern those control operations. In some embodiments, the sensed current includes errors introduced by the sensing device or system, which must be removed, mitigated, etc. Various processes for providing accurate inductor current sensing may offer advantages, including high accuracy, lossless measurement, and full-cycle sensing. However, these processes may also introduce efficiency losses for high accuracy, lower accuracy for lossless operation, specific knowledge of the physical properties of the inductor or other components, or the need for additional components that may increase material or manufacturing costs. Furthermore, in some embodiments, simply applying a trimming voltage to remove, mitigate, or otherwise remove an error signal from the inductor current sense voltage may distort the signal. In some embodiments, this distortion of the inductor current sense signal may reduce or eliminate the accuracy and effectiveness of the signal for inductor current sensing. Therefore, it would be advantageous to provide full-cycle error correction for inductor current measurement in switching regulators.

[0019] Figure 1 An example system according to the present embodiment is shown. Figure 1As illustrated by the example in , the example system 100 includes a converter circuit 110 , a ramp-down compensator 120 , a ramp-up compensator 130 , an inductor node 102 , an input node 104 , and an output node 106 .

[0020] The converter circuit 110 is operable to generate an uncorrected inductor voltage waveform. In some embodiments, the converter circuit is operatively coupled to a voltage regulator, a power supply, a regulator, a charger, etc. at an input node 104. In some embodiments, the converter circuit 110 is operable to include at least one of a current integrator device and a voltage integrator. In some embodiments, the converter circuit 110 generates, receives, obtains, etc. an uncorrected inductor voltage waveform according to equations (1), (2), and (3):

[0021] d(V L )=d(I L )-Z Equation (1)

[0022]

[0023]

[0024] In some embodiments, input node 104 receives an input uncorrected inductor current, one or more control signals, and the like. In some embodiments, input node 104 is a single trace, line, or the like associated with one or more signals in sequence. Alternatively, in some embodiments, input node 104 is or includes multiple traces, lines, buses, or the like associated with one or more signals in parallel. In some embodiments, output node 106 transmits an output corrected inductor voltage, one or more control signals, and the like. In some embodiments, output node 106 is a single trace, line, or the like associated with one or more signals in sequence. Alternatively, in some embodiments, output node 106 is or includes multiple traces, lines, buses, or the like associated with one or more signals in parallel. In some embodiments, converter circuit 110 includes one or more logic or electronic devices, including, but not limited to, integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, and the like. It should be understood that any electrical, electronic, or similar device or component associated with the converter circuit 110 may also be associated with, integrated with, integrable with, replaced by, supplemented by, complemented by, etc., one or more of the ramp-down compensator 120, the ramp-up compensator 130, or any components thereof.

[0025] The ramp-down compensator 120 is operable to correct the ramp-down portion of the uncorrected inductor voltage waveform. In some embodiments, the ramp-down compensator is operable to apply one or more correction voltages to the inductor voltage waveform during the ramp-down portion of the inductor cycle. In some embodiments, the ramp-down portion of the inductor cycle is half a cycle of the full cycle of the inductor voltage waveform of the uncorrected inductor voltage. In some embodiments, the ramp-down portion of the inductor cycle is half a cycle of the full cycle of the inductor voltage waveform of the uncorrected inductor voltage. In some embodiments, the ramp-down compensator 120 includes one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device or component associated with the ramp-down compensator 120 may also be associated with, integrated with, integrable with, replaced by, supplemented by, or the like, one or more of the ramp-down compensator 120, the ramp-up compensator 130, or any of their components.

[0026] The ramp compensator 130 is operable to correct the ramp-up portion of the uncorrected inductor voltage waveform. In some embodiments, the ramp compensator is operable to apply one or more correction voltages to the inductor voltage waveform during the ramp-up portion of the inductor cycle. In some embodiments, the ramp-up portion of the inductor cycle is the other half of the full cycle of the inductor voltage waveform of the uncorrected inductor voltage. In some embodiments, the ramp-up portion of the inductor cycle is the other half of the full cycle of the inductor voltage waveform of the uncorrected inductor voltage. In some embodiments, the ramp-up compensator 130 comprises one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, and the like. It should be understood that any electrical, electronic, or similar device or component associated with the ramp compensator 130 may also be associated with, integrated with, integrable with, replaced by, supplemented by, or otherwise augmented by the ramp-down compensator 120, the ramp compensator 130, or any of their components. Inductor node 102 is operable to receive at least one of an uncorrected voltage, a corrected voltage, and a partially corrected voltage. In some embodiments, inductor node 102 is operatively coupled to one or more of converter circuit 110 , ramp-down compensator 120 , and ramp-up compensator 130 .

[0027] Figure 2 An example device according to the present embodiment is shown. Figure 2As illustrated in the example of FIG, the example device 200 includes a converter circuit 110, a ramp-down compensator 120, a ramp-up compensator 130, an inductor node 102, and an input node 104. In some embodiments, the ramp-down compensator 120 includes a valley current sensing circuit 220 and a ramp-down buffer 222. In some embodiments, the ramp-up compensator 130 includes a system capacitor 230, a capacitor calibration circuit 232, and a ramp-down comparator 234.

[0028] In some embodiments, the input node 104 includes an input node 104, an output node 106, and a trimmed voltage input node 202. The trimmed voltage input node 202 is operable to provide a trimmed voltage to the converter circuit. In some embodiments, the trimmed voltage input node 202 is operable to provide a positive or negative voltage to the converter circuit 110 to modify the corrected inductor voltage output at the output node. In some embodiments, the trimmed voltage modifies the full cycle of the inductor voltage waveform by scalar shifting, amplitude modification, etc. In some embodiments, the converter circuit 110 operates according to a conversion factor Gm. In some embodiments, the input 104 corresponds to Vinput. In some embodiments, the converter circuit 110 generates and applies the conversion factor Gm according to equations (4), (5), and (6):

[0029]

[0030]

[0031]

[0032] The valley current sensing circuit 220 is operable to generate a valley current sensing voltage. In some embodiments, the valley current sensing voltage is an uncorrected offset of the inductor voltage that is or includes the offset described above. In some embodiments, the offset is a time-dependent or time-independent scalar value generated as a voltage. In some embodiments, the offset is time-dependent or time-independent. In some embodiments, the valley current sensing circuit 220 includes one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device or component associated with the valley current sensing circuit 220 may also be associated with, integrated with, integrable with, replaced by, supplemented by, or otherwise augmented by the ramp compensator 120 or any component thereof.

[0033] The ramp-down buffer 222 is operable to generate a compensation voltage associated with the ramp-down portion of the inductor ramp cycle. In some embodiments, the ramp-down buffer 222 includes a non-inverting input operably coupled to the output of the valley current sensing circuit 220, an inverting input operably coupled to the inductor node 102, and an output operably coupled to the inductor node 102 via an inductor voltage feedback line. It should be understood that any electrical, electronic, or similar device or component associated with the ramp-down buffer 222 may also be associated with, integrated with, integrable with, replaced by, supplemented by, or otherwise augmented by the ramp-down compensator 120 or any component thereof.

[0034] System capacitor 230 is operable to compensate for the voltage associated with the ramp-up portion of the inductor ramp cycle. In some embodiments, system capacitor 230 is a variable capacitor. In some embodiments, system capacitor 230 is electronically controlled, controllable, modifiable, settable, selectable, etc. In some embodiments, system capacitor 230 is or includes one or more capacitors, a capacitor array, etc. In some embodiments, system capacitor 230 is operably coupled to inductor node 102 at a first terminal and is operably coupled to ground, a reference voltage, etc. at a second terminal.

[0035] The capacitor calibration circuit 232 is operable to generate a compensation signal associated with the ramp-down portion of the inductor ramp cycle. In some embodiments, the capacitor calibration circuit 232 is operable to generate one or more control signals and apply the one or more control signals to the system capacitor 230 to modify the capacitance of the system capacitor. In some embodiments, the capacitor calibration circuit includes an output operably coupled to the system capacitor 230 and an input operably coupled to the ramp-down comparator 234. In some embodiments, the capacitor calibration circuit 232 includes one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device or component associated with the capacitor calibration circuit 232 can also be associated with, integrated with, integrable with, replaced by, supplemented by, or otherwise augmented by the ramp-up compensator 232 or any component thereof.

[0036] The ramp-up comparator 234 is operable to generate a compensation voltage associated with the ramp-up portion of the inductor ramp cycle. In some embodiments, the ramp-up comparator 234 includes a non-inverting input operably coupled to the non-inverting input of the ramp-down buffer 222, an inverting input operably coupled to the inductor node 102, and an output operably coupled to the capacitor calibration circuit 232. Thus, in some embodiments, the ramp-up comparator 234 is arranged to correct the voltage at the inductor node 102. It should be understood that any electrical, electronic, or similar device or component associated with the ramp-down buffer 222 may also be associated with, integrated with, integrable with, replaced by, supplemented by, or otherwise augmented by the ramp-down compensator 120 or any component thereof.

[0037] Figure 3 A first example timing diagram including a reference corrected voltage waveform and an uncorrected voltage waveform according to the present embodiment is illustrated. Figure 3 , the example timing diagram 300 includes a reference corrected voltage waveform 310 and an uncorrected voltage waveform 320. In some embodiments, the corrected voltage waveform 310 and the input voltage waveform 320 reach a corrected peak level 340 and an uncorrected peak level 342, respectively. In some embodiments, the reference corrected voltage waveform 310 and the uncorrected voltage waveform 320 are within a ramp-up period 330 and a ramp-down period 332 of a ramp period 334. It should be understood that the reference corrected waveform is shown in the timing diagram 300 for illustrative purposes and need not appear with the uncorrected voltage waveform 320.

[0038] At time t0 302, the uncorrected voltage waveform 320 begins a ramping portion 330 of a ramp period 334 at a low voltage level of the ramp period and begins increasing toward an uncorrected peak level 342. In some embodiments, the uncorrected peak level 342 is greater than the reference corrected peak level 340. In some embodiments, between time t0 302 and time t1 304, the slope of the uncorrected voltage waveform 320 is greater than the corresponding slope of the reference corrected voltage waveform 310, and between time t0 302 and time t1 304, the amplitude of the uncorrected voltage waveform 320 is greater than the corresponding amplitude of the reference corrected voltage waveform 310.

[0039] At time t1 304, the uncorrected voltage waveform 320 ends the ramping portion 330 of the ramp period 334 by reaching the uncorrected peak level 342 and begins to decrease toward the low voltage level of the ramp period. In some embodiments, between time t1 304 and time t2 306, the slope of the uncorrected voltage waveform 320 is greater than the corresponding slope of the reference corrected voltage waveform 310, and between time t1 304 and time t2 306, the amplitude of the uncorrected voltage waveform 320 is greater than the corresponding amplitude of the reference corrected voltage waveform 310.

[0040] At time t2 306, the uncorrected voltage waveform 320 reaches the low voltage level of the ramp period. In some embodiments, with the uncorrected voltage level remaining uncorrected, the uncorrected voltage waveform 320 begins to increase toward the uncorrected peak level 342 according to the operation at time t0 302. Alternatively, in some embodiments, at time t2 306, the voltage waveform may begin a correction process according to the present embodiment and continue to time t0 401.

[0041] Figure 4 A second example timing diagram including a first partially corrected voltage waveform and a second partially corrected voltage waveform according to the present embodiment is illustrated. Figure 4 As illustrated in the example of FIG, the example timing diagram 400 includes a first partially corrected voltage waveform 420, a second partially corrected voltage waveform 422, and a reference corrected voltage waveform 310. In some embodiments, the first partially corrected voltage waveform 420, the second partially corrected voltage waveform 422, and the corrected waveform 310 reach an uncorrected peak level 342, a first partially corrected peak level 430, and a corrected peak level 340, respectively. In some embodiments, the first partially corrected voltage waveform 420 is within a first ramp cycle period 410, and the second partially corrected voltage waveform 422 is within a second ramp cycle period 412. In some embodiments, the first ramp cycle period 410 includes a first calibration timing window 440, and the second ramp cycle period 412 includes a second calibration timing window 442. In some embodiments, at least one of the example systems 100, 600, and the example device iteratively performs full-cycle error correction over multiple ramp cycles. In some embodiments, full-cycle error correction is iterated from the uncorrected voltage waveform 320 to a corrected voltage waveform that substantially corresponds to the reference corrected voltage waveform 310. It should be understood that the reference corrected waveform is shown in the timing diagram 400 for illustrative purposes and need not be present with the first partially corrected voltage waveform 420 and the second partially corrected voltage waveform 422.

[0042] At time t0 401, the first partially corrected voltage waveform 420 begins the ramping portion of the ramp period 410 at a low voltage level and begins increasing toward the uncorrected peak level 342. In some embodiments, the uncorrected peak level 342 is greater than both the reference corrected peak level 340 and the first partially corrected peak level 430. In some embodiments, between time t0 401 and time t1 403, the slope of the first partially corrected voltage waveform 420 is greater than the corresponding slope of the reference corrected voltage waveform 310, and between time t0 401 and time t1 403, the amplitude of the first partially corrected voltage waveform 420 is greater than the corresponding amplitude of the reference corrected voltage waveform 310. In some embodiments, the slope and amplitude of the first partially corrected voltage waveform 420 correspond, respectively, to the slope and amplitude of the uncorrected voltage waveform 320 between time t0 302 and time t1 304. In some embodiments, there is no ramp correction applied by the ramp compensator 130 or any of its components between time t0 401 and time t2 403 because the first iteration of ramp compensation has not yet occurred.

[0043] At time t1 403, the first partially corrected voltage waveform 420 begins the ramp-down portion of the ramp period 410 and the first calibration timing window 440. In some embodiments, the first partially corrected voltage waveform 420 thus reaches the uncorrected peak level 342 and begins to decrease toward the first partially corrected ramp-down level. In some embodiments, the first partially corrected ramp-down level is less than the uncorrected peak level 342, the reference corrected peak level 340, and the first partially corrected peak level 430. In some embodiments, between time t1 403 and time t2 405, the slope of the first partially corrected voltage waveform 420 is greater than the corresponding slope of the reference corrected voltage waveform 310, and between time t1 403 and time t2 405, the amplitude of the first partially corrected voltage waveform 420 is greater than the corresponding amplitude of the reference corrected voltage waveform 310. In some embodiments, the slope of the first partially corrected voltage waveform 420 between time t1 403 and time t2 405 is greater than the slope of the uncorrected voltage waveform 320 between time t1 304 and time t2 306 .

[0044] At time t2 405, the first partially corrected voltage waveform 420 begins the corrected ramp-down portion of the ramp period 410 and exits the first calibration timing window 440. In some embodiments, the first partially corrected voltage waveform 420 thus continues to decrease from the first partially corrected ramp-down level to the low voltage level of the ramp period. In some embodiments, between time t2 405 and time t3 402, the slope of the first partially corrected voltage waveform 420 substantially corresponds to or is substantially equal to the corresponding slope of the reference corrected voltage waveform 310, and between time t2 405 and time t3 402, the amplitude of the first partially corrected voltage waveform 420 substantially corresponds to or is substantially equal to the corresponding amplitude of the reference corrected voltage waveform 310.

[0045] At time t3 402, the second partially corrected voltage waveform 422 begins the ramping portion of the ramp period 412 from a low voltage level and begins increasing toward the first partially corrected peak level 430. In some embodiments, between time t3 402 and time t4 404, the slope of the second partially corrected voltage waveform 422 is greater than the corresponding slope of the reference corrected voltage waveform 310 and less than the corresponding slope of the uncorrected voltage waveform 320. In some embodiments, between time t3 402 and time t4 404, the amplitude of the partially corrected voltage waveform 422 is greater than the corresponding amplitude of the reference corrected voltage waveform 310 and less than the corresponding amplitude of the uncorrected voltage waveform 320. In some embodiments, thus, in response to a first iteration of ramp compensation, a first ramp correction is applied by the ramp compensator 130 or any component thereof between time t3 402 and time t4 404. In some implementations, ramp compensation is applied at least between time t3 402 and time t4 404 in response to, among other things, measuring the first partially corrected voltage waveform 420 within the first calibration timing window 440 .

[0046] At time t4 404, the second partially corrected voltage waveform 422 begins the ramp-down portion of the ramp period 412 and the second calibration timing window 442. In some embodiments, the second partially corrected voltage waveform 422 thus reaches the first partially corrected peak level 430 and begins to decrease toward the second partially corrected ramp-down level. In some embodiments, the second partially corrected ramp-down level is less than the uncorrected peak level 342, the reference corrected peak level 340, and the first partially corrected peak level 430. In some embodiments, between time t4 404 and time t5 406, the slope of the second partially corrected voltage waveform 422 is greater than the corresponding slope of the reference corrected voltage waveform 310, and between time t4 404 and time t5 406, the amplitude of the second partially corrected voltage waveform 422 is greater than the corresponding amplitude of the reference corrected voltage waveform 310. In some embodiments, the slope of the second partially corrected voltage waveform 422 between time t4 404 and time t5 406 is greater than the corresponding slope of the uncorrected voltage waveform 320 between time t1 304 and time t2 306 .

[0047] At time t5 406, the second partially corrected voltage waveform 422 begins the corrected ramp-down portion of the ramp cycle 412 and exits the second calibration timing window 442. In some embodiments, the second partially corrected voltage waveform 422 thus continues to decrease from the second partially corrected ramp-down level to the low voltage level of the ramp cycle. In some embodiments, between time t5 406 and time t6 501, the slope of the second partially corrected voltage waveform 422 substantially corresponds to or is substantially equal to the corresponding slope of the reference corrected voltage waveform 310, and between time t5 406 and time t6 501, the amplitude of the second partially corrected voltage waveform 422 substantially corresponds to or is substantially equal to the corresponding amplitude of the reference corrected voltage waveform 310. In some embodiments, in response to the reduction in the error of the second partially corrected voltage waveform relative to the first partially corrected voltage waveform 420, the duration of the second calibration timing window 442 is less than the duration of the first calibration timing window 440.

[0048] Figure 5 The example shows the connection Figure 4 The third example timing diagram following the example timing diagram of , the third example timing diagram including the third partially corrected voltage waveform and the corrected voltage waveform, as shown by Figure 5As illustrated in the example of FIG, example timing diagram 500 includes a third partially corrected voltage waveform 520, a corrected voltage waveform 522, and a reference corrected voltage waveform 310. In some embodiments, the third partially corrected voltage waveform 520 reaches a second partially corrected peak level 530. In some embodiments, the corrected voltage waveform 522 and the reference corrected waveform 310 reach a corrected peak level 340. In some embodiments, the third partially corrected voltage waveform 520 is within a third ramp cycle period 510, and the corrected voltage waveform 522 is within a fourth ramp cycle period 512. In some embodiments, the third ramp cycle period 510 includes a third calibration timing window 540, and the fourth ramp cycle period 512 includes a fourth calibration timing window 542. It should be understood that the reference corrected waveform is shown in timing diagram 500 for illustrative purposes and need not be present with the third partially corrected voltage waveform 520 and the corrected voltage waveform 522.

[0049] At time t6 501, the third partially corrected voltage waveform 520 begins the ramping portion of the ramp period 510 from a low voltage level and begins increasing toward the second partially corrected peak level 530. In some embodiments, between time t6 501 and time t7 503, the third partially corrected voltage waveform 520 is less than the corresponding slope of the reference corrected voltage waveform 310 and less than the corresponding slope of the uncorrected voltage waveform 320. In some embodiments, between time t6 501 and time t7 503, the partially corrected voltage waveform 520 is less than the corresponding amplitude of the reference corrected voltage waveform 310 and less than the corresponding amplitude of the uncorrected voltage waveform 320. In some embodiments, thus, in response to a second iteration of ramp compensation, a second ramp correction is applied by the ramp compensator 130 or any component thereof between time t6 501 and time t7 503. In some embodiments, ramp compensation is applied at least between time t6 501 and time t7 503 in response to, among other things, measuring the second partially corrected voltage waveform 422 within the second calibration timing window 442. In some embodiments, the third partially corrected voltage waveform 502 represents an iteration that includes an overcorrection of the second partially corrected voltage waveform 422.

[0050] At time t7 503, the third partially corrected voltage waveform 520 begins the ramp-down portion of the ramp period 510 and the third calibration timing window 540. In some embodiments, the third partially corrected voltage waveform 520 thus reaches and substantially maintains the second partially corrected peak level 530. In some embodiments, the third partially corrected voltage waveform does not continue to decrease further because the second partially corrected peak level 530 is below the reference corrected peak level 340. In some embodiments, the second partially corrected peak level 530 is less than the uncorrected peak level 342 and the first partially corrected peak level 430, and is substantially equal to or substantially corresponds to the reference corrected peak level 340. In some embodiments, between time t7 503 and t8 505, the slope of the third partially corrected voltage waveform 520 is substantially zero, and between time t7 503 and t8 505, the amplitude of the third partially corrected voltage waveform 520 is less than the corresponding amplitude of the reference corrected voltage waveform 310.

[0051] At time t8 505, the third partially corrected voltage waveform 520 begins the corrected ramp-down portion of the ramp period 510 and exits the third calibration timing window 540. In some embodiments, the third partially corrected voltage waveform 520 begins decreasing from the third partially corrected ramp-down level toward the low voltage level of the ramp period. In some embodiments, between time t8 505 and time t9 502, the slope of the third partially corrected voltage waveform 520 substantially corresponds to or is substantially equal to the corresponding slope of the reference corrected voltage waveform 310, and between time t8 505 and time t9 502, the amplitude of the third partially corrected voltage waveform 520 substantially corresponds to or is substantially equal to the corresponding amplitude of the reference corrected voltage waveform 310.

[0052] At time t9 502, the corrected voltage waveform 522 begins the ramping portion of the ramp period 512 from a low voltage level and begins increasing toward the reference corrected peak level 340. In some embodiments, between time t9 502 and t10 504, the slope of the corrected voltage waveform 522 substantially corresponds to or is substantially equal to the corresponding slope of the reference corrected voltage waveform 310 and is less than the corresponding slope of the uncorrected voltage waveform 320. In some embodiments, between time t9 502 and t10 504, the amplitude of the corrected voltage waveform 522 substantially corresponds to or is substantially equal to the corresponding amplitude of the reference corrected voltage waveform 310 and is less than the corresponding amplitude of the uncorrected voltage waveform 320. In some embodiments, thus, in response to a third iteration of ramp compensation, a third ramp correction is applied by the ramp compensator 130 or any component thereof between times t9 502 and t10 504. In some embodiments, ramp compensation is applied at least between time t9 502 and t10 504 in response to, among other things, measuring the third partially corrected voltage waveform 520 within the third calibration timing window 540. In some embodiments, the corrected voltage waveform 522 represents an iteration that includes a precise correction of the second partially corrected voltage waveform 422.

[0053] At time t10 504, the corrected voltage waveform 552 begins the ramp-down portion of the ramp period 512 and the fourth calibration timing window 542. In some embodiments, the corrected voltage waveform 522 thus reaches the reference corrected peak level 340 and begins to decrease substantially toward the lower voltage level of the ramp period. In some embodiments, between time t10 504 and time t11 506, the slope of the corrected voltage waveform 522 substantially corresponds to or is substantially equal to the corresponding amplitude of the reference corrected voltage waveform 310.

[0054] At time t11 506, the corrected voltage waveform continues to decrease toward the low voltage level of the ramp cycle. In some embodiments, between time t11 and time t12, the slope and amplitude of the corrected voltage waveform 522 substantially correspond to or are substantially equal to the corresponding slope and amplitude of the reference corrected voltage waveform 310, respectively. At time t12 508, the corrected voltage waveform 522 reaches the low voltage level of the ramp cycle. In some embodiments, while the corrected voltage level remains corrected and no further modification iterations are performed on the system capacitors, the corrected voltage waveform 522 begins to increase toward the reference corrected peak level 340 according to the operation at time t9 502.

[0055] Figure 6 Another example system according to this embodiment is shown. Figure 6As illustrated in the example of FIG, example system 600 includes converter circuit 110, ramp-down compensator 120, ramp-up compensator 130, inductor node 102, input node 104, low-pass filter 610, analog-to-digital converter 620, digital filter 630, and output node 632. Low-pass filter 610 is operable to minimize analog noise in the corrected inductor voltage. In some embodiments, low-pass filter 610 includes an input operatively coupled to output 106 and an output operatively coupled to an input of analog-to-digital converter 620. In some embodiments, low-pass filter 610 includes one or more logic or electronic devices, including, but not limited to, integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, and the like. It should be understood that any electrical, electronic, or similar device or component associated with low-pass filter 610 may also be associated with, integrated with, integrable with, replaced by, supplemented by, or otherwise augmented by one or more other components in example system 600 or any of its components.

[0056] The analog-to-digital converter 620 is operable to convert the received corrected voltage or the filtered corrected voltage into a digital corrected voltage. In some embodiments, the digital corrected voltage is a quantized waveform. In some embodiments, the analog-to-digital converter 620 includes an input operably coupled to the low-pass filter 610 and an output operably coupled to the digital filter 630. In some embodiments, the analog-to-digital converter 620 includes one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device or component associated with the analog-to-digital converter 620 may also be associated with, integrated with, may be integrated with, replaced by, supplemented by, or otherwise be supplemented by one or more other components in the example system 600 or any of its components.

[0057] The digital filter 630 is operable to minimize digital noise in the digital corrected inductor voltage. In some embodiments, the digital filter 630 includes an output operably coupled to the output 632 and an input operably coupled to the output of the analog-to-digital converter 620. In some embodiments, the digital filter 630 includes one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device or component associated with the digital filter 630 may also be associated with, integrated with, integrable with, replaced by, supplemented by, or otherwise augmented by one or more other components in the example system 600 or any of its components.

[0058] Figure 7An example method for performing full-cycle error correction on an inductor current measurement of a switching regulator according to the present embodiment is illustrated. In some embodiments, at least one of the example device 200 and the example systems 100 and 600 performs the method 700 according to the present embodiment. In some embodiments, the method 700 begins at step 710.

[0059] At step 710, the example system obtains an inductor voltage at an inductor node. In some embodiments, at least one of the ramp-down compensator 120 and the ramp-up compensator 130 obtains the inductor voltage. In some embodiments, step 710 includes step 712. At step 712, the example system obtains the inductor voltage via a conversion circuit, which is operably coupled to a voltage regulator. Method 700 then proceeds to step 720. At step 720, the example system generates a valley current sense voltage. In some embodiments, at least one of the ramp-down compensator 120 and the valley current sense circuit 220 generates the valley current sense voltage. In some embodiments, step 720 includes step 722. At step 722, the example system generates the valley current sense voltage based on the inductance of the inductor, which is operably coupled to the inductor node. Method 700 then proceeds to step 730. At step 730, the example system generates the ramp-down compensation voltage. In some embodiments, at least one of the ramp-down compensator 120 and the ramp-down buffer 222 generates a ramp-down compensation voltage. In some embodiments, step 730 includes step 732. At step 732, the example system generates the ramp-down compensation voltage based on at least one of the valley current sense voltage and the inductor voltage. Method 700 then proceeds to step 740. At step 740, the example system applies the ramp-down compensation voltage to the inductor node. In some embodiments, at least one of the ramp-down compensator 120 and the ramp-down buffer 222 applies the ramp-down compensation voltage via a feedback line. Method 700 then proceeds to step 802.

[0060] Figure 8 The example shows the connection Figure 7 An example method for full-cycle error correction of inductor current measurements for a switching regulator is provided below. In some embodiments, at least one of the example device 200 and the example systems 100 and 600 performs method 800 according to this embodiment. In some embodiments, method 800 begins at step 802. At step 802, method 800 proceeds to step 810.

[0061] At step 810, the example system obtains a ramp calibration window. In some embodiments, at least one of the ramp compensator 130 and the capacitor calibration circuit 232 obtains the ramp calibration window. In some embodiments, step 810 includes step 812. At step 812, the example system obtains the ramp calibration timing window. Method 800 then proceeds to step 820.

[0062] At step 820, the example system generates a differential voltage associated with the calibration window. In some embodiments, at least one of the ramp compensator 130 and the capacitor calibration circuit 232 generates the differential voltage. In some embodiments, step 820 includes step 822. At step 822, the example system generates the differential voltage based at least in part on at least one of the valley current sense voltage and the inductor voltage. Method 800 then proceeds to step 830.

[0063] At step 830, the example system determines whether the valley current sense voltage is greater than the inductor voltage. In some embodiments, the ramp-down buffer 222 determines whether the valley current sense voltage is greater than the inductor voltage. Based on determining that the valley current sense voltage is greater than the inductor voltage, the method 800 proceeds to step 832. Alternatively, based on determining that the valley current sense voltage is not greater than the inductor voltage, the method 800 proceeds to step 840. At step 832, the example system reduces the capacitance of the system capacitor. In some embodiments, at least one of the ramp compensator 130 and the capacitor calibration circuit 232 reduces the capacitance of the system capacitor 230. The method 800 then proceeds to step 802.

[0064] At step 840, the example system determines whether the valley current sense voltage is less than the inductor voltage. In some embodiments, the ramp-down buffer 222 determines whether the valley current sense voltage is greater than the inductor voltage. In some embodiments, the ramp-down buffer 222 determines whether the valley current sense voltage is less than the inductor voltage. Based on determining that the valley current sense voltage is less than the inductor voltage, the method 800 continues to step 842. Alternatively, based on determining that the valley current sense voltage is not less than the inductor voltage, the method 800 continues to step 850. At step 842, the example system increases the capacitance of the system capacitor. In some embodiments, at least one of the ramp compensator 130 and the capacitor calibration circuit 232 increases the capacitance of the system capacitor 230. The method 800 then continues to step 850.

[0065] At step 850, the example system applies the trimming voltage to the inductor voltage. In some embodiments, the converter circuit 110 applies the trimming voltage to the inductor voltage. The method 800 then continues to step 802. Alternatively, in some embodiments, the method 800 ends at step 850. It should be understood that the example system can optionally perform step 850.

[0066] The subject matter described herein sometimes illustrates different components contained within or connected to different other components. It should be understood that the architecture depicted in this manner is illustrative and that many other architectures that achieve the same functionality can actually be implemented. Conceptually, any arrangement of components that achieve the same functionality is effectively "associated" to achieve the desired functionality. Therefore, any two components combined herein to achieve a specific functionality can be considered to be "associated" with each other to achieve the desired functionality, regardless of the architecture or intermediate components. Similarly, any two components that are so associated can also be considered to be "operably connected" or "operably coupled" to achieve the desired functionality, and any two components that can be so associated can also be considered to be "operably coupled" to achieve the desired functionality. Specific examples of operable coupling include, but are not limited to, physically interactive and / or physically interactive components and / or wirelessly interactive and / or wirelessly interactive components and / or logically interactive and / or logically interactive components.

[0067] Regarding the use of plural and / or singular terms in this document, those skilled in the art can convert the plural to the singular and / or the singular to the plural depending on the context and / or application. For clarity, various singular / plural permutations may be expressly set forth herein.

[0068] Those skilled in the art will understand that, in general, the terms used herein, and especially in the appended claims (e.g., the bodies of the appended claims), are generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “comprising” should be interpreted as “including but not limited to,” etc.).

[0069] Although the drawings and description may illustrate a particular order of method steps, unless otherwise specified above, the order of these steps may vary from that depicted and described. In addition, unless otherwise specified above, two or more steps may be performed simultaneously or partially simultaneously. Such variations may depend, for example, on the software and hardware systems selected and on the designer's choice. All such variations are within the scope of this disclosure. Similarly, software implementations of the described methods may be accomplished using standard programming techniques with rule-based logic and other logic to accomplish the various connection steps, processing steps, comparison steps, and decision steps.

[0070] Those skilled in the art will further understand that if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent exists. For example, to aid understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim introduced by the indefinite article "a" or "an" limits any particular claim containing such introduced claim to an invention containing only one such recitation, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should generally be interpreted to mean "at least one" or "one or more"); the same is true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of introduced claim recitations is expressly recited, those skilled in the art will recognize that such recitation should generally be interpreted to mean at least the recited number (e.g., the unmodified recitation of "two recitations," without other modifiers, generally means at least two recitations, or two or more recitations).

[0071] Furthermore, in those instances where a convention similar to “at least one of A, B, and C, etc.” is used, such construction is generally done in a sense that one skilled in the art would understand the convention (e.g., “a system having at least one of A, B, and C” would include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.). In those instances where a convention similar to “at least one of A, B, or C, etc.” is used, such construction is generally done in a sense that one skilled in the art would understand the convention (e.g., “a system having at least one of A, B, or C” would include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.). Those skilled in the art would further understand that, in practice, any disjunctive word and / or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one, either, or both of the terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0072] Furthermore, use of the words "approximately," "about," "approximately," "substantially," etc., refers to plus or minus ten percent unless otherwise indicated.

[0073] The foregoing description of illustrative embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limiting with respect to the precise forms disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the disclosed embodiments. It is intended that the scope of the invention be defined by the following claims and their equivalents.

Claims

1. A method for performing full-cycle error correction on an inductor current measurement of a switching regulator, the method comprising: generating a ramp-down compensation voltage based at least in part on an inductor voltage received at an inductor node and a valley current sensing voltage generated by a valley current sensing circuit; applying the ramp-down compensation voltage to the inductor node; as well as Based on a first determination that a valley current sense voltage is not equal to the inductor voltage, a predetermined capacitance of a system capacitor operatively coupled to the inductor node is modified to a first modified capacitance.

2. The method of claim 1 , wherein the first determination that the valley current sensing voltage is not equal to the inductor voltage comprises determining that the valley current sensing voltage is greater than the inductor voltage and the first modified capacitance is less than the predetermined capacitance of the system capacitor.

3. The method of claim 1 , wherein the first determination that the valley current sensing voltage and the inductor voltage are not equal comprises determining that the valley current sensing voltage is less than the inductor voltage and the first modified capacitance is greater than the predetermined capacitance of the system capacitor.

4. The method according to claim 1, further comprising: Based on a second determination that the valley current sense voltage and the inductor voltage are not equal, a predetermined capacitance of a system capacitor operatively coupled to the inductor node is modified to a second modified capacitance.

5. The method of claim 4 , wherein the second determination that the valley current sensing voltage and the inductor voltage are not equal comprises determining that the valley current sensing voltage is greater than the inductor voltage and the second modified capacitance is less than the predetermined capacitance of the system capacitor.

6. The method of claim 4 , wherein the second determination that the valley current sensing voltage and the inductor voltage are not equal comprises determining that the valley current sensing voltage is less than the inductor voltage, and modifying the capacitance of the system capacitor comprises: The capacitance of the system capacitor is increased.

7. The method according to claim 1, further comprising: The valley current sensing voltage is generated based at least in part on an inductance of the inductor.

8. The method according to claim 1, further comprising: The valley current sensing voltage and the inductor voltage are obtained within a calibrated timing window.

9. The method according to claim 1, further comprising: generating a differential voltage based at least in part on the valley current sensing voltage and the inductor voltage, Wherein the first determination that the valley current sense voltage and the inductor voltage are not equal includes determining that the differential voltage is not equal to zero.

10. The method according to claim 1, further comprising: A trimming voltage is applied to the inductor voltage.

11. A device comprising: a ramp-down compensator operable to generate a ramp-down compensation voltage based at least in part on an inductor voltage received at an inductor node and a valley current sensing voltage generated by a valley current sensing circuit, and to apply the ramp-down compensation voltage to the inductor node; as well as a ramp-up compensator comprising a system capacitor operably coupled to the inductor node, the ramp-up compensator operably coupled to the ramp-down compensator and operable to modify a predetermined capacitance of the system capacitor to a first modified capacitance based on a first determination that a valley current sense voltage and the inductor voltage are unequal.

12. The apparatus of claim 11 , wherein the first determination that the valley current sense voltage is not equal to the inductor voltage comprises determining that the valley current sense voltage is greater than the inductor voltage and the first modified capacitance is less than the predetermined capacitance of the system capacitor.

13. The apparatus of claim 11, wherein the first determination that the valley current sense voltage and the inductor voltage are not equal comprises determining that the valley current sense voltage is less than the inductor voltage and the first modified capacitance is greater than the predetermined capacitance of the system capacitor.

14. The apparatus of claim 11, wherein the ramp compensator is further operable to modify a predetermined capacitance of a system capacitor operably coupled to the inductor node to a second modified capacitance based on a second determination that the valley current sense voltage and the inductor voltage are not equal.

15. The apparatus of claim 14, wherein the second determination that the valley current sense voltage is not equal to the inductor voltage comprises determining that the valley current sense voltage is greater than the inductor voltage and the second modified capacitance is less than the predetermined capacitance of the system capacitor.

16. The apparatus of claim 14, wherein the second determination that the valley current sensing voltage is not equal to the inductor voltage comprises determining that the valley current sensing voltage is less than the inductor voltage and the second modified capacitance is greater than the predetermined capacitance of the system capacitor. 17 . The apparatus of claim 11 , wherein the ramp-down compensator is further operable to generate the valley current sensing voltage based at least in part on an inductance of the inductor.

18. The apparatus of claim 11 , wherein the ramp compensator is further operable to generate a differential voltage based at least in part on the valley current sensing voltage and the inductor voltage, and wherein the first determination that the valley current sensing voltage and the inductor voltage are not equal comprises determining that the differential voltage is not equal to zero.

19. The apparatus according to claim 11, further comprising: A converter circuit is operatively coupled to the ramp-down compensator and the ramp-up compensator and is operable to apply a trim voltage to the inductor voltage.

20. A method for performing full-cycle error correction on an inductor current measurement of a switching regulator, the method comprising: generating a ramp-down compensation voltage based at least in part on an inductor voltage received at an inductor node and a valley current sensing voltage generated by a valley current sensing circuit; applying the ramp-down compensation voltage to the inductor node; reducing a capacitance of a system capacitor operatively coupled to the inductor node based on a first determination that a valley current sense voltage is greater than the inductor voltage; as well as Based on a second determination that the valley current sense voltage is less than the inductor voltage, the capacitance of the system capacitor is increased.

Images