Cache storage device and operating method thereof, system including cache storage device

Abstract

A cache storage device is disclosed, including a cache circuit and a path prediction circuit. The cache circuit generates a cache hit signal indicating whether target data corresponding to an accessed address is stored in a cache line, and in path prediction mode, performs the current cache access operation primarily on candidate paths based on candidate path signals indicating candidate paths. The path prediction circuit stores accumulated information based on cache hit signals provided during previous cache access operations, by accumulating cache hit results indicating whether target data is stored in a path and path prediction hit results indicating whether target data is stored in a candidate path. In path prediction mode, the path prediction circuit generates candidate path signals based on the accumulated information by determining candidate paths for the current cache access operation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0010921, filed with the Korean Intellectual Property Office (KIPO) on January 30, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention relate generally to semiconductor integrated circuits, and more specifically, to cache storage devices, systems including the cache storage devices, and methods of operating the cache storage devices. Background Technology

[0004] Accessing the processor's cache storage device consumes significant power. The cache storage device includes a data array with multiple sets, such that each set includes multiple cache lines (e.g., storage locations). The cache storage device also includes multiple paths, such that each path includes a driver corresponding to the multiple cache lines. In response to an instruction to access data stored in the cache storage device, all drivers corresponding to the multiple paths are enabled (e.g., activated) to drive a specific set of the data array to a multiplexer.

[0005] In parallel (e.g., concurrently) with all drivers enabled, a tag lookup operation is performed to identify a specific cache line within the data array. Based on the result of the tag lookup operation, data provided via a single driver (corresponding to a single cache line) is selected as the output of the multiplexer. Assuming that only data from a single cache line is output based on this instruction, performing a tag lookup operation on all paths for the set driver could result in power inefficiency. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a cache storage device includes a cache circuit and a path prediction circuit. The cache circuit includes multiple paths, and each of the multiple paths includes multiple cache lines corresponding to multiple sets. The cache circuit generates a cache hit signal indicating whether target data corresponding to an access address is stored in one of the multiple cache lines, and in path prediction mode, performs a current cache access operation for a candidate path based on a candidate path signal indicating candidate paths among the multiple paths. The path prediction circuit stores accumulated information based on cache hit signals provided during multiple previous cache access operations, by accumulating cache hit results indicating whether target data is stored in one of the multiple paths and path prediction hit results indicating whether target data is stored in one of the candidate paths. In path prediction mode, the path prediction circuit generates a candidate path signal based on the accumulated information by determining candidate paths for the current cache access operation.

[0007] According to an exemplary embodiment of the present invention, a system includes: one or more processors; a main storage device configured to store data used by the one or more processors; and a cache storage device configured to store a portion of the data stored in the main memory and configured to be accessed by the one or more processors prior to accessing the main storage device by the one or more processors. The cache storage device includes cache circuitry and path prediction circuitry. The cache circuitry includes multiple paths, and each of the multiple paths includes multiple cache lines corresponding to multiple sets. The cache circuitry generates cache hit signals indicating whether target data corresponding to an access address is stored in the multiple cache lines, and performs a current cache access operation for a candidate path based on candidate path signals indicating candidate paths among the multiple paths in path prediction mode. The path prediction circuitry stores accumulated information based on cache hit signals provided during multiple previous cache access operations by accumulating cache hit results indicating whether target data is stored in one of the multiple paths and path prediction hit results indicating whether target data is stored in one of the candidate paths. In path prediction mode, the path prediction circuitry generates candidate path signals based on the accumulated information by determining candidate paths for the current cache access operation.

[0008] According to an exemplary embodiment of the present invention, a method for operating a cache storage device comprising multiple paths, each of the multiple paths comprising multiple cache lines corresponding to multiple sets, the method comprising: generating a hit signal indicating whether target data corresponding to an access address is stored in the multiple cache lines; storing accumulated information based on cache hit signals provided during multiple previous cache access operations by accumulating cache hit results indicating whether target data is stored in one of the multiple paths and path prediction hit results indicating whether target data is stored in one of the candidate paths; generating a candidate path signal based on the accumulated information in a path prediction mode by determining candidate paths for the current cache access operation in the multiple paths; and performing the current cache access operation for the candidate path based on the candidate path signal in the path prediction mode.

[0009] According to an exemplary embodiment of the present invention, a method for operating a cache storage device comprising multiple paths, each of the multiple paths comprising multiple cache lines corresponding to multiple sets, the method comprising: receiving a prediction mode signal and a candidate path signal; determining whether the prediction mode signal indicates a path prediction mode; determining whether the candidate path signal includes candidate paths among the multiple paths; performing a primary cache access operation for the candidate path; and determining whether a first cache hit signal for the primary cache access operation indicates a cache hit. Attached Figure Description

[0010] The above and other features of the inventive concept will become clearer from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0011] Figure 1 This is a block diagram illustrating an exemplary embodiment of a cache storage device according to a concept conceived in this invention.

[0012] Figure 2 This is a flowchart illustrating a method for operating a cache storage device according to an exemplary embodiment of the present invention.

[0013] Figure 3 This is a diagram illustrating a hierarchical cache structure of a system according to an exemplary embodiment of the present invention.

[0014] Figure 4 This is a diagram illustrating the cache circuitry included in a cache storage device according to an exemplary embodiment of the present invention.

[0015] Figure 5 This is a diagram illustrating a path prediction circuit included in a cache storage device according to an exemplary embodiment of the present invention.

[0016] Figure 6 This is a flowchart illustrating cache access operations of a cache storage device according to an exemplary embodiment of the present invention.

[0017] Figure 7 This is a diagram illustrating a main cache access operation of a cache storage device according to an exemplary embodiment of the present invention.

[0018] Figure 8 This is a diagram illustrating a secondary cache access operation of a cache storage device according to an exemplary embodiment of the present invention.

[0019] Figure 9 This is a diagram illustrating normal cache access operation of a cache storage device according to an exemplary embodiment of the present invention.

[0020] Figure 10 This is a diagram used to describe diagnostic bit pairs stored in a cache storage device according to an exemplary embodiment of the present invention.

[0021] Figure 11 This is a diagram illustrating a differential diagnostic register included in a cache storage device according to an exemplary embodiment of the present invention.

[0022] Figure 12 This is a diagram illustrating a path-level buffer included in a cache storage device according to an exemplary embodiment of the present invention.

[0023] Figure 13 This is a diagram illustrating an auxiliary inference buffer included in a cache storage device according to an exemplary embodiment of the present invention.

[0024] Figure 14 This is a diagram illustrating cache occupancy information stored in a cache storage device according to an exemplary embodiment of the present invention.

[0025] Figure 15 This is a diagram illustrating the effective rereference interval of a cache storage device according to an exemplary embodiment of the present invention.

[0026] Figure 16 This is a diagram illustrating a path prediction window stored in a cache storage device according to an exemplary embodiment of the present invention.

[0027] Figure 17 This is a diagram illustrating a priority update operation of a cache storage device according to an exemplary embodiment of the present invention.

[0028] Figure 18 This is a diagram illustrating a differential diagnostic register included in a cache storage device according to an exemplary embodiment of the present invention.

[0029] Figure 19 This is a diagram illustrating a path-level buffer included in a cache storage device according to an exemplary embodiment of the present invention.

[0030] Figure 20 This is a diagram illustrating a priority update operation of a cache storage device according to an exemplary embodiment of the present invention.

[0031] Figure 21 This is a block diagram illustrating an exemplary system according to a concept of the present invention. Detailed Implementation

[0032] Exemplary embodiments of the present invention provide a cache storage device, a system including the cache storage device, and a method for operating the cache storage device, capable of performing efficient path prediction.

[0033] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings. Throughout this application, similar reference numerals may refer to similar elements.

[0034] Figure 1 This is a block diagram illustrating an exemplary embodiment of a cache storage device according to a concept conceived in this invention.

[0035] refer to Figure 1 The cache storage device 10 may include a cache circuit 20 and a path prediction circuit 30.

[0036] The cache circuit 20 may include a cache memory CMEM 50 for storing data and tags, and a cache controller CCON 40 for controlling the overall operation of the cache memory 50.

[0037] The cache circuit 20 can receive a processor identifier (PID) indicating the processor or processor core associated with the current cache access operation, an access address (ADD) associated with the current cache access operation, and control signals or information (SPM, SCW, and SHD) provided from the path prediction circuit 30. The cache circuit 20 can generate a cache hit signal (HCT) based on the processor identifier (PID), the access address (ADD), and the control signals (SPM, SCW, and SHD), wherein the cache hit signal (HCT) indicates whether the target data (SDD) corresponding to the access address (ADD) is stored in the cache memory 50.

[0038] When the target data corresponding to the access address ADD is stored in the cache memory 50, the cache circuit 20 can read and provide the target data SDT. When the target data SDT corresponding to the access address ADD is not stored in the cache memory 50, the cache circuit 20 can store new data NDT in the cache memory 50.

[0039] Cache memory 50 may have a set-associated cache structure comprising multiple paths, such that each path includes multiple cache lines corresponding to multiple sets. See below for reference. Figure 4 Describe the cache structure associated with the collection.

[0040] The path prediction circuit 30 can receive the processor identifier PID, access address ADD, and cache hit signal CHT, and generate control signals or information SPM, SCW, and SHD to control the cache circuit 20.

[0041] Figure 2 This is a flowchart illustrating a method for operating a cache storage device according to an exemplary embodiment of the present invention. Figure 2 A method for a cache structure associated with a set is shown, the cache structure associated with the set comprising multiple paths, such that each path includes multiple cache lines corresponding to multiple sets.

[0042] refer to Figure 1 and Figure 2 The cache circuit 20 can generate a cache hit signal CHT (S100) indicating whether the target data SDT corresponding to the access address ADD is stored in multiple cache lines.

[0043] The path prediction circuit 30 can store accumulated information ACCI (S200) based on cache hit signals CHT provided during multiple previous cache access operations, by accumulating cache hit results indicating whether the target data SDT is stored in one of multiple paths and path prediction hit results indicating whether the target data SDT is stored in one of the candidate paths. In an exemplary embodiment of the inventive concept, the path prediction circuit 30 can store the accumulated information ACCI as multiple diagnostic bit pairs, such that each diagnostic bit pair includes a cache hit bit indicating a cache hit result and a path prediction hit bit indicating a cache hit result. Reference will be made below. Figure 10 and Figure 11 Describe the diagnostic position pairs.

[0044] The path prediction circuit 30 can generate a candidate path signal SCW (S300) based on accumulated information ACCI in path prediction mode by determining one or more candidate paths for the current cache access operation among multiple paths. In an exemplary embodiment of the present invention, the path prediction circuit 30 can generate a prediction mode signal SPM indicating whether the path prediction mode is enabled or disabled based on the accumulated information ACCI, and provide the prediction mode signal SPM to the cache circuit 20.

[0045] In path prediction mode, cache circuit 20 can perform current cache access operations primarily on candidate paths among multiple paths based on the candidate path signal SCW (S400). Here, "primarily perform current cache access operations" means that cache circuit 20 performs primary cache access operations on candidate paths, and only performs secondary cache access operations on the remaining paths among multiple paths when the target data SDT is not stored in a candidate path. "Remaining paths" can also be referred to as "other paths". The following will refer to... Figures 6 to 9 Further description of main cache access operations.

[0046] Thus, the cache storage device 10 and the method of operating the cache storage device 10 according to the exemplary embodiment of the present invention can reduce the power consumption of the cache storage device 10 by accurately predicting candidate paths based on accumulated information ACCI.

[0047] In an exemplary embodiment of the present invention, the path prediction circuit 30 may store evicted data associated with evicted data that is replaced by new data NDT and deleted from multiple cache lines during a valid rereference interval. The path prediction circuit 30 may generate masking information SHD associated with protection data based on the evicted data, such that the protection data indicates evicted data to be written back to the cache line during the valid rereference interval. The path prediction circuit 30 may provide the masking information to the cache circuit 20, and the cache circuit 20 may prevent the deletion of protection data from the cache line at least once based on the masking information.

[0048] Thus, the cache storage device 10 and the method of operating the cache storage device 10 according to the exemplary embodiment of the present invention can reduce power consumption and enhance the performance of the cache storage device 10 by increasing cache hit rate and path prediction hit rate based on masking information related to protected data with high reuse probability.

[0049] Figure 3 This is a diagram illustrating a hierarchical cache structure of a system according to an exemplary embodiment of the present invention.

[0050] refer to Figure 3System 500 may include multiple processors PRC0 to PRCn 511, 512 and 513, multiple cache storage devices L1_0 to L1_n, L2 and L3 521, 522, 523, 530 and 540, and main memory MEM 550. In the case of a multi-core system, processors 511, 512 and 513 may be referred to as processor cores.

[0051] At least one processor and at least one cache storage device can form a processing unit, and the processing unit can be implemented as a standalone device or part of a system-on-a-chip (SoC). For example, the processing unit may include a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc.

[0052] Main memory 550 may store data used by processors 511, 512, and 513. Here, the term "data" may include instructions executed by processors 511, 512, and 513. System 500 may have a hierarchical (or multi-level) cache structure to improve access speed to instructions or data stored in main memory 550 by storing copies of instructions or data in the cache. Figure 3 A non-limiting example of a hierarchical cache structure is shown. For example, a hierarchical cache structure may include more or fewer caches, more or fewer cache tiers, or other hierarchical arrangements of caches.

[0053] A hierarchical cache architecture may include cache storage devices 521, 522, and 523 at the lowest level (e.g., L1 level 1), and cache storage devices at higher levels, such as cache storage device 530 at L2 level 2 and cache storage device 540 at L3 level 3. The L1 level 1 cache storage devices may be dedicated cache storage devices accessed specifically by processors 511, 512, and 513, respectively. The L2 level 2 and L3 level 3 cache storage devices 530 and 540 may be shared cache storage devices accessed jointly by processors 511, 512, and 513.

[0054] L3 cache storage device 540 may include multiple cache lines to store copies of data stored in main memory 550. Cache lines can be identified by a combination of indexes and paths. L3 cache storage device 540 may be implemented using faster storage elements and / or deployed logically or physically closer to processors 511, 512, and 513 than main memory 550, enabling faster or less latency-based exchange of data or information between processors 511, 512, and 513 and L3 cache storage device 540.

[0055] L2 cache storage device 530 may include multiple cache lines to store copies of data stored in main memory 550. L2 cache storage device 530 may be implemented using faster storage elements and / or may be deployed logically or physically closer to processors 511, 512, and 513 than L3 cache storage device 540, enabling faster or less latency exchange of data or information between processors 511, 512, and 513 and L2 cache storage device 530.

[0056] Each of the L1 cache storage devices 521, 522, and 523 may include multiple cache lines to store copies of data stored in main memory 550 and used by each of the processors 511, 512, and 513. Each of the L1 cache storage devices 521, 522, and 523 may be implemented using faster storage elements and / or may be deployed logically or physically closer to the processors 511, 512, and 513 than the L2 cache storage device 530, enabling faster or less latency exchange of data or information between the processors 511, 512, and 513 and the L1 cache storage devices 521, 522, and 523.

[0057] In a cache access operation, each of processors 511, 512, and 513 may send a memory access request to a corresponding L1 cache storage device 521, 522, and 523 to obtain a copy of the instructions or data stored in the corresponding L1 cache storage device. If the requested information is stored in the corresponding L1 cache storage device (e.g., as indicated by a match between the address or part of the address in the memory access request and the cache tag associated with the cache line in the corresponding L1 cache memory), the processor may access the cache line. This is conventionally referred to as a cache hit.

[0058] If the requested information is not stored in any cache line of the corresponding L1 cache storage device (commonly referred to as a cache miss), the memory access request is forwarded to L2 cache storage device 530. If the memory access request hits in L2 cache storage device 530, the processor can access the cache line in L2 cache storage device 530.

[0059] If the memory access request is not hit in L2 cache storage device 530, the memory access request is forwarded to L3 cache storage device 540. This process iterates at progressively higher levels of the cache structure until a cache hit occurs or the requested information is accessed in main memory 550.

[0060] Cache lines in L3 cache storage 540, L2 cache storage 530, and L1 cache storage 521, 522, and 523 can be replaced in response to cache misses. For example, if a memory access request from processor 511 misses in L1 cache storage 521 but hits in L2 cache storage 530, the instructions or data stored in the cache line of L2 cache storage 530 can be copied to the cache line of L1 cache storage 521, making the copied data available for subsequent memory access requests from the corresponding processor 511. If all cache lines are currently storing information, previously stored information in one of the cache lines can be evicted to make room for new information. The cache line to be evicted is selected based on a cache replacement policy. For example, the cache replacement policy can be based on a Least Recently Used (LRU) policy or a Predicted Reuse Interval (RRIP) policy.

[0061] like Figure 3 The hierarchical cache structure shown may include at least one cache storage device according to an exemplary embodiment of the present invention. In an exemplary embodiment of the present invention, reference will be made to... Figures 11 to 17 As described, the cache storage device according to an exemplary embodiment of the present invention can be applied to shared cache storage devices 530 and 540. In an exemplary embodiment of the present invention, reference will be made to... Figures 18 to 20 As described, the cache storage device according to an exemplary embodiment of the present invention can be applied to dedicated cache storage devices 521, 522 and 523.

[0062] Figure 4 This is a diagram illustrating the cache circuitry included in a cache storage device according to an exemplary embodiment of the present invention. For ease of explanation, Figure 4Only exemplary embodiments of the present invention are shown, which are used to describe the path prediction strategy and the operation based on the path prediction strategy.

[0063] refer to Figure 4 The cache circuit 20 may include a cache memory 50, a tag comparison circuit 41, a data output circuit MUX 42, an update controller UCON 43, and a cache hit determination circuit 44. Components 41, 42, 43, and 44 may be included in... Figure 1 The cache controller 40 is located in the cache controller.

[0064] The cache memory 50 may include a tag memory (TARR) and a data memory (DARR). The data memory (DARR) is stored in... Figure 3 The main memory 550 stores some data (e.g., cached data). In other words, the cached data can be the same as any of the main data stored in the main memory 550. The tag memory TARR stores tag data corresponding to the cached data stored in the data memory DARR. The tag data can indicate the actual address of the main memory 550 where the cached data is stored.

[0065] Figure 4 An example of a 4-path set-associative cache structure with four paths is shown. The tag memory (TARR) and data memory (DARR) can include multiple paths and multiple sets containing multiple cache lines, allowing each set to be selected based on the set address (SADD) included in the access address (ADD). The rows and columns of the tag memory (TARR) and data memory (DARR) indicate the sets and paths, respectively. In other words, a set is stored in the same row of both the tag memory (TARR) and data memory (DARR).

[0066] Figure 4 This illustrates a 4-path set-related cache structure implemented using m+1 sets specified by indices from 0 to m and four paths WY0 to WY3. For example... Figure 4 As shown, a set can store first to fourth cache data DT0 to DT3 and first to fourth tag data TG0 to TG3 indicating the respective tag addresses of the first to fourth cache data DT0 to DT3.

[0067] Furthermore, the first to fourth tag data TG0 to TG3 are stored in the same row of the tag memory TARR. The first tag data TG0 corresponds to the first path WY0, the second tag data TG1 corresponds to the second path WY1, the third tag data TG2 corresponds to the third path WY2, and the fourth tag data TG3 corresponds to the fourth path WY3. The first to fourth cached data DT0 to DT3, which correspond to the first to fourth tag data TG0 to TG3 respectively, can be stored in the data memory DARR in the same manner as the first to fourth tag data TG0 to TG3.

[0068] The cache circuit 20 receives the access address ADD corresponding to the target data (e.g., data requested by the processor). Figure 4 As shown, the access address ADD includes a tag address TADD and a set address SADD. The set address SADD indicates the row address of the cache memory 50. In other words, the set address SADD indicates any one of the multiple sets included in the cache memory 50.

[0069] When there is an external request for data, for example, via the processor or processor core, the tag comparison circuit 41 can determine whether to store the requested data or target data in the cache memory 50. In other words, the tag comparison circuit 41 determines whether there is a cache hit or a cache miss.

[0070] Tag comparison circuit 41 may include comparators COM0-COM3 to compare each tag data TG0-TG3 stored in and read from the set corresponding to set address SADD with tag address TADD. When a corresponding tag data TG0-TG3 from the first to the fourth set matches tag address TADD, comparators COM0-COM3 may activate path hit signals HT0-HT3 respectively. Cache hit determination circuit 44 may activate cache hit signal CHT to indicate a cache hit when at least one of path hit signals HT0-HT3 is activated. In other words, a cache hit indicates the presence of the target data requested externally in data memory DARR.

[0071] When the cache hit signal CHT indicates a cache hit, the target data SDT corresponding to the tag data can be output, which matches the tag address TADD. In other words, the tag comparison circuit 41 outputs path hit signals HT0~HT3 to the data output circuit 42, and the data output circuit 42 can select one of the cache data DT0~DT3 that corresponds to the activated path hit signal to output the selected cache data as the target data SDT. Conversely, in the case of a cache miss, the cache hit determination circuit 44 can deactivate the cache hit signal CHT to indicate a cache miss.

[0072] The update controller 43 can delete cache data corresponding to the evicted data from a cache line, which can be determined by a cache replacement policy, and new data NDT (e.g., 550) provided from a higher-level cache storage device or main memory can be stored or written to a cache line that already stores the evicted data.

[0073] Figure 5 This is a diagram illustrating a path prediction circuit included in a cache storage device according to an exemplary embodiment of the present invention.

[0074] refer to Figure 5 The route prediction circuit 30 may include control logic circuit 31, differential diagnostic register DDR 32, route level buffer WRB 33, and auxiliary inference buffer AIB 34.

[0075] The differential diagnostic register 32 can store accumulated information ACCI for each of multiple processors and multiple sets by accumulating multiple diagnostic bit pairs during multiple previous cache access operations, such that each diagnostic bit pair includes a cache hit bit indicating a cache hit result and a path prediction hit bit indicating a path prediction hit result. (See below for reference.) Figure 10 and Figure 11 Further description of the multiple diagnostic bit pairs stored in the differential diagnostic register 32.

[0076] The path-level buffer 33 can store priority information indicating the order of multiple paths included in a candidate path, with respect to each of multiple processors and multiple sets. (See below for reference.) Figure 12 Further description of the priority information stored in path-level buffer 33.

[0077] The auxiliary inference buffer 34 can store evicted information related to evicted data that is replaced by new data and deleted from multiple cache lines during a valid rereference interval. (See below for reference.) Figure 13Further description of the eviction information stored in the auxiliary inference buffer 34.

[0078] The control logic circuit 31 can manage the diagnostic bit pairs stored in the differential diagnostic register 32, the priority information stored in the path level buffer 33, and the eviction information PID stored in the auxiliary inference buffer 34 based on the processor identifier, access address ADD, and cache hit signal CHT. In an exemplary embodiment of the present invention, the control logic circuit 31 can be implemented using a special function register (SFR).

[0079] The control logic circuit 31 can generate a candidate path signal SCW corresponding to the processor and set associated with the current cache access operation based on multiple diagnostic bit pairs stored in the differential diagnostic register 32.

[0080] In an exemplary embodiment of the present invention, control logic circuit 31 may store multiple path prediction windows WPW0 to WPWn corresponding to multiple processors and multiple sets, such that each path prediction window indicates the number of candidate paths corresponding to each processor and each set. Control logic circuit 31 may determine the candidate paths corresponding to the processor and set associated with the current cache access operation based on the multiple path prediction windows WPW0 to WPWn stored in path level buffer 33 and priority information.

[0081] The control logic circuit 31 can dynamically update multiple path prediction windows WPW0 to WPWn for each cache access operation based on multiple diagnostic bit pairs stored in the differential diagnostic register 32.

[0082] In an exemplary embodiment of the present invention, control logic circuit 31 may store cache occupancy information (COI), which indicates an identifier of the processor corresponding to data stored in a plurality of cache lines. Control logic circuit 31 may generate masking information (SHD) related to protected data based on the cache occupancy information (COI) and evict information stored in auxiliary inference buffer 34, such that protected data indicates evicted data rewritten in the cache line during a valid rereference interval, and the masking information SHD is provided to... Figure 1 The cache circuit 20 in the cache can prevent the deletion of protected data from the cache line at least once based on the masking information SHD.

[0083] In an exemplary embodiment of the present invention, the control logic circuit 31 can generate a prediction mode signal SPM indicating whether the path prediction mode is enabled or disabled based on accumulated information ACCI including diagnostic bit pairs stored in the differential diagnostic register 32, and provide the prediction mode signal SPM to the cache circuit 20. The cache circuit 20 can perform the current cache access operation primarily on candidate paths among multiple paths based on candidate path signals SCW indicating one or more candidate paths in the path prediction mode.

[0084] Figure 6 This is a flowchart illustrating cache access operations of a cache storage device according to an exemplary embodiment of the present invention.

[0085] For ease of explanation and description, Figure 6 An example is shown in which a logic high level H of the prediction mode signal SPM indicates a prediction mode and a logic high level H of the cache hit signal CHT indicates a cache hit, but the inventive concept is not limited to these specific logic levels of the signals.

[0086] refer to Figure 1 and Figure 6 The cache circuit 20 receives the prediction mode signal SPM and the candidate path signal SCW from the path prediction circuit 30. When the prediction mode signal SPM indicates a path prediction mode (S11: Yes), the cache circuit 20 determines whether the candidate path signal SCW does not include a candidate path (S12). When the candidate path signal SCW includes one or more candidate paths (S12: No), the cache circuit 20 can perform a main cache access operation PCAO for the candidate paths among the multiple paths (S13), as will be referred to below. Figure 7 The following description is provided. When the cache hit signal CHT for the main cache access operation PCAO indicates a cache hit (S14: Yes), the path prediction circuit 30 can store the diagnostic bit pair (e.g., "11") indicating the cache hit and the path prediction hit as accumulated information ACCI (S21). The cache hit signal CHT for the main cache access operation PCAO can be referred to as the first cache hit signal.

[0087] When the cache hit signal CHT used for the primary cache access operation PCAO indicates a cache miss (S14: No), the cache circuit 20 can perform a secondary cache access operation SCAO (S15) for the remaining paths among the multiple paths, excluding the candidate paths, as will be referred to below. Figure 8The following description is provided. When the cache hit signal CHT of the secondary cache access operation SCAO indicates a cache miss (S16: No), the path prediction circuit 30 can store the diagnostic bit pair indicating the cache miss (e.g., "00") as accumulated information ACCI (S22). The cache hit signal CHT used for the secondary cache access operation SCAO can be referred to as the second cache hit signal.

[0088] When the prediction mode signal SPM does not indicate a path prediction mode (S11: No), or when the candidate path signal SCW does not include any candidate paths (S12: Yes), the cache circuit 20 can perform a normal cache access operation NCAO (S17) for all paths in the multiple paths, as will be referred to below. Figure 9 Describe it.

[0089] When the cache hit signal CHT of a normal cache access operation (NCAO) indicates a cache hit (S18: Yes), or when the cache hit signal CHT of a secondary cache access operation (SCAO) indicates a cache hit (S16: Yes), the path prediction circuit 30 can store a pair of diagnostic bits (e.g., "10") indicating a cache hit but not containing information related to the path prediction hit result as cumulative information ACCI (S23). When the cache hit signal CHT of a normal cache access operation (NCAO) indicates a cache miss (S18: No), the path prediction circuit 30 can store a pair of diagnostic bits (e.g., "00") indicating a cache miss as cumulative information ACCI (S22). The cache hit signal CHT of a normal cache access operation (NCAO) can be referred to as a third cache hit signal.

[0090] Therefore, refer to Figure 6 The path prediction circuit 30 can store diagnostic bit pairs as accumulated information ACCI based on at least one of a first cache hit signal, a second cache hit signal, and a third cache hit signal. When the first cache hit signal indicates a cache hit, the diagnostic bit pair is set to a first value (e.g., "11"). When the second cache hit signal does not indicate a cache hit, the diagnostic bit pair is set to a second value (e.g., "00"). When either the second or third cache hit signal indicates a cache hit, the diagnostic bit pair is set to a third value (e.g., "10"). When the third cache hit signal does not indicate a cache hit, the diagnostic bit pair is set to a fourth value (e.g., "00").

[0091] Figure 7 This is a diagram illustrating a main cache access operation of a cache storage device according to an exemplary embodiment of the present invention. Figure 8 This is a diagram illustrating secondary cache access operations of a cache storage device according to an exemplary embodiment of the present invention, and... Figure 9 This is a diagram illustrating normal cache access operation of a cache storage device according to an exemplary embodiment of the present invention.

[0092] For ease of illustration and description, Figure 7 , Figure 8 and Figure 9 An example of a cache circuit including paths WY0 to WY8 from the first to the eighth is shown, but the inventive concept is not limited to a specific number of paths. Figure 7 , Figure 8 and Figure 9 The output circuit 60 shown may include a reference Figure 4 The tag comparison circuit 41, the data output circuit MUX 42, and the cache hit determination circuit 44 are described above.

[0093] refer to Figure 7 and Figure 8 The prediction mode signal SPM can be activated to indicate that the road prediction mode is enabled. For example, the candidate path signal SCW can indicate that the third path WY2, the fifth path WY4, and the sixth path WY5 are candidate paths.

[0094] like Figure 7 As shown, the cache circuit can perform a main cache access operation (PCAO) for candidate paths WY2, WY4, and WY5. In other words, the cache controller in the cache circuit can, for example, activate the path enable signals EN2, EN4, and EN5 corresponding to candidate paths WY2, WY4, and WY5 to logic high level H in the first to eighth path enable signals EN0 to EN7 corresponding to the first to eighth paths WY0 to WY7, respectively, and deactivate the path enable signals EN0, EN1, EN3, EN6, and EN7 corresponding to the remaining paths WY0, WY1, WY3, WY6, and WY7 (excluding candidate paths WY2, WY4, and WY5) to logic low level L. Therefore, only tag data TG2, TG4, and TG5, and cache data DT2, DT4, and DT5 corresponding to candidate paths WY2, WY4, and WY5, can be output and provided to the output circuit 60.

[0095] When the target data SDT is stored in candidate paths WY2, WY4 and WY5 as the result of the main cache access operation PCAO, the output circuit 60 can output a cache hit signal CHT indicating a cache hit and output the target data SDT.

[0096] When the target data SDT is not stored in candidate paths WY2, WY4, and WY5 as the result of the primary cache access operation PCAO, the output circuit 60 can output a cache hit signal CHT indicating a cache miss, and the cache circuit can perform a secondary cache access operation SCAO.

[0097] like Figure 8 As shown, in addition to candidate paths WY2, WY4, and WY5, the cache circuit can perform secondary cache access operations (SCAO) for the remaining paths WY0, WY1, WY3, WY6, and WY7. In other words, the cache controller in the cache circuit can, for example, activate the path enable signals EN0, EN1, EN3, EN6, and EN7 corresponding to the remaining paths WY0, WY1, WY3, WY6, and WY7 to logic high level H, and, for example, deactivate the path enable signals EN2, EN4, and EN5 corresponding to candidate paths WY2, WY4, and WY5 to logic low level L. Therefore, only the tag data TG0, TG1, TG3, TG6, and TG7, and the cache data DT0, DT1, DT3, DT6, and DT7 corresponding to the remaining paths WY0, WY1, WY3, WY6, and WY7, can be output and provided to the output circuit 60.

[0098] When the target data SDT is stored in the remaining paths WY0, WY1, WY3, WY6 and WY7 as the result of the secondary cache access operation SCAO, the output circuit 60 can output a cache hit signal CHT indicating a cache hit and output the target data SDT.

[0099] When the result of the target data SDT as a secondary cache access operation SCAO is not stored in the remaining paths WY0, WY1, WY3, WY6 and WY7, the output circuit 60 can output a cache hit signal CHT indicating a cache miss.

[0100] refer to Figure 9 When the deactivation prediction mode signal SPM is used to indicate that path prediction mode is disabled, the cache circuit can perform normal cache access operation NCAO for all candidate paths WY0 to WY7. In other words, the cache controller in the cache circuit can, for example, activate the path enable signals EN0 to EN7 corresponding to all first to eighth paths WY0 to WY7 to logic high level H. Therefore, TG0 to TG7 and cache data DT0 to DT7 corresponding to all paths WY0 to WY7 can be output and provided to the output circuit 60.

[0101] Additionally, when the candidate path signal SCW does not include any candidate paths (SCW: None), the cache circuit can perform normal cache access operation NCAO for all paths WY0 to WY7, as shown in the reference. Figure 6 As stated above.

[0102] When the target data SDT is stored in the path WY0~WY7 as the result of the normal cache access operation NCAO, the output circuit 60 can output the cache hit signal CHT indicating a cache hit and output the target data SDT.

[0103] When the target data SDT is not stored in the path WY0~WY7 as the result of the normal cache access operation NCAO, the output circuit 60 can output a cache hit signal CHT indicating a cache miss.

[0104] For reference Figure 6 and Figure 9 As described, power consumption in the primary cache access operation (PCAO) can be reduced by enabling only candidate paths and disabling the remaining paths. If a cache miss occurs in the PCAO, the latency for accessing data can be increased by performing a secondary cache access operation (SCAO). As described above, according to an exemplary embodiment of the present invention, candidate paths can be accurately predicted and determined based on accumulated information (ACCI), thus efficiently reducing power consumption while minimizing the increase in access latency.

[0105] Figure 10 This is a diagram used to describe diagnostic bit pairs stored in a cache storage device according to an exemplary embodiment of the present invention, and Figure 11 This is a diagram illustrating a differential diagnostic register included in a cache storage device according to an exemplary embodiment of the present invention.

[0106] refer to Figure 10 For each of the primary cache access operation (PCAO) and the secondary cache access operation (SCAO), when a cache hit occurs, the cache hit signal (CHT) can be activated to a logic high level.

[0107] In the first case, CS1 indicates that the target data SDT is stored in the candidate path. In this case, the path prediction circuit can store the value of the diagnostic bit pair indicating cache hit and path prediction hit (e.g., "11") as the accumulated information ACCI.

[0108] In the second case, CS2 indicates that the target data SDT is stored in the remaining paths besides the candidate paths. In this case, the path prediction circuit can store the value (e.g., "10") of the diagnostic bit pair indicating cache hits and path prediction misses as the cumulative information ACCI.

[0109] In the third case, CS3 indicates that the target data SDT is not stored in any path. In this case, the path prediction circuit can store the value of the diagnostic bit pair indicating a cache miss (e.g., "00") as the accumulated information ACCI.

[0110] Already referenced Figure 10 An exemplary embodiment has been described, in which a cache hit signal CHT indicates the cache hit result and the path prediction hit result; however, the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, two separate signals may be used to provide the cache hit result and the path prediction hit result from the cache circuitry to the path prediction circuitry.

[0111] refer to Figure 11 The differential diagnostic register DDR may include multiple diagnostic blocks 61, 62, and 63 to store multiple diagnostic bit pairs P1 to Ps for each of multiple processors PCR0 to PCRn and multiple sets (SET = 0 to m). Each of the diagnostic bit pairs P1 to Ps may include a cache hit bit (e.g., a higher significant bit) indicating a cache hit result and a path prediction hit bit (e.g., a lower significant bit) indicating a path prediction hit result. The number "s" of diagnostic bit pairs (P1 to Ps) may vary depending on the configuration and operating conditions of the system including the cache storage device.

[0112] For example, P1 could be a diagnostic bit pair corresponding to the most recent cache access operation, and Ps could be a diagnostic bit pair corresponding to the most recent cache access operation. Diagnostic bit pairs P1–Ps can be managed and stored using a first-in, first-out (FIFO) scheme. In other words, for each cache access operation, the oldest diagnostic bit pair can be deleted, and new diagnostic bit pairs can be stored in the diagnostic block and the set corresponding to each cache access operation. In this way, multiple diagnostic bit pairs P1–Ps can be accumulated as cumulative information ACCI during multiple previous cache access operations.

[0113] Figure 5 The control logic circuit 31 can determine whether the current cache access mode is suitable for path prediction based on multiple diagnostic bit pairs to enable or disable the path prediction mode. For example, if a predetermined number of cache misses and / or prediction misses occur consecutively, the path prediction mode can be disabled.

[0114] Figure 12 This is a diagram illustrating a path-level buffer included in a cache storage device according to an exemplary embodiment of the present invention.

[0115] refer to Figure 12 For each of the multiple processors with priorities PR1 to PRk and for each of the multiple sets (SET = 0 to m), the path-level buffer WRB stores priority information indicating the order of the multiple paths included in the candidate paths. Each line in the path-level buffer WRB can store priority information indicating a priority PR1 to PRk corresponding to each set. PR1 indicates the highest priority, while PRk indicates the lowest priority.

[0116] Each entity stored in the path-level buffer (WRB) can indicate the path number and processor number corresponding to its priority. For example, 31 is stored in the highest priority PR1 (SET=0) of the first set; 3 indicates the path number, and 1 indicates the processor number. In other words, path WY3 stores cached data corresponding to the processor with the highest priority PR1.

[0117] Priority information stored in the path-level buffer (WRB) can be dynamically updated for each cache access operation based on multiple diagnostic bit pairs. The following will refer to... Figure 17 Update the description priority information.

[0118] Figure 13 This is a diagram illustrating an auxiliary inference buffer included in a cache storage device according to an exemplary embodiment of the present invention.

[0119] refer to Figure 13 The Auxiliary Inference Buffer (AIB) can store eviction information related to eviction data that is replaced by new data and deleted from multiple cache lines during a valid rereference interval. The Auxiliary Inference Buffer (AIB) can include entries (1 to q) to store eviction information corresponding to q eviction data respectively. The number of entries q can be determined based on the valid rereference interval, which will be referenced below. Figure 15 Describe it.

[0120] like Figure 13 As shown, the eviction information stored in the auxiliary inference buffer AIB may include the address of the eviction data, the victim identifier PIDv indicating the processor that previously wrote the eviction data into the cache line, and the attacker identifier Pda indicating the processor that deleted the eviction data from the cache line. Figure 13 Example numbers of victim identifier PIDv and attacker identifier PIDa corresponding to the addresses of the evicted data are shown.

[0121] Figure 5 The control logic circuit 31 can set the value of the interference bit DI by determining whether the victim identifier PIDv is consistent with the attacker identifier PIDa. For example, when the victim identifier PIDv is consistent with the attacker identifier PIDa, the value of the interference bit DI can be set to 1.

[0122] Additionally, the control logic circuit 31 can set the value of the reuse bit RU by determining whether the address of newly stored data in the cache circuit matches the address of evicted data stored in the auxiliary inference buffer AIB. For example, when the address of the new data matches the address of the evicted data stored in the auxiliary inference buffer AIB, the value of the reuse bit RU can be set to 1.

[0123] The control logic circuit 31 in the path prediction circuit 30 can generate masking information SHD related to protection data based on the evicting information stored in the auxiliary inference buffer AIB, wherein the protection data indicates evicted data that is rewritten to the cache line during a valid rereference interval, and can provide the masking information SHD to Figure 1 The high-speed cache circuit 20 in the middle.

[0124] The cache circuit 20 can prevent the deletion of protected data from the cache line at least once based on the masking information SHD. In this way, the cache circuit 20 reflects the masking information SHD in the above-mentioned cache replacement strategy so that protected data with high reuse probability is not deleted and resides in the cache line for a longer time.

[0125] Figure 14 This is a diagram illustrating cache occupancy information stored in a cache storage device according to an exemplary embodiment of the present invention.

[0126] Figure 5 The control logic circuit 31 in the middle can store cache occupancy information COI, such as Figure 14 As shown in the diagram. Cache occupancy information (COI) can include the identifier of the processor corresponding to the data stored in multiple cache lines. Figure 14 Example processor numbers are shown that relate to data stored in multiple sets (SET = 0 to m) and multiple paths WY0 to WYk, respectively. For example, data stored by a processor with processor number "1" is stored in set (SET = 0) and set WY0. Control logic circuit 31 can determine the victim identifier PIDv included in the eviction information based on cache occupancy information COI.

[0127] Figure 15 This is a diagram illustrating the effective rereference interval of a cache storage device according to an exemplary embodiment of the present invention.

[0128] Figure 15 An example data stream is shown, sequentially evicted from the L1 caches dedicated to the four processors PRC0 through PRC3 and the L2 cache shared by the four processors PRC0 through PRC3. For example, data “a”, “b”, “c”, and “d” correspond to cached data stored in the L2 cache by processor PRC0, and data “e”, “f”, and “g” correspond to data stored in the L2 cache by processors PRC1, PRC2, and PRC3. Figure 15 In this context, SZA corresponds to the number "ε" and indicates the actual available cache size. SZV corresponds to the number "3ε" and indicates the virtual extended cache size.

[0129] In the evicted data stream, evicted data included in subsets α, β, γ, and δ are evicted within a shorter rereference interval Srri, while evicted data included in subset ω are evicted within a longer rereference interval Lrri. If data evicted during the short rereference interval Srri is rewritten into the L2 cache, it indicates that data with a high likelihood of reuse has been deleted and inefficiently rewritten. According to an exemplary embodiment of the present invention, an effective rereference interval corresponding to the short rereference interval Srri can be appropriately set, and a masking information SHD can be generated to reduce the likelihood of evicting reusable protected data with an effective rereference interval Srri, thereby enhancing the performance of a system including a cache storage device.

[0130] In an exemplary embodiment of the present invention, in the case of a shared L2 cache storage device, the effective rereference interval Srri can be set to expression 1.

[0131] Expression 1

[0132] Srri = n*R*ε or n*ε

[0133] R = m2 / m1

[0134] In Expression 1, n indicates the number of processors that co-access the shared L2 cache storage, ε indicates the number of paths to the shared L2 cache storage, m1 indicates the number of sets of dedicated L1 cache storage, and m2 indicates the number of sets of shared L2 cache storage. Thus, the effective rereference interval, for example, the amount of evicted data managed by the aforementioned Auxiliary Inference Buffer (AIB), can be determined based on the product of the number of processors (n) that co-access the shared cache storage and the number of paths to the shared cache storage (ε).

[0135] Figure 16This is a diagram illustrating a path prediction window stored in a cache storage device according to an exemplary embodiment of the present invention.

[0136] Figure 5 The control logic circuit 31 can store multiple path prediction windows WPW0~WPWn, such as Figure 16 As shown in the figure, multiple path prediction windows WPW0~WPWn correspond to multiple processors PRC0~PRCn, and each includes entries corresponding to multiple sets (SET=0~m).

[0137] Each entry in the multiple path prediction windows WPW0 to WPWn indicates the number of candidate paths corresponding to each of the multiple processors PRC0 to RPCn and each of the multiple sets (SET = 0 to m). For example, the path prediction window corresponding to processor PRC0 and set (SET = 0) could be 4.

[0138] As described above, multiple path prediction windows can be dynamically updated for each cache access operation based on multiple diagnostic bit pairs stored in the differential diagnostic register. The following will refer to... Figure 17 Describes the update of the path prediction window.

[0139] The control logic circuit 31 can be based on a reference. Figure 16 Described multiple path prediction windows and references Figure 12 The priority information described determines the candidate path, which corresponds to the processor and set corresponding to the current cache access operation.

[0140] Figure 17 This is a diagram illustrating a priority update operation of a cache storage device according to an exemplary embodiment of the present invention.

[0141] Figure 17 This illustrates example access results S31-S35 for a set of data, along with the update process of path prediction windows WPW0-WPW3 and priority information PRT, when a shared cache storage device is accessed jointly by four processors PRC0-PRC3 and includes eight paths WY0-WY7. The priority information PRT is marked and referenced. Figure 12 The description is the same. "10" s The “s” in the text indicates masking information, which makes the data in the corresponding cache line the protected data as described above.

[0142] As an example, at the first time point T1, the first through fourth path prediction windows have values ​​of 3+1=4, 1, 3, and 0. The first path prediction window WPW0 has an initial value of 3, and this value can be increased from 3 to 4 due to the presence of cache lines storing protected data.

[0143] After the first time point Tl, the first processor PRC0 can achieve a sequential path prediction hit (e.g., two consecutive path prediction hits) on the third path WY2 (S31). Figure 5 The control logic circuit 31 can obtain such access results based on diagnostic bit pairs as described above. The control logic circuit 31 can update the priority information PRT at the second time point T2 by decreasing the value of the first path prediction window WPW0 by 1 and increasing the priority of the third path WY2 corresponding to the sequential path prediction hit by 1.

[0144] After the second time point T2, the first processor PRC0 may experience a cache miss and may undergo destructive interference (DI), thereby evicting cache data already occupied by the third processor PRC2 in the eighth path WY7 (S32). In this case, as referenced... Figure 13 The interference bit DI in the eviction information can be set to 1. The control logic circuit 31 can update the priority information PRT at the third time point T3 by increasing the value of the first path prediction window WPW0 corresponding to the cache by 1, decreasing the value of the third path prediction window WPW2 corresponding to the eviction data by 1, and setting the eighth path WY7, which writes new cache data, to the highest priority.

[0145] After the third time point T3, the first processor PRC0 may experience a cache miss and may suffer destructive interference (DI), thereby evicting the cache data in the sixth path WY5 already occupied by the second processor PRC1 (S33). The control logic circuit 31 can update the priority information PRT at the fourth time point T4 by increasing the value of the first path prediction window WPW0 corresponding to the cache miss by 1, decreasing the value of the second path prediction window WPW1 corresponding to the evicted data by 1, and setting the sixth path WY5, which is used to write new cache data, to the highest priority.

[0146] After the fourth time point T4, the first processor PRC0 may experience a cache miss and may suffer destructive interference (DI), thereby evicting cache data from the seventh path WY6 already occupied by the third processor PRC2 (S34). The control logic circuit 31 can update the priority information PRT at the fifth time point T5 by increasing the value of the first path prediction window WPW0 corresponding to the cache miss by 1, decreasing the value of the third path prediction window WPW2 corresponding to the evicted data by 1, and setting the seventh path WY6, which is used to write new cache data, to the highest priority.

[0147] According to conventional cache replacement strategies, cached data in the second path WY1 corresponding to the lowest priority can be evicted. However, according to an exemplary embodiment of the present invention, based on a new cache replacement strategy, cached data in the second path WY1 can correspond to protection data. In this case, the deletion of protection data in the second path WY1 can be prevented, and cached data in the seventh path WY6 can be evicted instead of protection data. After such protection, cached data in the second path WY1 can be released from the protection data.

[0148] After the fifth time point T5, the first processor PRC0 may experience a cache miss, and the cache data already occupied by the first processor PRC0 can be evicted without destructive interference (S35). The control logic circuit 31 can update the priority information PRT at the sixth time point T6 by incrementing the value of the first path prediction window WPW0 corresponding to the cache miss by 1, and set the second path WY1 for writing new cache data to the highest priority.

[0149] In the following text, for the case where the dedicated cache storage device is accessed exclusively by a single processor PRC0, refer to... Figure 18 , Figure 19 and Figure 20 Describe an exemplary embodiment.

[0150] Figure 18 This is a diagram illustrating a differential diagnostic register included in a cache storage device according to an exemplary embodiment of the present invention, and Figure 19 This is a diagram illustrating a path-level buffer included in a cache storage device according to an exemplary embodiment of the present invention.

[0151] refer to Figure 18 The differential diagnostic register DDR can include a single diagnostic block 61. For each of a single processor PRCO and multiple sets (SET = 0 to m), the signal diagnostic block 61 can store accumulated information by accumulating multiple diagnostic bit pairs P1-Ps during multiple previous cache access operations. Description and reference of other components. Figure 11 The descriptions are essentially the same, with repeated details omitted.

[0152] Figure 5 The control logic circuit 31 in the middle can generate a candidate path signal SCW based on multiple diagnostic bit pairs P1 to Ps stored in the differential diagnostic register DDR. The candidate path signal SCW corresponds to a single processor PRC0 and set associated with the current cache access operation.

[0153] refer to Figure 19For a single processor PRCO and each of multiple sets (SET = 0 ~ m), the path-level buffer WRB can store priority information indicating the order in which multiple paths are included among candidate paths. Figure 12 Compared to the representation of priority information PRT in the case of shared cache storage devices. Figure 19 In the case of a dedicated cache storage device, each entry in the Priority Request (PRT) may exclude the processor number and include only the path number. Other descriptions and references. Figure 12 The descriptions are essentially the same, and repeated descriptions are omitted.

[0154] Figure 5 The control logic circuit 31 in the middle can be based on Figure 19 The path-level buffer WRB stores multiple diagnostic bits P1 to Ps, and the priority information PRT is dynamically updated for each cache access operation.

[0155] Figure 20 This is a diagram illustrating a priority update operation of a cache storage device according to an exemplary embodiment of the present invention.

[0156] Figure 20 This illustrates the update process of example access results S41–S45 for a set, along with the path prediction window WPW and priority information PRT, in the case of dedicated access by the signal processor and a dedicated cache storage device including eight paths WY0–WY7. (Aside from destructive interference,) Figure 20 The update process in Figure 17 The contents are basically the same, and repeated descriptions are omitted.

[0157] like Figure 20 As shown, the value of the path prediction window WPW can be increased by 1 in the case of a cache miss, and decreased by 1 in the case of a sequential path prediction hit.

[0158] Figure 21 This is a block diagram illustrating an exemplary system according to a concept of the present invention.

[0159] refer to Figure 21 The system 1000 may include a multi-core processor 110, a shared L2 cache storage device SL2 11, and a main memory MEM 130. Figure 21 Only components used to describe exemplary embodiments of the inventive concept are shown, and the system 1000 may also include various other components.

[0160] The multi-core processor 110 can be implemented as a system-on-a-chip that can be included in various computing devices. The multi-core processor 110 can send data and task requests to and receive data and task requests from the host device via an interface (e.g., interface circuitry). The multi-core processor 110 can include multiple processor cores C1 to C8 and multiple dedicated L1 cache storage devices L1_1 to L1_8 that are exclusively accessed by the multiple processor cores C1 to C8. Although Figure 21 Eight processor cores C1 to C8 are shown, but the inventive concept is not limited to a specific number of processor cores.

[0161] Processor cores C1 through C8 can be either homogeneous or heterogeneous. When processor cores C1 through C8 are homogeneous, each core is of the same type. When processor cores C1 through C8 are heterogeneous, some cores are of different types.

[0162] When processor cores C1 to C8 are heterogeneous processor cores, they can be classified into a first cluster CL1 and a second cluster CL2. Among processor cores C1 to C8, the first cluster CL1 may include high-performance cores C1 to C4 with a first processing speed, while the second cluster CL2 may include low-performance cores C5 to C8 with a second processing speed lower than the first processing speed.

[0163] At least one of the shared L2 cache storage device 11 and the plurality of dedicated L1 cache storage devices L1_1 to L1_8 can be implemented as a cache storage device capable of performing efficient path prediction according to an exemplary embodiment of the present invention.

[0164] As described above, the cache storage device, the system including the cache storage device, and the method of operating the cache storage device according to exemplary embodiments of the present invention can reduce the power consumption of the cache storage device and the system by accurately predicting candidate routes based on accumulated information. Furthermore, the cache storage device, the system including the cache storage device, and the method of operating the cache storage device according to exemplary embodiments of the present invention can reduce the power consumption of the cache storage device and the system and enhance performance by increasing cache hit rate and path prediction hit rate based on masking information of protected data with high reuse probability.

[0165] This invention concept can be applied to cache storage devices and any devices and systems that include cache storage devices. For example, this invention concept can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMC), universal flash memory (UFS), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable camcorders, personal computers (PCs), server computers, workstations, portable computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Things (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, and so on.

[0166] While the concept of the invention has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various modifications in form and detail may be made thereto without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A cache storage device, comprising: A cache circuit including multiple paths, each of which includes multiple cache lines corresponding to multiple sets, and the cache circuit is configured to generate a cache hit signal indicating whether target data corresponding to an access address is stored in the multiple cache lines, and is configured to perform a current cache access operation for a candidate path based on a candidate path signal indicating a candidate path among the multiple paths in path prediction mode. as well as The path prediction circuit is configured to store accumulated information based on the cache hit signals provided during multiple previous cache access operations by accumulating cache hit results indicating whether the target data is stored in one of the multiple paths and path prediction hit results indicating whether the target data is stored in one of the candidate paths, and is configured to generate the candidate path signal based on the accumulated information in the path prediction mode by determining the candidate path of the current cache access operation.

2. The cache storage device according to claim 1, wherein, The path prediction circuit generates a prediction mode signal indicating whether the path prediction mode is enabled or disabled based on the accumulated information, and provides the prediction mode signal to the cache circuit.

3. The cache storage device according to claim 2, wherein, When the prediction mode signal indicates that the path prediction mode is enabled, the cache circuit performs a primary cache access operation for the candidate path, and performs a secondary cache access operation for the other paths in the plurality of paths other than the candidate path only when the target data is not stored in the candidate path.

4. The cache storage device according to claim 2, wherein, When the prediction mode signal indicates that the path prediction mode is disabled, the cache circuit performs normal cache access operations for all of the multiple paths.

5. The cache storage device according to claim 1, wherein the path prediction circuit comprises: An auxiliary inference buffer is configured to store eviction information related to eviction data that is replaced by new data and deleted from the plurality of cache lines during a valid rereference interval.

6. The cache storage device of claim 5, wherein the path prediction circuit generates masking information related to data protection based on the eviction information and provides the masking information to the cache circuit. The protected data indicates that the evicted data is written back to the cache line during the effective rereference interval, and The cache circuitry thereunder prevents the protected data from being deleted from the cache line at least once based on the masking information.

7. The cache storage device according to claim 5, wherein the eviction information includes: The address of the evicted data indicates the victim identifier of the processor that previously wrote the evicted data into the cache line, and the attacker identifier of the processor that deleted the evicted data from the cache line.

8. The cache storage device of claim 7, wherein the path prediction circuit stores cache occupancy information indicating an identifier of a processor corresponding to data stored in the plurality of cache lines, and determines the victim identifier based on the cache occupancy information.

9. The cache storage device of claim 5, wherein the effective rereference interval is determined based on the product of the number of processors that jointly access the cache circuitry and the number of the plurality of paths.

10. The cache storage device according to claim 1, wherein the cache storage device is a shared cache storage device accessed by multiple processors.

11. The cache storage device of claim 10, wherein the path prediction circuit comprises: A differential diagnostic register is configured to store accumulated information for each of the plurality of processors and each of the plurality of sets by accumulating a plurality of diagnostic bit pairs during the plurality of previous cache access operations, wherein each diagnostic bit pair includes a cache hit bit indicating the cache hit result and a path prediction hit bit indicating the path prediction hit result. as well as The control logic circuit is configured to generate candidate path signals corresponding to the processor and set associated with the current cache access operation based on the plurality of diagnostic bit pairs stored in the differential diagnostic register.

12. The cache storage device of claim 11, wherein the path prediction circuit further comprises: A path-level buffer is configured to store priority information for each of the plurality of processors and for each of the plurality of sets, the priority information indicating the order in which the plurality of paths are included in the candidate paths.

13. The cache storage device of claim 12, wherein the control logic circuit dynamically updates the priority information for each cache access operation based on the plurality of diagnostic bit pairs.

14. The cache storage device of claim 12, wherein the control logic circuit stores a plurality of path prediction windows corresponding to the plurality of processors and the plurality of sets, wherein each of the plurality of path prediction windows indicates the number of candidate paths corresponding to each processor and each set, and the control logic circuit determines candidate paths corresponding to the processors and sets associated with the current cache access operation based on the plurality of path prediction windows and the priority information.

15. The cache storage device of claim 14, wherein the control logic circuit dynamically updates the plurality of path prediction windows for each cache access operation based on the plurality of diagnostic bit pairs.

16. The cache storage device of claim 1, wherein the cache storage device is a dedicated cache storage device accessed exclusively by a single processor.

17. The cache storage device of claim 16, wherein the path prediction circuit comprises: A differential diagnostic register is configured to store accumulated information for each of the single processor and the plurality of sets by accumulating a plurality of diagnostic bit pairs during the plurality of previous cache access operations, wherein each diagnostic bit pair includes a cache hit bit indicating the cache hit result and a path prediction hit bit indicating the path prediction hit result; as well as The control logic circuit is configured to generate candidate path signals corresponding to the individual processor and set associated with the current cache access operation, based on the plurality of diagnostic bit pairs stored in the differential diagnostic register.

18. The cache storage device of claim 17, wherein the path prediction circuit further comprises: A path-level buffer is configured to store priority information for each of the single processor and the plurality of sets, the priority information indicating the order in which the plurality of paths are included in the candidate paths, and The control logic circuit dynamically updates the priority information for each cache access operation based on the plurality of diagnostic bit pairs.

19. A system comprising: One or more processors; The main storage device is configured to store data used by the one or more processors; as well as A cache storage device configured to store a portion of the data stored in the main storage device, and configured to be accessed by the one or more processors prior to the one or more processors accessing the main storage device, wherein the cache storage device comprises: A cache circuit including multiple paths, each of which includes multiple cache lines corresponding to multiple sets, and the cache circuit is configured to generate a cache hit signal indicating whether target data corresponding to an access address is stored in the multiple cache lines, and is configured to perform a current cache access operation for a candidate path based on a candidate path signal indicating a candidate path among the multiple paths in path prediction mode. as well as The path prediction circuit is configured to store accumulated information based on the cache hit signals provided during multiple previous cache access operations by accumulating cache hit results indicating whether the target data is stored in one of the multiple paths and path prediction hit results indicating whether the target data is stored in one of the candidate paths, and is configured to generate the candidate path signal based on the accumulated information in the path prediction mode by determining the candidate path of the current cache access operation.

20. A method of operating a cache storage device comprising multiple paths, each of the multiple paths comprising multiple cache lines corresponding to multiple sets, the method comprising: Generate a cache hit signal indicating whether the target data corresponding to the access address is stored in the plurality of cache lines; Based on the cache hit signals provided during multiple previous cache access operations, accumulated information is stored by accumulating cache hit results indicating whether the target data is stored in one of the multiple paths and path prediction hit results indicating whether the target data is stored in one of the candidate paths; In path prediction mode, based on the accumulated information, candidate path signals are generated by determining candidate paths for the current cache access operation among the multiple paths; and In the path prediction mode, the current cache access operation is performed on the candidate path based on the candidate path signal.

Images