Integrated chip and method of forming an integrated chip

Abstract

The present invention relates to an integrated chip. The integrated chip includes a first interconnection member disposed in an interlayer dielectric (ILD) structure above a substrate. A barrier layer is disposed along the sidewall of the ILD structure. The barrier layer has a sidewall defining an opening above the first interconnection member. A second interconnection member is disposed on the barrier layer. The second interconnection member extends through the opening in the barrier layer and to the first interconnection member. Embodiments of the present application also relate to a method for forming an integrated chip.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated chips and methods of forming integrated chips. Background Art

[0002] Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., a silicon substrate). The semiconductor devices are electrically coupled together by interconnects. The interconnects include interconnect lines and interconnect vias disposed within a dielectric structure above the semiconductor substrate. By using interconnects to electrically couple the semiconductor devices together, the semiconductor devices are able to perform the logic functions that enable the integrated chip to operate. Summary of the invention

[0003] Some embodiments of the present application provide an integrated chip, comprising: a first interconnect, disposed in an interlayer dielectric (ILD) structure above a substrate; a barrier layer, disposed along sidewalls of the ILD structure and having sidewalls defining an opening above the first interconnect; and a second interconnect, disposed on the barrier layer, wherein the second interconnect extends through the opening in the barrier layer and extends to the first interconnect.

[0004] Other embodiments of the present application provide an integrated chip, comprising: a first interconnect, disposed in a first interlayer dielectric (ILD) layer above a substrate; a second interlayer dielectric layer, disposed above the first interlayer dielectric layer; a barrier layer, extending along the sidewalls of the second interlayer dielectric layer and along the upper surface of the first interlayer dielectric layer; and a first pad, disposed on the barrier layer and surrounding a conductive interior, wherein the first pad extends through the barrier layer to the first interconnect.

[0005] Still other embodiments of the present application provide a method for forming an integrated chip, comprising: forming a first interconnect in a first interlayer dielectric (ILD) layer above a substrate; forming a second interlayer dielectric layer above the first interlayer dielectric layer; patterning the second interlayer dielectric layer to form sidewalls defining an interconnect opening, the interconnect opening exposing an upper surface of the first interconnect; forming a barrier layer on the upper surface of the first interconnect, wherein the barrier layer is laterally separated from the sidewalls of the second interlayer dielectric layer; forming a barrier layer in the interconnect opening; removing the barrier layer to expose the upper surface of the first interconnect; and forming a second interconnect in the interconnect opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of integrated chips having back-end-of-line (BEOL) interconnects contacted at barrier-free interfaces are shown.

[0008] FIG. 2A to FIG. 2B Some additional embodiments of integrated chips with interconnects contacting at barrier-free interfaces are shown.

[0009] Figure 3 Cross-sectional views of some alternative embodiments of integrated chips having interconnects contacting at barrier-free interfaces are shown.

[0010] FIG. 4A to FIG. 4B Cross-sectional views of some alternative embodiments of integrated chips having interconnects contacting at barrier-free interfaces are shown.

[0011] Figure 5 Cross-sectional views of some alternative embodiments of integrated chips having interconnects contacting at barrier-free interfaces are shown.

[0012] Figures 6 to 21 Cross-sectional views of some embodiments of methods of forming integrated chips having interconnects contacting at barrier-free interfaces are shown.

[0013] Fig. 22 A flow chart illustrating some embodiments of a method of forming an integrated chip having interconnects contacting at a barrier-free interface. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] The integrated chip includes: a front-end of the line (FEOL) having devices disposed in a substrate; and a back-end of the line (BEOL) having interconnects (e.g., interconnect lines, interconnect vias, etc.) disposed in an interlayer dielectric (ILD) structure above the substrate. The interconnects are electrically coupled to the transistor devices. Over time, the size and distance between transistor devices decrease. In order to be able to connect to smaller transistor devices, the size of the interconnects is also reduced.

[0017] As the size of the interconnects gets smaller, the distance between adjacent interconnects also gets smaller. The smaller distance between adjacent interconnects increases the capacitance between adjacent interconnects. In addition, as the size of the interconnects decreases, it is more difficult for current to move through the interconnects, and the resistance of the interconnects increases. Because the product of resistance and capacitance (RC) is inversely proportional to the speed of the integrated chip, the interconnects may become a bottleneck for the speed of the integrated chip.

[0018] In order to provide an interconnect with low resistance, a low resistance metal can be used. For example, copper is often used to form an interconnect because it has low resistance and is easy to use. However, over time, atoms from some of these metals may diffuse into the surrounding ILD structure. The metal atoms in the ILD structure can generate a conductive path through the ILD structure and cause an electrical short circuit between adjacent interconnects. In order to prevent the metal atoms from diffusing into the surrounding ILD structure, a barrier layer can be formed around the metal. It is understood that the barrier layer can have a significantly higher resistance than the metal, and therefore can adversely affect the resistance of the interconnect structure and cause the performance of the integrated chip to be reduced.

[0019] In some embodiments, the present invention relates to an integrated chip with an interconnect structure, wherein the interconnect structure does not have a barrier layer that vertically separates an interconnect from an interconnect below. In some embodiments, the integrated chip may include a first interconnect in an interlayer dielectric (ILD) structure disposed above a substrate and a second interconnect in an ILD structure disposed above the first interconnect. The barrier layer laterally surrounds the second interconnect and separates the second interconnect from the ILD structure. The barrier layer has a sidewall that defines an opening just above the first interconnect. The second interconnect extends vertically through the opening defined by the sidewall of the barrier layer to contact the upper surface of the first interconnect. Because the second interconnect extends through the opening in the barrier layer, the barrier layer does not separate the second interconnect from the first interconnect, and the barrier layer does not significantly increase the resistance of the interconnect structure.

[0020] Figure 1 Cross-sectional views of some embodiments of an integrated chip 100 having back-end-of-line (BEOL) interconnects contacted at a barrier-free interface are shown.

[0021] The integrated chip 100 includes an interlayer dielectric (ILD) structure 104 disposed above a substrate 102. The ILD structure 104 surrounds a plurality of interconnects 106 to 108. The plurality of interconnects 106 to 108 include a first interconnect 106 and a second interconnect 108 above the first interconnect 106. In some embodiments, the plurality of interconnects 106 to 108 may include a middle-of-line (MOL) interconnect, a conductive contact, an interconnect line, and / or an interconnect via. For example, in some embodiments, the first interconnect 106 may include an interconnect via, and the second interconnect 108 may include an interconnect line.

[0022] The barrier layer 110 extends along the sidewalls of the second interconnect 108 and separates the second interconnect 108 laterally from the ILD structure 104. The barrier layer 110 is configured to prevent atoms from the second interconnect 108 from diffusing into the ILD structure 104. In some embodiments, the barrier layer 110 may also extend along the lower surface of the second interconnect 108 and separate the second interconnect 108 vertically from the ILD structure 104. The barrier layer 110 includes sidewalls that define an opening extending through the barrier layer 110.

[0023] The second interconnect 108 extends vertically through the opening in the barrier layer 110 to physically contact the upper surface of the first interconnect 106. In some embodiments, the second interconnect 108 includes a lower surface 108L that rests on the barrier layer 110 and a protrusion 108P that extends outward from the lower surface 108L and through the barrier layer 110. The barrier layer 110 may be composed of a material having a lower conductivity (e.g., a higher resistivity) than the second conductive material of the second interconnect 108. However, because the second interconnect 108 extends vertically through the barrier layer 110, the barrier layer 110 does not separate the first interconnect 106 from the second interconnect 108. Because the barrier layer 110 does not separate the first interconnect 106 from the second interconnect 108, the resistance between the first interconnect 106 and the second interconnect 108 is reduced. For example, the resistance between the first interconnect 106 and the second interconnect 108 may be reduced by about 20% or more relative to an interconnect separated by a barrier layer. Reducing the resistance between the first interconnect 106 and the second interconnect 108 may improve the performance of the integrated chip 100 (eg, the ring oscillator may increase the speed by approximately 1.5% or more).

[0024] Figure 2A Cross-sectional views of some additional embodiments of integrated chips 200 having interconnects contacting at barrier-free interfaces are shown.

[0025] The integrated chip 200 includes a plurality of interconnects 105 to 108 within an ILD structure 104 disposed above a substrate 102. In some embodiments, the ILD structure 104 includes a plurality of stacked interlayer dielectric (ILD) layers 204a to 204c. The plurality of stacked ILD layers 204a to 204c include a lower ILD layer 204a, a first ILD layer 204b above the lower ILD layer 204a, and a second ILD layer 204c above the first ILD layer 204b. In some embodiments, the plurality of stacked ILD layers 204a to 204c may include one or more of silicon dioxide, silicon nitride, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), a porous dielectric material, and the like. In some embodiments, adjacent ILD layers of the plurality of stacked ILD layers 204a to 204c may be separated by an etch stop layer 206. In various embodiments, the etch stop layer 206 may include carbide (e.g., silicon carbide, silicon oxycarbide, etc.), nitride (e.g., silicon nitride, silicon oxynitride, etc.), or the like.

[0026] A plurality of stacked interlayer dielectric (ILD) layers 204a to 204c surround a plurality of interconnects 105 to 108. In some embodiments, the plurality of interconnects 105 to 108 include a lower interconnect 105, a first interconnect 106 above the lower interconnect 105, and a second interconnect 108 above the first interconnect 106. In some embodiments, the plurality of interconnects 105 to 108 may include one or more of MOL interconnects, conductive contacts, interconnect lines, and / or interconnect vias. In some embodiments, the lower ILD layer 204a surrounds the lower interconnect 105, the first ILD layer 204b surrounds the first interconnect 106, and the second ILD layer 204c surrounds the second interconnect 108. In some embodiments, the plurality of interconnects 105 to 108 are coupled to a transistor device 202 disposed within the substrate 102. In some embodiments, the transistor device 202 may include a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device, a BJT (Bipolar Junction Transistor), a JFET (Junction Gate Field Effect Transistor), and the like.

[0027] In some embodiments, the first interconnect 106 may include and / or be a first conductive material. In some embodiments, the first conductive material may be a material having low diffusivity to the surrounding first ILD layer 204b (e.g., diffusivity to the surrounding first ILD layer 204b is lower than that of copper). In some such embodiments, the first conductive material is not separated from the ILD structure 104 by a barrier layer, so that the first interconnect 106 directly contacts the first ILD layer 204b. In some such embodiments, the first conductive material may include or be tungsten, ruthenium, cobalt, etc. In other embodiments (not shown), the first conductive material may be separated from the ILD structure 104 by a barrier layer.

[0028] The second interconnect 108 is separated from the second ILD layer 204c by the barrier layer 110. The barrier layer 110 extends along the sidewalls of the second interconnect 108 and has a sidewall directly below the second interconnect 108. The sidewalls of the barrier layer 110 define an opening at a position directly above the first interconnect 106, and the opening extends through the lower surface of the barrier layer 110. The second interconnect 108 extends through the opening to directly contact the upper surface of the first interconnect 106. In some embodiments, the second interconnect 108 extends continuously between the sidewalls of the barrier layer 110, so that the second interconnect completely fills the opening. In some embodiments, the sidewalls of the barrier layer 110 that define the opening can be spaced apart by a distance substantially equal to the width of the top surface of the first interconnect 106. In some such embodiments, the bottom angle of the barrier layer 110 can be aligned with the top angle of the first interconnect 106 along an imaginary line perpendicular to the upper surface of the substrate 102.

[0029] Figure 2BSome embodiments of a plan view 216 of an integrated chip 200 are shown. Figure 2B Plan view 216 (along Figure 2A As shown in the cross-sectional view taken along the line AA′ of FIG. 1 , the barrier layer 110 extends in a closed loop around the second interconnect 108. In some embodiments, the barrier layer 110 includes a ring shape extending around the second interconnect 108.

[0030] In some embodiments, the barrier layer 110 includes: a vertical extension segment 110v disposed along a sidewall of the second ILD layer 204c; and a horizontal extension segment 110h protruding outward from the sidewall of the vertical extension segment 110v toward the second interconnect 108. In some embodiments, the vertical extension segment 110v may be inclined at an angle greater than 90° relative to the upper surface of the horizontal extension segment 110h. In various embodiments, the barrier layer 110 may include tantalum, tantalum nitride, titanium, titanium nitride, etc.

[0031] In some embodiments, the second interconnect 108 includes a first liner 208 surrounding the conductive inner portion 212. The first liner 208 is disposed on the barrier layer 110 and extends vertically through the barrier layer 110 to contact the upper surface of the first interconnect 106. In some embodiments, the first liner 208 includes a lower surface resting on the barrier layer 110 and a protrusion extending outward from the lower surface and through the barrier layer 110. In some embodiments, the first liner 208 completely fills the opening extending through the barrier layer 110 so that the bottommost surface of the conductive inner portion 212 is above the top surface of the horizontal extension 110h of the barrier layer 110. In some embodiments, the first liner 208 may include a material with a lower resistivity than the barrier layer 110. In some embodiments, the first liner 208 may include or be the same material as the first interconnect 106. For example, in some embodiments, the first liner 208 may include ruthenium, cobalt, tungsten, etc. In some such embodiments, there may be a seam 301 between the first interconnect 106 and the first liner 208. In other embodiments, the first liner 208 can include or be a different material than the first interconnect 106. In some embodiments, the conductive inner portion 212 can include copper, aluminum, or the like.

[0032] In some embodiments, the second liner 210 can be disposed between the first liner 208 and the conductive inner portion 212. The second liner 210 laterally and vertically separates the first liner 208 from the conductive inner portion 212. In some embodiments, the second liner 210 can include and / or be cobalt, ruthenium, tungsten, etc. In some embodiments, the barrier layer 110, the first liner 208, the second liner 210, and the conductive inner portion 212 extend vertically to the upper surface of the second ILD layer 204c. In some embodiments, the second liner 210 can include or be a different material than the first liner 208.

[0033] The capping layer 214 is disposed on the second interconnect 108. In some embodiments, the capping layer 214 extends from directly above the conductive inner portion 212 to directly above the first liner 208 and / or the second liner 210. In some embodiments, the barrier layer 110 is laterally located outside the capping layer 214. The capping layer 214 may include and / or be cobalt, ruthenium, tungsten, etc. In some embodiments, the second liner 210 and the capping layer 214 may include and / or be the same material. In other embodiments, the second liner 210 and the capping layer 214 may include or be different materials. In some embodiments, the capping layer 214 may include a sidewall that is inclined at an angle θ relative to a lower surface of the capping layer 214, the angle being measured through the capping layer 214. In some embodiments, the angle θ may be greater than or equal to about 90°. In some embodiments, the angle θ may be greater than 90°.

[0034] Figure 3 Cross-sectional views of some alternative embodiments of integrated chips 300 with interconnects contacting at barrier-free interfaces are shown.

[0035] The integrated chip 300 includes an ILD structure 104 disposed over a substrate 102. The ILD structure 104 surrounds a lower interconnect 105 disposed in a lower ILD layer 204a, a first interconnect 106 disposed in a first ILD layer 204b, and a second interconnect 108 disposed in a second ILD layer 204c.

[0036] The second interconnect 108 is separated from the second ILD layer 204c by a barrier layer 110 disposed along opposite sides of the second interconnect 108. The barrier layer 110 includes one or more sidewalls disposed directly below the second interconnect 108. In some embodiments, the one or more sidewalls may include sidewalls that are inclined at an angle Φ relative to an upper surface of the first ILD layer 204b, the angle being measured through the barrier layer 110. In some embodiments, the angle Φ may be greater than or equal to about 90°. In some embodiments, the angle Φ may be greater than 90°.

[0037] The second interconnect 108 extends through the barrier layer 110 to contact the upper surface of the first interconnect 106. In some embodiments, the second interconnect 108 includes a conductive inner portion 212 surrounded by a first liner 208. The first liner 208 separates the conductive inner portion 212 from the barrier layer 110. In some embodiments, the first liner 208 may include a horizontal extension extending between sidewalls of the first liner 208. The horizontal extension includes a first upper surface 304 directly above the barrier layer 110. In some embodiments, the horizontal extension may also include a recessed area 302 that is laterally separated from the inner sidewalls of the first liner 208 by the first upper surface 304. The recessed area 302 is directly above the first interconnect 106. In some embodiments, the recessed area 302 is defined by a second upper surface 306 that is recessed below the first upper surface 304. In some embodiments, the first upper surface 304 is spaced apart from the first ILD layer 204b by a first distance 308, and the second upper surface 306 is spaced apart from the first interconnect 106 by a second distance 310 that is less than the first distance 308. In some embodiments, the second upper surface 306 may include a curved surface. In some embodiments, the conductive inner portion 212 is conformal to the first liner 208 such that a center of the conductive inner portion 212 along a bottom portion is vertically closer to the first interconnect 106 than along an outer edge of the bottom portion of the conductive inner portion 212.

[0038] Figure 4A Cross-sectional views of some alternative embodiments of integrated chips 400 with interconnects contacting at barrier-free interfaces are shown.

[0039] The integrated chip 400 includes a lower interconnect 105 disposed above the substrate 102. In some embodiments, the lower interconnect 105 may include a lower surface that contacts the upper surface of the substrate 102. In other embodiments, the lower interconnect 105 may be separated from the upper surface of the substrate 102 by one or more additional interconnect layers. The lower interconnect 105 includes a lower barrier layer 402 surrounding the conductive core 404. The lower barrier layer 402 extends continuously along the sidewall and lower surface of the conductive core 404. The lower barrier layer 402 separates the conductive core 404 from the surrounding lower ILD layer 204a laterally. In some embodiments, the lower barrier layer 402 may include titanium, tantalum, titanium nitride, tantalum nitride, etc. In some embodiments, the conductive core 404 may include ruthenium, tungsten, cobalt, etc. In some embodiments, the lower ILD layer 204a may include silicon nitride, silicon dioxide, etc.

[0040] The first ILD layer 204b is vertically separated from the lower ILD layer 204a by the first etch stop layer 206a. The first ILD layer 204b laterally surrounds the first interconnect 106 disposed above the lower interconnect 105. In some embodiments, the first interconnect 106 may laterally contact the sidewalls of the first etch stop layer 206a and the first ILD layer 204b. In some embodiments, the first interconnect 106 may include the same material as the conductive core 404 (e.g., ruthenium, tungsten, cobalt, etc.). In some embodiments, the first interconnect 106 may include a single material that extends continuously between the outermost sidewalls of the first interconnect 106.

[0041] The second interconnect 108 is disposed above the first interconnect 106. The second interconnect 108 is laterally surrounded by the second ILD layer 204c. In some embodiments, the second ILD layer 204c is separated from the first ILD layer 204b by the second etch stop layer 206b. The second interconnect 108 includes a first liner 208, a second liner 210 surrounded by the first liner 208, and a conductive inner portion 212 surrounded by the second liner 210. In some embodiments, the first liner 208 may include the same material as the first interconnect 106 and the conductive core 404. In some such embodiments, the same material extends continuously from the upper surface of the second interconnect 108 to the bottommost surface of the conductive core 404.

[0042] Figure 4B Cross-sectional views of some alternative embodiments of integrated chips 406 with interconnects contacting at barrier-free interfaces are shown.

[0043] The integrated chip 406 includes a lower interconnect 105 disposed above the substrate 102. In some embodiments, the lower interconnect 105 may include a lower surface that contacts the upper surface of the substrate 102. In other embodiments, the lower interconnect 105 may be separated from the upper surface of the substrate 102 by one or more additional interconnect layers. In some embodiments, the lower interconnect 105 may laterally contact the sidewall lower ILD layer 204a. In some embodiments, the lower interconnect 105 may include a single material that extends continuously between the outermost sidewalls of the lower interconnect 105. In some embodiments, the single material may include ruthenium, tungsten, cobalt, etc.

[0044] The first ILD layer 204b is vertically separated from the lower ILD layer 204a by the first etch stop layer 206a. The first ILD layer 204b laterally surrounds the first interconnect 106 disposed above the lower interconnect 105. In some embodiments, the first interconnect 106 may laterally contact the sidewalls of the first etch stop layer 206a and the first ILD layer 204b. In some embodiments, the first interconnect 106 may include the same material as the lower interconnect 105 (e.g., ruthenium, tungsten, cobalt, etc.). In some embodiments, the first interconnect 106 may include a single material that extends continuously between the outermost sidewalls of the first interconnect 106.

[0045] The second interconnect 108 is disposed above the first interconnect 106. The second interconnect 108 is laterally separated from the second ILD layer 204c by the barrier layer 110. The second interconnect 108 includes a first liner 208, a second liner 210 surrounded by the first liner 208, and a conductive inner portion 212 surrounded by the second liner 210. In some embodiments, the first liner 208 may include a different material than the first interconnect 106. For example, in some embodiments, the first liner may include ruthenium and the first interconnect may include tungsten. In some such embodiments, an interface 408 between the first interconnect 106 and the first liner 208 is substantially aligned with a bottom surface of the barrier layer 110.

[0046] Figure 5 Cross-sectional views of some alternative embodiments of integrated chips 500 with interconnects contacting at barrier-free interfaces are shown.

[0047] The integrated chip 500 includes a lower interconnect 105 disposed in a lower ILD layer 204a on a substrate 102. In some embodiments, the lower interconnect 105 contacts a transistor device 202 disposed on and / or within an upper surface of the substrate 102. A first interconnect 106 is disposed in a first ILD layer 204b above the lower ILD layer 204a. A second interconnect 108 is disposed above the first interconnect 106. The second interconnect 108 is laterally separated from the second ILD layer 204c by a barrier layer 110. The second interconnect 108 extends vertically through a lower surface of the barrier layer 110 to contact an upper surface of the first interconnect 106. A capping layer 214 is disposed along an upper surface of the second interconnect 108.

[0048] The upper ILD layer 204d is vertically separated from the second ILD layer 204c by the upper etch stop layer 502. In some embodiments, the upper etch stop layer 502 may include a multi-layer etch stop layer. In some such embodiments, the upper etch stop layer 502 may include a first material 502a, a second material 502b disposed on the first material 502a, and a third material 502c disposed on the second material 502b. In some embodiments, the first material 502a may be the same material as the third material 502c, and may be a different material from the second material 502b. In some embodiments, the first material 502a, the second material 502b, and the third material 502c may include or be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), etc.

[0049] The upper ILD layer 204d surrounds the upper interconnect 504. The upper interconnect 504 extends vertically from the top of the upper ILD layer 204d to the capping layer 214. In some embodiments, the upper interconnect 504 includes a first upper liner 508, a second upper liner 510 surrounded by the first upper liner 508, and an upper conductive inner portion 512 surrounded by the second upper liner 510. In some embodiments, the upper interconnect 504 is surrounded by an upper barrier layer 506. In some embodiments, the upper barrier layer 506 extends continuously along the bottom surface of the upper interconnect 504 and from a first sidewall of the upper interconnect 504 to an opposite second sidewall of the upper interconnect 504.

[0050] Figures 6 to 21 Cross-sectional views 600 to 2100 of some embodiments of methods of forming an integrated chip having interconnects contacting at barrier-free interfaces are shown. Figures 6 to 21 , but it should be understood that Figures 6 to 21 The structure disclosed in is not limited to the method, but can exist independently as a structure independent of the method.

[0051] like Figure 6 As shown in cross-sectional view 600 of , a substrate 102 is provided. In various embodiments, the substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers associated therewith. In some embodiments, a transistor device 202 is formed on and / or within the substrate 102. In some such embodiments, the transistor device 202 can be formed by depositing a gate dielectric film and a gate electrode film over the substrate 102. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric 202d and a gate electrode 202e. The substrate 102 can then be implanted to form a source / drain region 202 within the substrate 102 and on the opposite side of the gate electrode 202e.sd1 To 202 sd2 .

[0052] In some embodiments, the lower interconnect 105 may be formed in the lower ILD layer 204a formed over the substrate 102. In some embodiments, the lower interconnect 105 may include an MOL interconnect or a conductive contact. In some embodiments, the lower interconnect 105 may be formed by forming the lower ILD layer 204a over the substrate 102, selectively etching the lower ILD layer 204a to form a lower interconnect opening 602 in the lower ILD layer 204a, forming a first conductive material (e.g., copper, aluminum, etc.) in the lower interconnect opening 602, and performing a first planarization process (e.g., a chemical mechanical planarization process) to remove excess first conductive material from over the lower ILD layer 204a.

[0053] like Figure 7 As shown in the cross-sectional view 700 of , the first ILD layer 204b is formed over the lower ILD layer 204a. The first interconnect 106 is then formed within the first ILD layer 204b and over the lower interconnect 105. In some embodiments, the first interconnect 106 may be formed by forming the first ILD layer 204b over the lower ILD layer 204a, selectively etching the first ILD layer 204b to form a first interconnect opening 702 within the first ILD layer 204b, forming a second conductive material (e.g., copper, aluminum, etc.) within the first interconnect opening 702, and performing a second planarization process (e.g., a chemical mechanical planarization process) to remove excess second conductive material from over the first ILD layer 204b. In various embodiments, the second conductive material may include tungsten, ruthenium, cobalt, etc.

[0054] like Figure 8 As shown in the cross-sectional view 800 of FIG. 8 , the second ILD layer 204c is formed over the first ILD layer 204b. In some embodiments, an etch stop layer 206 may be formed over the first ILD layer 204b before forming the second ILD layer 204c. In various embodiments, the etch stop layer 206 and / or the second ILD layer 204c may be formed by a deposition process (e.g., an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PE-CVD) process, etc.).

[0055] A first mask structure 801 is formed over the second ILD layer 204c. In some embodiments, the first mask structure 801 may include a photosensitive material (e.g., photoresist). In other embodiments, the first mask structure 801 may include a dielectric mask layer 802 and a hard mask 804 over the dielectric mask layer 802. In some embodiments, the dielectric mask layer 802 may include an oxide (e.g., silicon oxide, silicon dioxide, etc.). In some embodiments, the hard mask 804 may include a carbide (e.g., silicon carbide, silicon oxycarbide, etc.), a nitride (e.g., silicon nitride, silicon oxynitride, titanium nitride, etc.), an oxide (e.g., silicon oxide, titanium oxide, etc.).

[0056] The first etching process is performed to selectively etch the second ILD layer 204c according to the first mask structure 801 and define an intermediate interconnect opening 806. The intermediate interconnect opening 806 is defined by the sidewalls and the horizontally extending surface of the second ILD layer 204c. In some embodiments, the second ILD layer 204c can be selectively patterned by exposing the second ILD layer 204c to a first etchant 808 in the area exposed by the first mask structure 801. In some embodiments, the first etchant 808 can include a dry etchant (e.g., having a fluorine chemistry, a chlorine chemistry, etc.). In other embodiments, the first etchant 808 can include a wet etchant (e.g., including hydrofluoric acid, potassium hydroxide, etc.).

[0057] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 8 , a portion of the first mask structure 801 is removed. In some embodiments, the hard mask ( 802 ) may be removed while the dielectric mask layer 802 is maintained in place over the second ILD layer 204 c. Figure 8 804). In various embodiments, the hard mask ( Figure 8 804).

[0058] like Fig.10 As shown in the cross-sectional view 1000 of , the second ILD layer 204c and the etch stop layer 206 are further etched according to the second etching process to form a second interconnect opening 1002. In some embodiments, the second interconnect opening 1002 exposes the upper surface of the first interconnect 106. In some embodiments, the second interconnect opening 1002 also exposes the upper surface of the first ILD layer 204b. In some embodiments, the second etching process may expose the second ILD layer 204c and the first etch stop layer 206a to the second etchant 1004 according to the dielectric mask layer 802. In some embodiments, the second etching process may include a linear removal method (LRM).

[0059] In some alternative embodiments (not shown), the second ILD layer 204c may be etched according to a single etching process. In some additional embodiments, the second ILD layer 204c and the etch stop layer 206 may be etched according to separate etching processes using different etchants. For example, in some embodiments, a first single etching process may etch through the second ILD layer 204c to expose the etch stop layer 206, and a second single etching process may etch through the etch stop layer 206 to expose the upper surface of the first interconnect 106.

[0060] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , a barrier layer 1102 is formed within the second interconnect opening 1002 and on the upper surface of the first interconnect 106. In some embodiments, the barrier layer 1102 is laterally spaced apart from the sidewalls of the etch stop layer 206 and / or the second ILD layer 204c. In some additional embodiments, the barrier layer 1102 is confined above the upper surface of the first interconnect 106, such that the upper surface of the first ILD layer 204b is exposed between the sidewalls of the barrier layer 1102 and the sidewalls of the second ILD layer 204c.

[0061] In some embodiments, the barrier layer 1102 may include a self-assembled monolayer (SAM). In some embodiments, the self-assembled monolayer may include an organic material. For example, the barrier layer 1102 may include silane (e.g., chlorosilane, alkoxysilane, organosilane, etc.), thiolate (e.g., organic thiolate), etc. In some embodiments, the self-assembled monolayer may be formed by a spin coating process. In some embodiments, the barrier layer 1102 may be formed to have a thickness of about 10 angstroms. About In other embodiments, the barrier layer 1102 may be formed to have a thickness in the range of about About Between Egypt and about About The thickness is within the range between or other suitable values.

[0062] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a barrier layer 1202 is selectively formed within the second interconnect opening 1002. In some embodiments, the barrier layer 1102 is configured to be used as a mask to prevent the barrier layer 1202 from being formed on the upper surface of the first interconnect 106. The barrier layer 1202 covers the surface of one or more of the first ILD layer 204b, the second ILD layer 204c, and / or the first interconnect 106. The barrier layer 1202 is not formed on the surface of the barrier layer 1102, so that the barrier layer 1102 has one or more surfaces exposed after the barrier layer 1202 is formed. In some embodiments, the barrier layer 1202 may be formed at about About In other embodiments, the barrier layer 1202 may be formed to have a thickness in the range of about About Between About The thickness is within the range between or other suitable values.

[0063] In some embodiments, the barrier layer 1202 may be selectively formed by an atomic layer deposition (ALD) process. In such embodiments, the ALD process may be performed by performing a plurality of ALD cycles. The plurality of ALD cycles respectively introduce a first precursor gas into a processing chamber containing the substrate 102, purge the processing chamber to extract the first precursor gas from the processing chamber, introduce a second precursor gas into the processing chamber, and then purge the processing chamber to extract the second precursor gas from the processing chamber. The barrier layer 1102 is inert to the first precursor so that the first precursor does not adhere to the barrier layer 1102. Instead, the first precursor gas is selectively formed on one or more surfaces of the first ILD layer 204b, the second ILD layer 204c, and / or the etch stop layer 206. The second precursor gas interacts with the first precursor gas to form a single layer of the barrier layer 1202 on one or more surfaces of the first ILD layer 204b, the second ILD layer 204c, and / or the etch stop layer 206. Since the first precursor gas is not formed on the barrier layer 1102 , a monolayer is not formed on the barrier layer 1102 .

[0064] like Fig.13 As shown in the cross-sectional view 1300, the barrier layer ( Fig.12 1102). Removing the barrier layer ( Fig.12 1102) exposes the upper surface of the first interconnect 106 and leaves an opening 1302 extending through the barrier layer 1202 to the first interconnect 106. In some embodiments, the barrier layer ( Fig.12 1102) is exposed to plasma to remove the barrier layer ( Fig.12 1102). For example, in some embodiments, the barrier layer ( Fig.12 In some embodiments, because the sidewalls of the barrier layer 1202 are formed by the blocking layer ( Fig.12 1102) rather than being defined by an etching process, one or more of the sidewalls of the barrier layer 1202 defining the opening 1302 may be inclined at an obtuse angle relative to the upper surface of the first ILD layer 204b, the obtuse angle being measured through the barrier layer 110. In other embodiments, one or more of the sidewalls of the barrier layer 1202 defining the opening 1302 may be inclined at a right angle or an acute angle relative to the upper surface of the first ILD layer 204b, the right angle or the acute angle being measured through the barrier layer 110. Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , a first liner layer 1402 is formed within the second interconnect opening 1002. The first liner layer 1402 is formed over the barrier layer 1202 and extends through the opening 1302 in the barrier layer 1202 to contact the first interconnect 106. In various embodiments, the first liner layer 1402 may include ruthenium, tungsten, cobalt, etc. In some embodiments, the first liner layer 1402 may be formed by a deposition process (e.g., an ALD process, a CVD process, a PE-CVD process, etc.). In some embodiments, the first liner layer 1402 may be formed to be approximately About Between About The thickness is within the range between or other suitable values.

[0065] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , the second liner layer 1502 is formed within the second interconnect opening 1002 and above the first liner layer 1402. In some embodiments, the second liner layer 1502 may include cobalt, tungsten, ruthenium, etc. In some embodiments, the second liner layer 1502 may include a different material than the first liner layer 1402. In various embodiments, the second liner layer 1502 may be formed by a deposition process (e.g., an ALD process, a CVD process, a PE-CVD process, etc.). In some embodiments, the second liner layer 1502 may be formed to be approximately About Between About The thickness is within the range of or other suitable values.

[0066] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , the third conductive material 1602 is formed in the second interconnect opening 1002 and over the second liner layer 1502. In some embodiments, the third conductive material 1602 may be formed using a deposition process and / or a plating process (e.g., electroplating, chemical plating, etc.). In various embodiments, the third conductive material 1602 may include copper, aluminum, etc.

[0067] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17, a planarization process is performed. A planarization process is performed along line 1702 to remove the third conductive material ( Fig.16 1602) and defines a second interconnect 108. In some embodiments, the planarization process also removes the barrier layer ( Fig.16 1202), the first liner layer ( Fig.16 1402) and the second liner layer ( Fig.161502). The second interconnect 108 includes a first liner 208 contacting the first interconnect 106, a second liner 210 surrounded by the first liner 208, and a conductive inner portion 212 surrounded by the second liner 210. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. In some embodiments, the planarization process causes the upper surfaces of the barrier layer 110, the first liner 208, the second liner 210, and the conductive inner portion 212 to be substantially coplanar with the upper surface of the second ILD layer 204c (e.g., coplanar within the tolerance of the CMP process).

[0068] like Fig.18 As shown in cross-sectional view 1800 of FIG. 18 , capping layer 214 is formed over second interconnect 108. In some embodiments, capping layer 214 may be formed by multiple deposition cycles that form sublayers of capping layer 214, respectively. In some embodiments, multiple deposition cycles may be performed by depositing a metal over second interconnect 108 and then performing a plasma treatment, respectively. In some embodiments, the metal may include cobalt, ruthenium, tungsten, etc. In some embodiments, the plasma treatment may be performed by exposing the deposited metal to a plasma including nitrogen, hydrogen, etc. In some embodiments, the plasma may include an ammonia (NH 3 ) based plasma. In some embodiments, capping layer 214 may be formed at about About Between, about About The thickness is within the range of or other suitable values.

[0069] In some embodiments, the cover layer 214 may be formed to be completely confined over the second liner 210 and the conductive inner portion 212. In some such embodiments, the cover layer 214 may have a maximum width substantially equal to the maximum width of the second liner 218. In other embodiments, the cover layer 214 may be formed to be completely confined over the first liner 208, the second liner 210, and the conductive inner portion 212. In some such embodiments, the cover layer 214 may have a maximum width substantially equal to the maximum width of the first liner 208. In still other embodiments, the cover layer 214 may be formed to extend continuously beyond the opposite outermost edges of the first liner 208.

[0070] like Fig.19As shown in the cross-sectional view 1900 of FIG. 1 , the upper ILD layer 204d is formed over the second ILD layer 204c. In various embodiments, the upper ILD layer 204d may be formed by a deposition process (e.g., an ALD process, a CVD process, a PE-CVD process, etc.). In some embodiments, before forming the upper ILD layer 204d, an upper etch stop layer 502 may be formed on the second ILD layer 204c. In some embodiments, the upper etch stop layer 502 may include a multilayer etch stop layer having a first material 502a, a second material 502b over the first material 502a, and a third material 502c over the second material 502b. In some embodiments, the first material 502a, the second material 502b, and the third material 502c may include one or more of an oxide, a nitride, or a carbide.

[0071] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 2004 , the upper ILD layer 204d is patterned to define an upper interconnect opening 2002. In some embodiments, the upper ILD layer 204d may be patterned by selectively exposing the upper ILD layer 204d to a third etchant 2004 according to a second mask structure 2006. In some embodiments, the second mask structure 2006 may include a photoresist layer, a hard mask layer, etc. In various embodiments, the third etchant 2004 may include a dry etchant (e.g., having a chlorine etching chemistry, a fluorine etching chemistry, etc.) or a wet etchant (e.g., including hydrofluoric acid, potassium hydroxide, etc.).

[0072] like Fig.21 As shown in the cross-sectional view 2100 of , an upper interconnect 504 is formed in the upper interconnect opening 2002. The upper interconnect 504 may be formed to be separated from the upper ILD layer 204d by the upper barrier layer 506. In some embodiments, the upper barrier layer 506 is formed by depositing the upper barrier layer in the upper interconnect opening 2002. The upper interconnect 504 is then formed by forming a first upper liner layer on the upper barrier layer and in the upper interconnect opening 2002, forming a second upper liner layer on the first upper liner layer and in the upper interconnect opening 2002, and forming an upper conductive material on the second upper liner layer and in the upper interconnect opening 2002. After forming the upper conductive material, a planarization process (e.g., a CMP process) may be performed to remove excess upper conductive material, the first upper liner, the second upper liner, and / or the upper barrier layer from above the upper ILD layer 204d. The planarization process defines the upper interconnect 504 to have a first upper liner 508 over the upper barrier layer 506 , a second upper liner 510 over the first upper liner 508 , and an upper conductive inner portion 512 over the second upper liner 510 .

[0073] The upper barrier layer, the first upper liner layer, the second upper liner layer and the upper conductive material can be formed by a deposition process (e.g., CVD, PVD, PE-CVD, etc.). In some embodiments, the upper barrier layer may include tantalum, titanium, tantalum nitride, titanium nitride, etc. In various embodiments, the first upper liner layer may include tungsten, ruthenium, cobalt, etc. In some embodiments, the second upper liner layer may include a material different from the first upper liner. In various embodiments, the second upper liner layer may include tungsten, ruthenium, cobalt, etc. In various embodiments, the upper conductive material may include copper, aluminum, etc.

[0074] Fig. 22 A flow chart illustrating some embodiments of a method 2200 of forming an integrated chip having interconnects contacting at a barrier-free interface.

[0075] Although the disclosed method 2200 is shown and described herein as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be interpreted in a restrictive sense. For example, some steps may occur in different orders and / or occur simultaneously with other steps or events other than the steps or events shown and / or described herein. In addition, to implement one or more aspects of the embodiments, not all of the operations described are required. In addition, one or more operations described herein may be performed in one or more separate operations and / or stages.

[0076] At step 2202, a first interconnect is formed within a first inter-layer dielectric (ILD) layer over a substrate. Figure 6 to Figure 7 Cross-sectional views 600 to 700 corresponding to some embodiments of step 2202 are shown.

[0077] At step 2204 , a second ILD layer is formed over the first ILD layer. Figure 8 A cross-sectional view 800 corresponding to some embodiments of step 2204 is shown.

[0078] At step 2206 , the second ILD layer is etched to form an inner surface defining an interconnect opening exposing an upper surface of the first interconnect. Figures 8 to 10 Cross-sectional views 800 to 1000 corresponding to some embodiments of step 2206 are shown.

[0079] At step 2208, a barrier layer is formed on the upper surface of the first interconnect. In some embodiments, the barrier layer may include a self-assembled monolayer (SAM). Fig.11 A cross-sectional view 1100 corresponding to some embodiments of step 2208 is shown.

[0080] At step 2210, a barrier layer is selectively formed within the interconnect opening. Fig.12A cross-sectional view 1200 corresponding to some embodiments of step 2210 is shown.

[0081] At step 2212, the barrier layer is removed to expose an upper surface of the first interconnect. Fig.13 A cross-sectional view 1300 corresponding to some embodiments of step 2212 is shown.

[0082] At step 2214, a second interconnect is formed on the barrier layer and on an upper surface of the first interconnect. In some embodiments, the second interconnect can be formed according to steps 2216 to 2222.

[0083] At step 2216, a first liner is formed on an upper surface of the barrier layer and the first interconnect. Fig.14 A cross-sectional view 1400 corresponding to some embodiments of step 2216 is shown.

[0084] At step 2218, a second pad is formed on the first pad. Fig.15 A cross-sectional view 1500 corresponding to some embodiments of step 2218 is shown.

[0085] At step 2220, a conductive material is formed on the second pad. Fig.16 A cross-sectional view 1600 corresponding to some embodiments of step 2220 is shown.

[0086] At step 2222, a planarization process is performed to remove excess conductive material from over the second ILD layer and define a second interconnect. Fig.17 A cross-sectional view 1700 corresponding to some embodiments of step 2222 is shown.

[0087] At step 2224, a capping layer is formed on the second interconnect. Fig.18 A cross-sectional view 1800 corresponding to some embodiments of step 2224 is shown.

[0088] At step 2226 , an upper interconnect is formed in the upper ILD layer over the second ILD layer. Figures 19 to 21 Cross-sectional views 1900 to 2100 corresponding to some embodiments of step 2226 are shown.

[0089] Thus, in some embodiments, the present invention is directed to an integrated chip having an interconnect structure without a barrier layer vertically separating an interconnect from an underlying interconnect.

[0090] In some embodiments, the present invention relates to an integrated chip. The integrated chip includes: a first interconnect, which is arranged in an interlayer dielectric (ILD) structure above a substrate; a barrier layer, which is arranged along the sidewall of the ILD structure and has a sidewall defining an opening above the first interconnect; and a second interconnect, which is arranged on the barrier layer, the second interconnect extending through the opening in the barrier layer and reaching the first interconnect. In some embodiments, the barrier layer is arranged on an upper surface of the ILD structure, and the upper surface is laterally located between the sidewall of the ILD structure and the first interconnect. In some embodiments, the second interconnect includes a first liner arranged on the barrier layer and surrounding the conductive interior. In some embodiments, the first interconnect and the first liner include the same material; and the conductive interior and the first liner include different materials. In some embodiments, the integrated chip also includes a second liner, which is arranged on the first liner and surrounding the conductive interior. In some embodiments, the integrated chip also includes a capping layer arranged on the conductive interior and the second liner, and the capping layer and the second liner include the same material. In some embodiments, the barrier layer is laterally located outside the capping layer. In some embodiments, the first liner includes a lower surface resting on the barrier layer and a protrusion extending outward from the lower surface and through the barrier layer.

[0091] The integrated chip includes: a first interconnect, which is arranged in a first interlayer dielectric (ILD) layer above a substrate; a second ILD layer, which is arranged above the first ILD layer; a barrier layer, which extends along the sidewall of the second ILD layer and along the upper surface of the first ILD layer; and a first liner, which is arranged on the barrier layer and surrounds the conductive inner part, and the first liner extends through the barrier layer to the first interconnect. In some embodiments, the barrier layer includes: a vertical extension segment, which is arranged along the sidewall of the second ILD layer; and a horizontal extension segment, which protrudes from the vertical extension segment toward the first interconnect. In some embodiments, the first liner layer has a lower resistivity than the barrier layer. In some embodiments, the first interconnect and the first liner are the same material, which extends continuously from the bottom of the first interconnect to the top of the second ILD layer. In some embodiments, the barrier layer has sidewalls, and the sidewalls are spaced apart by a distance substantially equal to the width of the top surface of the first interconnect. In some embodiments, the conductive inner part is vertically closer to the first interconnect along the center of the bottom of the conductive inner part than along the outer edge of the bottom of the conductive inner part. In some embodiments, the conductive inner portion includes a lower surface directly above the barrier layer and a protrusion extending outward from the lower surface, the protrusion directly above the first interconnect. In some embodiments, the bottom surface of the barrier layer defines a closed loop around the first pad from a plan view of the barrier layer.

[0092] In other embodiments, the present invention relates to a method for forming an integrated chip. The method includes: forming a first interconnect in a first interlayer dielectric (ILD) layer above a substrate; forming a second ILD layer above the first ILD layer; patterning the second ILD layer to form a sidewall defining an interconnect opening, the interconnect opening exposing the upper surface of the first interconnect; forming a barrier layer on the upper surface of the first interconnect, the barrier layer being laterally separated from the sidewall of the second ILD layer; forming a barrier layer in the interconnect opening; removing the barrier layer to expose the upper surface of the first interconnect; and forming a second interconnect in the interconnect opening. In some embodiments, the barrier layer is removed after forming the barrier layer in the interconnect opening. In some embodiments, the barrier layer includes a self-assembled monolayer. In some embodiments, the method also includes: forming a first liner on the barrier layer and directly contacting the upper surface of the first interconnect; forming a conductive material on the first liner; and performing a planarization process to remove a portion of the conductive material from above the second ILD layer.

[0093] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip, comprising: a first interconnect disposed within an interlayer dielectric structure above the substrate; a barrier layer disposed along a sidewall of the interlayer dielectric structure and having a sidewall defining an opening above the first interconnect; as well as a second interconnect disposed on the barrier layer, wherein the second interconnect extends through the opening in the barrier layer and to the first interconnect, and wherein a bottommost surface of the barrier layer extends laterally past an inner sidewall of the barrier layer facing the second interconnect, The second interconnect includes a first pad, which is arranged on the barrier layer and surrounds the conductive interior, wherein the bottom of the first pad has a first portion extending laterally along the barrier layer and a second portion extending through the opening in the barrier layer, wherein the first portion and the second portion have different thicknesses.

2. The integrated chip according to claim 1, wherein: The barrier layer is disposed on an upper surface of the interlayer dielectric structure, the upper surface being laterally located between the sidewall of the interlayer dielectric structure and the first interconnection.

3. The integrated chip according to claim 1, wherein: The first liner includes ruthenium, cobalt, and tungsten.

4. The integrated chip according to claim 3, in, The first interconnect and the first gasket comprise the same material; and Wherein, the conductive inner portion and the first liner comprise different materials.

5. The integrated chip according to claim 3, further comprising: The second pad is disposed on the first pad and surrounds the conductive inner portion.

6. The integrated chip according to claim 5, further comprising: A cover layer is disposed on the conductive inner portion and the second liner, wherein the cover layer and the second liner include a same material.

7. The integrated chip according to claim 6, wherein: The barrier layer is laterally located outside the cover layer.

8. The integrated chip according to claim 3, wherein: The first pad includes a lower surface resting on the barrier layer and a protrusion extending outward from the lower surface through the barrier layer.

9. An integrated chip comprising: a first interconnect disposed in a first interlayer dielectric layer above the substrate; a second interlayer dielectric layer, disposed above the first interlayer dielectric layer; a barrier layer extending along the sidewalls of the second interlayer dielectric layer and along the upper surface of the first interlayer dielectric layer, wherein the barrier layer comprises: a vertical extension portion extending along the sidewalls of the second interlayer dielectric layer; and a horizontal extension portion extending from the vertical extension portion toward the first interconnect; a first liner disposed on the barrier layer and surrounding the conductive inner portion, wherein the first liner extends through the barrier layer to the first interconnect, wherein a bottom portion of the first liner has a first portion extending laterally along the barrier layer and a second portion extending through an opening in the barrier layer, wherein the first portion and the second portion have different thicknesses; and A second liner is disposed on the first liner and surrounds the conductive interior, wherein the first liner extends completely through the barrier layer to physically contact the first interconnect, and wherein the second liner has a bottommost surface that contacts the first liner along an interface that extends continuously between the outermost sidewalls of the second liner, the entirety of the interface being vertically located above an upper surface of the barrier layer, and the upper surface of the barrier layer is located directly below the conductive interior.

10. The integrated chip according to claim 9, wherein: The first liner includes ruthenium, cobalt, and tungsten.

11. The integrated chip according to claim 9, wherein: The first liner has a lower resistivity than the barrier layer.

12. The integrated chip according to claim 9, wherein: The first interconnection and the first liner are made of the same material, and the first liner continuously extends from a bottom of the first interconnection to a top of the second interlayer dielectric layer.

13. The integrated chip according to claim 9, wherein: The barrier layer has sidewalls that are spaced apart a distance substantially equal to a width of a top surface of the first interconnect.

14. The integrated chip according to claim 9, wherein: The conductive inner portion is vertically closer to the first interconnect along a center of a bottom of the conductive inner portion than along an outer edge of a bottom of the conductive inner portion.

15. The integrated chip according to claim 9, wherein: The conductive interior comprising: a lower surface directly above the barrier layer; and a protrusion extending outwardly from the lower surface, the protrusion being directly above the first interconnecting member.

16. The integrated chip according to claim 9, wherein: The bottom surface of the barrier layer defines a closed loop surrounding the first pad when viewed from a plan view of the barrier layer.

17. A method for forming an integrated chip, comprising: forming a first interconnect within a first interlayer dielectric layer over the substrate; forming a second interlayer dielectric layer over the first interlayer dielectric layer; patterning the second interlayer dielectric layer to form sidewalls defining an interconnect opening, the interconnect opening exposing an upper surface of the first interconnect; forming a barrier layer on the upper surface of the first interconnect, wherein the barrier layer is laterally separated from the sidewalls of the second interlayer dielectric layer by a space exposing an outermost sidewall of the barrier layer; forming a barrier layer within the interconnect opening; removing the barrier layer to expose the upper surface of the first interconnect; as well as A second interconnect is formed in the interconnect opening.

18. The method according to claim 17, wherein: The blocking layer is removed after forming the barrier layer within the interconnect opening.

19. The method according to claim 17, wherein: The barrier layer comprises a self-assembled monolayer.

20. The method of claim 17, further comprising: forming a first liner on the barrier layer and directly contacting the upper surface of the first interconnect; forming a conductive material on the first pad; as well as A planarization process is performed to remove a portion of the conductive material from over the second interlayer dielectric layer.

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