Transistor gate and method of forming the same

Abstract

This disclosure relates to transistor gates and methods of forming the same. A device includes: a semiconductor substrate; and a first gate stack disposed on the semiconductor substrate, the first gate stack being located between a first gate spacer and a second gate spacer. The device further includes a second gate stack disposed on the semiconductor substrate, the second gate stack being located between the first gate spacer and the second gate spacer; and a dielectric material separating the first gate stack and the second gate stack. The dielectric material is at least partially located between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material being greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer being less than a fourth width of a lower portion of the first gate spacer.

Description

Technical Field

[0001] This disclosure relates to transistor gates and methods for forming them. Background Technology

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a first gate stack disposed on the semiconductor substrate and between a first gate spacer and a second gate spacer; a second gate stack disposed on the semiconductor substrate and between the first gate spacer and the second gate spacer; and a dielectric material separating the first gate stack from the second gate stack, the dielectric material being at least partially disposed between the first gate spacer and the second gate spacer, wherein a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a first transistor located at a top surface of a semiconductor substrate, the first transistor including: a first channel region; and a first gate stack located above and along the sidewall of the first channel region; a second transistor located at a top surface of the semiconductor substrate, the second transistor including: a second channel region; and a second gate stack located above and along the sidewall of the second channel region; a dielectric material separating the first gate stack and the second gate stack in a channel width direction of the first transistor, the dielectric material including: a first portion having a first width; and a second portion located above the first portion, the second portion having a second width greater than the first width; and a first passivation region located between the second portion of the dielectric material and the first gate stack.

[0006] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: etching an opening in a gate stack, the opening exposing a sidewall of a gate spacer, the gate spacer being disposed on the sidewall of the gate stack; performing a processing in the opening, wherein the processing defines: a first passivation region located in the sidewall of the gate spacer; and a second passivation region located in the gate stack; using an etching process to extend the opening through the gate stack, the etching process removing the first passivation region; and after extending the opening through the gate stack, filling the opening with a dielectric material. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A and Figure 1B An example of a FinFET according to some embodiments is shown in a 3D view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 22E , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 26A , Figure 26B , Figure 26C , Figure 27 , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A , Figure 30B , Figure 31A , Figure 31B , Figure 32A and Figure 32B These are cross-sectional and top views of intermediate stages in the fabrication of a FinFET according to some embodiments.

[0010] Figure 33A , Figure 33B , Figure 34A , Figure 34B , Figure 35A , Figure 35B , Figure 36A , Figure 36B , Figure 36C , Figure 36D , Figure 37A , Figure 37B , Figure 38A and Figure 38BThese are cross-sectional and top views of intermediate stages in the fabrication of a FinFET according to some alternative embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the disclosure. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially related terms (such as "below," "below," "lower than," "above," "upper," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0013] This invention describes various embodiments applied to FinFETs. These embodiments can be applied to other transistor technologies, including nanosheet FETs (NSFETs, including gate-around-the-ring FETs (GAAFETs), nanowire FETs, nanosheet FETs, etc.).

[0014] In various embodiments, a dielectric material can be used to separate the metal gates of adjacent transistors. The dielectric material can be formed by patterning openings in a dummy gate stack or a metal gate stack and filling the openings with dielectric material. In various embodiments, the upper portion of the opening can be widened, thereby improving the gap-filling window of the dielectric material. For example, small critical dimensions can result in voids in the dielectric material, and these voids may subsequently be filled by undesirable materials (e.g., metal gate material in a dummy gate process). By widening the gap-filling window for the dielectric material, these voids can be reduced or eliminated. Furthermore, the lower portion of the opening may not be widened, and the effective gate width of adjacent gate stacks can be maintained. In some embodiments, widening the upper portion of the opening can be achieved through one or more cycles of processing and etching processes. Thus, an atomic layer etching (ALE) type process can be implemented to control the effective gate width and widen the dielectric material gap-filling window. Manufacturing defects can be reduced, and device performance can be improved.

[0015] Figure 1A and Figure 1B Examples of devices 10 and 20 according to some embodiments are shown in three-dimensional views. Each of devices 10 and 20 includes a FinFET and is similar, with the same reference numerals denoteing the same elements. Parts of devices 10 and 20 are cut away to show the following features (e.g., features outlined with dashed lines). Devices 10 and 20 each include a fin 52 located on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and fins 52 protrude over and between adjacent isolation regions 56. Although isolation regions 56 are described / illustrated as separate from the substrate 50, as used herein, the term "substrate" can be used to refer only to a semiconductor substrate or a semiconductor substrate including the isolation regions. Additionally, although fins 52 are illustrated as a single continuous material of the substrate 50, fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 52A refers to the portion extending between adjacent isolation regions 56. Figure 1A As shown, device 10 also includes a dummy fin 52' located between adjacent fins 52. The dummy fin 52' is optional and can be omitted, for example, in... Figure 1B In the device 20 shown.

[0016] A gate dielectric layer 92 extends along the sidewall of fin 52 and is located above the top surface of fin 52. A gate electrode 94 is located above the gate dielectric layer 92, and a gate mask layer 96 is located above the gate electrode 94. The gate dielectric layer 92, gate electrode 94, and gate mask layer 96 may also be disposed on the sidewall of the dummy channel region 52'. One or more gate spacers 86 may be located on the sidewalls of the gate dielectric layer 92, gate electrode 94, and gate mask layer 96. Source / drain regions 82 are disposed in fin 52A on opposite sides of the gate dielectric layer 92, gate electrode 94, and gate mask layer 96. Dummy fins 52' may be disposed between adjacent source / drain regions 82, physically separating adjacent source / drain regions 82. Source / drain regions 82 may also extend from a recessed portion of fin 52A.

[0017] Dielectric material 38 extends through the gate mask layer 96 into the gate electrode 94. Figure 1A In device 10, dielectric material 38 may extend to dummy fin 52', and the combination of dielectric material 38 and dummy fin 52' may isolate the gate electrode of adjacent FinFETs (e.g., see...). Figure 30A ).exist Figure 1B In device 20, dielectric material 38 may extend into isolation region 56 to isolate the gate electrode of adjacent FinFETs (e.g., see...). Figure 32A A contact etch stop layer (CESL) 87 is disposed over the isolation region 56, and a dielectric layer 88 is disposed over the CESL 87. The dielectric layer 88 may also surround the source / drain region 82, a portion of the dummy fin 52' (if present), the gate mask layer 96, the gate dielectric layer 92, and the gate electrode 94.

[0018] Figure 1A and Figure 1B Reference cross sections used in subsequent figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the current flow direction between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of fin 52, in a direction, for example, perpendicular to the current flow direction between the source / drain regions 82 of the FinFET. Cross section BB extends through the source / drain regions of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections. Cross section DD is parallel to cross section BB. Figure 1A In the middle, the cross-section DD extends through the dummy fin of the FinFET, while... Figure 1B In the middle, the cross section DD extends through the FinFET and intersects with... Figure 1A Similar locations.

[0019] Some embodiments discussed herein are described in the context of FinFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are considered for use in planar devices (e.g., planar FETs, NSFETs, etc.).

[0020] Figures 2 to 38B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figures 2 to 11 , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 21A , Figure 24A , Figure 25A , Figure 26A , Figure 27 , Figure 28A , Figure 29A , Figure 30A , Figure 31A , Figure 32A , Figure 33A , Figure 34A , Figure 35A , Figure 36A , Figure 37A and Figure 38A It shows Figure 1A The reference section AA shown in / 1B, in addition to the multiple fins / FinFETs. Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 24B , Figure 25B , Figure 26C , Figure 28B , Figure 29B , Figure 30B , Figure 31B , Figure 32B , Figure 37B and Figure 38B Along Figure 1A The similar cross section BB shown in / 1B illustrates the presence of multiple fins / FinFETs. Figure 14C , Figure 14D and Figure 14E It is shown along the reference section CC shown in Figure 1, in addition to the multiple fins / FinFETs. Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22A , Figure 23A , Figure 23B, Figure 23C , Figure 33B , Figure 34B , Figure 35B and Figure 36B Shown as along Figure 1A The reference cross section DD shown in / 1B, in addition to the multiple fins / FinFETs.

[0021] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate (typically a silicon or glass substrate). Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0022] Substrate 50 has region 50N and region 50P. Region 50N can be used to form n-type devices, such as NMOS transistors, or n-type FinFETs. Region 50P can be used to form p-type devices, such as PMOS transistors, or p-type FinFETs. Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0023] A hard mask 53 is deposited on the substrate 50. The hard mask 53 can be used to define the pattern of subsequently formed semiconductor fins. In some embodiments, the hard mask is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The hard mask 53 may include silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, the aforementioned multilayers, etc. For example, although only one hard mask layer is shown, a multilayer structure (e.g., a silicon oxide layer on a silicon nitride layer) can be formed as the hard mask 53.

[0024] Figures 3 to 32B Various additional steps in the manufacture of the embodiment device are shown. Figures 3 to 32B Features in either region 50N or region 50P are shown. For example, Figures 3 to 32BThe structure shown can be applied to both region 50N and region 50P. The structural differences between region 50N and region 50P (if any) are described in the text accompanying each figure.

[0025] Figures 3 to 7 Cross-sectional views of the fabrication of semiconductor fins and dummy fins according to various embodiments are shown (e.g., along...). Figure 1A The formation of the dummy fin is optional and may be omitted in other embodiments (e.g., as shown in section AA). Figure 1B (As shown). In Figure 3 In this embodiment, fins 52A and 52B are formed in substrate 50. Fins 52A / 52B are semiconductor strips. Fins 52A / 52B include fins 52B located between fins 52A. As will be described in the following figures, fins 52B may optionally be removed and replaced with dummy fins 52' (see [reference]). Figure 6 ).

[0026] In some embodiments, fin 52A can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. Etching can be anisotropic.

[0027] Fins can be patterned using any suitable method. For example, fins can be patterned using one or more photolithography processes that include dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, a mask (or other layer) may be retained on the fins 52A / 52B.

[0028] exist Figure 4In this embodiment, an insulating material 54 is formed on the substrate 50 and between adjacent fins 52A / 52B. The insulating material 54 can be an oxide, such as silicon oxide, a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In this embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52A / 52B. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a conformal liner (not shown) can be formed first along the surfaces of the substrate 50 and the fins 52A / 52B. A filler material, such as those discussed above, can then be formed on the liner.

[0029] Following deposition, a removal process is applied to the insulating material 54 to remove excess insulating material 54 located on the fins 52A / 52B. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back, or a combination thereof, can be used. The planarization process exposes the fins 52A / 52B such that, after the planarization process is completed, the fins 52A / 52B and the top surface of the insulating material 54 are flush. In embodiments where the mask 53 remains on the fins 52A / 52B, the planarization process may expose or remove the mask 53 such that, after the planarization process is completed, the mask or the fins 52A / 52B are flush with the top surface of the insulating material 54, respectively.

[0030] exist Figure 5 In this process, at least a portion of the fin 52B is removed using, for example, an acceptable etching process. Thus, an opening 55 is formed in the insulating material 54 located between the fins 52A. In subsequent processes, a dummy channel region can be formed in the opening 55. The fin 52B can be completely removed, or a portion of the fin 52B can be retained below the opening 55.

[0031] exist Figure 6 In this configuration, a dummy fin 52' is formed in the opening 55. The dummy fin 52' may comprise one or more layers of silicon-based materials (e.g., SiN, SiON, SiOCN, SiC, SiOC, SiO2, etc.), metal-based materials (e.g., metal oxides, metal nitrides, such as TaN, TaO, HfO, etc.), and / or similar materials. Although Figure 6The dummy fin 52' is shown as a single material, but the dummy fin 52' may comprise multiple layers of material, which may be vertically and / or horizontally stacked. For example, in some embodiments, the first layer of the dummy fin 52' may be aligned with the sidewalls and side surfaces of the second layer of the dummy fin 52'. As another example, a third layer of the dummy fin 52' may be disposed on top of the second layer of the dummy fin 52'. In some embodiments, the width W of the dummy fin 52' may be approximately to approximately Within the range.

[0032] The dummy fin 52' can be formed using one or more deposition processes (e.g., CVD, plasma-enhanced CVD (PECVD), plasma-enhanced ALD (PEALD), ALD, PVD, etc.). In embodiments where the dummy fin 52' comprises a multilayer structure, forming the dummy fin 52' may further include one or more etch-back and / or planarization steps prior to depositing one or more additional material layers of the dummy fin 52'. Furthermore, the dummy fin 52' can be deposited to initially cover the insulating material 54, and processes such as planarization and etch-back can be used to remove excess portions of the dummy fin 52' and expose the insulating material 54.

[0033] exist Figure 7 In this process, insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The insulating material 54 is recessed so that the upper portions of fins 52A and dummy fins 52' protrude from between adjacent STI regions 56. Furthermore, the top surface of the STI region 56 may have a flat surface, a raised surface, a recessed surface (e.g., concave), or a combination thereof, as shown. The top surface of the STI region 56 can be formed as flat, raised, and / or recessed by appropriate etching. The STI region 56 can be recessed using acceptable etching processes, such as selective etching processes for the material of insulating material 54 (e.g., etching the material of insulating material 54 at a faster rate than the material of fins 52). For example, it can be removed using, for example, an oxide of dilute hydrofluoric acid (dHF). The insulating material 54 can be recessed using a process that selectively etches the insulating material 54 compared to dummy fins 52' (if present).

[0034] refer to Figures 2 to 7 The described process is merely one example of how fin 52A can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed on the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form a fin. Additionally, in some embodiments, heteroepitaxial structures can be used for fin 52A. For example, Figure 7The fin 52A can be recessed, and a different material from the fin 52A can be epitaxially grown on the recessed fin 52A. In such an embodiment, the fin 52A includes a recessed material and an epitaxial growth material disposed on the recessed material. In yet another embodiment, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52A. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxial growth material can be in-situ doped during growth, which avoids prior and subsequent implantation, although in-situ and implantation doping can be used together.

[0035] Furthermore, it may be advantageous to epitaxially grow a material different from that in region 50P (e.g., the PMOS region) in region 50N (e.g., the NMOS region). In various embodiments, the upper portion of fin 52A may be made of silicon-germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0036] In addition, Figure 7 In this process, suitable wells (not shown) may be formed in fin 52A and / or substrate 50. In some embodiments, a P-well may be formed in region 50N and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.

[0037] In embodiments with different well types, different implantation steps for regions 50N and 50P can be implemented using photoresist or other masks (not shown). For example, photoresist can be formed over fin 52A and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into region 50N (e.g., an NMOS region). The n-type impurity can be phosphorus, arsenic, antimony, etc., which are implanted into the region at a concentration of 10 or less. 18 cm -3 The concentration, for example, at about 1016 cm -3 Peace Treaty 10 18 cm -3 Between. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0038] After implantation into region 50P, photoresist is formed over fin 52A and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into region 50P (e.g., a PMOS region). The p-type impurity can be boron, boron fluoride, indium, etc., with an implantation depth of at least 10 ppm in the region. 18 cm -3 The concentration, for example, at about 10 16 cm -3 Peace Treaty 10 18 cm -3 Between. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0039] After implantation into regions 50N and 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, although in-situ and implantation doping can be used together.

[0040] exist Figure 7 In one embodiment, the dummy fin 52' is shown to have a top surface that is substantially flush with (e.g., within manufacturing tolerances) the top surface of fin 52A. For example, the height H1 by which fin 52A extends over STI region 56 is equal to the height H2 by which dummy fin 52' extends over STI region 56. Other configurations are also possible. For example, height H1 may be less than or greater than height H2, and the top surface of dummy fin 52' may be higher or lower than the top surface of fin 52A.

[0041] Figures 3 to 7 This is just one example of how the dummy fin 52' can be formed. Other methods are also possible. For example, Figures 8 to 10 The intermediate steps for forming a dummy fin 52' in device 15 according to an alternative embodiment are shown. Figures 8 to 10 In this context, the same reference numerals indicate the use of the same as those mentioned above. Figures 3 to 7 The same components are formed using the same processes as described in the text. Figure 8 In, for example, using the above Figure 2A process similar to that described herein forms fins 52 extending from substrate 50. A hard mask 53 is used to pattern the fins 52 and can be retained on the fins 52.

[0042] For example Figure 8 As shown, insulating material 54 is deposited on and along the sidewalls of fins 52. The insulating material 54 can be deposited using a conformal process, which only partially fills the space between the fins 52. As a result of the deposition process, openings 55 are defined between the fins 52 and on the insulating material 54. One or more materials can then be filled into the openings 55 to form dummy fins 52'.

[0043] exist Figure 9 In this configuration, a dummy fin 52' is formed in the opening 55. The dummy fin 52' can be disposed between fins 52, and the dummy fin 52' can be embedded in an insulating material 54. For example, the insulating material 54 can contact the bottom surface and sidewalls of the dummy fin 52'. The dummy fin 52' can be formed using the method described above. Figure 6 The process described is similar to the process used to perform the operation.

[0044] exist Figure 10 In this process, the insulating material 54 is etched back to expose the sidewalls of the fin 52, expose the sidewalls of the dummy fin 52', and define the STI region 56. The etched-back insulating material 54 can be the same as the one referenced above. Figure 7 The process described is similar to the process described above. Therefore, the method for forming the dummy fin 52' can be accomplished according to alternative embodiments. The subsequent description of the additional process can be applied to device 10 (e.g., Figure 7 (as shown) or device 15 (e.g.) Figure 10 (As shown).

[0045] Figures 11 to 31B A cross-sectional view is shown of the additional steps involved in manufacturing device 10. It should be understood that these steps can also be applied to device 15 (e.g., ...). Figure 10 (as shown) or device 20 (see) Figure 1B ).exist Figure 11 In this device 10, a dummy dielectric layer 60 is formed on the fins 52A and dummy fins 52'. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques.

[0046] A dummy gate layer 62 is formed over a dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 may be deposited over the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polycrystalline silicon), polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used for depositing the selected material. The dummy gate layer 62 may be made of other materials that have high etch selectivity relative to the etching of the isolation region.

[0047] Mask layer 64 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across regions 50N and 50P. It should be noted that, for illustrative purposes only, a dummy dielectric layer 60 covering only fin 52A is shown. In some embodiments, the dummy dielectric layer 60 may be deposited such that it covers STI region 56 and extends between the dummy gate layer 62 and STI region 56.

[0048] Figures 12A to 16B The additional intermediate stages of manufacturing are shown. Figures 12A to 16B In the diagram, the one ending with "A" is along... Figure 1A and Figure 1B The corresponding section AA is shown, and the attached figure ending with "B" is along... Figure 1A and Figure 1B The corresponding section BB is shown. Figure 14C , Figure 14D and Figure 14E It is along Figure 1A and Figure 1B The corresponding section CC is shown.

[0049] exist Figure 12A and Figure 12B In the middle, mask layer 64 (see Figure 11The mask 74 can be patterned using acceptable photolithography and etching techniques. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using acceptable etching techniques to form the dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52A. The dummy gate 72 also covers the top surface and sidewalls of the dummy fin 52'. The pattern of the mask 74 can be used to physically separate each of the dummy gates 72 from the adjacent dummy gates. The longitudinal direction of the dummy gate 72 can also be substantially perpendicular to the longitudinal direction of the corresponding epitaxial fin 52A.

[0050] In addition, Figure 12A and Figure 12B In this process, a gate sealing spacer 80 can be formed on the exposed surfaces of the dummy gate 72, mask 74, and / or fin 52A / dummy fin 52'. The gate sealing spacer 80 can be formed by thermal oxidation or deposition followed by anisotropic etching. The gate sealing spacer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc.

[0051] After the gate sealing spacer 80 is formed, implantation of lightly doped source / drain (LDD) regions (not explicitly shown) can be performed. In embodiments with different device types, similar to the above... Figure 6 The implantation discussed earlier can involve forming a mask, such as photoresist, over region 50N while exposing region 50P, and implanting an impurity of an appropriate type (e.g., p-type) into the exposed fins 52A in region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The impurity concentration in the lightly doped source / drain regions can be between approximately 10⁻⁶. 15 cm -3 Peace Treaty 10 19 cm -3 Annealing can be used to repair injection damage and activate injected impurities.

[0052] exist Figure 13A and Figure 13B In this configuration, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0053] It should be noted that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the gate sealing spacer 80 may not be etched before forming the gate spacer 86, resulting in an "L-shaped" gate sealing spacer, spacers can be formed and removed, etc.). Furthermore, different structures and steps can be used to form n-type and p-type devices. For example, the LDD region for an n-type device can be formed before forming the gate sealing spacer 80, while the LDD region for a p-type device can be formed after forming the gate sealing spacer 80.

[0054] exist Figures 14A to 14E In the fin 52A, epitaxial source / drain regions 82 are formed. The source / drain regions 82 can apply stress to the corresponding channel regions 58, thereby improving performance. The epitaxial source / drain regions 82 are formed in the fin 52A such that each dummy gate 72 is disposed between each pair of adjacent epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into and may penetrate the fin 52A. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 82 do not short-circuit the subsequently formed gate of the resulting FinFET.

[0055] The epitaxial source / drain region 82 in region 50N (e.g., an NMOS region) can be formed by masking region 50P (e.g., a PMOS region) and etching the source / drain region of fin 52A in region 50N to form a trench in fin 52A. The epitaxial source / drain region 82 in region 50N is then epitaxially grown in the trench. The epitaxial source / drain region 82 can comprise any acceptable material, such as materials suitable for n-type FinFETs. For example, if fin 52A is silicon, the epitaxial source / drain region 82 in region 50N can comprise a material for applying tensile strain in channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 82 in region 50N can have a surface protruding from the corresponding surface of fin 52A and can have a small facet.

[0056] The epitaxial source / drain region 82 in region 50P (e.g., a PMOS region) can be formed by masking region 50N (e.g., an NMOS region) and etching the source / drain region of fin 52A in region 50P to form a groove in fin 52A. The epitaxial source / drain region 82 in region 50P is then epitaxially grown in the groove. The epitaxial source / drain region 82 can include any acceptable material, such as materials suitable for p-type FinFETs. For example, if fin 52A is silicon, the epitaxial source / drain region 82 in region 50P can include a material that applies compressive strain in channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 82 in region 50P can also have a surface protruding from the corresponding surface of fin 52A and can have a facet.

[0057] The epitaxial source / drain regions 82 and / or fins 52A can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions followed by annealing. The impurity concentration of the source / drain regions can be between approximately 10⁻⁶. 19 cm -3 Peace Treaty 10 21 cm -3 Between. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities mentioned above. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0058] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P, the small facets on the upper surfaces of the epitaxial source / drain regions extend laterally outward beyond the sidewalls of fin 52A. A gate spacer 86 is formed, which covers the portion of the sidewalls of fin 52A extending above STI region 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacer 86 can be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of STI region 56.

[0059] In embodiments with dummy fin 52', such as Figure 14C As shown, after the epitaxial process is completed, adjacent source / drain regions 82 remain separated. For example, source / drain regions 82 can be grown to physically contact dummy fins 52', which physically separate adjacent source / drain regions 82 from each other. Therefore, it is possible to prevent adjacent epitaxial source / drain regions 82 from merging and unintentionally short-circuiting.

[0060] In other embodiments (e.g., Figure 1BDevice 20) may not form a dummy fin 52'. In such an embodiment, the small facets of the epitaxial source / drain regions 82 cause adjacent source / drain regions 82 of the same FinFET to merge, such as Figure 14D As shown. In other embodiments, such as Figure 14E As shown, after the epitaxial process is completed, adjacent source / drain regions 82 remain separated. Figure 14C , Figure 14D and Figure 14E In the illustrated embodiment, a gate spacer 86 is formed that covers a portion of the sidewall of the fin 52 extending above the STI region 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacer 86 may be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 56.

[0061] exist Figure 15A and Figure 15B In the middle, the first interlayer dielectric (ILD) 88 is deposited on Figure 14A and Figure 14B The structure shown is above the first ILD 88. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain region 82, mask 74, and gate spacer 86. CESL 87 can include a dielectric material having an etch rate different from that of the material overlying the first ILD 88, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0062] exist Figure 16A and Figure 16B In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72, as well as portions of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, gate sealing spacers 80, gate spacers 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 can be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0063] Figures 17A to 21B An additional intermediate stage is shown in which dielectric material is formed in the dummy gate 72 to separate the gates of adjacent transistors. Figures 17A to 21B In the middle, along Figure 1A and Figure 1B The corresponding section AA is shown in the attached figure ending with "A", and along... Figure 1A and Figure 1B The corresponding section DD is shown in the attached figure ending with "B".

[0064] exist Figure 17A and Figure 17B In this embodiment, an opening 30 is patterned in the dummy gate 72. In some embodiments, the opening 30 may be aligned with and positioned directly above the dummy fin 52'. For example, the opening 30 may be formed in the dummy gate 72 by a combination of photolithography and etching. The opening 30 may expose a gate spacer (e.g., gate sealing spacer 80 / gate spacer 86, see [link]). Figure 17B The sidewalls of the opening 30. The depth of the opening 30 can be controlled by adjusting one or more parameters of the etching process (e.g., etching time, etc.).

[0065] In some embodiments, etching the opening 30 in the dummy gate 72 includes a plasma process, such as plasma etching, remote plasma etching, radical etching, etc. The etching gas used during the plasma process may include Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, combinations thereof, etc. The plasma process may also include flowing a passivation gas over the device 10 to adjust (e.g., increase) the etching selectivity between the dummy gate 72 and other features of the device 10. The passivation gas may include N2, O2, CO2, SO2, CO, SiCl4, combinations thereof, etc. One or more carrier gases may also be used during the plasma process, such as Ar, He, Ne, combinations thereof, etc. Furthermore, the plasma process can be performed at a plasma source power in the range of about 10 W to about 3000 W, a bias power in the range of about 0 W to about 3000 W, a pressure in the range of about 1 mTorr to about 800 mTorr, and a gas mixture flow rate in the range of about 10 sccm to about 5000 sccm, etc.

[0066] In some embodiments, etching the opening 30 in the dummy gate 72 includes a wet etching process (sometimes referred to as wet cleaning). Etching agents that can be used during the wet etching process may include HF, F2, combinations thereof, etc. The wet etching process may also include allowing auxiliary etching chemicals to flow over the device 10 to adjust (e.g., increase) the etching selectivity between the dummy gate 72 and other features of the device 10. Auxiliary etching chemicals may include H2SO4, HCl, HBr, NH3, combinations thereof, etc. Deionized water (DIW), alcohols, acetone, etc., may be used as solvents for mixing the etchant and / or auxiliary etching chemicals during the wet etching process.

[0067] exist Figure 18A and Figure 18B In this process, processing 32 is applied to device 10, for example, to the sidewalls and bottom surface of opening 30. Processing 32 can form passivation regions 34 and 36 on the sidewalls and bottom surface of opening 30. Passivation region 34 can be formed in dummy gate 72, and passivation region 36 can be formed in gate spacers (e.g., gate sealing spacer 80 and / or gate spacer 86). Furthermore, although not explicitly shown, processing 32 can also form passivation regions in other exposed surfaces of wafer 10 (e.g., the upper surface of dummy gate 72 and the upper surface of first ILD 88). Such passivation regions can be removed in subsequent processing steps.

[0068] Processing technology 32 can be a conversion process that converts the exposed portion of the dummy gate 72 into a passivation region 34 and the exposed portion of the gate spacer (e.g., gate sealing spacer 80 and optional gate spacer 86) into a passivation region 36. Processing technology 32 can be performed in situ (e.g., in the same process chamber) or off-site (e.g., in different process chambers) of the etching process to form the opening 30. The respective thickness of each of the passivation region 34 and the passivation layer 36 can be approximately to approximately Within the range.

[0069] In some embodiments, the processing technology 32 includes a plasma process, such as plasma injection. The passivation gas used during the plasma process may include N2, O2, CO2, SO2, CO, combinations thereof, etc. The plasma process may also include the inflow of additional gases, such as carbon-based (CH4), silicon-based gases (e.g., SiCl4), combinations thereof, etc., to help form passivation regions 34 and 36. Furthermore, the plasma process can be performed at a plasma source power in the range of about 10 W to about 3000 W, a bias power in the range of about 0 W to about 3000 W, a pressure in the range of about 1 mTorr to about 800 mTorr, and a gas mixture flow rate in the range of about 10 sccm to about 5000 sccm, etc.

[0070] In some embodiments, process 32 is a non-plasma dry chemical process using a process gas (e.g., HF, NF3, CH4, combinations thereof, etc.). In some embodiments, process 32 is a wet process using a solution containing deionized water (DIW), O3, CO2, HF, HCl, NH3, combinations thereof, etc. In some embodiments, process 32 is a deposition process that reacts with existing materials of the dummy gate 72 and the gate spacer and also deposits a dielectric material (e.g., SiN, SiON, SiCON, SiC, SiOC, SiO2, SiC, combinations thereof) on the surface of the opening 30. In such embodiments, passivation regions 34 and 36 include the reaction regions of the dummy gate 72, the reaction regions of the gate spacer, and the deposited dielectric material. The deposition process may include ALD, CVD, combinations thereof, etc.

[0071] Because the material of the dummy gate 72 differs from the material of one or more gate spacers (e.g., gate sealing spacer 80 / gate spacer 86), the material composition of the processing region 34 can differ from that of the processing region 36. For example, in an embodiment where the processing process 32 includes the use of nitrogen and the gate spacers include oxygen, the passivation region 34 may include silicon and nitrogen, while the passivation region 36 may include silicon, oxygen, and nitrogen. As another example where the processing process 32 includes the use of oxygen and the gate spacers include nitrogen, the passivation region 34 may include silicon and oxygen, while the passivation region 36 may include silicon, oxygen, and nitrogen. As another example where the processing process 32 includes the use of nitrogen and the gate spacers include nitrogen, the nitrogen concentration in the passivation region 34 may be lower than that in the passivation region 36. As another example where the processing process 32 includes the use of oxygen and the gate spacers include oxygen, the oxygen concentration in the passivation region 34 may be lower than that in the passivation region 36. Therefore, the processing process 32 forms two distinct passivation regions 34 and 36, and etch selectivity can be achieved between the passivation regions 34 and 36. Etching selectivity can also be achieved between the passivation region 36 and the rest of the gate spacer.

[0072] exist Figure 19A and Figure 19B In this process, an etching process is applied to the dummy gate 72, which extends the opening 30 further toward the dummy fin 52' (if present) and the semiconductor substrate 50. In some embodiments, the opening 30 may be extended to expose the dummy fin 52' or the semiconductor substrate 50.

[0073] The etching process can be selected between the material of the passivation region 36 and the material of the gate spacer (e.g., gate sealing spacer 80), such that the etching process removes the passivation region 36. For example, the etching process can remove the material of the passivation region 36 at a higher rate than the material of the gate spacer. As a result, and as... Figure 19B As shown, the width W1 of the upper part of the opening 30 can be greater than the width W2 of the lower part of the opening 30.

[0074] Furthermore, the etching process can be a directional process that removes the passivation region 34 from the bottom surface of the recess 30 without significantly removing the passivation region 34 from the sidewalls of the recess 30. In some embodiments, the etching process can select between the materials of the passivation regions 34 and 36, such that the material of the passivation region 36 is removed from the sidewalls of the opening 30 without significantly removing the passivation region 34 from the sidewalls of the opening 30. As a result, the effective gate width of the dummy gate 72 (and the corresponding alternative metal gate) can be maintained, thereby improving the device performance of the resulting device.

[0075] In some embodiments, removing the passivation region 36 and enlarging the opening 30 includes a plasma process, such as plasma etching, remote plasma processing, radical etching, etc. The etching gas used during the plasma process may include Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, combinations thereof, etc. The plasma process may also include flowing a passivation gas over the device 10 to adjust (e.g., increase) the etching selectivity between the dummy gate 72 and other features of the device 10. The passivation gas may include N2, O2, CO2, SO2, CO, SiCl4, combinations thereof, etc. One or more carrier gases, such as Ar, He, Ne, combinations thereof, etc., may also be used during the plasma process. Furthermore, the plasma process can be performed at a plasma source power in the range of about 10 W to about 3000 W, a bias power in the range of about 0 W to about 3000 W, a pressure in the range of about 1 mTorr to about 800 mTorr, and a gas mixture flow rate in the range of about 10 sccm to about 5000 sccm, etc.

[0076] In some embodiments, removing the passivation region 36 and expanding the opening 30 includes a wet etching process (sometimes referred to as wet cleaning). Etching agents that can be used during the wet etching process may include HF, F2, combinations thereof, etc. The wet etching process may also include allowing auxiliary etching chemicals to flow over the device 10 to adjust (e.g., increase) the etching selectivity between the dummy gate 72 and other features of the device 10. Auxiliary etching chemicals may include H2SO4, HCl, HBr, NH3, combinations thereof, etc. Deionized water (DIW), alcohols, acetone, etc., may be used as solvents for mixing the etchant and / or auxiliary etching chemicals during the wet etching process.

[0077] although Figures 18A to 19B A processing and etching cycle is shown applied to opening 30 to expose the dummy fin 52', but any number of processing and etching cycles can be performed. For example, see reference... Figures 18A to 19B The described steps can be repeated any number of times until the dummy fin 52' is exposed and the opening 30 has the desired profile. By repeating the above processing and etching processes, an atomic layer etching process can be achieved to form an opening with an extended upper portion.

[0078] exist Figure 20A and Figure 20BIn the opening 30, dielectric material 38 is filled. Dielectric material 38 can be deposited using PVD, CVD, ALD, PECVD, etc. Dielectric material 38 can be deposited first to overfill the opening 30 and cover the top surfaces of the dummy gate 72 and the first ILD 88. Subsequently, a planarization process (e.g., CMP, etc.) can be performed to remove excess dielectric material 38 from above the dummy gate 72 and the first ILD 88.

[0079] In device 10, which includes dummy fins 52', dielectric material 38, combined with dummy fins 52', divides the dummy gate 72 into different regions (e.g., regions 72A and 72B). In device 20, which does not include dummy fins 52', dielectric material 38 separately divides the dummy gate 72 into different regions 72A and 72B (see [link to device 10]). Figure 21A and Figure 21B In device 20, dielectric material 38 extends into and contacts semiconductor substrate 50. Regions 72A and 72B may, for example, correspond to the locations of different transistor devices. Thus, dielectric material 38 and dummy fins 52' (if present) can provide isolation between adjacent FinFETs.

[0080] As a result of widening the upper portion of the opening 30, the upper portion of the dielectric material 38 can have a width W1 that is greater than the width W2 of the lower portion of the dielectric material 38. The widened opening 30 allows the dielectric material 38 to be filled with fewer defects (e.g., voids). The widened opening 30 also results in the gate spacers (e.g., gate sealing spacer 80 and / or gate spacer 86) being thinner on the upper portion of the dielectric material 38 than on the lower portion. For example, the upper portion of the gate spacer is thinner than the lower portion. Furthermore, by reducing the etching along the bottom portion of the dummy gate 72, the effective gate width of the dummy gate 72 (and subsequently formed replacement gates) can be maintained.

[0081] Figure 20C and Figure 20D A top view of dielectric material 38 is shown. Figure 20C It shows along Figure 20B The top view intercepted by line XX, and Figure 20D It shows along Figure 20B The top view taken by the YY line. For example... Figure 20C and Figure 20D As shown, the upper region of the dielectric material 38 is wider than the lower region of the dielectric material 38. Furthermore, in Figure 20CIn this configuration, the upper region of the dielectric material 38 may extend toward the second sidewall of the gate spacer 80 / 86 through the first sidewall of the gate spacer 80 / 86. The first sidewall may abut the dummy gate 72, and the second sidewall is opposite to a corresponding one of the first sidewalls. In the upper region, the dielectric material 38 has a width W1, which is greater than the dimension CD1 of the dummy gate 72. The dimension CD1 may be the distance between the opposing sidewalls of the dummy gate 72, measured along the channel length direction of the dummy gate 72. The width W1 of the dielectric material 38 may also be less than the dimension CD2 of the gate spacer 80 / 86. The dimension CD2 may be the distance between the opposing outer sidewalls (e.g., the second sidewalls) of the gate spacer 80 / 86. Figure 20D In this configuration, the dielectric material 38 can be defined by the first sidewall of the gate spacers 80 / 86. For example, the dielectric material 38 in... Figure 20D The lower region shown has a width W2, and the width W2 can be equal to the dimension CD1 of the dummy gate 72. The width W2 can also be smaller than the dimension CD2 of the gate spacer 80 / 86.

[0082] Figures 22A to 22E An optional structure for dielectric material 38 is shown, which can be applied to device 10 (see [reference]). Figure 20A and Figure 20B ) or device 20 (see Figure 21A and Figure 21B ). Figure 22A A cross-sectional view of the dielectric layer 38 having regions 38A, 38B, 38C and 38D is shown. Figure 22B , Figure 22C , Figure 22D and Figure 22E A top view of each of regions 38A, 38B, 38C, and 38D is shown. Each of regions 38A, 38B, 38C, and 38D has a different width, which decreases in the direction toward the semiconductor substrate 50 (see [reference]). Figure 20A and Figure 21A For example, region 38A has a width W3, which is greater than the width W4 of region 38B. The width W3 can also be greater than the dimension CD3 of the dummy gate 72 and greater than the dimension CD4 of the gate spacers 80 / 86. Figures 22B to 22EIn this context, dimension CD3 can be the distance between opposite sidewalls of the dummy gate 72, measured along the channel length direction of the dummy gate 72, while dimension CD4 can be the distance between opposite outer sidewalls of the gate spacers 80 / 86 (e.g., opposite to the dummy gate 72). The width W4 of region 38B is greater than the width W5 of region 38C. Width W4 can also be greater than dimension CD3 of the dummy gate 72 and equal to dimension CD4 of the gate spacers 80 / 86. The width W5 of region 38C is greater than the width W6 of region 38D. Width W5 can be less than dimension CD4 of the gate spacers 80 / 86 and greater than dimension CD3 of the dummy gate 72. Width W6 can be equal to dimension CD3 of the dummy gate 72 and less than dimension CD4 of the gate spacers 80 / 86.

[0083] Figures 22A to 22E The configuration can be found in the application above. Figures 18A to 19B The process described is generated through multiple loops. For example, Figures 22A to 22E This can be achieved by applying three cycles. Furthermore, by applying multiple cycles, the upper portion of the gate spacers 80 / 86 can be completely removed, allowing the sidewalls of the dielectric material 38 to directly contact the first ILD 88. In other embodiments, additional cycles or fewer cycles may be applied. For example, in other embodiments, one or more of regions 38A or 38B may be omitted, or the dielectric material 38 may include one or more additional regions (e.g., wider regions) located above region 38A.

[0084] Figures 23A to 23C A cross-sectional view of an additional embodiment of dielectric material 38 is shown. Figures 20A to 22E Compared to the embodiment (which shows dielectric material 38 as having substantially (e.g., within manufacturing tolerances) straight sidewalls that are substantially perpendicular to the main surface of semiconductor substrate 50), dielectric material 38 may also have sloping sidewalls. Figure 23A An embodiment is shown in which the dielectric material 38 has a continuously and constantly decreasing width in the direction toward the semiconductor substrate 50. Figure 23B An embodiment is shown in which the dielectric material 38 has a continuously decreasing width in the direction toward the semiconductor substrate 50. For example, in Figure 23B In this process, the width of the dielectric material 38 can be abruptly reduced at discrete intervals. Figure 23CAn embodiment is shown in which the dielectric material 38 has both straight and sloping sidewalls, and the gate spacers 80 / 86 extend only partially along the sidewalls of the dielectric material 38. The portion of the dielectric material 38 defined by the gate spacers 80 / 86 may have a width that continuously and consistently decreases in the direction toward the semiconductor substrate 50, while the portion of the dielectric material 38 above the gate spacers 80 / 86 may have a substantially constant width (e.g., within manufacturing tolerances).

[0085] Figures 24A to 32B This illustrates the additional intermediate stages involved in forming the replacement gate and contacts to a transistor device. Figures 24A to 32B In the middle, along Figure 1A and Figure 1B The corresponding section AA is shown in the attached figure ending with "A", and along... Figure 1A and Figure 1B The corresponding section BB is shown in the attached figure ending with "B".

[0086] exist Figure 24A and Figure 24B In one or more etching steps, the remaining dummy gate 72 and mask 74 (if present) are removed to form a recess 90. A portion of the dummy dielectric layer 60 located in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, while the dummy dielectric layer 60 is retained and exposed by the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., a core logic region) and the dummy dielectric layer 60 is retained in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etches the dummy gate 72 without etching the first ILD 88 or the gate spacer 86. Each recess 90 exposes and / or covers the channel region 58 of the corresponding fin 52A. Each channel region 58 is disposed between each pair of adjacent epitaxial source / drain regions 82. During removal, when the dummy gate 72 is etched, the dummy dielectric layer 60 can be used as an etch stop layer.

[0087] Then, after removing the dummy gate 72, the dummy dielectric layer 60 can be selectively removed. In some embodiments, the dummy dielectric layer 60 may have the same or similar material composition as the passivation region 34. Therefore, removing the dummy dielectric layer 60 may also remove part or all of the passivation region 34 (e.g., as shown in the image). Figure 25A and Figure 25B (As shown).

[0088] exist Figure 26A and Figure 26B In this process, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 26C It shows Figure 26B Detailed view of area 89. Figure 27 An embodiment in which the passivation region 35 is removed is shown, in which a gate dielectric layer 92 and a gate electrode 94 are formed. The gate dielectric layer 92 is conformally deposited in a recess 90, for example, on the top surface and sidewalls of fin 52A, on the sidewalls of dummy fin 52', on the sidewalls of dielectric material 38, on the sidewalls of passivation region 34 (if present), and on the sidewalls of gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. According to some embodiments, the gate dielectric layer 92 comprises silicon oxide, silicon nitride, or a multilayer of the foregoing. In some embodiments, the gate dielectric layer 92 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In an embodiment in which a portion of the dummy gate dielectric 60 is retained in the recess 90, the gate dielectric layer 92 comprises the material of the dummy gate dielectric 60 (e.g., SiO2).

[0089] Gate electrodes 94 are deposited on the gate dielectric layer 92 and fill the remainder of the recess 90. By removing a portion of the thin film 106 from the sidewalls of the dummy fin 52', the space between the fin 52 and the dummy fin 52' can be increased. As a result, gate electrodes 94 can be deposited with fewer defects (e.g., fewer voids) in the space around and between the fin 52 and the dummy fin 52'.

[0090] The gate electrode 94 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although in Figure 26B The diagram shows a single-layer gate electrode 94, but the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler material 94C, such as... Figure 26CAs shown. After filling the recess 90, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 92 and gate electrode 94, which lies above the top surface of the ILD 88. The remaining material of the gate electrode 94 and gate dielectric layer 92 thus forms the replacement gate of the resulting FinFET. The gate electrode 94 and gate dielectric layer 92 can be collectively referred to as the “gate stack”. The gate and gate stack can extend along the sidewalls of the channel region 58 of the fin 52A. When adjacent gate stacks correspond to different FinFETs, the dielectric material 38 and dummy fins 52' isolate adjacent gate stacks (e.g., gate stacks 92A / 94A and gate stacks 92B / 94B). For example, gate stacks 92A / 94A are arranged along the channel width direction and separated from gate stacks 92B / 94B in the channel width direction by the dielectric material 38 and dummy fins 52' (if present). Adjacent gate stacks can be separated and arranged along the channel width direction of the FinFET.

[0091] The formation of the gate dielectric layer 92 in regions 50N and 50P can occur simultaneously, such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed using different processes, such that the gate dielectric layer 92 can be made of different materials, and / or the gate electrode 94 in each region can be formed using different processes, such that the gate electrode 94 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0092] exist Figure 28A and Figure 28B In this process, the gate stack (including the gate dielectric layer 92 and the corresponding overlying gate electrode 94) is recessed, such that a groove is formed directly above the gate stack and between the opposite portions of the gate spacer 86. The etching process can be selective, such that the dielectric material 38 is not significantly etched. The groove is filled with a gate mask 96 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), followed by a planarization process to remove excess portions of the dielectric material extending above the first ILD 88. The gate contact 110 is then formed. Figure 29A and Figure 29B It penetrates the gate mask 96 to contact the top surface of the recessed gate electrode 94. The dielectric material 38 may extend through the gate mask 96.

[0093] exist Figure 29A and Figure 29BIn this process, the second ILD 108 is deposited on top of the first ILD 88. In some embodiments, the second ILD 108 is a flowable thin film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material (e.g., PSG, BSG, BPSG, USG, etc.) and can be deposited by any suitable method (e.g., CVD and PECVD).

[0094] Also in Figure 29A and Figure 29B As shown, according to some embodiments, the gate contact 110 and the source / drain contact 112 are formed to pass through the second ILD 108 and the first ILD 88. Figure 30A and Figure 30B A similar step is shown in an embodiment in which the passivation region 34 has been removed. Figure 31A and Figure 31B A similar manufacturing stage in device 20 is shown, wherein the dummy fin 52' is omitted, and Figure 32A and Figure 32B A similar manufacturing stage in device 20 is shown, where the dummy fin 52' is omitted and the passivation region 34 is also removed. An opening for the source / drain contact 112 is formed through the first ILD 88 and the second ILD 108, and an opening for the gate contact 110 is formed through the second ILD 108 and the gate mask 96. This opening can be formed using acceptable photolithography and etching techniques. Liners and conductive materials, such as diffusion barrier layers and adhesion layers, are formed within the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the surface of the ILD 108. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 110 within the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 106. The source / drain contact 112 and the gate contact 110 can be formed in different processes or in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 112 and the gate contact 110 can be formed in a different cross-section, which avoids short circuits in the contacts.

[0095] The above embodiments describe forming the dielectric material 38 prior to the gate stack 92 / 94. In other embodiments, the gate stack (e.g., including the gate dielectric 92 and the gate electrode 94) may be formed prior to the formation of the dielectric material 38. For example, Figures 33A to 36D An intermediate cross-sectional view is shown, illustrating the formation of the dielectric material using, for example, a metal gate dicing process, after a 92 / 94 gate stack. Figures 33A to 36B In the diagram, the one ending with "A" is along... Figure 1A and Figure 1B The corresponding section AA is shown, and the attached figure ending with "B" is along... Figure 1A and Figure 1B The corresponding cross section DD is shown. Figure 36C and Figure 36D A top view is shown. Figures 33A to 36D The above reference shows Figures 17A to 20D The processes described are similar, wherein the same reference numerals denote the same components formed using the same processes.

[0096] exist Figure 33A and Figure 33B In this process, gate stacks 92 / 94 can be etched to define an opening (e.g., as referenced above). Figure 17A and Figure 17B (as described). In an embodiment with a dummy fin 52', the opening 30 may be formed directly above the dummy fin 52'.

[0097] Processing techniques can be applied to opening 30 (e.g., as referenced above). Figure 18A and Figure 18B The above-mentioned) and etching processes (e.g., as referenced above) Figure 19A and Figure 19B One or more cycles of the above) until the dummy fin 52' or STI region 56 is exposed. Figure 34A and Figure 34B The processing technology is shown. Figure 35A and Figure 35B The etching process is illustrated. As... Figure 34A and Figure 34B As a result of one or more processing steps, a passivation region 40 may be formed in the gate electrode 94. The passivation region 40 may include the material of the gate electrode 94 and the elements used during one or more processing steps. For example, the passivation region 40 may include metal oxides, metal nitrides, etc.

[0098] exist Figure 36A and Figure 36B Then, dielectric material 38 can be deposited in the opening 30 (e.g., as referenced above). Figures 20A to 20DThe dielectric material 38 and dummy fins 52' (if present) separate the gate stacks 92A / 94A and 92B / 94B of adjacent transistor devices. For example, the gate stacks 92A / 94A are arranged along the channel width direction and separated from the gate stacks 92B / 94B in the channel width direction by the dielectric material 38 and dummy fins 52' (if present). The passivation region 40 may have a generally uniform material composition and is disposed on the sidewalls of the dielectric material 38. For example, the passivation region 40 may separate a portion of the dielectric material 38 from the gate electrode 94. Figure 36C A top-down view of the upper portion of the dielectric material is shown (e.g., along...). Figure 36B (The line XX is cut off), and Figure 36D A top-down view of the lower portion of the dielectric material 38 is shown (e.g., along...). Figure 36B (The line YY is cut off). As shown in the figure, the width W1 of the upper part of the dielectric material 38 can be wider than the width W2 of the lower part of the dielectric material 38.

[0099] The above references can be applied. Figures 28A to 29B A similar process is described to recess the gate stack 92 / 94, form a gate mask layer 96 on top of the recessed gate stack 92 / 94, and form contacts to the transistor. Figure 37A and Figure 37B The resulting structure is shown in the figure. Figure 38A and Figure 38B An alternative embodiment is shown in which the dummy fin 52' is not included and the dielectric material 38 is formed after the gate stack 92 / 94.

[0100] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructured (e.g., nanosheets, nanowires, gate-around, etc.) field-effect transistors (NSFETs). In NSFET embodiments, fins are formed by patterning a stack of alternating channel and sacrificial layers. Embodiments may include, for example, two to ten channel / sacrificial layer pairs. In some embodiments, the width of the stack can be approximately to approximately Within a certain range, for example, in approximately to approximately Within the range. The dummy gate stack and source / drain are formed in a manner similar to that described above. After removing the dummy gate stack, the sacrificial layer may be partially or completely removed in the channel region. The replacement gate structure is formed in a manner similar to that described above, and the channel layer is partially or completely surrounded in the channel region of the NSFET device. The ILD and contacts to the gate structure and source / drain are formed in a manner similar to that described above. The nanostructure device may be formed as disclosed in U.S. Patent Application Publication 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0101] In various embodiments, a dielectric material can be used to separate the metal gates of adjacent transistors. The dielectric material can be formed by patterning openings in a dummy gate stack or a metal gate stack and filling the openings with the dielectric material. The upper portion of the opening can be widened to improve the gap-filling window of the dielectric material and reduce manufacturing defects. Furthermore, the lower portion of the opening may not be widened, and the effective gate width of adjacent gate stacks can be maintained. In some embodiments, widening the upper portion of the opening can be achieved through one or more cycles of processing and etching. Therefore, an atomic layer etching process can be implemented to control the effective gate width and expand the gap-filling window of the dielectric material. Manufacturing defects can be reduced, and device performance can be improved.

[0102] In some embodiments, a device includes: a semiconductor substrate; and a first gate stack disposed on the semiconductor substrate, the first gate stack being located between a first gate spacer and a second gate spacer. The device further includes a second gate stack disposed on the semiconductor substrate, the second gate stack being located between the first gate spacer and the second gate spacer; and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially located between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material being greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer being less than a fourth width of a lower portion of the first gate spacer. In some embodiments, a fifth width of an upper portion of the second gate spacer is less than a sixth width of a lower portion of the second gate spacer. In some embodiments, the device further includes a passivation region disposed between the upper portion of the dielectric material and the first gate stack. In some embodiments, the passivation region comprises a metal oxide or a metal nitride. In some embodiments, the device further includes a dummy fin disposed below the dielectric material, the dummy fin separating the first gate stack from the second gate stack. In some embodiments, the dielectric material extends into and contacts the shallow trench isolation (STI) region. In some embodiments, the dielectric material has sloping sidewalls. In some embodiments, the dielectric material has straight sidewalls perpendicular to the main surface of the semiconductor substrate. In some embodiments, the upper portion of the dielectric material is located above the first gate spacer and the second gate spacer. In some embodiments, the upper portion of the first gate spacer contacts the sidewall of the upper portion of the dielectric material. In some embodiments, the first width is greater than the distance between the first sidewall and the second sidewall of the first gate stack, which is measured along the channel length direction of the first gate stack.

[0103] In some embodiments, a device includes: a first transistor located at a top surface of a semiconductor substrate, the first transistor including: a first channel region; and a first gate stack located above and along the sidewalls of the first channel region; a second transistor located at a top surface of the semiconductor substrate, the second transistor including: a second channel region; and a second gate stack located above and along the sidewalls of the second channel region; a dielectric material separating the first gate stack and the second gate stack in a channel width direction of the first transistor, the dielectric material including: a first portion having a first width; and a second portion located above the first portion, the second portion having a second width greater than the first width; and a first passivation region located between the second portion of the dielectric material and the first gate stack. In some embodiments, the device further includes a first gate spacer along the first sidewalls of the first transistor, the second transistor, and the dielectric material; and a second gate spacer along the second sidewalls of the first transistor, the second transistor, and the dielectric material. In some embodiments, the device further includes a dummy fin located below and adjacent to the dielectric material, the dummy fin separating the first gate stack from the second gate stack in the channel width direction of the first transistor.

[0104] In some embodiments, a method includes: etching an opening in a gate stack that exposes a sidewall of a gate spacer disposed on the sidewall of the gate stack; performing a processing step in the opening, wherein the processing step defines: a first passivation region located in the sidewall of the gate spacer; and a second passivation region located in the gate stack; using an etching process to extend the opening through the gate stack, the etching process removing the first passivation region; and filling the opening with a dielectric material after extending the opening through the gate stack. In some embodiments, the gate stack includes a metal gate electrode. In some embodiments, the gate stack is a dummy gate stack, and the method further includes replacing the gate stack with a second gate stack after filling the opening with the dielectric material. In some embodiments, extending the opening through the gate stack includes exposing a dummy fin. In some embodiments, the etching process is a directional etching process. In some embodiments, the etching process is selective etching that removes the first passivation region at a rate greater than that removing the second passivation region.

[0105] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or realizing the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

[0106] Example 1 is a semiconductor device comprising: a semiconductor substrate; a first gate stack disposed on the semiconductor substrate and between a first gate spacer and a second gate spacer; a second gate stack disposed on the semiconductor substrate and between the first gate spacer and the second gate spacer; and a dielectric material separating the first gate stack from the second gate stack, the dielectric material being at least partially disposed between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material being greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer being less than a fourth width of a lower portion of the first gate spacer.

[0107] Example 2 is the device described in Example 1, wherein the fifth width of the upper portion of the second gate spacer is smaller than the sixth width of the lower portion of the second gate spacer.

[0108] Example 3 is the device described in Example 1, further comprising: a passivation region located between the upper portion of the dielectric material and the first gate stack.

[0109] Example 4 is the device described in Example 3, wherein the passivation region comprises a metal oxide or a metal nitride.

[0110] Example 5 is the device described in Example 1, further comprising: a dummy fin located below the dielectric material, the dummy fin separating the first gate stack from the second gate stack.

[0111] Example 6 is the device described in Example 1, wherein the dielectric material extends into and contacts the shallow trench isolation (STI) region.

[0112] Example 7 is the device described in Example 1, wherein the dielectric material has inclined sidewalls.

[0113] Example 8 is the device described in Example 1, wherein the dielectric material has straight sidewalls perpendicular to the main surface of the semiconductor substrate.

[0114] Example 9 is the device described in Example 1, wherein the upper portion of the dielectric material is located above the first gate spacer and the second gate spacer.

[0115] Example 10 is the device described in Example 1, wherein the upper portion of the first gate spacer is in contact with the sidewall of the upper portion of the dielectric material.

[0116] Example 11 is the device described in Example 1, wherein the first width is greater than the distance between the first sidewall of the first gate stack and the second sidewall of the first gate stack, the distance being measured along the channel length direction of the first gate stack.

[0117] Example 12 is a semiconductor device comprising: a first transistor located at a top surface of a semiconductor substrate, the first transistor including: a first channel region; and a first gate stack located above and along the sidewalls of the first channel region; a second transistor located at a top surface of the semiconductor substrate, the second transistor including: a second channel region; and a second gate stack located above and along the sidewalls of the second channel region; a dielectric material separating the first gate stack and the second gate stack in a channel width direction of the first transistor, the dielectric material including: a first portion having a first width; and a second portion located above the first portion, the second portion having a second width greater than the first width; and a first passivation region located between the second portion of the dielectric material and the first gate stack.

[0118] Example 13 is the device described in Example 12, further comprising: a first gate spacer along a first sidewall of the first transistor, the second transistor, and the dielectric material; and a second gate spacer along a second sidewall of the first transistor, the second transistor, and the dielectric material.

[0119] Example 14 is the device described in Example 12, further comprising: a dummy fin located below and adjacent to the dielectric material, the dummy fin separating the first gate stack from the second gate stack in the channel width direction of the first transistor.

[0120] Example 15 is a method for forming a semiconductor device, comprising: etching an opening in a gate stack that exposes a sidewall of a gate spacer disposed on the sidewall of the gate stack; performing a processing in the opening, wherein the processing defines: a first passivation region located in the sidewall of the gate spacer; and a second passivation region located in the gate stack; using an etching process to extend the opening through the gate stack, the etching process removing the first passivation region; and after extending the opening through the gate stack, filling the opening with a dielectric material.

[0121] Example 16 is the method described in Example 15, wherein the gate stack includes a metal gate electrode.

[0122] Example 17 is the method of Example 15, wherein the gate stack is a dummy gate stack, and the method further includes replacing the gate stack with a second gate stack after filling the opening with the dielectric material.

[0123] Example 18 is the method of Example 15, wherein causing the opening to extend through the gate stack includes exposing a dummy fin.

[0124] Example 19 is the method described in Example 15, wherein the etching process is a directional etching process.

[0125] Example 20 is the method of Example 15, wherein the etching process is a selective etching of the first passivation region at a greater rate than the removal of the second passivation region.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; A first gate stack is located on the semiconductor substrate and between a first gate spacer and a second gate spacer. A second gate stack is located on the semiconductor substrate and between the first gate spacer and the second gate spacer; as well as A dielectric material separating the first gate stack from the second gate stack, the dielectric material being at least partially located between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material being greater than a second width of a lower portion of the dielectric material, the first width and the second width being measured along a cross section extending through the first gate spacer and the second gate spacer, the second width being equal to the width of the first gate stack measured along a cross section extending through the first gate spacer and the second gate spacer, and a third width of an upper portion of the first gate spacer being less than a fourth width of a lower portion of the first gate spacer.

2. The device according to claim 1, wherein, The fifth width of the upper portion of the second gate spacer is smaller than the sixth width of the lower portion of the second gate spacer.

3. The device according to claim 1, further comprising: A passivation region is located between the upper portion of the dielectric material and the first gate stack.

4. The device according to claim 3, wherein, The passivation region includes metal oxides or metal nitrides.

5. The device according to claim 1, further comprising: A dummy fin is located below the dielectric material and separates the first gate stack from the second gate stack.

6. The device according to claim 1, wherein, The dielectric material extends into and contacts the shallow trench isolation STI region.

7. The device according to claim 1, wherein, The dielectric material has inclined sidewalls.

8. The device according to claim 1, wherein, The dielectric material has straight sidewalls perpendicular to the main surface of the semiconductor substrate.

9. The device according to claim 1, wherein, The upper portion of the dielectric material is located above the first gate spacer and the second gate spacer.

10. The device according to claim 1, wherein, The upper portion of the first gate spacer is in contact with the sidewall of the upper portion of the dielectric material.

11. The device according to claim 1, wherein, The first width is greater than the distance between the first sidewall of the first gate stack and the second sidewall of the first gate stack, the distance being measured along the channel length direction of the first gate stack.

12. A semiconductor device, comprising: A first transistor, located at the top surface of a semiconductor substrate, comprises: The first trench area; and A first gate stack is located on and along the sidewall of the first channel region; A second transistor, located at the top surface of the semiconductor substrate, comprises: The second trench area; and A second gate stack is located above and along the sidewall of the second channel region; A dielectric material, wherein the dielectric material separates the first gate stack from the second gate stack in the channel width direction of the first transistor, the dielectric material comprising: The first part, the first part having a first width; and The second part is located above the first part, and the second width of the second part is greater than the first width; A first passivation region is located between a second portion of the dielectric material and the first gate stack; A first gate spacer, the first gate spacer being along a first sidewall of the first transistor, the second transistor, and the dielectric material; and A second gate spacer is located along the second sidewall of the first transistor, the second transistor, and the dielectric material. Wherein, the first width and the second width are measured along a cross section extending through the first gate spacer and the second gate spacer, and wherein the first width is equal to the width of the first gate stack measured along a cross section extending through the first gate spacer and the second gate spacer.

13. The device according to claim 12, further comprising: A dummy fin is located below and adjacent to the dielectric material, and the dummy fin separates the first gate stack from the second gate stack in the channel width direction of the first transistor.

14. A method for forming a semiconductor device, comprising: An opening is etched in the gate stack, the opening exposing the sidewalls of the gate spacers, and the gate spacers are disposed on the sidewalls of the gate stack; A processing technique is performed in the opening, wherein the processing technique is defined by the following: A first passivation region is located in the sidewall of the gate spacer; and A second passivation region is located within the gate stack; An etching process is used to extend the opening through the gate stack, the etching process removing the first passivation region; and After the opening extends through the gate stack, the opening is filled with a dielectric material. Wherein, the first width of the upper portion of the dielectric material is greater than the second width of the lower portion of the dielectric material, the first width and the second width are measured along a cross section extending through the gate spacer, and wherein the second width is equal to the width of the gate stack measured along a cross section extending through the gate spacer.

15. The method according to claim 14, wherein, The gate stack includes a metal gate electrode.

16. The method of claim 14, wherein, The gate stack is a dummy gate stack, and the method further includes replacing the gate stack with a second gate stack after filling the opening with the dielectric material.

17. The method of claim 14, wherein, This causes the opening to extend through the gate stack, including the exposure of dummy fins.

18. The method according to claim 14, wherein, The etching process is a directional etching process.

19. The method of claim 14, wherein, The etching process is a selective etching process that removes the first passivation region at a greater rate than the removal of the second passivation region.

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