Semiconductor device and method of forming a semiconductor device

Abstract

A semiconductor device and a method of forming a semiconductor device include a semiconductor substrate, a semiconductor insulating layer, an oxide layer, and one or more device features. The semiconductor insulating layer completely covers the semiconductor substrate. The oxide layer completely covers the semiconductor insulating layer. The one or more device features are formed over the oxide layer. The disclosure provides robust isolation across an SOI structure. In contrast to forming a charge-trapping layer in specific regions on the structure, the charge-trapping layer can be built across the insulating / substrate interface. The charge-trapping layer can be an implant layer formed through and under the insulating layer. Devices built on this SOI structure have reduced cross-talk between devices. Due to the uniform structure, the isolation is robust across the structure and not limited to certain regions. Additionally, deep trench implants are not needed to form the structure, eliminating costs. The semiconductor-on-insulator substrate can include an active silicon layer on the oxide layer. The oxide layer can be on the charge-trapping layer. The charge-trapping layer can be on the silicon substrate.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and more particularly, to semiconductor-on-insulator devices and methods for fabricating the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic equipment. As technology has advanced, the demand for smaller semiconductor devices with improved performance has increased. As feature density increases, the size of transistors and the spaces between transistors also need to be proportionally smaller.

[0003] Integrated circuits have traditionally been formed on bulk semiconductor substrates. In recent years, semiconductor-on-insulator (SOI) has emerged as an alternative to bulk semiconductor substrates. SOI substrates offer advantages over bulk semiconductor substrates in terms of reducing crosstalk. SOI substrates include a substrate and an insulating layer overlying the substrate. A device layer can be constructed over the insulating layer.

[0004] To adapt to the development of front-end processes, there is a need for improved semiconductor-on-insulator (SOI) substrates and devices and methods for forming the same. Summary of the Invention

[0005] One aspect of the present disclosure provides a semiconductor device comprising a semiconductor substrate, a semiconductor insulating layer, an oxide layer, and one or more device features. The semiconductor insulating layer completely covers the semiconductor substrate. The oxide layer completely covers the semiconductor insulating layer. The one or more device features are formed above the oxide layer.

[0006] One aspect of the present disclosure provides a semiconductor device comprising a semiconductor substrate, a semiconductor insulating layer, a buried oxide layer, and one or more device features. The semiconductor insulating layer extends along the entirety of an active region. The buried oxide layer completely covers the semiconductor insulating layer. The one or more device features are formed above the buried oxide layer in the active region.

[0007] One aspect of the present disclosure provides a method for forming a semiconductor device, comprising the following steps: providing a first substrate; forming a buried oxide layer; forming an active layer; and forming a semiconductor insulating layer between the buried oxide layer and the first substrate, the semiconductor insulating layer extending entirely across the active device area without interruption. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 and Figure 2 illustrates a cross-sectional view of a section of an example semiconductor device according to some embodiments;

[0010] Figure 3 illustrating a method for producing a novel substrate-on-insulator device according to some embodiments;

[0011] Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 Illustration of a method according to some embodiments Figure 3 cross-sectional views of an example semiconductor device during various stages of fabrication;

[0012] Figure 14 illustrating a method for producing a novel substrate-on-insulator device according to some embodiments;

[0013] Figure 15 and Figure 16 Illustration of a method according to some embodiments Figure 14 cross-sectional views of an example semiconductor device during various stages of fabrication;

[0014] Figure 17 Illustration of a method according to some embodiments Figure 3 or Figure 14 cross-sectional views of an example semiconductor device during various stages of fabrication;

[0015] Figure 18 Illustration of a method according to some embodiments Figure 3 or Figure 14 An example of a multilayer semiconductor device manufactured by the method.

[0016]

Explanation of symbols

[0017] 110,410:Semiconductor substrate / substrate

[0018] 112: Charge trapping layer / semiconductor isolation layer

[0019] 114: Oxide layer / Buried oxide layer / BOX / Insulation layer

[0020] 116: First epitaxial layer

[0021] 120: Metal Oxide Semiconductor Field Effect Transistor or MOSFET Structure

[0022] 302~322,1602~1622: Steps

[0023] 416: Second epitaxial layer DETAILED DESCRIPTION

[0024] Silicon-on-insulator (SOI) devices have significantly lower device crosstalk than bulk silicon devices. However, performance can be degraded when a highly conductive charge layer forms at the insulator-substrate interface of the SOI structure. This can be attributed to a degradation in SOI isolation performance.

[0025] To prevent the formation of this charge layer, a charge trapping layer 112 or semiconductor isolation layer 112 can be formed at the interface between the insulating layer 114 and the substrate. This can be formed at specific areas on the device, but this approach has drawbacks. It requires implantation via deep trenches, which increases costs and results in reinforced isolation limited to specific areas on the substrate. Therefore, there is a need for a low-cost SOI structure that provides reinforced isolation across the SOI structure.

[0026] The present disclosure provides enhanced isolation across SOI structures. Instead of forming a charge trapping layer in specific regions on the structure, a charge trapping layer can be built across the insulator / substrate interface (or sometimes, the oxide / silicon interface). The charge trapping layer can be an implanted layer that penetrates and forms beneath the insulating layer. Devices built on this SOI structure can have reduced crosstalk between devices. Due to the uniform structure, isolation is enhanced across the structure and is not confined to certain regions. Additionally, deep trench implants are not required to form the structure, thereby eliminating costs.

[0027] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. In addition, in various examples, the disclosure may repeat reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0028] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0029] As used herein, the term "nominal" refers to a desired or target value for a characteristic or parameter set during the design phase of a product or process for a component or process operation, together with a range of values ​​above and / or below the desired value. The range of values ​​is typically due to slight variations in manufacturing processes or tolerances.

[0030] The term "vertical" as used herein means nominally perpendicular to the surface of the substrate.

[0031] The present disclosure provides various embodiments of a silicon-on-insulator structure. The silicon-on-insulator structure can provide enhanced isolation of devices formed on its surface. The present disclosure also provides methods of manufacturing the silicon-on-insulator structure. The present disclosure also discloses semiconductor devices including the silicon-on-insulator structure and methods of forming the same. The semiconductor device can be included in a microprocessor, a memory cell, and / or other integrated circuits (ICs). Note that Figure 3 The method does not produce a finished semiconductor device. A finished semiconductor device can be manufactured using complementary metal-oxide-semiconductor (CMOS) technology. Therefore, it should be understood that Figure 3 Additional processes are provided before, during, and after methods 302 to 322, and some other processes may only be briefly described herein. Again, for a better understanding of the present disclosure, Figures 1 to 2 、 Figures 4 to 14 and Figures 16 to 18 For example, although these figures illustrate semiconductor devices, it should be understood that an IC may include many other devices, including transistors, resistors, capacitors, inductors, fuses, and the like.

[0032] Figure 1 and Figure 2 Illustrated is a cross-sectional view of a section of an example semiconductor structure, in accordance with some embodiments. Figure 3 is a flow chart of a method for manufacturing a semiconductor device according to various aspects of the present disclosure. Figure 4、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 Shown in accordance with Figure 3 Schematic cross-sectional views of a semiconductor device at various fabrication stages according to an embodiment of the present invention. Figure 14 A method of producing a novel substrate-on-insulator device according to some embodiments is illustrated. Figure 15 and Figure 16 Illustration of a method according to some embodiments Figure 15 Cross-sectional views of an example semiconductor device during various fabrication stages fabricated by a method of Figure 16 and Figure 17 Illustration of a method according to some embodiments Figure 15 Cross-sectional views of an example semiconductor device during various fabrication stages fabricated by a method of Figure 18 Illustration of a method according to some embodiments Figure 3 or Figure 15 An example of a silicon-on-insulator substrate manufactured by the method.

[0033] Figure 1 An example of a type of device that can be formed according to some embodiments is shown. In one embodiment, a metal oxide semiconductor field effect transistor, or MOSFET, structure 120 can be formed on an active silicon layer 116. Active silicon layer 116 can be directly on oxide layer 114, which can be referred to as a buried oxide layer 114 or BOX. BOX 114 can be directly on charge trapping layer 112. Charge trapping layer 112 can be formed on substrate 110.

[0034] Figure 2 An example structure that can be formed according to some embodiments is shown. The structure can include an active silicon layer 116. Active silicon layer 116 can be directly on an insulating layer 114, such as an oxide layer 114, which can be referred to as a buried oxide layer 114 or BOX. Insulating layer 114 can be directly on charge trapping layer 112. Charge trapping layer 112 can be formed on substrate 110. Figure 2 The entire structure can be used as a silicon-on-insulator (SOI) substrate to form many types of devices. This SOI can be used instead of bulk silicon to make any device that can use bulk silicon.

[0035] Figure 3One embodiment of a method for producing a silicon-on-insulator substrate is shown. Method 300 may proceed to step 302 where substrate 110 is secured. Next, at step 304, a charge trapping layer 112 may be formed. Next, at step 306, an oxide layer 114 may be deposited.

[0036] In parallel with steps 302 to 306, the following steps 316 to 322 may be performed. First, in step 316, a wafer may be secured. Next, in step 318, an implanted surface may be formed. Next, in step 320, a surface may be formed by epitaxy 116 / 416. Next, in step 322, a second surface may be formed by epitaxy.

[0037] At step 308, the wafer from step 306 may be bonded to the wafer at step 322. Next, at step 310, the surface of the bonded wafer may be removed to reveal the first epitaxial layer 116 / 416. At step 312, the surface may be further removed to expose the second epitaxial layer 116.

[0038] Figures 4 to 13 Graphic Figure 3 A cross-sectional view of an embodiment of the method illustrated in FIG. In some embodiments, steps may be combined. For example, in some embodiments, the method may be performed by tightening Figure 6 Steps 316 and 318 are combined by securing the doped device semiconductor substrate 110 / 112 to the substrate 110 / 112 shown in FIG.

[0039] See Figure 3 and Figure 5 Method 300 proceeds to step 302 where a semiconductor substrate 110 is secured. Semiconductor substrate 110 is a substrate such as that used in the manufacture of semiconductor integrated circuits, and integrated circuits may be formed therein and / or thereon. As used herein, the term "semiconductor substrate" refers to any structure comprising semiconductor material, for example, a silicon substrate with or without an epitaxial layer.

[0040] In some embodiments, semiconductor substrate 110 is a high-resistivity silicon wafer. The high-resistivity silicon wafer may be single crystal silicon. In some embodiments, the high-resistivity silicon wafer has a bulk resistivity greater than 40 ohm-cm. In some embodiments, the high-resistivity silicon wafer has a bulk resistivity greater than 1 kOhm-cm. In some embodiments, the high-resistivity silicon wafer has a bulk resistivity greater than 10 kOhm-cm. The high-resistivity silicon wafer may have a bulk resistivity between 1 kOhm-cm and 10 kOhm-cm. These values ​​are given as examples, and other values ​​and ranges of values ​​are within the scope of the present disclosure. The high-resistivity silicon wafer may form a substrate for a silicon-on-insulator structure, which may be due in part to the substrate's resistivity. The surface of the wafer may be passivated, for example, by thin film deposition. A pre-cleaning process may be performed to clean the surface of the substrate. This process may be a wet cleaning process (such as RCA cleaning) or a dry cleaning process (such as thermal or plasma treatment).

[0041] See Figure 3 and Figure 6 Method 300 proceeds to step 304, where a charge trapping layer 112 is formed. Charge trapping layer 112 may be an amorphous or disordered silicon layer. Charge trapping layer 112 may be an implanted silicon layer. Charge trapping layer 112 may contain a plurality of crystal defects that can trap charge carriers. Charge trapping layer 112 may be composed of one layer or multiple layers.

[0042] In some embodiments, the charge trapping layer 112 can be formed by implanting a substance, such as by ion implantation. The ion implantation can be continuous on the substrate. According to an exemplary embodiment, the implanted substance can be a charge-neutral substance. In some cases, the implanted substance can be a substance with a large atomic weight. The implanted substance can be an inert gas. Non-limiting examples of implanted substances include Xe, Ar, Ge, Si, and combinations thereof. The thickness of the charge trapping layer 112 or semiconductor isolation layer 112 can be, for example, between about 5 nm and about 300 nm. This thickness can be sufficient to prevent charge accumulation in the structure and can be manufactured using the processes disclosed herein.

[0043] The implant depth can range from 5 nm to 300 nm. In some embodiments, the implant depth can be between 1 nm and 300 nm. 12 ions / cm 2 with 1e 15 ions / cm 2 In some embodiments, the implantation process may be performed using a dose greater than or equal to 1e 15 ions / cm 2 The implant process may be performed at a dose of approximately 1 kV to approximately 1 MV. In some embodiments, the implant process may be performed at an energy ranging between approximately 1 kV and approximately 1 MV. These values ​​are given as examples, and other values ​​and ranges of values ​​are within the scope of the present disclosure.

[0044] See Figure 3 and Figure 7 , method 300 proceeds to step 306, where an insulating layer 114 is formed. Insulating layer 114 may be an oxide layer 114. In one example, oxide layer 114 may be silicon dioxide. Insulating layer 114 may form a buried oxide, or BOX. In some embodiments, insulating layer 114 may be between 10 nm and 10,000 nm. In some embodiments, insulating layer 114 may be between 10 nm and 1,000 nm. In some embodiments, insulating layer 114 may be between 10 nm and 800 nm. Insulating layer 114 may be between 10 nm and 600 nm. These values ​​are given as examples, and other values ​​and value ranges are within the scope of the present disclosure.

[0045] The insulating layer 114 may be formed by deposition. Non-limiting deposition methods include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), remote plasma enhanced chemical vapor deposition (RPECVD), liquid source misted chemical vapor deposition (LSMCD), coating, spin coating, or another process suitable for forming a thin film layer on a substrate. The insulating layer 114 may be formed by thermal growth. Thermal growth may include gas immersion in a gas such as N2, H2, CO2, O2, air, or a mixture thereof at ambient temperature or elevated temperature. Other methods of forming the insulating layer may include plasma treatment in a vacuum environment or in the presence of a gas such as N2, H2, NH3, CO2, O2, air, or a mixture thereof at ambient temperature or elevated temperature. If the insulating layer 114 is an oxide, the oxide layer 114 may be formed by wet oxidation (e.g., by a thermal treatment using steam). The oxide layer 114 may be formed using dry oxidation (eg, by thermal or plasma treatment in air or O 2 ).

[0046] See Figure 3 and Figure 8 , method 300 proceeds to step 316, which can be performed in parallel with steps 302 to 306. At step 316, semiconductor substrate 410 is secured. Substrate 410 can be a device wafer. Secured substrate 410 can be P- / P+ silicon, allowing method 300 to skip step 318.

[0047] See Figure 3 and Figure 9 In some embodiments, method 300 proceeds to step 318, which can be performed in parallel with steps 302 to 306. At step 318, an implanted interface is formed on semiconductor substrate 410. The implanted interface can transform substrate 410 from device silicon to P- / P+ silicon. Implantation can occur by ion implantation, for example, by doping with dopant atoms such as boron, phosphorus, or arsenic. These are merely examples, and those skilled in the art are well aware of various methods for forming doped silicon.

[0048] See Figure 3 and Figure 10 , method 300 proceeds to step 320, which may be performed in parallel with steps 302 to 306. At step 320, layer 416 may be formed by epitaxial growth. This layer may be silicon germanium. Silicon germanium may be expressed as Si 1-x Ge x , where x is the atomic percentage of germanium in the silicon germanium and may be greater than 0 and less than or equal to 1. According to other embodiments, the layer may be a III-V compound semiconductor material, such as GaAs, InP, GaN, InGaAs, InAlAs, GaAs, GaSb, AlAs, AlP, GaP, or many others. Epitaxial growth may occur via molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), metal-organic CVD (MOCVD), or similar processes.

[0049] See Figure 3 and Figure 11 , method 300 proceeds to step 322, which may be performed in parallel with steps 302 to 306. In step 322, the second layer 116 may be formed by epitaxial growth. The second layer formed by epitaxial growth may be silicon. The epitaxially grown silicon may form the active silicon layer 116. Epitaxial growth may occur by molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), metal-organic CVD (MOCVD), or a similar process. In some embodiments, steps 320 and 322 may occur in a single step.

[0050] See Figure 3 and Figure 12 The method 300 proceeds to step 308, wherein the substrate 110 ( Figures 5 to 7 ) (also referred to as a high resistance wafer) is bonded to the substrate 410 ( Figures 8 and 9 ) (also referred to as a device wafer). Bonding can occur by contacting the face of the insulating (BOX) layer of the high resistivity wafer with the face of the epitaxial layer of the device wafer. In some embodiments, the high resistivity wafer can be bonded to the device wafer using direct bonding. In some embodiments, the high resistivity wafer can be bonded to the device wafer using thermal bonding. In some embodiments, the high resistivity wafer can be bonded to the device wafer at room temperature. In some embodiments, the high resistivity wafer is bonded to the device wafer by annealing at a temperature at or above room temperature and at or below 450°C. This value is given as an example, and other values ​​and ranges of values ​​are within the scope of the present disclosure. In some embodiments, the high resistivity wafer can be bonded to the device wafer at a temperature above room temperature. In some embodiments, the high resistivity wafer is bonded to the device wafer by annealing at a temperature at or below 300°C, 400°C, 700°C, or 800°C. These values ​​are given as examples, and other values ​​and ranges of values ​​are within the scope of the present disclosure.

[0051] These substrates may optionally be pretreated prior to bonding. Pretreatment may be performed using dry processing techniques such as plasma treatment, thermal treatment, or UV / ozone treatment. Pretreatment may also be performed using wet processing techniques such as standard cleaning 1. In some embodiments, the pretreatment is plasma surface activation, for example, by subjecting the surface to oxygen plasma or nitrogen plasma. Oxygen plasma surface oxidation may render the substrate surface hydrophilic.

[0052] Wafer bonding can occur by plasma-activated bonding, surface-activated bonding, or ultra-high vacuum. Wafer bonding can occur by surface passivation (due to chemical mechanical polishing (CMP), chemical surface treatment, or implantation). Wafer bonding by annealing can be supplemented with one of the additional treatments described above. The supplementary treatment can lower the annealing temperature. After pretreatment or other supplementary treatment, the high-resistance wafer is bonded to the device wafer by annealing at a temperature at or below 300° C., 400° C., 700° C., or 800° C. These values ​​are given as examples, and other values ​​and value ranges are within the scope of the present disclosure.

[0053] See Figure 3 and Figure 13Method 300 then proceeds to step 310, where the surface of the bonded wafer can be removed down to the epitaxial SiGe layer. Removal can include thinning, for example, by polishing. Polishing can be performed by chemical mechanical polishing (CMP). Removal can be performed by wet etching, dry etching, or a combination of processes. These methods are given as examples, and other methods known in the art are within the scope of this disclosure.

[0054] See Figure 3 and Figure 14 , method 300 proceeds to step 312, in which the epitaxial SiGe layer is removed. Removal can be by polishing, wet etching, dry etching, or a combination of processes. Polishing can be chemical mechanical polishing (CMP). The dry etching process can be plasma etching. The dry etching process can be reactive ion etching. The dry etching process can be sputter etching. The dry etching can be vapor phase etching. The dry etching can be ion milling. This list is representative, and those skilled in the art are aware of the many methods currently used and that may be used in the future in dry etching processes.

[0055] Removal can be performed by a wet etching process. Wet etching can be acid etching or solution etching. Wet etching can occur at room temperature, low temperature, or high temperature. Wet etching can be isotropic or anisotropic. Those skilled in the art are aware of the many chemistries currently used and that may be used in the future in wet etching processes.

[0056] Figures 15 and 16 An alternative embodiment of the present disclosure is shown. Figures 15 and 16 A second embodiment of a method for producing a silicon-on-insulator substrate is proposed. The second embodiment differs from the first embodiment in that the oxide layer 114 is formed before the charge trapping layer 112 . Figure 15 The details of the method correspond mainly to those for Figure 3 The details of the method outlined in and are omitted here except for their relevance to Figure 3 Except for deviations from the method details in .

[0057] Figure 16 Illustration of a method according to some embodiments Figure 15Cross-sectional views of an example semiconductor device during various stages of fabrication as fabricated by a method of method 1600. Method 1600 may proceed to step 1602, where a substrate is secured. Next, at step 1604, an oxide layer 114 may be deposited. Next, at step 1606, a charge trapping layer 112 may be formed. In parallel with steps 1602 through 1606, the following steps 1616 through 1622 may be performed. First, at step 1616, a wafer may be secured. Next, at step 1618, an implanted surface may be formed. Next, at step 1620, a surface may be formed, for example, by epitaxy. Next, at step 1622, a second surface may optionally be formed, for example, by epitaxy. At step 1608, the wafer from step 1606 may be bonded to the wafer at step 1622. Next, at step 1610, the surfaces of the bonded wafers may be removed to reveal the first formed (e.g., epitaxy) layer 116 / 416. In optional step 1612 , the surface may be further removed to expose the second formed (eg, epitaxial) layer 116 .

[0058] Figure 17 Illustration of a method according to some embodiments Figure 15 FIG1 is a cross-sectional view of step 1606 of the method for fabricating a silicon substrate. In this embodiment, after depositing the oxide layer 114, the charge trapping layer 112 is formed. The charge trapping layer 112 can be formed by ion implantation. This method is provided as an example, and other methods of forming the charge trapping layer 112 are within the scope of the present disclosure. The charge trapping layer 112 can be formed between the insulating layer 114 or the buried oxide layer 114 and the silicon substrate.

[0059] Figure 18 One embodiment of a silicon-on-insulator substrate formed using one of the methods 300 or 1600 is illustrated. Figure 18 The entire structure can be used as a silicon-on-insulator (SOI) substrate to form many types of devices.

[0060] The structure may include an active layer 116. Active layer 116 may be the layer beneath the gate oxide of the MOSFET. Other devices may be formed on active layer 116. Active layer 116 may contain silicon. The active layer may be doped. The active layer refers to a layer of semiconductor material in or on which components are subsequently fabricated.

[0061] Active silicon layer 116 may be directly on insulating layer 114. Insulating layer 114 may extend along the entire length and width of active silicon layer 116. The span of insulating layer 114 allows for enhanced isolation of devices built on the active layer from each other. Insulating layer 114 may be an oxide layer 114, which may be referred to as a buried oxide layer 114 or BOX.

[0062] BOX 114 may be directly on charge trapping layer 112. The insulating charge trapping layer 114 may extend along the entire length and width of the active silicon layer 116 and insulating layer 114. The length of the charge trapping layer 112 allows for enhanced isolation between devices built on the active layer. The length of the charge trapping layer 112 also prevents charge accumulation. The charge trapping layer 112 may be formed on substrate 110. The charge trapping layer 112 may be an amorphous, disordered, or implanted silicon layer.

[0063] The charge trapping layer 112 may be on a substrate. The substrate may be a high-resistivity silicon wafer. In some embodiments, the high-resistivity silicon wafer is single crystal silicon. The high-resistivity silicon wafer may have a bulk resistivity greater than 40 ohm-cm. The high-resistivity silicon wafer may have a bulk resistivity greater than 1 kOhm-cm. The high-resistivity silicon wafer may have a bulk resistivity greater than 10 kOhm-cm. The high-resistivity silicon wafer may have a bulk resistivity between 1 kOhm-cm and 10 kOhm-cm. These values ​​are given as examples, and other values ​​and value ranges are within the scope of the present disclosure.

[0064] The aforementioned methods, structures, devices, and embodiments exhibit numerous advantages. Specific area etching and implantation by deep trench etching are not required. Instead, the structure may include a charge trapping layer 112 between the buried oxide layer 114 and the silicon substrate, extending through the substrate and spanning the length and width of the substrate. Additionally, the charge trapping layer 112 may be created by implantation or bombardment. Forming the charge trapping layer 112 between the buried oxide layer 114 and the high-resistance silicon substrate through the structure (e.g., by implantation or bombardment through the structure) may achieve better isolation and lower leakage performance. When compared to a similar device formed on a substrate having implantation in specific areas rather than throughout, the device formed on this substrate may exhibit better isolation and lower leakage performance. Additionally, the aforementioned process does not depend on a deep trench etching process, such as a process used to form a structure having implantation in specific areas. Avoiding the need for a deep trench etching process may result in lower manufacturing costs.

[0065] In some embodiments, the disclosed structure is a semiconductor-on-insulator substrate including an active silicon layer 116, which may be on an oxide layer 114. The oxide layer 114 may be on a charge trapping layer 112. The charge trapping layer 112 may be on a silicon substrate 110. In some embodiments, the charge trapping layer 112 may include one or more of amorphous silicon, a disordered silicon layer, and implanted silicon. The silicon substrate 110 may have a resistivity between 1,000 ohm-cm and 10,000 ohm-cm.

[0066] In some embodiments, the charge trapping layer 112 implant material is one of Xe, Ar, Ge, or Si. These materials are given as examples, and other materials for forming the charge trapping layer are within the scope of this disclosure. The thickness of the charge trapping or semiconductor insulating layer 112 can be between 5 nm and 300 nm. This thickness is sufficient to prevent charge accumulation in the structure and can be manufactured using the processes disclosed herein. These values ​​are given as examples, and other value ranges are within the scope of this disclosure.

[0067] In some embodiments, the disclosed semiconductor-on-insulator substrate may further include a source, a gate, and a drain on the active silicon layer 116. The source, the gate, and the drain may be in direct contact with the active silicon layer 116.

[0068] In some embodiments, a method of forming a semiconductor-on-insulator substrate may include multiple steps. These steps may include forming a charge trapping layer 112 on a first silicon substrate 110. These steps may include forming an oxide layer 114 on the charge trapping layer 112. These steps may include forming an implanted interface on a second substrate 410. These steps may include depositing a first epitaxial layer 116 on the implanted interface of the second substrate 410. These steps may include bonding the first epitaxial layer 116 to the oxide layer 114. These steps may include removing the second substrate 410. These steps may include removing additional layers to reach the first epitaxial layer 116.

[0069] The method may further include forming a second epitaxial layer 416 between the first epitaxial layer 116 and the implanted interface of the second substrate 410. The second epitaxial layer 416 may be silicon germanium. Silicon germanium is given as an example, and other epitaxial layers are within the scope of the present disclosure. The first epitaxial layer 116 may be active silicon.

[0070] The charge trapping layer 112 may be formed by ion implantation. Ion implantation may be performed by bombarding with one or more of Xe, Ge, Ar, and Si. These materials are given as examples, and other materials for forming the charge trapping layer 112 are within the scope of the present disclosure.

[0071] The first epitaxial layer 116 may be bonded to the oxide layer 114 via thermal annealing. The first epitaxial layer 116 may be treated with plasma before thermal annealing. The oxide layer 114 may be treated with plasma before thermal annealing.

[0072] In some embodiments, the charge trapping layer 112 is formed before the oxide layer 114 is formed. In other embodiments, the charge trapping layer 112 is formed after the oxide layer 114 is formed.

[0073] In some embodiments, a method of forming a semiconductor-on-insulator substrate may include the steps outlined below. The method may include forming a charge trapping layer 112 on a silicon substrate 110. The method may include forming an oxide layer 114 on the charge trapping layer 112. The method may include securing a doped second substrate 410. The method may include depositing a first epitaxial layer 116 on the doped substrate 410. The method may include bonding the first epitaxial layer 116 to the oxide layer 114. The method may include removing at least a portion of the doped substrate 410. The method may include removing additional layers to reach the first epitaxial layer 116.

[0074] In some embodiments, the doped substrate 410 may be P+ silicon. In some embodiments, the doped substrate 410 may be P- silicon.

[0075] The method may include removing at least a portion of the doped substrate 410 using chemical mechanical polishing (CMP).

[0076] In one aspect of the present disclosure, a semiconductor device is disclosed, which may include a semiconductor substrate. The device may also include a semiconductor insulating layer completely covering the semiconductor substrate. The device may additionally include an oxide layer completely covering the semiconductor insulating layer. In some embodiments, the device may include one or more device features formed on the oxide layer.

[0077] In various embodiments, the semiconductor insulating layer is selected from the group consisting of amorphous silicon, a disordered silicon layer, and implanted silicon. In various embodiments, the semiconductor substrate has a resistivity between 1,000 ohm-cm and 10,000 ohm-cm. In various embodiments, the semiconductor insulating layer is formed by an implanted material selected from the group consisting of Xe, Ar, Ge, and Si. In various embodiments, the thickness of the semiconductor insulating layer is between approximately 5 nm and approximately 300 nm. In various embodiments, the semiconductor device further includes a source, a gate, and a drain above the active silicon layer. In various embodiments, the source, gate, and drain are in direct contact with the active silicon layer.

[0078] In another aspect of the present disclosure, a disclosed structure may be a semiconductor device including a semiconductor substrate. The structure may also include a semiconductor insulating layer extending along the entire active area. The structure may further include a buried oxide layer completely covering the semiconductor insulating layer. In some embodiments, the structure may include one or more device features formed on the oxide layer in the active area.

[0079] In various embodiments, the semiconductor insulating layer is selected from the group consisting of amorphous silicon, a disordered silicon layer, and implanted silicon. In various embodiments, the semiconductor insulating layer has a thickness between approximately 5 nm and approximately 300 nm. In various embodiments, the buried oxide layer is in direct contact with the active region.

[0080] In another aspect of the present disclosure, a method of forming a structure may be disclosed. The structure may be a substrate. The structure may be a semiconductor device. The method may include securing a substrate. The method may include forming a buried oxide layer. The method may include forming a semiconductor insulating layer between the buried oxide layer and the substrate. In some embodiments, the method may include forming an active layer. In some embodiments, the semiconductor insulating layer extends entirely across an active device region without interruption.

[0081] In some embodiments, the method further comprises: bonding a second substrate to the first substrate in a wafer bonding process; depositing an epitaxial layer on the second substrate and bonding the epitaxial layer to the buried oxide layer; removing the second substrate; and removing additional layers to reach the epitaxial layer. In some embodiments, the epitaxial layer is silicon germanium. In some embodiments, the semiconductor insulating layer is formed by ion implantation. In some embodiments, the semiconductor insulating layer is formed by bombardment with one or more of Xe, Ge, Ar, and Si. In some embodiments, the ion implantation extends entirely over the first substrate. In some embodiments, the ion implantation extends entirely over the buried oxide layer. In some embodiments, the semiconductor insulating layer is formed before forming the buried oxide layer. In some embodiments, the semiconductor insulating layer is formed after forming the buried oxide layer.

[0082] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processing procedures and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a semiconductor substrate; a semiconductor insulating layer completely covering the semiconductor substrate; an oxide layer completely covering the semiconductor insulating layer; and A plurality of device features are formed above the oxide layer, wherein the semiconductor insulating layer is an implanted silicon layer, and the semiconductor insulating layer extends entirely across the plurality of device features without interruption.

2. The semiconductor device according to claim 1, wherein The plurality of device features include an epitaxial layer bonded to the oxide layer by thermal annealing.

3. The semiconductor device according to claim 1, wherein The semiconductor substrate has a resistivity between 1,000 ohm-cm and 10,000 ohm-cm.

4. The semiconductor device according to claim 1, wherein The semiconductor insulating layer is formed by an implanted substance selected from the group consisting of Xe, Ar, Ge and Si.

5. The semiconductor device according to claim 1, wherein A thickness of the semiconductor insulating layer is between 5 nm and 300 nm.

6. The semiconductor device according to claim 1, wherein The invention further comprises an active silicon layer, a source, a gate and a drain above the oxide layer.

7. The semiconductor device according to claim 6, wherein The source electrode, the gate electrode and the drain electrode are in direct contact with the active silicon layer.

8. A semiconductor device, characterized in that: Include: a semiconductor substrate; a semiconductor insulating layer extending along the entirety of an active region; a buried oxide layer completely covering the semiconductor insulating layer; and A plurality of device features are formed above the buried oxide layer in the active area, wherein the semiconductor insulating layer is an implanted silicon layer, and the semiconductor insulating layer extends entirely across the plurality of device features without interruption.

9. The semiconductor device according to claim 8, wherein The plurality of device features include an epitaxial layer bonded to the oxide layer by thermal annealing.

10. The semiconductor device according to claim 8, wherein A thickness of the semiconductor insulating layer is between 5 nm and 300 nm.

11. The semiconductor device according to claim 8, wherein The buried oxide layer is in direct contact with the active area.

12. A method of forming a semiconductor device, characterized in that: The following steps are involved: providing a first substrate; forming a buried oxide layer; forming an active layer on a second substrate; forming a plurality of device features on the active layer; forming a semiconductor insulating layer between the buried oxide layer and the first substrate, wherein the semiconductor insulating layer completely covers the first substrate, wherein the semiconductor insulating layer is formed by ion implantation; and A second substrate is bonded to the first substrate in a wafer bonding process, wherein the semiconductor insulating layer extends entirely across the plurality of device features without interruption.

13. The method according to claim 12, wherein: Further comprising the following steps: Depositing an epitaxial layer on the second substrate and bonding the epitaxial layer to the buried oxide layer; removing the second substrate; and Additional layers are removed to reach the epitaxial layer.

14. The method according to claim 13, wherein The epitaxial layer is silicon germanium.

15. The method according to claim 12, wherein The semiconductor insulating layer is an implanted silicon layer.

16. The method according to claim 15, wherein The semiconductor insulating layer is formed by bombarding with one or more of Xe, Ge, Ar and Si.

17. The method according to claim 15, wherein The ion implantation extends completely on the first substrate.

18. The method according to claim 15, wherein The ion implantation extends completely on the buried oxide layer.

19. The method according to claim 12, wherein Before forming the buried oxide layer, the semiconductor insulating layer is formed.

20. The method according to claim 12, wherein After the buried oxide layer is formed, the semiconductor insulating layer is formed.

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