Memory device and method of manufacturing the same

Abstract

Various embodiments of the present disclosure are directed to a memory device and a method for manufacturing the same, the memory device comprising a protective sidewall spacer layer that laterally surrounds a memory cell. An upper interlayer dielectric (ILD) layer overlies a substrate. The memory cell is disposed within the upper ILD layer. The memory cell comprises a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top electrode and the bottom electrode. The sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure comprises a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer. The first sidewall spacer layer and the second sidewall spacer layer comprise a first material, and the protective sidewall spacer layer comprises a second material different from the first material. A conductive trace overlies the first memory cell. The conductive trace contacts the top electrode and the protective sidewall spacer layer.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method for manufacturing the same Background Art

[0002] Many modern electronic devices contain electronic memory. Electronic memory can be volatile memory or non-volatile memory. Non-volatile memory is able to retain its stored data in the absence of electricity, while volatile memory loses its stored data when power is removed. Due to its advantages over current electronic memory, magnetoresistive random-access memory (MRAM) is a promising candidate for the next generation of non-volatile electronic memory. Compared to current non-volatile memories such as flash memory, MRAM is generally faster and more durable. Compared to current volatile memories such as dynamic random-access memory (DRAM) and static random-access memory (SRAM), MRAM generally has similar performance and density, but lower power consumption. Summary of the invention

[0003] The present disclosure provides a memory device, which includes: an upper interlayer dielectric (ILD) layer overlying a substrate; a first memory cell arranged in the upper interlayer dielectric layer, wherein the first memory cell includes a top electrode, a bottom electrode and a magnetic tunnel junction (MTJ) structure arranged between the top electrode and the bottom electrode; a sidewall spacer structure surrounding the first memory cell in a laterally direction, wherein the sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer and a protective sidewall spacer layer arranged between the first sidewall spacer layer and the second sidewall spacer layer, wherein the first sidewall spacer layer and the second sidewall spacer layer include a first material, and the protective sidewall spacer layer includes a second material different from the first material; and a conductive trace overlying the first memory cell, wherein the conductive trace contacts the top electrode and the protective sidewall spacer layer.

[0004] The present disclosure provides a memory device, which includes: a first magnetoresistive random access memory (MRAM) cell, overlying a substrate and arranged in an embedded storage area, wherein the embedded storage area is adjacent to a logic area; a second magnetoresistive random access memory cell, overlying the substrate, wherein the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell respectively include a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure arranged between the top electrode and the bottom electrode; an upper interlayer dielectric (ILD) layer, overlying the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, wherein the upper interlayer dielectric layer includes a sidewall defining a trench between the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, wherein the The upper interlayer dielectric layer comprises a first material; a first dielectric protection layer, which is arranged in the groove and comprises a second material different from the first material, wherein the first dielectric protection layer is offset by a non-zero distance in the lateral direction relative to the logic area; a sidewall spacer structure, which surrounds the first magnetoresistive random access memory unit and the second magnetoresistive random access memory unit in the lateral direction, respectively, wherein the sidewall spacer structure comprises a protective sidewall spacer layer arranged between the first sidewall spacer layer and the second sidewall spacer layer; and a conductive trace, which overlies the first magnetoresistive random access memory unit and the second magnetoresistive random access memory unit, wherein the first conductive trace directly contacts the top surface of the first magnetoresistive random access memory unit, and the second conductive trace directly contacts the top surface of the second magnetoresistive random access memory unit.

[0005] The present disclosure provides a method for manufacturing a memory device, comprising: forming a first magnetoresistive random access memory (MRAM) cell on a substrate; forming a second magnetoresistive random access memory cell on the substrate; forming a sidewall spacer structure around the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, respectively, wherein the sidewall spacer structure comprises a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer; forming an upper interlayer dielectric (ILD) layer on the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, wherein the upper interlayer dielectric The invention relates to a method for manufacturing a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell, wherein the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell are each provided with a dielectric layer and a dielectric protection layer. The method comprises: forming a dielectric layer and a dielectric protection layer on the upper interlayer dielectric layer, wherein the dielectric protection layer fills the trench; performing a first planarization process on the upper interlayer dielectric layer and the dielectric protection layer, wherein the dielectric protection layer remains in the trench after the first planarization process; and forming a conductive trace on the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, wherein the conductive trace directly contacts the top electrode of the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features are not necessarily drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A to Figure 1C Various diagrams showing memory devices having magnetoresistive random access memory (MRAM) cells each including a protective sidewall spacer layer laterally surrounding a magnetic tunnel junction (MTJ) and contacting a top electrode overlying a conductive wire.

[0008] Figure 2A Show according to Figure 1A to Figure 1C Cross-sectional views of memory devices illustrating some alternative embodiments of memory devices are shown.

[0009] Figure 2B Show Figure 2A A top view of some embodiments of a memory device is shown.

[0010] FIG. 3A to FIG. 3B Show Figure 1A to Figure 1CCross-sectional views of some alternative embodiments of memory devices are shown.

[0011] Figure 4 Show according to Figure 1A to Figure 1C Cross-sectional views of memory devices illustrating some alternative embodiments of memory devices are shown.

[0012] Figure 5 Cross-sectional views of some embodiments of a memory device having an embedded memory region laterally adjacent to a logic region, the embedded memory region having MRAM cells are shown.

[0013] Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 Various diagrams showing some embodiments of methods of forming a memory device having an MRAM cell, each including a protective sidewall spacer layer laterally surrounding an MTJ and contacting a top electrode overlying a conductive trace.

[0014] Fig.17 Flowcharts showing some embodiments of methods of forming a memory device having an MRAM cell, each including a protective sidewall spacer layer laterally surrounding an MTJ and contacting a top electrode overlying a conductive trace.

[0015] [Explanation of Symbols]

[0016] 100, 200, 300a, 300b, 400, 500: memory devices

[0017] 101: Embedded Storage Area

[0018] 102: Substrate

[0019] 103: Logical area

[0020] 104: Semiconductor devices

[0021] 106: Source / drain region

[0022] 108: Gate dielectric layer

[0023] 110: Gate structure

[0024] 112: Side wall partition structure

[0025] 114: Lower interlayer dielectric (ILD) layer

[0026] 116: Conductive contact

[0027] 118: Lower internal connection wiring

[0028] 120: First dielectric layer

[0029] 122: Second dielectric layer

[0030] 124: Lower metal layer

[0031] 125: Bottom electrode through hole

[0032] 126: Diffusion barrier layer

[0033] 128: First bottom electrode layer

[0034] 130: Second bottom electrode layer

[0035] 132: Bottom electrode

[0036] 134: First side wall spacer layer

[0037] 136: Protective sidewall spacer layer

[0038] 138: Second side wall spacer layer

[0039] 140: Side wall partition structure

[0040] 142: Magnetic Tunnel Junction (MTJ) Structure

[0041] 144: Top electrode

[0042] 146: Outer wall partition layer

[0043] 148: Magnetoresistive random access memory (MRAM) cell / first MRAM cell

[0044] 150: Magnetoresistive random access memory (MRAM) cell / second MRAM cell

[0045] 152: Upper interlayer dielectric (ILD) layer

[0046] 152us: upper surface

[0047] 153: Via hole

[0048] 154: Upper conductive trace

[0049] 156, 1002: First dielectric protection layer

[0050] 158: Groove

[0051] 202: Seed layer

[0052] 204: Pinning layer

[0053] 206: Tunnel barrier layer

[0054] 208: Free Tier

[0055] 210: Top cover

[0056] 212: Inner wall partition layer

[0057] 220: Straight horizontal line

[0058] 302: Second dielectric protection layer

[0059] 504: Conductor

[0060] 506: Conductive pad

[0061] 600, 700, 800, 900, 1000, 1100a, 1100b, 1200, 1300, 1400, 1500, 1600: Sectional view

[0062] 1102: Smooth horizontal line

[0063] 1202, 1204: Second dielectric protection structure

[0064] 1206: Mask layer

[0065] 1302: Opening

[0066] 1502: Conductive structure

[0067] 1700: Methods

[0068] 1702, 1704, 1706, 1708, 1710, 1712, 1714, 1716: Action

[0069] A-A', B-B', C-C': Line

[0070] d1: first distance

[0071] d2: second distance

[0072] d5, dlat, dv: distance

[0073] h1: height

[0074] t1: thickness

[0075] α: Angle DETAILED DESCRIPTION

[0076] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0077] Furthermore, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0078] In addition, for ease of description, "first", "second", "third", etc. may be used herein to distinguish different elements shown in one figure or a series of figures. "First", "second", "third", etc. are not intended to describe corresponding elements. Thus, the "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to the "first dielectric layer" described in conjunction with another figure.

[0079] A magnetoresistive random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) within a back-end-of-the-line (BEOL) metal stack arranged in a vertical direction between a bottom electrode and a top electrode. The MTJ includes a pinned layer and a free layer separated in a vertical direction by a tunnel barrier layer. The magnetic orientation of the pinned layer is static (i.e., fixed), while the magnetic orientation of the free layer can be switched between a parallel configuration and an anti-parallel configuration relative to the magnetic orientation of the pinned layer. The parallel configuration provides a low resistance state, which digitally stores data as a first data state (e.g., a logical "0"). The anti-parallel configuration provides a high resistance state, which digitally stores data as a second data state (e.g., a logical "1").

[0080] A process for forming an MRAM device may include forming an MRAM cell on a lower interconnect wire in an embedded storage region of an integrated chip. The MRAM cell includes a top electrode, a bottom electrode, and an MTJ disposed between the top electrode and the bottom electrode. A dielectric layer stack is formed on the MRAM cell and on a logic region laterally adjacent to the embedded storage region. A first etching process is performed according to a first mask layer to remove at least a portion of the dielectric layer stack located in the logic region. An upper interlayer dielectric (ILD) layer is formed on the embedded storage region and the logic region. A first upper surface of the upper ILD layer in the embedded storage region is offset in a vertical direction by a non-zero distance relative to a second upper surface of the upper ILD layer in the logic region. A second etching process is performed according to a second mask layer to significantly reduce or eliminate the vertical offset between the first upper surface and the second upper surface of the upper ILD layer. Subsequently, a third etching process is performed according to a third mask layer to form a top electrode opening in the upper ILD layer overlying the top electrode. A fourth etching process is performed based on the fourth mask layer to form a conductive trace opening on the interconnect trace disposed in the logic region. In addition, a fifth etching process is performed based on the third mask layer to enlarge both the top electrode opening and the conductive trace opening. Finally, an upper conductive trace and a top electrode through hole are formed on the top electrode.

[0081] The challenges of the aforementioned method may occur during multiple etching processes. For example, in order to expose the entire upper surface of the top electrode to facilitate a strong electrical connection between the top electrode and the top electrode through hole, a high-power etching process with a long etching time may be used during the fifth etching process. However, the high-power etching process and / or the long etching time may over-etch and expose the tunnel barrier layer in the MTJ. This in turn may cause an electrical short circuit between the pinned layer and the free layer and / or damage to the tunnel barrier layer, thereby damaging the MTJ (e.g., making the MTJ inoperable). In another example, the etching power and / or etching time of the fifth etching process may be reduced to reduce damage to the MTJ. However, this may result in poor electrical connection and / or open circuit between the top electrode and the top electrode through hole. In addition, multiple etching processes using multiple mask layers will increase the time and cost associated with forming an MRAM device.

[0082] In some embodiments, the present disclosure relates to a simplified method for forming an MRAM device. For example, the method may include forming an MRAM cell on an interconnection line, the interconnection line being laterally disposed in an embedded storage area. A protective sidewall spacer layer may be formed laterally around the MRAM cell. An upper interlayer dielectric (ILD) structure is formed on the MRAM cell and an adjacent logic area. A planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed on the upper ILD structure to reduce the height variation of the upper ILD structure between the embedded storage area and the logic area. A first mask layer is formed over the embedded storage area and the logic area. A first etching process is performed according to the first mask layer to expose the upper surface of the top electrode of the MRAM cell and the upper surface of the lower interconnection line disposed in the logic area. During the first etching process, the protective sidewall spacer layer is etched at a slower rate (e.g., at least five times slower) than the upper ILD structure. A first conductive trace is formed over the top electrode, and a second conductive trace and a via are formed over the lower interconnect trace in the logic region, so that the first conductive trace contacts the top electrode. Since the etching of the protective sidewall spacer layer is slower than that of the upper ILD structure, the top electrode via can be omitted, and a strong electrical connection is formed between the first conductive trace and the top electrode without over-etching and damaging the MTJ. In addition, the protective sidewall spacer layer helps to expose the upper surface of the top electrode and the upper surface of the lower interconnect trace using a single etch and a single mask layer. This in turn helps to form an MRAM device using fewer etching processes and fewer mask layers, thereby reducing the cost and time associated with forming an MRAM device.

[0083] Figure 1A Cross-sectional views of some embodiments of a memory device 100 are shown having magnetoresistive random access memory (MRAM) cells 148 , 150 , each including a protective sidewall spacer layer 136 laterally surrounding a magnetic tunnel junction (MTJ) structure 142 and a top electrode 144 contacting an upper conductive trace 154 .

[0084] The memory device 100 includes an embedded memory region 101 laterally adjacent to a logic region 103. A lower interlayer dielectric (ILD) layer 114 overlies a substrate 102. One or more semiconductor devices 104 are disposed in and / or on the substrate 102. The one or more semiconductor devices 104 may be configured as transistors and may include source / drain regions 106, sidewall spacer structures 112, gate structures 110, and gate dielectric layers 108. A conductive contact 116 extends from a lower interconnect 118 to the one or more semiconductor devices 104. A first dielectric layer 120 overlies the lower ILD layer 114, and a second dielectric layer 122 overlies the first dielectric layer 120.

[0085] The MRAM cells 148, 150 are laterally spaced apart within the embedded memory region 101 and include a top electrode 144, a bottom electrode 132, and an MTJ structure 142 disposed between the top electrode 144 and the bottom electrode 132, respectively. The bottom electrode via 125 extends through the first dielectric layer 120 and the second dielectric layer 122 to electrically couple the bottom electrode 132 to the lower interconnect 118. The bottom electrode via 125 includes a lower metal layer 124 and a diffusion barrier layer 126. The bottom electrode 132 includes a first bottom electrode layer 128 below the second bottom electrode layer 130. In some embodiments, the MTJ structure 142 includes a free layer, a pinned layer, and a tunnel barrier layer disposed between the free layer and the pinned layer. The MRAM cells 148, 150 are configured to store data states based on the resistance values ​​of the MRAM cells 148, 150, respectively. For example, if the first MRAM cell 148 has a low resistance state, the first MRAM cell 148 will store a first data state (e.g., logic "0"), or if the first MRAM cell 148 has a high resistance state, the first MRAM cell 148 will store a second data state (e.g., logic "1"). During operation, the MTJ structure 142 can change between the low resistance state and the high resistance state through the tunnel magnetoresistance (TMR) effect. The upper ILD layer 152 overlies the MRAM cells 148, 150.

[0086] The sidewall spacer structure 140 is disposed between the MTJ structure 142 and the upper ILD layer 152. The sidewall spacer structure 140 includes a first sidewall spacer layer 134, a second sidewall spacer layer 138, and a protective sidewall spacer layer 136 disposed between the first sidewall spacer layer 134 and the second sidewall spacer layer 138. In some embodiments, the first sidewall spacer layer 134 and the second sidewall spacer layer 138 may, for example, each be or include a first material, such as silicon nitride, silicon carbide, etc. In further embodiments, the protective sidewall spacer layer 136 may, for example, be or include a second material, such as a metal oxide (e.g., aluminum oxide), a metal nitride (e.g., aluminum nitride), etc. In some embodiments, the first material is different from the second material. The protective sidewall spacer layer 136 contacts the sidewall of the top electrode 144 and extends continuously along the sidewall of the top electrode 144 and along the sidewall of the MTJ structure 142 to the upper surface of the bottom electrode 132. The outer sidewall spacer layer 146 overlies the MRAM cells 148 and 150 and extends laterally to the lower interconnect trace 118 disposed in the logic region 103 .

[0087] In the logic region 103, the upper conductive trace 154 and the via 153 overlie the lower interconnect trace 118. The via 153 is disposed between the upper conductive trace 154 and the lower interconnect trace 118. In some embodiments, in the embedded memory region 101, the upper conductive trace 154 directly contacts the top electrode 144 of the first MRAM cell 148 and the top electrode 144 of the second MRAM cell 150, respectively. In some embodiments, the upper conductive trace 154 directly contacts the protective sidewall spacer layer 136. The upper ILD layer 152 includes sidewalls defining a trench 158 between the first MRAM cell 148 and the second MRAM cell 150. The trench 158 may be filled with a first dielectric cap layer 156.

[0088] In some embodiments, during the method for forming the memory device 100, the protective sidewall spacer layer 136 is used as an etch stop layer in the etching process for forming the opening, in which the upper conductive trace 154 and the via 153 are located. This is because, during the etching process, the protective sidewall spacer layer 136 has a slower etching rate (e.g., at least 5 times slower) than the surrounding dielectric material (e.g., the upper ILD layer 152). The etching process is performed based on a single mask layer, and the opening is formed simultaneously in the embedded memory area 101 and the logic area 103, thereby reducing the time and cost associated with forming the memory device 100.

[0089] Figure 1B Shown along Figure 1A A top view of an alternative embodiment of the memory device 100 is shown along line AA′ of the cross-sectional view shown.

[0090] The memory device 100 includes an embedded memory region 101 and a logic region 103 that is laterally adjacent to the embedded memory region 101. The embedded memory region 101 includes an array of MRAM cells arranged in rows and columns. It should be understood that the memory array may include any number of MRAM cells, and thus Figure 1B Merely by way of example. In some embodiments, the groove 158 is centered between four adjacent upper conductive traces 154. In further embodiments, a first distance d1 is defined between two adjacent upper conductive traces 154, and a second distance d2 is defined between two adjacent grooves 158, wherein the two adjacent grooves 158 include the first dielectric cap layer 156. In some embodiments, the first distance d1 is the minimum distance between two adjacent upper conductive traces 154 and / or the second distance d2 is the minimum distance between two adjacent grooves 158. In some embodiments, the second distance d2 is, for example, approximately equal to the first distance d1 (e.g., approximately 1*d1) or in the range of approximately 0.5*d1 to 2*d1.

[0091] Figure 1C Shown along Figure 1B The cross-sectional view of an alternative embodiment of the memory device 100 is shown along the line BB' of the top view, wherein the first dielectric protection layer ( Figure 1B 156) is laterally offset relative to the first MRAM cell 148 and the second MRAM cell 150. In addition, the first dielectric protection layer ( Figure 1B 156 ) is laterally offset relative to the logic region 103 .

[0092] Figure 2A Show according to Figure 1A to Figure 1C A cross-sectional view of a memory device 200 is shown as an alternative embodiment of the memory device 100 .

[0093] The memory device 200 includes an embedded memory region 101 laterally adjacent to a logic region 103. A lower ILD layer 114 overlies a substrate 102. In some embodiments, the substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. In further embodiments, the lower ILD layer 114 may include one or more dielectric layers, which may, for example, include a low-k dielectric material, an oxide (e.g., silicon dioxide), etc. A first dielectric layer 120 overlies the lower ILD layer 114, and a second dielectric layer 122 overlies the first dielectric layer 120. In still further embodiments, the first dielectric layer 120 may be, for example, or include hydrogen and nitrogen doped carbide (HNDC), silicon carbide, etc., and / or may have a thickness of about 250 angstroms or some other suitable thickness. In some embodiments, the second dielectric layer 122 may be configured as an etch stop layer and / or may include silicon-rich oxide, silicon nitride, etc., and / or may have a thickness of about 230 angstroms or some other suitable thickness. The bottom electrode via 125 extends through the first dielectric layer 120 and the second dielectric layer 122. The bottom electrode via 125 includes a lower metal layer 124 and a diffusion barrier layer 126.

[0094] The first MRAM cell 148 and the second MRAM cell 150 are overlying the second dielectric layer 122 and are laterally spaced apart in the embedded memory area 101. The first MRAM cell 148 and the second MRAM cell 150 respectively include a bottom electrode 132, a top electrode 144, and an MTJ structure 142 disposed between the top electrode 144 and the bottom electrode 132. The bottom electrode 132 includes a first bottom electrode layer 128 and a second bottom electrode layer 130 overlying the first bottom electrode layer 128. In some embodiments, the first bottom electrode layer 128 may be, for example, or include tantalum, tantalum nitride, etc., and / or may have a thickness of about 100 angstroms. In further embodiments, the second bottom electrode layer 130 may be, for example, or include titanium, titanium nitride, etc., and / or may have a thickness of about 100 angstroms. In still further embodiments, the top electrode 144 may be, for example, or include titanium, tungsten, etc., and / or may have a thickness of about 450 angstroms.

[0095] In some embodiments, the MTJ structure 142 may be, for example, or include a plurality of storage layers, and / or may have a thickness of about 280 angstroms or some other suitable thickness. For example, the MTJ structure 142 may include a seed layer 202, a pinned layer 204, a tunnel barrier layer 206, a free layer 208, and a cap layer 210. In some embodiments, the seed layer 202 may be, for example, or include tantalum, ruthenium, tantalum nitride, etc., and / or may have a thickness of about 20 angstroms or some other suitable thickness. In some embodiments, the pinned layer 204 may be, for example, or include iron, cobalt, nickel, iron cobalt, a combination of the foregoing, etc. In further embodiments, the tunnel barrier layer 206 may be, for example, or include magnesium oxide (MgO), aluminum oxide (e.g., Al2O3), nickel oxide, etc. In still further embodiments, the free layer 208 may be, for example, or include iron, cobalt, nickel, iron boride, iron platinum, a combination of the foregoing, etc. In some embodiments, cap layer 210 may be, for example, or include, ruthenium, magnesium oxide, or the like, and / or may have a thickness of about 30 angstroms or some other suitable thickness.

[0096] In some embodiments, the pinned layer 204 may have a fixed or "pinned" magnetic orientation pointing in a first direction. The free layer 208 may have a variable or "free" magnetic orientation that can be switched between two or more different magnetic polarities that each represent a different data state (e.g., a different binary state). In some embodiments, if the magnetization directions of the pinned layer 204 and the free layer 208 are oriented in parallel, charge carriers (e.g., electrons) will be more likely to tunnel through the tunnel barrier layer 206, so that the MTJ structure 142 is in a low resistance state. Conversely, in some embodiments, if the magnetization directions of the pinned layer 204 and the free layer 208 are oriented in anti-parallel, charge carriers (e.g., electrons) will be less likely to tunnel through the tunnel barrier layer 206, so that the MTJ structure 142 is in a high resistance state. Under normal operating conditions, the MTJ structure 142 can switch between a low resistance state and a high resistance state based on a bias applied between the top electrode 144 and the bottom electrode 132.

[0097] The sidewall spacer structure 140 may continuously surround the opposite sidewalls of the top electrode 144 and the opposite sidewalls of the MTJ structure 142. In some embodiments, the opposite sidewalls of the MTJ structure 142 and / or the opposite sidewalls of the top electrode 144 are defined according to a cross-sectional view. For example, if the first MRAM cell 148 and / or the second MRAM cell 150 are respectively circular / oval when viewed from above, the opposite sidewalls of the MTJ structure 142 are a single continuous sidewall when viewed from above, and therefore, when depicted in a cross-sectional view, the opposite “sidewalls” of the MTJ structure 142 refer to the nature of such a single continuous sidewall.

[0098] The sidewall spacer structure 140 includes an inner sidewall spacer layer 212, a first sidewall spacer layer 134, a second sidewall spacer layer 138, and a protective sidewall spacer layer 136 disposed between the first sidewall spacer layer 134 and the second sidewall spacer layer 138. In some embodiments, the inner sidewall spacer layer 212, the first sidewall spacer layer 134, and / or the second sidewall spacer layer 138 may be, for example, or include silicon nitride, silicon carbide, silicon oxynitride, etc. In some embodiments, the protective sidewall spacer layer 136 may be, for example, or include aluminum oxide (e.g., Al2O3), aluminum nitride, etc., and / or may have a thickness of about 30 angstroms. The outer sidewall spacer layer 146 overlies the first MRAM cell 148 and the second MRAM cell 150, and extends to the logic region 103 in the lateral direction. In some embodiments, the outer sidewall spacer layer 146 may be, for example, or include silicon nitride, silicon carbide, etc., and / or may be formed by a plasma enhanced atomic layer deposition (PEALD) process. The upper ILD layer 152 overlies the first MRAM cell 148 and the second MRAM cell 150. In some embodiments, the upper ILD layer 152 may be, for example, or include silicon dioxide, a low-κ dielectric material, etc., and / or may have a thickness of about 1,625 angstroms or a thickness in the range of about 1,500 angstroms to 1,750 angstroms.

[0099] The upper conductive trace 154 and the via 153 are disposed within the upper ILD layer 152. The upper conductive trace 154 and / or the via 153 may be, for example, or include copper, aluminum, titanium, tantalum, a combination of the foregoing, etc. In some embodiments, the upper conductive trace 154 may directly contact the upper surface of the top electrode 144, and / or the upper conductive trace 154 may directly contact the upper surface of the protective sidewall spacer layer 136. In further embodiments, due to the material and / or layout of the protective sidewall spacer layer 136, a top electrode through hole (not shown) may be omitted between the top electrode 144 and the upper conductive trace 154, so that the upper conductive trace 154 directly contacts the top electrode 144. This in turn reduces the cost and time associated with forming the memory device 200. In some embodiments, the upper conductive trace 154 and the via 153 within the logic region 103 may be a continuous conductor including the same material.

[0100] A height h1 is defined between the upper surface of the lower ILD layer 114 and the upper surface of the upper ILD layer 152. In some embodiments, the height h1 is about 2,000 angstroms or in a range of about 1,500 angstroms to 2,500 angstroms. In further embodiments, if the height h1 is less than about 1,500 angstroms, the electrical connection between the MRAM cells 148, 150 and adjacent conductive layers or structures may be negatively affected. For example, adjacent conductive layers or structures may be electrically shorted together, rendering the MRAM cells within the embedded memory area 101 inoperable. In still further embodiments, if the height h1 is greater than about 2,500 angstroms, the number of devices that can be disposed on the substrate 102 may be reduced, thereby reducing the performance of the memory device 200.

[0101] The first dielectric protection layer 156 is disposed in the trench 158 of the upper ILD layer 152. The first dielectric protection layer 156 is disposed laterally between the first MRAM cell 148 and the second MRAM cell 150. In some embodiments, the first dielectric protection layer 156 is configured to protect the upper ILD layer 152 during a planarization process (e.g., a CMP process). In some embodiments, the thickness t1 of the first dielectric protection layer 156 is about 8 nanometers or in a range of about 2 nanometers to 15 nanometers. In further embodiments, if the thickness t1 is less than about 2 nanometers, the first dielectric protection layer 156 may not be able to prevent damage to the upper ILD layer 152 during the planarization process. In still further embodiments, if the thickness t1 is greater than about 15 nanometers, the planarization process may not be able to expose the upper surface of the upper ILD layer 152. This in turn may cause problems during the formation of the upper conductive traces 154 and / or the vias 153.

[0102] In some embodiments, an angle α is defined between the sidewall of the upper ILD layer 152 and the straight horizontal line 220. In some embodiments, the straight horizontal line 220 is parallel to the top surface of the substrate 102. In some embodiments, the angle α is about 35 degrees or in a range of about 10 degrees to 85 degrees. In some embodiments, if the angle α is less than about 10 degrees, the duration of the planarization process may be increased to expose the upper surface of the upper ILD layer 152. In such an embodiment, the increased duration of the planarization process may result in a significant reduction in the height h1 (e.g., reducing the height h1 to less than 1,500). In further embodiments, if the angle α is greater than about 85 degrees, the first dielectric cap layer 156 may not be able to prevent damage to the upper ILD layer 152 during the planarization process.

[0103] The upper conductive trace 154 is laterally spaced apart from the upper ILD layer 152 by a distance dlat. In some embodiments, the distance dlat is about 65 nanometers or in a range of about 20 nanometers to 130 nanometers. In some embodiments, the distance dlat is the minimum lateral distance between the upper conductive trace 154 and the upper ILD layer 152. In further embodiments, if the distance dlat is less than 20 nanometers, the first MRAM cell 148 and the second MRAM cell 150 may be too close together, so that the conductive layer between the first MRAM cell 148 and the second MRAM cell 150 may be shorted together, thereby making the MRAM cell in the memory device 200 inoperable. In still further embodiments, if the distance dlat is greater than 130 nanometers, the number of MRAM cells that can be set in the embedded memory area 101 is significantly reduced, thereby reducing the performance of the memory device 200.

[0104] Figure 2B Shown is a view taken along line CC' Figure 2A A top view of some alternative embodiments of the memory device 200 is shown, wherein the sidewalls of the upper ILD layer 152 defining the trench 158 are diamond-shaped when viewed from above. In some embodiments, the sidewalls of the upper ILD layer 152 defining the trench 158 can be, for example, circular, oval, rectangular, or another suitable shape.

[0105] Figure 3A Show according to Figure 1A to Figure 1C A cross-sectional view of a memory device 300 a of some alternative embodiments of the memory device 100 is shown.

[0106] In some embodiments, the first dielectric protection layer 156 is disposed in the trench 158 in the embedded memory region 101, and the second dielectric protection layer 302 is disposed in the logic region 103. In further embodiments, the second dielectric protection layer 302 may extend laterally from the logic region 103 to the embedded memory region 101. In further embodiments, the first dielectric protection layer 156 and the second dielectric protection layer 302 may be, for example, or include, respectively, an extremely low-κ dielectric material, silicon nitride, silicon carbide, another suitable dielectric material, etc. In further embodiments, the thickness of the first dielectric protection layer 156 may be greater than the thickness of the second dielectric protection layer 302. In still further embodiments, the first dielectric protection layer 156 may have a thickness of about 8 nanometers or a thickness in the range of about 2 nanometers to 15 nanometers, and / or the second dielectric protection layer 302 may have a thickness of about 5 angstroms or a thickness in the range of about 0 angstroms to 50 angstroms. In some embodiments, the second dielectric capping layer 302 may be removed from the logic region 103 and / or the thickness of the second dielectric capping layer 302 may be significantly small (e.g., in the range of 0 angstroms to 5 angstroms) due to the duration of the planarization process performed on the upper ILD layer 152. In such embodiments, the second dielectric capping layer 302 is configured to mitigate and / or prevent damage to the upper ILD layer 152 disposed within the logic region 103 during the planarization process.

[0107] Figure 3B Show according to Figure 1A to Figure 1C A cross-sectional view of a memory device 300 b of some alternative embodiments of the memory device 100 is shown.

[0108] In some embodiments, the lower surface of the upper conductive trace 154 overlying the second MRAM cell 150 extends a distance dv laterally below the lower surface of the tunnel barrier layer 206. In some embodiments, the distance dv is non-zero. In further embodiments, the center of the upper conductive trace 154 overlying the second MRAM cell 150 may be offset laterally by a non-zero distance relative to the center of the top electrode 144. This may be due to misalignment of the mask layer used when forming the upper conductive trace 154. In such an embodiment, the material and / or layout of the protective sidewall spacer layer 136 prevents the sidewalls of the MTJ structure 142 from being exposed during the etching process for forming an opening in the upper ILD layer 152, in which the upper conductive trace 154 exists. This in turn prevents shorting of the layers within the MTJ structure 142, thereby increasing the stability, performance and / or durability of the second MRAM cell 150.

[0109] Figure 4 Show according to Figure 1A to Figure 1C Cross-sectional views of memory devices 400 are shown that illustrate some alternative embodiments of memory device 100 .

[0110] In some embodiments, the upper conductive trace 154 extends continuously from the upper surface of the top electrode 144 along the upper surface and sidewalls of the first sidewall spacer layer 134 to the upper surface of the protective sidewall spacer layer 136 .

[0111] Figure 5 A cross-sectional view of some embodiments of a memory device 500 having an embedded memory region 101 laterally adjacent to a logic region 103 is shown.

[0112] like Figure 5 As shown in , the upper conductive trace 154, the via 153 and / or the lower interconnect trace 118 are respectively formed by a conductor 504 surrounded by a conductive pad 506. In some embodiments, the conductor 504 may be, for example, or include aluminum, copper, the alloys thereof, etc. In further embodiments, the conductive pad 506 may be, for example, or include tungsten, titanium, etc.

[0113] Figures 6 to 16 Various cross-sectional views 600 to 1600 of some embodiments of methods of forming a memory device having an MRAM cell, each including a protective sidewall spacer layer laterally surrounding the MTJ and a top electrode contacting an overlying conductive trace. Figures 6 to 16 The various cross-sectional views 600 to 1600 shown in FIG. 1 are described with reference to one method, however, it should be understood that Figures 6 to 16 The structure shown in is not limited to the method described, but can be independent of the method described. Figures 6 to 16 It is described as a series of actions, but it should be understood that these actions are not limited, because in other embodiments, the order of actions can be changed, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0114] like Figure 6As shown in the cross-sectional view 600, a lower interlayer dielectric (ILD) layer 114 is formed on a substrate (not shown). A lower interconnect line 118 is formed in the embedded memory area 101 and the logic area 103. In some embodiments, the lower interconnect line 118 may be or include, for example, copper, aluminum, tungsten, a combination of the foregoing, etc. A first dielectric layer 120 is formed on the lower ILD layer 114, and a second dielectric layer 122 is formed on the first dielectric layer 120. In some embodiments, the first dielectric layer 120 and / or the second dielectric layer 122 may each be formed by performing a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or another suitable deposition process. After the first deposition process, the first dielectric layer 120 and the second dielectric layer 122 are selectively patterned to define bottom electrode via openings extending through the first dielectric layer 120 and the second dielectric layer 122 to the underlying lower interconnect trace 118 in the embedded memory region 101 .

[0115] In a further embodiment, a bottom electrode via 125 contacting the lower interconnect trace 118 is formed within the bottom electrode via opening. In some embodiments, the process for forming the bottom electrode via 125 may include forming a diffusion barrier layer 126 within the bottom electrode via opening. The diffusion barrier layer 126 may be configured to prevent diffusion between adjacent layers. In yet further embodiments, the diffusion barrier layer 126 may be configured as a conductive liner and / or may include a glue layer configured to increase adhesion between adjacent layers. A lower metal layer 124 is formed over the diffusion barrier layer 126 within the bottom electrode via opening. In some embodiments, the diffusion barrier layer 126 and / or the lower metal layer 124 may be deposited, for example, by CVD, PVD, sputtering, electroless plating, or another suitable growth or deposition process. A planarization process (e.g., a chemical mechanical planarization (CMP) process) may then be performed.

[0116] Figure 6, a first bottom electrode layer 128 is formed over the second dielectric layer 122 and the bottom electrode via 125. In addition, a second bottom electrode layer 130 is formed over the first bottom electrode layer 128. In some embodiments, the first bottom electrode layer 128 and / or the second bottom electrode layer 130 may each be formed by, for example, CVD, PVD, sputtering, or another suitable deposition or growth process. After forming the first bottom electrode layer 128 and the second bottom electrode layer 130, a top electrode 144 and an MTJ structure 142 are formed over the second bottom electrode layer 130. In some embodiments, a process for forming the top electrode 144 and the MTJ structure 142 may include: forming a memory stack over the second bottom electrode layer 130, wherein the memory stack includes one or more layers for the MTJ structure 142 and one or more layers for the top electrode 144; and performing one or more etching processes on the memory stack to define the top electrode 144 and the MTJ structure 142. In some embodiments, the one or more etching processes may be performed according to a mask layer (not shown).

[0117] like Figure 7 As shown in the cross-sectional view 700, an inner sidewall spacer layer 212 is formed along the sidewall of the top electrode 144 and along the sidewall of the MTJ structure 142. A first sidewall spacer layer 134 is formed along the sidewall of the inner sidewall spacer layer 212. A protective sidewall spacer layer 136 is formed over the first sidewall spacer layer 134 and the top electrode 144. A second sidewall spacer layer 138 is formed over the protective sidewall spacer layer 136. In some embodiments, the inner sidewall spacer layer 212, the first sidewall spacer layer 134, the protective sidewall spacer layer 136, and / or the second sidewall spacer layer 138 may be deposited, for example, by PVD, CVD, ALD, or another suitable deposition process, respectively. In some embodiments, the protective sidewall spacer layer 136 may be, for example, or include a metal oxide (e.g., aluminum oxide (e.g., AlO x , where x is a positive integer)), etc., and / or may be formed to a thickness of about 30 angstroms or a thickness in the range of about 20 angstroms to 50 angstroms. In further embodiments, the protective sidewall spacer layer 136 may be, for example, or include a metal nitride (e.g., aluminum nitride), etc., and / or may be formed to a thickness in the range of about 40 angstroms to 100 angstroms. However, other thicknesses and / or materials are also suitable for the protective sidewall spacer layer 136.

[0118] like Figure 8 As shown in the cross-sectional view 800, Figure 7The structure shown is subjected to a patterning process to define the bottom electrode 132, the first MRAM cell 148 and the second MRAM cell 150, and the sidewall spacer structure 140. In some embodiments, the patterning process may include, for example, performing wet etching, dry etching, blanket etching, or a combination thereof.

[0119] In some embodiments, the bottom electrode 132 includes a first bottom electrode layer 128 and a second bottom electrode layer 130. The sidewall spacer structure 140 may include an inner sidewall spacer layer 212, a first sidewall spacer layer 134 and a second sidewall spacer layer 138, and a protective sidewall spacer layer 136. The first MRAM cell 148 and the second MRAM cell 150 include a bottom electrode 132, a top electrode 144, and an MTJ structure 142, respectively. In some embodiments, the patterning process defines and exposes an upper surface of the top electrode 144. In addition, the patterning process removes a portion of the protective sidewall spacer layer 136 located above the upper surface of the top electrode 144.

[0120] In some embodiments, the patterning process may include performing a dry etching process until the upper surface of the second dielectric layer 122 is reached. In some embodiments, the dry etching process may include using one or more etchants, such as a chlorine-based etchant. For example, the chlorine-based etchant may be, for example, or include boron chloride (e.g., BCl3), chloride gas (Cl2), a combination of the foregoing, and the like. In some embodiments, the dry etching process may selectively etch the second sidewall spacer layer 138, the first bottom electrode layer 128, and / or the second bottom electrode layer 130 at a first etching rate, and may selectively etch the protective sidewall spacer layer 136 at a second etching rate, wherein the second etching rate is less than the first etching rate. For example, in some embodiments, the first etching rate may be at least 5 times greater than the second etching rate. Therefore, the etching process used to form the bottom electrode 132 and / or the first and second MRAM cells 148 and 150 has a low selectivity for the protective sidewall spacer layer 136 relative to the adjacent layers (e.g., the second sidewall spacer layer 138, the first bottom electrode layer 128, and / or the second bottom electrode layer 130). This helps, in part, to form the first and second MRAM cells 148 and 150 and the bottom electrode 132 while preventing damage to the protective sidewall spacer layer 136 and / or the MTJ structure 142.

[0121] like Fig. 9As shown in the cross-sectional view 900, an outer sidewall spacer layer 146 is formed over the first MRAM cell 148 and the second MRAM cell 150 and the second dielectric layer 122. In some embodiments, the outer sidewall spacer layer 146 can be deposited by, for example, plasma enhanced atomic layer deposition (PEALD).

[0122] like Fig.10 As shown in the cross-sectional view 1000, an upper interlayer dielectric (ILD) layer 152 is formed over the first MRAM cell 148 and the second MRAM cell 150, and a first dielectric cap layer 1002 is formed over the upper ILD layer 152. In some embodiments, the upper ILD layer 152 may be, for example, or include a low-κ dielectric material, or another suitable dielectric material, and / or may be formed to a thickness of about 1625 angstroms or a thickness in a range of about 1,500 angstroms to 1,750 angstroms. In further embodiments, the first dielectric cap layer 1002 may be, for example, or include an extremely low-κ dielectric material, silicon nitride, silicon carbide, another suitable dielectric material, etc., and / or may be formed to a thickness of about 100 angstroms or a thickness in a range of about 75 angstroms to 125 angstroms. In some embodiments, the upper ILD layer 152 and / or the first dielectric cap layer 1002 may be deposited, for example, by PVD, CVD, ALD, or another suitable deposition process. In some embodiments, while forming the upper ILD layer 152, a trench 158 may be defined between the first MRAM cell 148 and the second MRAM cell 150. In some embodiments, the first dielectric cap layer 1002 fills the trench 158.

[0123] like Fig.11A As shown in the cross-sectional view 1100a, the upper ILD layer 152 and the first dielectric protection layer ( Fig.10 1002) performs a planarization process (eg, a chemical mechanical planarization (CMP) process) to define the first dielectric protection layer 156 and the second dielectric protection layer 302. The first dielectric protection layer ( Fig.10 1002) is configured to protect the upper ILD layer 152 from damage during the planarization process. In some embodiments, the second dielectric protection layer 302 is in the range of about 0 angstroms to 50 angstroms. In further embodiments, the planarization process is configured to completely remove the first dielectric protection layer ( Fig.10 1002), so that the second dielectric protection layer 302 is omitted (see Fig. 11B ). In addition, after the planarization process, the first dielectric capping layer 156 remains in the trench 158 between the first MRAM cell 148 and the second MRAM cell 150 .

[0124] In some embodiments, the planarization process is configured to ensure that the upper ILD layer 152 has a substantially flat upper surface (e.g., a flat upper surface within the tolerance of the CMP process). For example, in some embodiments, at any point, the height of the upper surface 152us of the upper ILD layer 152 varies from a flat horizontal line 1102 disposed along the top surface of the first dielectric cap layer 156 in a range of -25 angstroms to +25 angstroms. In other embodiments, at any point, the height of the upper surface 152us of the upper ILD layer 152 varies from a range of -5 angstroms to +5 angstroms from the flat horizontal line 1102. In still other embodiments, at any point, the height of the upper surface 152us of the upper ILD layer 152 varies from approximately +10% to -10% of the thickness of the upper ILD layer 152 in a range of approximately +10% to -10% of the thickness of the upper ILD layer 152 in a range of -25 angstroms to +25 angstroms from the flat horizontal line 1102 disposed along the top surface of the first dielectric cap layer 156.

[0125] In some embodiments, the planarization process is configured to define a height h1 defined between the upper surface of the upper ILD layer 152 and the upper surface of the lower ILD layer 114. In further embodiments, the height h1 is about 2,000 angstroms or in a range of about 1,500 to 2,500 angstroms. In addition, the planarization process defines a distance d5 between the upper surface of the top electrode 144 and the upper surface of the upper ILD layer 152. In some embodiments, the distance d5 is in a range of about 300 to 700 angstroms. In further embodiments, if the distance d5 is less than 300 angstroms, there may not be sufficient space above the top electrode 144 to properly form an overlying conductive layer. In still further embodiments, if the distance d5 is greater than 700 angstroms, a gap may occur between the conductive layer formed above the top electrode 144 and the top electrode 144, so that the top electrode 144 is electrically isolated from the conductive layer.

[0126] Fig. 11B Show Fig.11A Cross-sectional views 1100b of some alternative embodiments of the cross-sectional view 1100a are shown. Fig. 11B As shown in FIG. , the upper ILD layer 152 and the first dielectric protection layer ( Fig.10 1002) is subjected to a planarization process (eg, a CMP process) to define the first dielectric protection layer 156. In some embodiments, to ensure that the first dielectric protection layer ( Fig.10 The duration of the planarization process is controlled in such a way that the upper surface 152us of the upper ILD layer 152 and the upper surface of the first dielectric protection layer 156 are completely removed from the logic area 103. In some embodiments, the upper surface 152us of the upper ILD layer 152 and the upper surface of the first dielectric protection layer 156 are respectively arranged along the planarization horizontal line 1102. In some embodiments, the planarization horizontal line 1102 is parallel to the upper surface of the lower ILD layer 114.

[0127] In some embodiments, the method may be performed from Fig.11A Flow direction Fig.12 , and in an alternative embodiment, the method may be performed from Fig. 11B Flow direction Fig.12 .

[0128] like Fig.12 As shown in the cross-sectional view 1200, a second dielectric protection structure 1202 is formed over the upper ILD layer 152. A second dielectric protection structure 1204 is formed over the second dielectric protection structure 1202. A mask layer 1206 is formed over the second dielectric protection structure 1204. In some embodiments, the second dielectric protection structure 1202 includes the same material as the first dielectric protection layer 156 and / or is formed to a thickness of about 100 angstroms. In some embodiments, the second dielectric protection structure 1204 is a nitrogen free anti-reflective (NFARC) layer including a silicon oxide layer having a thickness in a range between about 150 angstroms and 250 angstroms. In further embodiments, the mask layer 1206 may be, for example, or include titanium nitride, tantalum nitride, etc., and / or may be formed to a thickness of about 350 angstroms. In some embodiments, the second dielectric protection structure 1202 , the second dielectric protection structure 1204 , and / or the mask layer 1206 may be deposited, for example, by CVD, PVD, ALD, or another suitable deposition or growth process.

[0129] like Fig.13 As shown in the cross-sectional view 1300 , a patterning process is performed on the mask layer 1206 and the second dielectric protection structure 1204 to define a plurality of openings 1302 .

[0130] like Fig.14 As shown in the cross-sectional view 1400, Fig.13The structure shown is subjected to a patterning process to expand the plurality of openings 1302. In some embodiments, the patterning process includes performing one or more etching processes and exposing the unmasked area of ​​the layer below the mask layer 1206 to one or more etchants. The one or more etching processes may include performing a first dry etching process in the second dielectric protection structure 1202 and the upper ILD layer 152 until the upper surface of the outer sidewall spacer layer 146 is reached. In such an embodiment, the outer sidewall spacer layer 146 may not be etched by the first dry etching process. The one or more etching processes may also include performing a second dry etching process (e.g., linear removal (LMR)) to remove at least a portion of the outer sidewall spacer layer 146 and expose the upper surface of the top electrode 144. In some embodiments, the second dry etching process may utilize one or more etchants, such as (for example) carbon fluoride (e.g., C4F8), argon (Ar), oxygen (O2), a combination of the foregoing, and the like. In some embodiments, the second dry etching process may etch the outer sidewall spacer layer 146 at a rate at least 5 times faster than the protective sidewall spacer layer 136 is etched during the second dry etching process.

[0131] In some embodiments, since the protective sidewall spacer layer 136 has a lower etch rate than adjacent layers and / or structures (e.g., the outer sidewall spacer layer 146), after the patterning process, the protective sidewall spacer layer 136 continuously surrounds and / or directly contacts the outer sidewall of the top electrode 144. This, in part, ensures that the protective sidewall spacer layer 136 persists during the over-etching cycle and continues to protect the top electrode 144 and the sidewalls of the MTJ structure 142, thereby preventing damage to the MTJ structure 142 during the patterning process and during subsequent processing steps.

[0132] like Fig.15 As shown in the cross-sectional view 1500, in the plurality of openings ( Fig.14 1302) to form a conductive structure 1502. In some embodiments, the conductive structure 1502 may be, for example, or include aluminum, copper, tantalum, titanium, a combination of the foregoing, etc. In further embodiments, the conductive structure 1502 may be deposited, for example, by CVD, PVD, sputtering, electroless plating, or another suitable growth or deposition process.

[0133] like Fig.16 As shown in the cross-sectional view 1600 , a planarization process (eg, a CMP process) is performed on the conductive structure 1502 to define the upper conductive traces 154 and the vias 153. In some embodiments, the planarization process is performed until the upper surface of the upper ILD layer 152 is reached.

[0134] Fig.17A flowchart of some embodiments of a method 1700 for forming a memory device having an MRAM cell is shown, wherein the MRAM cell includes a protective sidewall spacer layer that laterally surrounds the MTJ and a top electrode that contacts the overlying conductive trace. Although method 1700 is shown and described herein as a series of actions or events, it should be understood that the order of such actions or events should not be interpreted as having a limiting meaning. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown may be required to implement one or more aspects or embodiments of the description herein. In addition, one or more of the actions depicted herein may be performed in one or more separate actions and / or stages.

[0135] At act 1702, one or more lower interconnect layers are formed over a substrate. Figure 6 Cross-sectional view 600 is shown corresponding to some embodiments of act 1702 .

[0136] At action 1704, a magnetoresistive random access memory (MRAM) cell is formed on the lower interconnect layer. The MRAM cell includes a bottom electrode, a top electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top electrode and the bottom electrode. Figures 6 to 8 Cross-sectional views 600 through 800 are shown corresponding to some embodiments of act 1704 .

[0137] At act 1706, sidewall spacer structures are formed around the MRAM cell. The sidewall spacer structures each include a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer between the first sidewall spacer layer and the second sidewall spacer layer. Figure 7 and Figure 8 Cross-sectional views 700 and 800 are shown corresponding to some embodiments of act 1706 .

[0138] At act 1708, an upper interlayer dielectric (ILD) layer and a first dielectric cap layer are formed over the MRAM cells. The upper ILD layer includes sidewalls defining trenches between the MRAM cells, wherein the first dielectric cap layer fills the trenches. Fig.10 Cross-sectional view 1000 is shown corresponding to some embodiments of act 1708 .

[0139] At act 1710, a planarization process is performed on the upper ILD layer and the first dielectric capping layer, thereby defining the first dielectric capping layer in the trench. Fig.11A shows a cross-sectional view 1100a corresponding to some embodiments of act 1710, and Fig. 11B A cross-sectional view 1100b corresponding to an alternative embodiment of act 1710 is shown.

[0140] At act 1712, a mask layer is formed over the upper ILD layer. Fig.12 and Fig.13 Cross-sectional views 1200 and 1300 are shown corresponding to some embodiments of act 1712 .

[0141] At act 1714, the upper ILD layer is patterned to define a plurality of openings above the top electrode of each MRAM cell. Fig.14 Cross-sectional view 1400 is shown corresponding to some embodiments of act 1714 .

[0142] At act 1716, an upper conductive trace is formed over the top electrode of each MRAM cell. Fig.15 and Fig.16 Cross-sectional views 1500 and 1600 are shown corresponding to some embodiments of act 1716 .

[0143] Therefore, in some embodiments, the present disclosure relates to a method for forming a memory device including an MRAM cell having a protective sidewall spacer layer disposed in an embedded memory region and a lower interconnection line disposed in a logic region. The method includes forming a dielectric structure over the MRAM cell and the lower interconnection line, and then performing a single etching process based on a single mask layer to expose the upper surface of the MRAM cell and the upper surface of the lower interconnection line.

[0144] In some embodiments, the present application provides a memory device, which includes: an upper interlayer dielectric (ILD) layer overlying a substrate; a first memory cell disposed in the upper ILD layer, wherein the first memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top electrode and the bottom electrode; a sidewall spacer structure laterally surrounding the first memory cell, wherein the sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer disposed between the first sidewall spacer layer and the second sidewall spacer layer, wherein the first sidewall spacer layer and the second sidewall spacer layer include a first material, and the protective sidewall spacer layer includes a second material different from the first material; and a conductive trace overlying the first memory cell, wherein the conductive trace contacts the top electrode and the protective sidewall spacer layer.

[0145] In some embodiments, the present application provides a memory device, the memory device comprising: a first magnetoresistive random access memory (MRAM) cell overlying a substrate and disposed in an embedded storage area, wherein the embedded storage area is adjacent to a logic area; a second MRAM cell overlying the substrate, wherein the first MRAM cell and the second MRAM cell respectively comprise a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top electrode and the bottom electrode; an upper interlayer dielectric (ILD) layer overlying the first MRAM cell and the second MRAM cell, wherein the upper ILD layer comprises a trench defined between the first MRAM cell and the second MRAM cell The invention relates to a first MRAM cell and a second MRAM cell, wherein the upper ILD layer comprises a first material; a first dielectric protection layer disposed in the trench and comprising a second material different from the first material, wherein the first dielectric protection layer is offset by a non-zero distance in a lateral direction relative to the logic region; a sidewall spacer structure, which surrounds the first MRAM cell and the second MRAM cell in a lateral direction, respectively, wherein the sidewall spacer structure comprises a protective sidewall spacer layer disposed between the first sidewall spacer layer and the second sidewall spacer layer; and a conductive trace overlying the first MRAM cell and the second MRAM cell, wherein the first conductive trace directly contacts a top surface of the first MRAM cell, and the second conductive trace directly contacts a top surface of the second MRAM cell.

[0146] In some embodiments, the present application provides a method for forming a memory device, the method comprising: forming a first magnetoresistive random access memory (MRAM) cell on a substrate; forming a second MRAM cell on the substrate; forming sidewall spacer structures around the first MRAM cell and the second MRAM cell, respectively, wherein the sidewall spacer structures respectively include a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer; forming an upper layer spacer on the first MRAM cell and the second MRAM cell A dielectric (ILD) layer is provided, wherein an upper ILD layer includes sidewalls defining a trench laterally spaced apart between a first MRAM cell and a second MRAM cell; a dielectric cap layer is formed over the upper ILD layer, wherein the dielectric cap layer fills the trench; a first planarization process is performed on the upper ILD layer and the dielectric cap layer, wherein the dielectric cap layer remains in the trench after the first planarization process; and a conductive trace is formed over the first MRAM cell and the second MRAM cell, wherein the conductive trace directly contacts top electrodes of the first MRAM cell and the second MRAM cell, respectively.

[0147] According to some embodiments of the present disclosure, a memory device is provided, comprising: an upper interlayer dielectric (ILD) layer overlying a substrate; a first memory cell arranged in the upper interlayer dielectric layer, wherein the first memory cell comprises a top electrode, a bottom electrode and a magnetic tunnel junction (MTJ) structure arranged between the top electrode and the bottom electrode; a sidewall spacer structure laterally surrounding the first memory cell, wherein the sidewall spacer structure comprises a first sidewall spacer layer, a second sidewall spacer layer and a protective sidewall spacer layer arranged between the first sidewall spacer layer and the second sidewall spacer layer, wherein the first sidewall spacer layer and the second sidewall spacer layer comprise a first material, and the protective sidewall spacer layer comprises a second material different from the first material; and a conductive trace overlying the first memory cell, wherein the conductive trace contacts the top electrode and the protective sidewall spacer layer.

[0148] In some embodiments, the memory device also includes: a second memory cell disposed within the upper interlayer dielectric layer and laterally offset relative to the first memory cell; and a first dielectric protection layer disposed between the first memory cell and the second memory cell, wherein the first dielectric protection layer is disposed between side walls of a defined groove of the upper interlayer dielectric layer, wherein the first dielectric protection layer includes inclined relative side walls, and wherein the first dielectric protection layer includes a first dielectric material, and the upper interlayer dielectric layer includes a second dielectric material different from the first dielectric material.

[0149] In some embodiments, the inclined opposing sidewalls are laterally offset by a non-zero distance relative to the conductive trace.

[0150] In some embodiments, the conductive trace directly contacts a top surface of the top electrode and directly contacts a top surface of the protective sidewall spacer layer.

[0151] In some embodiments, the conductive trace directly contacts the second sidewall spacer layer.

[0152] In some embodiments, the first material includes silicon nitride or silicon carbide, and the second material includes aluminum oxide.

[0153] In some embodiments, a maximum width of the conductive trace is greater than a maximum width of the magnetic tunnel junction structure.

[0154] In some embodiments, the conductive trace directly contacts an upper surface and sidewalls of the top electrode.

[0155] In some embodiments, a bottom surface of the conductive trace is disposed below a top surface of the magnetic tunnel junction structure, wherein the conductive trace extends continuously along a top surface and sidewalls of the protective sidewall spacer layer.

[0156] According to some other embodiments of the present disclosure, a memory device is provided, comprising: a first magnetoresistive random access memory (MRAM) cell overlying a substrate and disposed in an embedded storage area, wherein the embedded storage area is adjacent to a logic area; a second magnetoresistive random access memory cell overlying the substrate, wherein the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell respectively include a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top electrode and the bottom electrode; an upper interlayer dielectric (ILD) layer overlying the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, wherein the upper interlayer dielectric layer includes a side surface defining a trench between the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell; A first dielectric protection layer is disposed in the groove and comprises a second material different from the first material, wherein the first dielectric protection layer is offset by a non-zero distance in the lateral direction relative to the logic area; a sidewall spacer structure surrounds the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell in the lateral direction, respectively, wherein the sidewall spacer structure comprises a protective sidewall spacer layer disposed between the first sidewall spacer layer and the second sidewall spacer layer; and a conductive trace overlying the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, wherein the first conductive trace directly contacts the top surface of the first magnetoresistive random access memory cell, and the second conductive trace directly contacts the top surface of the second magnetoresistive random access memory cell.

[0157] In some embodiments, the memory device further includes: a lower interconnect routing, disposed in the logic area, wherein the lower interconnect routing is located below the first magnetoresistive random access memory unit and the second magnetoresistive random access memory unit in a vertical direction; a via hole overlying the lower interconnect routing; and an upper conductive routing overlying the via hole, wherein an upper surface of the upper conductive routing is aligned with an upper surface of the first dielectric protection layer.

[0158] In one embodiment, a bottom surface of the upper conductive trace disposed in the logic region is located vertically below a bottom surface of the conductive trace disposed in the embedded memory region.

[0159] In some embodiments, the first material is a low-k dielectric material and the second material is a very low-k dielectric material.

[0160] In one embodiment, the first sidewall spacer layer and the second sidewall spacer layer include the second material, wherein the second material is silicon nitride, and wherein the protective sidewall spacer layer includes aluminum oxide.

[0161] In some embodiments, the first conductive trace directly contacts the protective sidewall spacer layer laterally surrounding the first MRAM cell, and the second conductive trace directly contacts the protective sidewall spacer layer laterally surrounding the second MRAM cell.

[0162] According to some other embodiments of the present disclosure, a method for manufacturing a memory device is provided, comprising: forming a first magnetoresistive random access memory (MRAM) cell on a substrate; forming a second magnetoresistive random access memory cell on the substrate; forming sidewall spacer structures around the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, respectively, wherein the sidewall spacer structures respectively include a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer; forming an upper interlayer dielectric (ILD) layer on the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, wherein the The upper interlayer dielectric layer includes sidewalls defining a trench, the sidewalls being laterally spaced apart between the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell; forming a dielectric protection layer over the upper interlayer dielectric layer, wherein the dielectric protection layer fills the trench; performing a first planarization process on the upper interlayer dielectric layer and the dielectric protection layer, wherein the dielectric protection layer remains in the trench after the first planarization process; and forming a conductive trace over the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, wherein the conductive trace directly contacts the top electrodes of the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, respectively.

[0163] In some embodiments, forming the conductive trace comprises: forming a mask layer on the upper interlayer dielectric layer; patterning the upper interlayer dielectric layer according to the mask layer, thereby exposing the upper surfaces of the top electrodes of the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, respectively, and defining openings on the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, wherein during the patterning process, the upper interlayer dielectric layer is etched at a first rate, and the protective sidewall spacer layer is etched at a second rate, wherein the first rate is at least 5 times faster than the second rate;

[0164] A conductive structure is formed in the opening; and a second planarization process is performed on the conductive structure until the upper surface of the dielectric protection layer is reached, thereby defining the conductive trace above the first magnetoresistive random access memory unit and the second magnetoresistive random access memory unit, wherein the conductive trace directly contacts the corresponding protective sidewall spacer layer.

[0165] In some embodiments, the memory device includes an embedded storage area laterally adjacent to a logic area, wherein the first magnetoresistive random access memory unit and the second magnetoresistive random access memory unit are laterally disposed within the embedded storage area and are laterally offset from the logic area by a non-zero distance, wherein after the first planarization process, the dielectric protection layer is removed from the logic area.

[0166] In some embodiments, the upper interlayer dielectric layer includes a first dielectric material, and the dielectric cap layer includes a second dielectric material, wherein the first dielectric material is a different material from the second dielectric material.

[0167] In some embodiments, sidewalls of the upper interlayer dielectric layer defining the trench are inclined at a non-zero angle relative to a horizontal line aligned with a bottom surface of the dielectric capping layer.

[0168] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that include: an upper interlayer dielectric layer overlying the substrate; A first memory cell is disposed in the upper interlayer dielectric layer, wherein the first memory cell comprises a top electrode, a bottom electrode, and a magnetic tunnel junction structure disposed between the top electrode and the bottom electrode; a sidewall spacer structure surrounding the first memory cell in a lateral direction, wherein the sidewall spacer structure comprises a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer disposed between the first sidewall spacer layer and the second sidewall spacer layer, wherein the first sidewall spacer layer and the second sidewall spacer layer comprise a first material, and the protective sidewall spacer layer comprises a second material different from the first material; as well as A conductive trace overlying the first storage unit, wherein the conductive trace directly contacts the top surface of the top electrode, directly contacts the top surface of the protective sidewall spacer layer, and directly contacts the second sidewall spacer layer, and the protective sidewall spacer layer is arranged between the top surface of the bottom electrode and the lower surface of the second sidewall spacer layer.

2. The memory device according to claim 1, further comprising: a second memory cell disposed in the upper interlayer dielectric layer and laterally offset relative to the first memory cell; as well as A first dielectric protection layer is arranged between the first memory cell and the second memory cell, wherein the first dielectric protection layer is arranged between the side walls of the defining groove of the upper interlayer dielectric layer, wherein the first dielectric protection layer includes inclined relative side walls, and wherein the first dielectric protection layer includes a first dielectric material, and the upper interlayer dielectric layer includes a second dielectric material different from the first dielectric material. 3 . The memory device of claim 2 , wherein the sloped opposing sidewalls are laterally offset by a non-zero distance relative to the conductive trace. 4 . The memory device of claim 1 , wherein the conductive trace extends laterally from the top electrode continuously to a sidewall of the second sidewall spacer layer. 5 . The memory device of claim 1 , wherein a top surface of the second sidewall spacer layer is perpendicular to and above a bottom surface of the conductive trace. 6 . The memory device of claim 1 , wherein the first material comprises silicon nitride or silicon carbide, and the second material comprises aluminum oxide. 7 . The memory device of claim 1 , wherein a maximum width of the conductive trace is greater than a maximum width of the magnetic tunnel junction structure.

8. The memory device of claim 1, wherein the conductive trace directly contacts an upper surface and sidewalls of the top electrode.

9. The memory device of claim 1, wherein a bottom surface of the conductive trace is disposed below a top surface of the magnetic tunnel junction structure, wherein the conductive trace extends continuously along a top surface and sidewalls of the protective sidewall spacer layer.

10. A memory device, characterized in that include: A first magnetoresistive random access memory unit overlying the substrate and disposed in an embedded storage area, wherein the embedded storage area is adjacent to the logic area; A second magnetoresistive random access memory cell overlying the substrate, wherein the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell respectively include a top electrode, a bottom electrode, and a magnetic tunnel junction structure disposed between the top electrode and the bottom electrode; an upper interlayer dielectric layer overlying the first MRAM cell and the second MRAM cell, wherein the upper interlayer dielectric layer includes sidewalls defining a trench between the first MRAM cell and the second MRAM cell, wherein the upper interlayer dielectric layer comprises a first material; a first dielectric protection layer disposed in the trench and comprising a second material different from the first material, wherein the first dielectric protection layer is laterally offset by a non-zero distance relative to the logic region; A sidewall spacer structure, surrounding the first magnetoresistive random access memory unit and the second magnetoresistive random access memory unit in a lateral direction, respectively, wherein the sidewall spacer structure comprises a protective sidewall spacer layer disposed between the first sidewall spacer layer and the second sidewall spacer layer, and the protective sidewall spacer layer is disposed between the top surface of the bottom electrode and the lower surface of the second sidewall spacer layer; A conductive trace overlying the first magnetoresistive random access memory unit and the second magnetoresistive random access memory unit, wherein the first conductive trace directly contacts a top surface of the first magnetoresistive random access memory unit, and the second conductive trace directly contacts a top surface of the second magnetoresistive random access memory unit; as well as The outer sidewall spacer layer laterally surrounds the first sidewall spacer layer, the second sidewall spacer layer, the protective sidewall spacer layer and the bottom electrode.

11. The memory device according to claim 10, further comprising: A lower interconnect wiring is disposed in the logic area, wherein the lower interconnect wiring is located below the first magnetoresistive random access memory unit and the second magnetoresistive random access memory unit in a vertical direction; A via hole overlying the lower inner connecting line; and An upper conductive trace overlies the via, wherein an upper surface of the upper conductive trace is aligned with an upper surface of the first dielectric protection layer. 12 . The memory device of claim 11 , wherein a bottom surface of the upper conductive trace disposed in the logic region is located vertically below a bottom surface of the conductive trace disposed in the embedded memory region.

13. The memory device of claim 10, wherein the first material is a low-k dielectric material and the second material is a very low-k dielectric material.

14. The memory device of claim 10, wherein the first sidewall spacer layer and the second sidewall spacer layer comprise the second material, wherein the second material is silicon nitride, and wherein the protective sidewall spacer layer comprises aluminum oxide.

15. The memory device of claim 10, wherein the first conductive trace directly contacts the protective sidewall spacer layer that laterally surrounds the first magnetoresistive random access memory cell, and the second conductive trace directly contacts the protective sidewall spacer layer that laterally surrounds the second magnetoresistive random access memory cell.

16. A method for manufacturing a memory device, characterized in that include: forming a first magnetoresistive random access memory cell over the substrate; forming a second magnetoresistive random access memory cell on the substrate; forming sidewall spacer structures around the first magnetoresistive random access memory unit and the second magnetoresistive random access memory unit, respectively, wherein the sidewall spacer structures respectively include a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first sidewall spacer layer and the second sidewall spacer layer, and the protective sidewall spacer layer is disposed between the top surface of the bottom electrode of the first magnetoresistive random access memory unit and the second magnetoresistive random access memory unit and the lower surface of the second sidewall spacer layer; forming an upper interlayer dielectric layer over the first and second MRAM cells, wherein the upper interlayer dielectric layer includes sidewalls defining trenches, the sidewalls being laterally spaced apart between the first and second MRAM cells; forming a dielectric protection layer on the upper interlayer dielectric layer, wherein the dielectric protection layer fills the trench; performing a first planarization process on the upper interlayer dielectric layer and the dielectric protection layer, wherein the dielectric protection layer remains in the trench after the first planarization process; as well as A conductive trace is formed over the first MRAM cell and the second MRAM cell, wherein the conductive trace directly contacts top electrodes of the first MRAM cell and the second MRAM cell, respectively.

17. The method for manufacturing a memory device according to claim 16, wherein forming the conductive trace comprises: forming a mask layer over the upper interlayer dielectric layer; Patterning the upper interlayer dielectric layer according to the mask layer to expose upper surfaces of the top electrodes of the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, respectively, and defining openings above the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell, wherein during the patterning process, the upper interlayer dielectric layer is etched at a first rate, and the protective sidewall spacer layer is etched at a second rate, wherein the first rate is at least 5 times faster than the second rate; forming a conductive structure within the opening; as well as A second planarization process is performed on the conductive structure until reaching the upper surface of the dielectric protection layer, thereby defining the conductive traces above the first and second magnetoresistive random access memory cells, wherein the conductive traces directly contact the corresponding protective sidewall spacer layers.

18. A method for manufacturing a memory device according to claim 16, wherein the memory device includes an embedded storage area laterally adjacent to a logic area, wherein the first magnetoresistive random access memory cell and the second magnetoresistive random access memory cell are laterally arranged in the embedded storage area and are laterally offset from the logic area by a non-zero distance, wherein after the first planarization process, the dielectric protection layer is removed from the logic area.

19. The method for manufacturing a memory device according to claim 16, wherein the upper interlayer dielectric layer comprises a first dielectric material, and the dielectric protection layer comprises a second dielectric material, wherein the first dielectric material is a different material from the second dielectric material. 20 . The method for manufacturing a memory device according to claim 16 , wherein a sidewall of the upper interlayer dielectric layer defining the trench is inclined at a non-zero angle relative to a horizontal line aligned with a bottom surface of the dielectric protection layer.

Images