Pulsing neural network circuit and operation method thereof

Abstract

The present invention discloses a pulse neural network circuit and an operation method thereof. The pulse neural network circuit includes a bit line input synaptic array and a neuron circuit. The bit line input synaptic array includes a plurality of page buffers, a plurality of bit line transistors, a plurality of bit lines, a plurality of storage units, a word line, a plurality of source lines and a plurality of source line transistors. The page buffer is used to provide a plurality of data signals. Each bit line transistor is electrically connected to one of these page buffers. Each bit line receives one of these data signals. These source line transistors are connected together. The neuron circuit is used to output a feedback pulse.

Description

Technical Field

[0001] The present invention relates to a circuit and an operating method thereof, and in particular to a pulse neural network circuit and an operating method thereof. Background Art

[0002] With the vigorous development of artificial intelligence, the emerging architecture of edge computing that can provide privacy protection, powerful computing power and low energy consumption has attracted widespread attention in various application fields.

[0003] Taking advantage of training and reasoning on local storage devices, the energy consumption of data movement in the von Neumann architecture can be drastically reduced, and spiking neural networks (SNNs) are considered one of the most promising candidates for edge computing. Although the use of spiking neural networks can conceptually improve energy efficiency, the operating power consumption of storage arrays is still quite high and cannot be ignored. Summary of the invention

[0004] The present invention relates to a pulse neural network circuit and its operation method, which uses a bit line input structure to input data signals. Compared with the word line input structure, the bit line input structure not only reduces energy consumption, but also significantly increases the area efficiency of the storage array.

[0005] According to one aspect of the present invention, a spiking neural network circuit (SNN circuit) is proposed. The spiking neural network circuit includes a bit-line input synapse array and a neuron circuit. The bit-line input synapse array includes a plurality of page buffers, a plurality of bit-line transistors, a plurality of bit lines, a plurality of storage cells, a word line, a plurality of source lines and a plurality of source line transistors. The page buffer is used to provide a plurality of data signals. Each bit-line transistor is electrically connected to one of these page buffers. Each bit-line is electrically connected to one of these bit-line transistors to receive one of these data signals. Each storage cell is electrically connected to one of these bit lines. The word line is electrically connected to these storage cells. Each source line is electrically connected to one of these storage cells. Each source line transistor is electrically connected to one of these source lines. These source line transistors are connected together. The neuron circuit is used to output a feedback pulse.

[0006] According to one aspect of the present invention, a method for operating a spiking neural network circuit (SNN circuit) is proposed. The spiking neural network circuit includes a bit-line input synapse array and a neuron circuit. The bit-line input synapse array includes a plurality of bit lines, a plurality of memory cells, a word line, and a plurality of source lines. Each memory cell is electrically connected to one of these bit lines. The word line is electrically connected to these memory cells. Each source line is electrically connected to one of these memory cells. The operating method includes the following steps. In a read phase, a plurality of data signals are input to these bit lines. In the read phase, a plurality of currents reflecting these data signals are collected by these source lines.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Draw a conceptual diagram of a neural system.

[0009] Figure 2 A conceptual diagram showing a spiking neural networks circuit (SNN circuit)

[0010] Figure 3 A schematic diagram showing a spiking neural network circuit is shown.

[0011] Figure 4 A schematic diagram of a bit line input synapse array is shown.

[0012] Figure 5 A flow chart illustrating how a spiking neural network circuit operates.

[0013] Figure 6 Explain the winner-take-all rule.

[0014] Figure 7 The operation flow of the bit line input synapse array is shown.

[0015] Figures 8A to 8E illustrate Figure 7 each step.

[0016] Fig. 9A Describe the operating conditions when the winner is input with a pattern signal.

[0017] Fig. 9B Describe the operating conditions when the winner is input with a background signal.

[0018] Fig. 10A Describes the operation of the page buffer in the input process.

[0019] Fig. 10B The operation of the page buffer during the read process is described.

[0020] Fig. 10C Describes the operation of the winner's page buffer during the update process.

[0021] Fig. 10D Explain the operation of the loser's page buffer during the update process.

[0022]

Explanation of symbols

[0023] 1000: Spiking Neural Network Circuit

[0024] A1, A2: axon

[0025] B1, B2: fine unit body

[0026] BL: Bit Line

[0027] BLT: Bit Line Transistor

[0028] R1, R2: dendrites

[0029] d1: data signal

[0030] d1': data signal after offset

[0031] EP: Erase Pulse

[0032] I1: Current

[0033] IAF: Integrated and Launched Circuit

[0034] IH: Inhibitor Field Effect Transistor

[0035] LC: Latch

[0036] LS: Level Shifter

[0037] LTD: Long-term inhibitory signal

[0038] LTP: Long Term Potential Signal

[0039] N1, N2: NMOS transistors

[0040] NC: Neuronal Circuit

[0041] NC': other neuronal circuits

[0042] N_post: postsynaptic neuron

[0043] N_pre: presynaptic neuron

[0044] NS: Nervous system

[0045] N_in: Input neuron

[0046] N_out: output neuron

[0047] M1: First current mirror

[0048] M2: Second current mirror

[0049] MC: Film capacitor

[0050] MEM: Memory Unit

[0051] MR: Current mirror circuit

[0052] PS1: Feedback pulse

[0053] PS2: Output pulse

[0054] PB: Page Buffer

[0055] PG: Pulse Generator

[0056] PP: Programming Pulse

[0057] S12: Synapse

[0058] S51, S52, S53, S54, S55, S56, S57, S71, S72, S73, S74, S75, S76: Steps

[0059] SA: Bit Line Input Synaptic Array

[0060] SA': post-bit line input synaptic array

[0061] SL: Source Line

[0062] SLT: Source Line Transistor

[0063] S_update: Update program

[0064] S_read: Read program

[0065] S_ers: Erasing Steps

[0066] S_pgm: Programming steps

[0067] SM: Surge Rate Measurement Unit

[0068] WL: Word Line

[0069] Z0: Synaptic zone

[0070] Z1: synaptic zone presynaptic zone

[0071] Z2: synaptic zone and postsynaptic zone DETAILED DESCRIPTION

[0072] Please refer to Figure 1 , which depicts a conceptual diagram of a neural system NS. The presynaptic cell N_pre includes a cell body B1, multiple dendrites R1, and an axon A1. The postsynaptic cell N_post includes a cell body B2, multiple dendrites R2, and an axon A2. The signal is output from the axon A1 to the dendrite R2. The connection between the axon A1 and the dendrite R2 is the synapse S12.

[0073] Please refer to Figure 2 , which depicts a conceptual diagram of a spiking neural networks circuit (SNN circuit) 1000. The spiking neural network circuit 1000 can be used to perform neuromorphic computing. Similar to the presynaptic neuron N_pre and the postsynaptic neuron N_post of the neuromorphic system NS, the input neuron N_in transmits a data signal d1 to the output neuron N_out. The data signal d1 is input to a bit-line input synapse array SA, and a current I1 reflecting the data signal d1 is accumulated in a membrane capacitor MC. When the potential of the membrane capacitor MC exceeds a critical value, an integrated-and-fired circuit IAF triggers a pulse generator PG to generate a feedback pulse PS1 or an output pulse PS2.

[0074] Please refer to Figure 3, which depicts a schematic diagram of the pulse neural network circuit 1000. The bit line input synapse array SA includes a plurality of page buffers PB, a plurality of bit line transistors BLT, a plurality of bit lines BL, a plurality of memory cells MEM, a word line WL, a plurality of source lines SL, and a plurality of source line transistors SLT. The page buffer PB provides a plurality of data signals d1. Each bit line transistor BLT is electrically connected to one of the page buffers PB. For example, the bit line transistor BLT is, for example, a triple well device. Each bit line BL is electrically connected to one of the bit line transistors BLT to receive one of the data signals d1. Each memory cell MEM is electrically connected to one of the bit lines BL. A word line WL is electrically connected to the memory cell MEM. Each source line SL is electrically connected to one of the memory cells MEM. Each source line transistor SLT is electrically connected to one of the source lines SL. For example, the source line transistor SLT is, for example, a triple well device. The source line transistors SLT are connected together to collect a current I1 reflecting the data signal d1.

[0075] The neuron circuit NC includes a current mirror circuit MR, a thin film capacitor MC, an inhibitory field-effect transistor (FET) IH, an integrated-and-fired circuit IAF and a pulse generator PG. The current mirror circuit MR is electrically connected to the bit line input synapse array SA. The current I1 is copied by the current mirror circuit MR and transmitted backward. The thin film capacitor MC is electrically connected to the current mirror circuit MR to receive and accumulate the current I1. The integrated-and-fired circuit IAF is electrically connected to the thin film capacitor MC and the inhibitory field-effect transistor IH. The pulse generator PG is electrically connected to the integrated-and-fired circuit IAF, the bit line transistor BLT and the source line transistor SLT.

[0076] When the potential of the film capacitor MC exceeds the critical value, the integrated and transmitting circuit IAF triggers the pulse generator PG to generate a feedback pulse PS1 or triggers the pulse generator PG to generate an output pulse PS2 to the postbit-line input synapse array SA', and the inhibition field effect transistor IH will suspend the firing action of other neuron circuits NC'.

[0077] The current mirror circuit MR includes a first current mirror M1 and a second current mirror M2. The first current mirror M1 includes two NMOS transistors (N type Metal-Oxide-Semiconductor transistors) N1 and N2. For example, the NMOS transistors N1 and N2 are triple well components. The second current mirror M2 is connected to the first current mirror M1. The second current mirror M2 includes two PMOS transistors (P type Metal-Oxide-Semiconductor transistors) P1 and P2. The second current mirror M2 is a reverse current mirror designed for a bit line input mechanism.

[0078] In one embodiment, the current mirror circuit MR may include a plurality of current mirrors connected in series to reduce the size of the film capacitor MC.

[0079] Please refer to Figure 4 , which illustrates a schematic diagram of the bit line input synaptic array SA. The bit line transistor BLT and the bit line BL form a presynaptic zone Z1, the memory cell MEM and the word line WL form a synaptic zone Z0, and the source line transistor SLT and the source line SL form a postsynaptic zone Z2. Data is stored in a word line WL (with 4V input). In other words, the memory cell MEM corresponding to the weights stored in this data is only connected to one word line WL. This disclosure refers to word line direction data storage or one-dimensional data storage. Other word lines WL can store other types of data. Therefore, the area efficiency of the memory cell array can be significantly improved.

[0080] Please refer to Figure 5, which illustrates the process of the operation method of the pulse neural network circuit 1000. The operation method of the pulse neural network circuit 1000 includes a read phase S_read and an update phase S_update. The read phase S_read includes steps S51 to S54. In step S51, the data signal d1 is input from the input neuron N_in to the bit line input synapse array SA. Then, in step S52, the current I1 reflecting the data signal d1 is accumulated. Next, in step S53, the integrated and transmitting circuit IAF generates a spike and provides it to the pulse generator PG. In step S54, after receiving the spike, the pulse generator PG generates an output pulse PS2 and provides it to the spike rate measurement unit SM.

[0081] The update procedure S_update includes steps S51, S52, S55, S56 and S57. In step S55, the integration and emission circuit IAF generates a surge and provides it to the pulse generator PG. In step S56, after receiving the surge, the pulse generator PG generates a feedback pulse PS1 to the bit line input synapse array SA to turn on the bit line transistor BLT. In step S57, the integration and emission circuit IAF generates an inhibitory signal and provides it to other neuron circuits NC' to suspend the firing action of other neuron circuits NC' (loser).

[0082] In this embodiment, the update procedure S_update is performed according to a Winner-Take-All operation (WTA operation). Figure 6 , which illustrates the winner-takes-all rule. Only one output neuron N_out closest to the input neuron N_in can win the update opportunity to strengthen the connection with the data signal d1. Moreover, the winner can inhibit the connection between the input neuron N_in and other output neurons N_out. The winner-takes-all rule allows each output neuron N_out to learn different features.

[0083] According to the winner-takes-all rule, the winner and loser execute different update procedures S_update. Figures 7-8E . Figure 7 The operation flow of the bit line input synapse array SA is shown. Figures 8A to 8E illustrate Figure 7 each step.

[0084] In step S71, a read procedure S_read is executed to read the data signal d1. Fig. 8AIn the read procedure S_read, 4V is applied to the word line WL. 0.9V is applied to the gate of the bit line transistor BLT. The data signal d1 is input to the bit line BL. Each data signal d1 is a pattern signal or a background signal. The pattern signal is 0.2V. The background signal is 0V. Part of the memory cell MEM has been erased, and part of the memory cell MEM has been programmed so that the weights stored in the memory cell MEM can represent the features to be identified. The current I1 flowing through the memory cell MEM can reflect the content of the data signal d1. For example, if the data signal d1 is 0.2V and the memory cell MEM has been erased, a higher current I1 will be formed; if the data signal d1 is 0V and the memory cell MEM has been erased, a lower current I1 will be formed.

[0085] 3.3V is applied to the source line transistor SLT to turn on the source line transistor SLT. Then, the current I1 reflecting the data signal d1 can be collected. This current I1 is accumulated in the film capacitor MC (such as Figure 3 If the data signal d1 is close to the feature to be identified, the potential of the film capacitor MC will quickly exceed the critical value, and this output neuron N_out will become the winner. The other output neurons N_out will become losers.

[0086] Next, in step S72, it is determined whether the output neuron N_out is a winner or a loser. For the output neuron N_out of the winner, the process will enter steps S73 and S74 to execute the update procedure S_update; for the output neuron N_out of the loser, the process will enter steps S75 and S76 to suppress the update procedure S_update. In other words, the winner and the loser perform different actions in the update procedure S_update.

[0087] In step S73, the erasing step S_ers of the update program S_update is executed. Figure 8B, in the erasing step S_ers of the update procedure S_update, -6V is applied to the word line WL. 8V is applied to the gate of the bit line transistor BLT to turn on the bit line transistor BLT. 0V is applied to the gate of the source line transistor SLT to turn off the source line transistor SLT and place the source line SL in a floating state. The shifted data signal d1' is input to the bit line BL. Each shifted data signal d1' is a shifted pattern signal or a shifted background signal. The shifted pattern signal is a 6V signal obtained after the 0.2V signal is shifted. The shifted background signal is a -6V signal obtained after the 0V signal is shifted. The voltage difference between the shifted pattern signal of the word line WL and the shifted data signal d1' is -12V, so the memory cell MEM through which the shifted pattern signal passes will be erased. The voltage difference between the post-shift background signal of the word line WL and the post-shift data signal d1 ′ is 0V, so the memory cell MEM through which the post-shift background signal passes will not be erased.

[0088] In step S74, the programming step S_pgm of the update program S_update is executed. Figure 8C , in the programming step S_pgm of the update program S_update, 6V is applied to the word line WL. 8V is applied to the gate of the bit line transistor BLT to turn on the bit line transistor BLT. 0V is applied to the gate of the source line transistor SLT to turn off the source line transistor SLT and place the source line SL in a floating state. The offset data signal d1' is input to the bit line BL. Each offset data signal d1' is an offset pattern signal or an offset background signal. The offset pattern signal is a 6V signal obtained after the 0.2V signal is offset. The offset background signal is a -6V signal obtained after the 0V signal is offset. The voltage difference between the offset pattern signal of the word line WL and the offset data signal d1' is 0V, so the memory cell MEM through which the offset pattern signal passes will not be programmed. The voltage difference between the offset background signal of the word line WL and the offset data signal d1' is 12V, so the memory cell MEM through which the offset background signal passes will be programmed.

[0089] Based on the above steps S73 and S74, the memory cell MEM through the offset pattern signal (6V) will be erased, and the memory cell MEM through the offset background signal (-6V) will be programmed.

[0090] In step S75, the erasing step S_ers of the update program S_update is suppressed. Fig.8D, in the erasing step S_ers of the update procedure S_update, -6V is applied to the word line. 0V is applied to the gate of the bit line transistor BLT to turn off the bit line transistor BLT. 0V is applied to the gate of the source line transistor SLT to turn off the source line transistor SLT and maintain the source line SL in a floating state. The shifted data signal d1' is input to the bit line BL. Since the bit line transistor BLT is turned off, the bit line BL is blocked and the memory cell MEM cannot be erased.

[0091] In step S76, the programming step S_pgm of the update program S_update is suppressed. Fig. 8E , in the programming step S_pgm of the update procedure S_update, 6V is applied to the word line. 0V is applied to the gate of the bit line transistor BLT to turn off the bit line transistor BLT. 0V is applied to the source line transistor SLT to turn off the source line transistor SLT and keep the source line SL in a floating state. The shifted data signal d1' is input to the bit line BL. Since the bit line transistor BLT is turned off, the bit line BL is blocked and the memory cell MEM cannot be programmed.

[0092] Based on the above steps S75 and S76, the memory unit MEM will not be erased or programmed.

[0093] Please refer to Fig. 9A , which illustrates the operating conditions when the pattern signal is input. In the read process S_read, the data signal d1 (0.2V) of the pattern signal is input to the bit line BL, the word line WL is applied with 4V, and the source line SL is applied with 0V. Therefore, in the read process S_read, the current I1 (shown in Figure 3 ) can be collected through the source line SL.

[0094] In the update procedure S_update, the shifted data signal d1' (6V) is input to the bit line BL. In the erasing step S_ers of the update procedure S_update, a long-term potentiation signal LTP (-6V) is applied to the word line WL, and the source line SL is maintained in a floating state. Therefore, an erasing pulse EP (-12V) is formed between the word line WL and the bit line BL, and the memory cell MEM is erased.

[0095] Please refer to Fig. 9B, which illustrates the operating condition when the background signal is input. In the read process S_read, the data signal d1 (0V) of the background signal is input to the bit line BL, the word line WL is applied with 4V, and the source line SL is applied with 0V. Therefore, in the read process S_read, the current I1 (shown in Figure 3 ) can be collected through the source line SL.

[0096] In the update procedure S_update, the shifted data signal d1' (-6V) is input to the bit line BL. In the programming step S_pgm of the update procedure S_update, a long-term depression signal LTD (6V) is applied to the word line WL, and the source line SL is maintained in a floating state. Therefore, a programming pulse PP (12V) is formed between the word line WL and the bit line BL, and the memory cell MEM is programmed.

[0097] like Figures 9A to 9B As shown, the memory cell MEM through the offset pattern signal (6V) will be erased, and the memory cell MEM through the offset background signal (-6V) will be programmed.

[0098] Please refer to Fig. 10A , which illustrates the operation of the page buffer PB during the input phase. Fig. 10A As shown, the page buffer PB includes a latch LC and a level shifter LS. In the input process, the data signal d1 is obtained from an input / output device and is connected to Q and Stored in the latch LC. When the received signal is a pattern signal, Q is 1.8V; when the received signal is a background signal, Q is 0V.

[0099] Please refer to Fig. 10B , which illustrates the operation of the page buffer PB in the read procedure S_read. In the read procedure S_read, the level shifter LS maintains Q at 1.8V or 0V. The gate of the bit line transistor BLT is applied with 0.9V and the base of the bit line transistor BLT is applied with 0V. Due to the signal clamping effect, when Q is 1.8V, the data signal d1 output by the bit line transistor BLT is 0.2V, and when Q is 0V, the data signal d1 output by the bit line transistor BLT is 0V. The gate of the memory cell MEM is applied with 4V through the word line WL. The gate of the source line transistor SLT is applied with 3.3V and the base of the source line transistor SLT is applied with 0V. The current I1 through the memory cell MEM will reflect the content of the data signal d1.

[0100] Please refer to Fig. 10C , which illustrates the operation of the winner's page buffer PB in the update program S_update. In the update program S_update, the level shifter LS outputs the offset data signal d1'. Each offset data signal d1' is an offset pattern signal or an offset background signal. The offset pattern signal is a 6V signal obtained after the 0.2V signal is offset. The offset background signal is a -6V signal obtained after the 0V signal is offset. The offset amount of the offset data signal d1' is greater than the offset amount of the data signal d1. 8V is applied to the gate of the bit line transistor BLT, and -6V is applied to the base of the bit line transistor BLT. The memory cell MEM through the offset pattern signal (6V) will be erased, and the memory cell MEM through the offset background signal (-6V) will be programmed.

[0101] Please refer to Fig. 10D , which illustrates the operation of the loser's page buffer PB in the update procedure S_update. 0V is applied to the gate of the bit line transistor BLT to turn off the bit line transistor BLT. Since the bit line transistor BLT is turned off, the bit line BL is blocked and the memory cell MEM cannot be erased or programmed.

[0102] According to the above embodiment, the pulse neural network circuit 1000 inputs data signals through the bit line BL. Compared with the word line input architecture, the bit line input architecture not only reduces energy consumption, but also significantly increases the area efficiency of the storage array. This low-power architecture is particularly suitable for edge computing technology.

[0103] For example, in the experiment of the pulse neural network circuit, the word line input architecture and the bit line input architecture were compared, and the results are shown in Table 1 below. From the measurement results, it can be seen that the capacitance value of the bit line is 0.075pF, and the capacitance value of the word line is 1.882pF (the capacitance value of the bit line is lower than the capacitance value of the word line). The pulse neural network circuit using the bit line input architecture can reduce the energy consumption by 91% in the reading process and 56% in the updating process compared to the pulse neural network circuit using the word line input architecture.

[0104]

[0105] Table 1

[0106] In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the claims.

Claims

1. A pulse neural network circuit, comprising: A one-bit line input synapse array comprising: A plurality of page buffers for providing a plurality of data signals; A plurality of bit line transistors, each of the bit line transistors being electrically connected to one of the page buffers; A plurality of bit lines, each of the bit lines being electrically connected to one of the bit line transistors; A plurality of memory cells, each of which is electrically connected to one of the bit lines; a word line electrically connected to the memory cells; A plurality of source lines, each of the source lines being electrically connected to one of the memory cells; and a plurality of source line transistors, each of the source line transistors being electrically connected to one of the source lines, wherein the source line transistors are connected together; and A neuron circuit, configured to output a feedback pulse; The bit line transistors and the bit lines form a presynaptic region, the memory cells and the word line form a synaptic region, and the source line transistors and the source lines form a postsynaptic region.

2. The spiking neural network circuit of claim 1, wherein the neuron circuit comprises: a current mirror circuit electrically connected to the bit line input synapse array; a thin film capacitor electrically connected to the current mirror circuit; an integrated and transmitting circuit electrically connected to the thin film capacitor; as well as A pulse generator is electrically connected to the integration and emission circuit and the bit line transistors, wherein when a potential of the film capacitor exceeds a critical value, the integration and emission circuit triggers the pulse generator to generate the feedback pulse or an output pulse.

3. The pulse neural network circuit as described in claim 2, wherein the feedback pulse is used to turn on these bit line transistors.

4. The spiking neural network circuit as claimed in claim 2, wherein the current mirror circuit comprises: a first current mirror comprising two NMOS transistors; as well as A second current mirror is connected to the first current mirror, wherein the second current mirror includes two PMOS transistors.

5. The spiking neural network circuit as claimed in claim 1, wherein each of the page buffers comprises: A level shifter is used to output a shifted data signal, wherein the shift amount of the shifted data signal is greater than the shift amount of the data signal.

6. An operation method of a spiking neural network circuit, wherein the spiking neural network circuit comprises a bit line input synaptic array and a neuron circuit, the bit line input synaptic array comprises a plurality of bit lines, a plurality of memory cells, a word line and a plurality of source lines, each of the memory cells is electrically connected to one of the bit lines, the word line is electrically connected to the memory cells, and each of the source lines is electrically connected to one of the memory cells, the operation method comprising: In a read process, a plurality of data signals are input to the bit lines; as well as In the reading process, the source lines are used to collect a plurality of currents reflecting the data signals; The bit line transistors and the bit lines form a presynaptic region, the memory cells and the word line form a synaptic region, and the source line transistors and the source lines form a postsynaptic region.

7. The operation method of claim 6, wherein in the reading process, a plurality of bit line transistors are turned on, a plurality of source line transistors are turned on, each of the bit line transistors is connected to one of the bit lines, and each of the source line transistors is connected to one of the source lines.

8. The operation method of claim 6, wherein if the neuron circuit is the winner, the operation method further comprises: In an update process, a plurality of shifted data signals are input to the bit lines, wherein the shifted data signals are generated by a level shifter and the shift amounts of the shifted data signals are greater than the shift amounts of the data signals; In an erasing step of the refresh procedure, applying a long-term gain signal to the word line long-term gain signal so that an erase pulse is formed between the word line and the bit lines; and In a programming step of the refresh procedure, a long-term inhibit signal is applied to the word line so that a programming pulse is formed between the word line and the bit lines.

9. The operating method as described in claim 8, wherein in the update procedure, if the neuron circuit is the winner, multiple bit line transistors are turned on, and multiple source line transistors are turned on, each of the bit line transistors is connected to one of the bit lines, and each of the source line transistors is connected to one of the source lines.

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