Display device and method of driving the same

Abstract

The present invention discloses a display device and a method for driving the display device. The display device includes: a first transistor including a first electrode connected to a first power line, a second electrode connected to a third node, and a gate electrode connected to the first node; a first capacitor formed between the first power line and the second node; a second capacitor formed between the first node and the second node; an emission transistor including a first electrode connected to the third node, a second electrode, and a gate electrode connected to an emission control line; and a light-emitting element connected to the second electrode of the emission transistor and the second power line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0014326 filed on February 6, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present disclosure generally relate to a display device and a method of driving the display device. Background Art

[0004] The display device includes pixels, each of which may include a light-emitting diode that emits light having a brightness corresponding to a driving current and a driving transistor that controls the driving current in response to a data voltage. Since the threshold voltage of the driving transistor varies, the display device writes the data voltage to the pixel during a data write period while compensating the data voltage with the threshold voltage of the driving transistor.

[0005] The resolution and driving frequency (or image reproduction factor) of display devices may increase. Therefore, the width of the data writing period may become narrower, and the data voltage may not be properly compensated during the data writing period. Therefore, corresponding to the increase in the resolution and driving frequency of display devices, there has been research on various technologies and pixel structures for compensating the data voltage. Summary of the Invention

[0006] Exemplary embodiments provide a display device capable of sufficiently compensating for a data voltage by considering a threshold voltage of a driving transistor and a method of driving the display device.

[0007] According to aspects of the present disclosure, a display device includes a first power line, a second power line, a reference power line, an initialization power line, a data line configured to transmit a data signal, a first scan line configured to transmit a scan signal, a first gate line and a second gate line configured to sequentially transmit a gate signal, an emission control line configured to transmit an emission control signal, and a pixel. The pixel includes a first transistor, the first transistor including a first electrode connected to the first power line, a second electrode connected to a third node, and a gate electrode connected to the first node. The pixel further includes a first capacitor formed between the first power line and the second node, and a second capacitor formed between the first node and the second node. The pixel further includes a second transistor, the second transistor including a third electrode connected to the data line, a fourth electrode connected to the second node, and a gate electrode connected to the first scan line. The pixel further includes a third transistor, the third transistor including a fifth electrode connected to the first node, a sixth electrode connected to the third node, and a gate electrode connected to the first gate line. The pixel further includes a fourth transistor, the fourth transistor including a seventh electrode connected to the first node, an eighth electrode connected to the initialization power line, and a gate electrode connected to the second gate line. The pixel further includes a fifth transistor including a ninth electrode connected to the second node, a tenth electrode connected to the reference power line, and a gate electrode connected to the first gate line. The pixel further includes a sixth transistor including an eleventh electrode connected to the third node, a twelfth electrode, and a gate electrode connected to the emission control line. The pixel further includes a light-emitting element connected between the twelfth electrode of the sixth transistor and the second power line.

[0008] At least one of the second transistor, the third transistor, the fourth transistor, and the fifth transistor may be implemented as a double-gate transistor including a plurality of sub-transistors connected in series.

[0009] The display device may further include a scan driver configured to supply a gate signal having a gate-on voltage level to the second gate line in the first period and the third period, configured to supply a gate signal having a gate-on voltage level to the first gate line in the second period and the fourth period, and configured to supply a scan signal having a gate-on voltage level to the first scan line in the scan period. The first period, the second period, the third period, and the fourth period may be sequentially located in one frame.

[0010] A frame may include a non-emission period and an emission period. The first period, the second period, the third period, the fourth period, and the scan period may be included in the non-emission period and may not overlap with each other. The emission driver may provide an emission control signal having a gate-on voltage level to the emission control line during the emission period.

[0011] The width of each of the first to fourth periods may be three times or more the width of the scanning period.

[0012] A width of each of the first to fourth periods may be four times the width of the scan period.

[0013] The width of the scanning period may be one horizontal time interval.

[0014] In the second period, the first node may have a voltage corresponding to a difference between a first power voltage applied to the first power line and a threshold voltage of the first transistor. The voltage of the first node may change according to a previous data voltage of a previous frame. In the fourth period, the first node may have a voltage substantially equal to the difference between the first power voltage and the threshold voltage of the first transistor.

[0015] The bias or operating point of the first transistor in the scan period may be equal to the bias or operating point of the first transistor in the emission period.

[0016] The display device may further include a seventh transistor including a thirteenth electrode connected to the initialization power line, a fourteenth electrode connected to the anode electrode of the light emitting element, and a gate electrode connected to the second scan line. The scan driver may provide a scan signal having a gate-on voltage level to the second scan line after a scan period.

[0017] The scan signal supplied to the second scan line may have a waveform in which the scan signal supplied to the first scan line is shifted by a scan period.

[0018] The scan driver may further sequentially supply a gate signal having a gate-on voltage level to the second gate line and the first gate line between the fourth period and the scan period.

[0019] The gate signal supplied to the first gate line may have a waveform in which the gate signal supplied to the second gate line is shifted by a first period.

[0020] The gate signal supplied to the second gate line may include a plurality of pulses having a gate-on voltage level.

[0021] Each of the pulses may have the same pulse width.The gate signal supplied to the first gate line may have a waveform in which the gate signal supplied to the second gate line is shifted by a pulse width.

[0022] According to aspects of the present disclosure, a method for driving a display device may include the following operations, the display device including a first transistor, a first capacitor formed between a first power line and a second node, a second capacitor connected between the first node and the second node, an emission transistor, and a light-emitting element, wherein the first transistor includes a first electrode connected to the first power line, a second electrode connected to a third node, and a gate electrode connected to the first node, the emission transistor includes a first electrode connected to the third node and a gate electrode connected to an emission control line, and the light-emitting element is connected to the second electrode of the emission transistor and the second power line. The method may include: applying an initialization voltage to the first node for a first time during a first period; applying a reference voltage to the second node for a first time during a second period with the second electrode of the first transistor connected to the gate electrode of the first transistor; applying the initialization voltage to the first node for a second time during a third period; applying the reference voltage to the second node for a second time during a fourth period with the second electrode of the first transistor connected to the gate electrode of the first transistor; applying a data voltage to the second node during a scan period; and turning on the emission transistor during an emission period.

[0023] The first to fourth periods may be included in the non-transmission period of one frame and do not overlap with each other.

[0024] The width of each of the first to fourth periods may be three times or more the width of the scanning period.

[0025] The width of the scanning period may be one horizontal time interval.

[0026] The method may further include: applying the initialization voltage to the first node for a third time between the fourth period and the scan period; and applying the reference voltage to the second node for a third time. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0028] Figure 1 is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0029] Figure 2A The diagram is included in Figure 1 A circuit diagram of an example of a pixel in a display device shown in FIG.

[0030] Figure 2B The diagram is included in Figure 1 A circuit diagram of another example of a pixel in a display device shown in .

[0031] Figure 3A The diagram is provided to Figure 2A : is a waveform diagram of an example of a signal of a pixel shown in FIG.

[0032] Figure 3B The diagram is provided to Figure 2A : is a waveform diagram of an example of a signal of a pixel shown in FIG.

[0033] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E and Figure 4F It is an icon Figure 2A The operation of the pixel is shown in the circuit diagram.

[0034] Figure 5A The diagram is included in Figure 2A Graph of a comparative example of characteristics of the first transistor in the pixel shown in .

[0035] Figure 5B The diagram is included in Figure 2A Graph of an example of characteristics of a first transistor in a pixel shown in FIG.

[0036] Figure 6A The diagram is included in Figure 2A Graph of a comparative example of the source-gate voltage of the first transistor in the pixel shown in .

[0037] Figure 6B The diagram is included in Figure 2A Graph of an example of the source-gate voltage of the first transistor in the pixel shown in .

[0038] Figure 7 It is an icon Figure 2A Graph of the stepping efficiency of the pixels shown in .

[0039] Figure 8 The diagram is provided to Figure 2A 2 is a waveform diagram of another example of a signal of a pixel shown in FIG.

[0040] Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D is a diagram showing the driving frequency provided to Figure 2A : is a waveform diagram of an example of a signal of a pixel shown in FIG.

[0041] Figure 10 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] Exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which like reference numerals may refer to like elements throughout.

[0043] It will be understood that the terms "first," "second," "third," etc., are used herein to distinguish one element from another, and that these elements are not limited by these terms. Thus, a "first" element in an exemplary embodiment may be described as a "second" element in another exemplary embodiment.

[0044] It should be understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0045] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0046] It will be understood that when a component is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another component, it can be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or intervening components may be present. It will also be understood that when a component is referred to as being “between” two components, it can be the only component between the two components, or one or more intervening components may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0047] In this article, when a value is described as being approximately equal to another value or being substantially the same as or equal to another value, it should be understood that these values are the same, that these values are equal to each other within the measurement error, or, if not equal in measurement, that they are close enough in value to be functionally equal to each other, as will be understood by one of ordinary skill in the art. For example, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the term "approximately" as used herein includes the stated values and means within an acceptable deviation range of the particular value determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, as will be understood by one of ordinary skill in the art. In addition, it should be understood that although a parameter may be described herein as having "approximately" a particular value, according to exemplary embodiments, the parameter may be exactly that particular value or approximately that particular value within the measurement error, as will be understood by one of ordinary skill in the art.

[0048] Herein, the phrase "element A (or element B)" may indicate that elements A and B are different names that may be used to refer to the same element.

[0049] Figure 1is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0050] refer to Figure 1 , the display device 100 may include a display 110 (or display panel), a scan driver 120 (or gate driver), a data driver 130 (or source driver), a timing controller 140 and an emission driver 150 .

[0051] The display 110 may include scan lines SL1 to SLn (n is a positive integer) (or first gate lines), gate lines SSL1 to SSLn (or second gate lines), data lines DL1 to DLm (m is a positive integer), emission control lines EL1 to ELn, and pixels PXL. The pixels PXL may be arranged in a region (e.g., a pixel region) defined by the scan lines SL1 to SLn and the data lines DL1 to DLm.

[0052] The pixel PXL can be connected to at least one of the scan lines SL1 to SLn, at least one of the gate lines SSL1 to SSLn, one of the data lines DL1 to DLm, and one of the emission control lines EL1 to ELn. In exemplary embodiments of the present disclosure, the term "connection" may mean electrical connection and / or physical connection. For example, the pixel PXL arranged on the i-th pixel row and the j-th pixel column can be connected to the scan line SLi, the next scan line SLi+1, the gate line SSLi, the previous gate line SSLi-k, the data line DLj, and the emission control line ELi (j is a positive integer, k is an integer of 3 or greater, and i is an integer greater than k).

[0053] The pixel PXL may perform an initialization operation of performing initialization in response to a gate signal provided through a previous gate line SSLi-k (or a previous gate signal provided at a previous time), and may perform sampling or compensation of an internal transistor (e.g., a reference transistor) in response to a gate signal provided through the gate line SSLi (or a gate signal provided at a current time). Figure 2A In some exemplary embodiments, the pixel PXL may repeat the initialization operation and the compensation operation two or more times. In addition, the pixel PXL may store or record the data signal provided through the data line DLj in response to the scan signal provided through the scan line SLi (or the scan signal provided at the current time), and initialize the anode electrode of the light-emitting element in the pixel PXL in response to the next scan signal provided through the next scan line SLi+1. In addition, the pixel PXL may emit light corresponding to the stored data signal in response to the emission control signal provided through the emission control line ELi. This will be referred to later. Figure 2A and Figure 3A The detailed configuration and operation of the pixel PXL are described.

[0054] A first power voltage VDD, a second power voltage VSS, a reference voltage VREF, and an initialization voltage VINIT may be provided to the display 110. The first power voltage VDD, the second power voltage VSS, the reference voltage VREF, and the initialization voltage VINIT are voltages for operating the pixel PXL and may be provided to the display 110 from a separate power supply. The first power voltage VDD may have a voltage level higher than that of the second power voltage VSS. The reference voltage VREF may be a DC voltage having a voltage level equal to that of the first power voltage VDD or having a specific voltage level. The initialization voltage VINIT may have a voltage level lower than that of the data voltage.

[0055] The scan driver 120 may generate a gate signal and a scan signal based on the scan control signal, sequentially supply the gate signal to the gate lines SSL1 to SSLn, and sequentially supply the scan signal to the scan lines SL1 to SLn.

[0056] In some exemplary embodiments, the scan driver 120 may include a first scan driver 121 (or a first gate driver) and a second scan driver 122 (or a second gate driver).

[0057] The first scan driver 121 may generate a gate signal based on a first scan control signal SCS1 (or a first gate control signal) and sequentially provide the gate signal to the gate lines SSL1 to SSLn. The first scan control signal SCS1 may include a first scan start signal (or a first gate start signal), a first scan clock signal (or a first gate clock signal), etc., and may be provided from the timing controller 140. For example, the first scan driver 121 may include a shift register (or a stage) that sequentially generates and outputs a pulse-type gate signal corresponding to the pulse-type first scan start signal using the first scan clock signal.

[0058] Similar to the first scan driver 121, the second scan driver 122 can generate a scan signal based on the second scan control signal SCS2 (or the second gate control signal) and sequentially provide the scan signal to the scan lines SL1 to SLn. The second scan control signal SCS2 may include a second scan start signal (or a second gate start signal), a second scan clock signal (or a second gate clock signal), etc., and is provided from the timing controller 140. For example, the second scan driver 122 may include a shift register that sequentially generates and outputs a pulse-shaped gate signal corresponding to the pulse-shaped second scan start signal using the second scan clock signal.

[0059] The data driver 130 may generate a data signal based on the image data DATA2 and the data control signal DCS provided from the timing controller 140, and provide the data signal to the display 110 (e.g., the pixel PXL of the display 110). The data control signal DCS is a signal for controlling the operation of the data driver 130 and may include a load signal (or a data enable signal) instructing the output of a valid data signal, a vertical synchronization signal, a horizontal synchronization signal, etc.

[0060] The timing controller 140 may receive input image data DATA1 and a control signal CS from a source external to the display device 100 (e.g., from a graphics processor), generate a scan control signal (or a first scan control signal SCS1 and a second scan control signal SCS2) and a data control signal DCS, and generate image data DATA2 by converting the input image data DATA1. For example, the timing controller 140 may convert the input image data DATA1 in RGB format into image data DATA2 in RGBG format (which corresponds to the pixel arrangement in the display 110).

[0061] The emission driver 150 may generate an emission control signal based on the emission drive control signal ECS and sequentially provide the emission control signal to the emission control lines EL1 to ELn. The emission drive control signal ECS may include an emission start signal, an emission clock signal, etc., and is provided from the timing controller 140. For example, the emission driver 150 may include a shift register that sequentially generates and outputs a pulse-form emission control signal corresponding to the pulse-form emission start signal using the emission clock signal.

[0062] At least one of the scan driver 120, the data driver 130, the timing controller 140, and the emission driver 150 may be formed in the display 110, or may be implemented as an integrated circuit (IC) to be connected to the display 110 through a flexible circuit board. In addition, at least two of the scan driver 120, the data driver 130, the timing controller 140, and the emission driver 150 may be implemented as ICs.

[0063] Figure 2A The diagram is included in Figure 1 A circuit diagram of an example of a pixel in a display device shown in FIG. Figure 2B The diagram is included in Figure 1 A circuit diagram of another example of a pixel in a display device shown in FIG. Figure 2A and Figure 2B , a pixel PXL located on an i-th pixel row and a j-th pixel column is illustrated as an example.

[0064] First, refer to Figure 2AThe pixel PXL may include a light emitting element LD and a pixel circuit (or a pixel driving circuit) for controlling the amount of current flowing through the light emitting element LD.

[0065] The light-emitting element LD is connected between a first power voltage VDD (or a first power source) and a second power voltage VSS (or a second power source). For example, the anode electrode of the light-emitting element LD is connected to a first power line PL1 (e.g., a first power line PL1 to which the first power voltage VDD is applied) via a pixel circuit, and the cathode electrode of the light-emitting element LD can be connected to a second power line PL2 (e.g., a second power line PL2 to which the second power voltage VSS is applied). The light-emitting element LD can emit light having a brightness corresponding to the drive current supplied from the pixel circuit.

[0066] The first power voltage VDD and the second power voltage VSS have a potential difference that allows the light-emitting element LD to emit light. For example, the first power voltage VDD may be a high-potential pixel power source, and the second power voltage VSS may be a low-potential pixel power source having a potential lower than that of the first power voltage VDD by a threshold voltage of the light-emitting element LD.

[0067] The light emitting element LD may be an organic light emitting diode (OLED) including an organic light emitting layer, but the present disclosure is not limited thereto. For example, the light emitting element LD may include a micro inorganic light emitting diode as small as nanometer to micrometer scale.

[0068] The pixel circuit may include at least one transistor and at least one capacitor. For example, the pixel circuit may include a first transistor T1 (or a driving transistor), a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 (or an emission transistor), a seventh transistor T7 (or an initialization transistor), a first capacitor C1 (or a storage capacitor), and a second capacitor C2. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be implemented with a P-type transistor (e.g., a P-type MOSFET). However, the present disclosure is not limited thereto, and at least one transistor may be implemented with an N-type transistor.

[0069] The first transistor T1 may include a first electrode connected to the first power line PL1, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. A first power voltage VDD may be applied to the first power line PL1. The first transistor T1 may control the amount of drive current flowing through the light emitting element LD in response to a source-gate voltage (e.g., a voltage between the first electrode and the gate electrode).

[0070] The first capacitor C1 may be connected or formed between the first power line PL1 and the second node N2. The first capacitor C1 may store the voltage of the second node N2 and stabilize the voltage of the second node N2. The second capacitor C2 may be connected between the first node N1 and the second node N2. The second capacitor C2 may store the voltage supplied to the first node N1 and the second node N2.

[0071] The second transistor T2 may include a first electrode connected to the data line DLj, a second electrode connected to the second node N2, and a gate electrode connected to the scan line SLi. The scan line SLi may also be referred to as the first scan line SLi. The second transistor T2 may be turned on in response to a scan signal GW provided through the scan line SLi and having a gate-on voltage level (e.g., a gate-on voltage level that may be a logic low level), and provide a data voltage DATA (e.g., a data voltage or data signal applied to the data line DLj) to the second node N2. Since the first transistor T1 is a P-type transistor, the voltage level of the data voltage DATA may become lower as the grayscale to be represented becomes higher.

[0072] The third transistor T3 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode connected to the gate line SSLi. The gate line SSLi may be referred to as the first gate line SSLi. The third transistor T3 may be turned on in response to the compensation control signal GC having a gate-on voltage level (or a gate signal provided through the gate line SSLi) and connect the first node N1 and the third node N3. That is, the first transistor T1 may be turned on in a diode-connected manner through the third transistor T3. A voltage corresponding to the difference between the first power voltage VDD and the threshold voltage of the first transistor T1 may be sampled at the first node N1.

[0073] The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the fourth power line PL4 (or initialization power line), and a gate electrode connected to the previous gate line SSLi-k. The previous gate line SSLi-k may also be referred to as the second gate line SSLi-k. An initialization voltage VINIT may be applied to the fourth power line PL4. The fourth transistor T4 may be turned on in response to a first initialization control signal GI having a gate-on voltage level (or a previous gate signal provided by the previous gate line SSLi-k) and provide the initialization voltage VINIT to the first node N1. The initialization voltage VINIT may be set to be lower than the data voltage DATA. For example, the initialization voltage VINIT may be set to be lower than the lowest voltage of the data voltage DATA. That is, the fourth transistor T4 may initialize the first node N1 to the initialization voltage VINIT.

[0074] The fifth transistor T5 may include a first electrode connected to the second node N2, a second electrode connected to the third power line PL3 (or a reference power line), and a gate electrode connected to the gate line SSLi. A reference voltage VREF may be applied to the third power line PL3. The fifth transistor T5 may be turned on in response to a compensation control signal GC having a gate-on voltage level (or a gate signal provided via the gate line SSLi) and provide the reference voltage VREF to the second node N2. The reference voltage VREF may be equal to the first power voltage VDD or may be a DC voltage having a specific voltage level. That is, the fifth transistor T5 may initialize the second node N2 to the reference voltage VREF.

[0075] The sixth transistor T6 may include a first electrode connected to the third node N3, a second electrode connected to the anode electrode of the light-emitting element LD, and a gate electrode connected to the emission control line ELi. The sixth transistor T6 may be turned on in response to an emission control signal EM having a gate-on voltage level (e.g., an emission control signal EM provided via the emission control line ELi), and form a current path between the third node N3 and the light-emitting element LD. That is, when the sixth transistor T6 is turned on, a drive current may be provided to the light-emitting element LD, and the light-emitting element LD may emit light having a brightness corresponding to the drive current. Conversely, when the sixth transistor T6 is turned off, the current path of the drive current may be interrupted, and the light-emitting element LD may not emit light.

[0076] The seventh transistor T7 may include a first electrode connected to the fourth power line PL4, a second electrode connected to the anode electrode of the light emitting element LD, and a gate electrode connected to the next scan line SLi+1. The seventh transistor T7 may be turned on in response to a second initialization control signal GB having a gate-on voltage level (e.g., a bypass control signal or a next scan signal provided by the next scan line SLi+1), and provide an initialization voltage VINIT (e.g., an initialization voltage VINIT applied to the fourth power line PL4) to the anode electrode of the light emitting element LD. The charge charged in the parasitic capacitor formed in the light emitting element LD (e.g., a parasitic capacitor generated due to the structure of the light emitting element LD) may be initialized by the initialization voltage VINIT. Although in Figure 2A, the gate electrode of the seventh transistor T7 is connected to the next scan line SLi+1, but the present disclosure is not limited thereto. For example, the gate electrode of the seventh transistor T7 may be connected to a control line formed separately from the next scan line SLi+1, and the second initialization control signal GB may be applied to the control line. When the seventh transistor T7 transmits the initialization voltage VINIT to the anode electrode of the light-emitting element LD before the emission period in which the light-emitting element LD emits light, the pixel PXL may exhibit more uniform luminance characteristics relative to the data voltage DATA.

[0077] In an exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed as transistors having similar structures and similar sizes. In an exemplary embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed as a transistor having a structure and size different from those of the other transistors.

[0078] In an exemplary embodiment, at least one of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be implemented as a dual-gate transistor (or a transistor including a plurality of sub-transistors connected in series). Figure 2B As shown in , in an exemplary embodiment, each of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be implemented as a dual-gate transistor and include two sub-transistors connected in series. In a state where each of the third transistor T3 and the fourth transistor T4 is turned off, the leakage current flowing through the third transistor T3 and the fourth transistor T4 can be reduced. In addition, the leakage current flowing through the second transistor T2 and the fifth transistor T5 can be reduced, and the voltage fluctuation of each of the second node N2 and the first node N1 (for example, the first node N1 capacitively coupled to the second node N2) can be reduced. Reference Figure 2B , for ease of explanation, the previous reference is omitted Figure 2A Further description of the elements and techniques described.

[0079] Figure 3A The diagram is provided to Figure 2A : is a waveform diagram of an example of a signal of a pixel shown in FIG. Figure 3B The diagram is provided to Figure 2A : is a waveform diagram of an example of a signal of a pixel shown in FIG. Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E and Figure 4F It is an icon Figure 2A The operation of the pixel is shown in the circuit diagram. For example, Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E and Figure 4F The picture shows Figure 2A The pixels shown in Figure 3A The sequential operation of the signals shown in .

[0080] First, refer to Figure 2A and Figure 3A ,exist Figure 3A , an emission control signal EM, a first initialization control signal GI, a compensation control signal GC, a scan signal GW, and a second initialization control signal GB are illustrated in FIG. Herein, a signal applied to a gate line including, for example, the first initialization control signal GI and the compensation control signal GC may be referred to as a gate signal, and a signal applied to a scan line including, for example, the scan signal GW and the second initialization control signal GB may be referred to as a scan signal. As shown in FIG. Figure 2A As described, the emission control signal EM can be provided through the emission control line ELi, the first initialization control signal GI can be provided through the previous gate line SSLi-k, the compensation control signal GC can be provided through the gate line SSLi, the scan signal GW can be provided through the scan line SLi, and the second initialization control signal GB can be provided through the next scan line SLi+1 or a separate control line.

[0081] The period during which the emission control signal EM has a gate-off voltage level (e.g., a logic-high-level cut-off voltage level) (e.g., a non-emission period of the pixel PXL) may include a first period P1, a second period P2, a third period P3, a fourth period P4, a fifth period P5 (or a scanning period), and a sixth period P6. The first period P1, the second period P2, the third period P3, the fourth period P4, the fifth period P5, and the sixth period P6 do not overlap with each other in the non-emission period. In addition, the period during which the emission control signal EM has a gate-on voltage level (e.g., a logic-low-level turn-on voltage level) (e.g., an emission period of the pixel PXL) may include a seventh period P7. The first period P1, the second period P2, the third period P3, the fourth period P4, the fifth period P5, the sixth period P6, and the seventh period P7 may be included in one frame (or one frame cycle).

[0082] During the first period P1, the first initialization control signal GI may have a gate-on voltage level. That is, the first initialization control signal GI may have a first pulse PLS1 of the gate-on voltage level in the first period P1. Herein, the gate-on voltage level may correspond to a logic low level, and the gate-off voltage level may correspond to a logic high level. However, the present disclosure is not limited thereto. The pulse width of the first pulse PLS1 is greater than three horizontal time intervals (e.g., 3×1 horizontal time intervals (1H)). For example, the pulse width of the first pulse PLS1 (and the width of the first period P1) may be four horizontal time intervals. One horizontal time interval is the amount of time allocated to apply a data voltage to one pixel row. For example, when the display device 100 (see Figure 1 ) when reproducing an image at a frequency of 240 Hz, one horizontal time interval may be about 1.84 μs or less. The previous gate line SSLi-k to which the first initialization control signal GI is applied may be a gate line three lines (or three pixel rows) before the gate line SSLi (for example, k=3). In another example, as Figure 3B As shown in , the pulse width of the first pulse PLS1' (and the width of the first period P1') can be three horizontal time intervals. The previous gate line SSLi-k to which the first initialization control signal GI is applied can be a gate line (for example, k=4) four lines (or four pixel rows) before the gate line SSLi.

[0083] Each of the compensation control signal GC, the scan signal GW, and the second initialization control signal GB may have a gate-off voltage level.

[0084] refer to Figure 4A , the fourth transistor T4 may be turned on in response to the first initialization control signal GI (or the first pulse PLS1) having a gate-on voltage level, and the initialization voltage VINIT may be supplied to the first node N1 for the first time. That is, the first node N1 may be initialized to the initialization voltage VINIT, and the voltage Vg (or the voltage of the gate electrode of the first transistor T1) may become equal to the initialization voltage VINIT.

[0085] Herein, when a voltage is described as being supplied (or applied) to a node for the first time, supplied (or applied) to the node for the second time, supplied (or applied) to the node for the third time, etc., the voltage may be supplied (or applied) to the node at different times. For example, the voltage may be supplied (or applied) to the node for the first time at a first time point, the voltage may be supplied (or applied) to the node for the second time at a second time point after the first time point, the voltage may be supplied (or applied) to the node for the third time at a third time point after the second time point, and so on.

[0086] Since the first electrode (or source electrode) of the first transistor T1 is connected to the first power line PL1 , the voltage Vs of the source electrode of the first transistor T1 may be equal to the first power voltage VDD.

[0087] Meanwhile, the voltage Va of the second node N2 may have a previous data voltage (eg, a data voltage of a previous frame) due to the first capacitor C1.

[0088] That is, the first node N1 (or the gate electrode of the first transistor T1 ) may be initialized by the initialization voltage VINIT in the first period P1 .

[0089] Return Reference Figure 3A , during the second period P2, the compensation control signal GC may have a gate-on voltage level. That is, the compensation control signal GC may have a second pulse PLS2 of the gate-on voltage level in the second period P2. The compensation control signal GC may have a waveform in which the first initialization control signal GI is shifted by the first period P1 (for example, four or three horizontal time intervals). Therefore, like the pulse width of the first pulse PLS1, the pulse width of the second pulse PLS2 is greater than three horizontal time intervals. For example, the pulse width of the second pulse PLS2 (and the width of the second period P2) may be four horizontal time intervals. In another example, as Figure 3B As shown in FIG, the pulse width of the second pulse PLS2′ (and the width of the second period P2′) may be three horizontal time intervals.

[0090] Meanwhile, each of the first initialization control signal GI, the scan signal GW, and the second initialization control signal GB may have a gate-off voltage level.

[0091] refer to Figure 4B , the fifth transistor T5 may be turned on in response to the compensation control signal GC (or the second pulse PLS2) having the gate-on voltage level, and the reference voltage VREF may be supplied to the second node N2 for the first time. That is, the second node N2 may be initialized to the reference voltage VREF, and the voltage Va of the second node N2 may be changed to be equal to the reference voltage VREF.

[0092] In addition, the third transistor T3 can be turned on in response to the compensation control signal GC (or the second pulse PLS2) having a gate-on voltage level, and the gate electrode and the drain electrode (or the second electrode) of the first transistor T1 can be connected to each other. That is, the first transistor T1 can be diode-connected. A voltage corresponding to the difference (or voltage difference) between the first power voltage VDD and the threshold voltage of the first transistor T1 can be sampled at the first node N1. The voltage Vg of the first node N1 is similar to the voltage corresponding to the difference between the first power voltage VDD and the threshold voltage of the first transistor T1, but can be different from the difference between the first power voltage VDD and the threshold voltage of the first transistor T1. For example, the voltage Vg of the first node N1 (for example, in the second period P2) can be expressed as "VDD-Vth+α". Vth can be the threshold voltage of the first transistor T1, and α can be a component of the previous data voltage of the previous frame due to capacitor coupling of the second capacitor C2.

[0093] Since the voltage Va of the second node N2 changes from the previous data voltage to the reference voltage VREF, the change in the voltage Va of the second node N2 can be transmitted to the first node N1 through capacitor coupling of the second capacitor C2. Therefore, unlike the ideal sampling voltage (e.g., "VDD-Vth"), the voltage Vg of the first node N1 can further include a component of the previous data voltage (e.g., the change in the voltage Va of the second node N2).

[0094] When the compensation control signal GC has three or more horizontal time intervals (eg, about 3.2 μs or greater), the threshold voltage of the first transistor T1 is more accurately sampled. Therefore, the threshold voltage of the first transistor T1 can be accurately reflected to the data voltage DATA.

[0095] Return Reference Figure 3A , during the third period P3, the first initialization control signal GI may have a gate-on voltage level. That is, the first initialization control signal GI may have a third pulse PLS3 in the third period P3, and the third pulse PLS3 has a gate-on voltage level. The pulse width of the third pulse PLS3 (or the width of the third period P3) may be equal to the pulse width of the first pulse PLS1 (or the width of the first period P1). For example, the pulse width of the third pulse PLS3 (and the width of the third period P3) may be four horizontal time intervals. In another example, as Figure 3B As shown in FIG, the pulse width of the third pulse PLS3' (and the width of the third period P3') may be three horizontal time intervals.

[0096] Each of the compensation control signal GC, the scan signal GW, and the second initialization control signal GB may have a gate-off voltage level.

[0097] refer to Figure 4C , and reference Figure 4A The operation of the pixel PXL described above is similar, the fourth transistor T4 can be turned on in response to the first initialization control signal GI (or the third pulse PLS3) having a gate-on voltage level, and the initialization voltage VINIT can be supplied to the first node N1 for the second time. That is, the first node N1 (or the gate electrode of the first transistor T1) can be initialized by the initialization voltage VINIT in the third period P3.

[0098] Meanwhile, since the reference voltage VREF is applied in the second period P2 , the voltage Va of the second node N2 may be maintained equal to the reference voltage VREF.

[0099] Return Reference Figure 3A , during the fourth period P4, the compensation control signal GC may have a gate-on voltage level. That is, the compensation control signal GC may have a fourth pulse PLS4 in the fourth period P4, and the fourth pulse PLS4 has a gate-on voltage level. The pulse width of the fourth pulse PLS4 (or the width of the fourth period P4) may be equal to the pulse width of the second pulse PLS2 (or the width of the second period P2). For example, the pulse width of the fourth pulse PLS4 (and the width of the fourth period P4) may be four horizontal time intervals. In another example, as Figure 3B As shown in FIG, the pulse width of the fourth pulse PLS4' (and the width of the fourth period P4') may be three horizontal time intervals.

[0100] Each of the first initialization control signal GI, the scan signal GW, and the second initialization control signal GB may have a gate-off voltage level.

[0101] refer to Figure 4D , and reference Figure 4B The operation of the pixel PXL described above is similar. The fifth transistor T5 can be turned on in response to the compensation control signal GC (or the fourth pulse PLS4) having a gate-on voltage level, and the reference voltage VREF can be supplied to the second node N2 for the second time. In addition, the third transistor T3 can be turned on in response to the compensation control signal GC (or the fourth pulse PLS4) having a gate-on voltage level, and the gate electrode and the drain electrode (or the second electrode) of the first transistor T1 can be connected to each other. That is, the first transistor T1 can be diode-connected.

[0102] A voltage corresponding to the difference (or voltage difference) between the first power voltage VDD and the threshold voltage of the first transistor T1 may be sampled at the first node N1. For example, in the fourth period P4, the voltage Vg of the first node N1 may be substantially equal to the difference between the first power voltage VDD and the threshold voltage of the first transistor T1.

[0103] Since the voltage Va of the second node N2 is in a state where the voltage Va of the second node N2 is maintained as the reference voltage VREF, the component of the previous data voltage can be removed from the voltage Vg of the first node N1. Therefore, the voltage Vg of the first node N1 can be normally compensated.

[0104] Return Reference Figure 3A During the fifth period P5, the scanning signal GW may have a gate-on voltage level. That is, the scanning signal GW may have a pulse of the gate-on voltage level in the fifth period P5. The width of the pulse of the scanning signal GW (or the width of the fifth period P5) may be one horizontal time interval. Since the width of the pulse of the scanning signal GW is one horizontal time interval, the display device 100 (see Figure 1 ) can have higher resolution or operate at higher driving frequency without any structural changes (e.g., without adding any data lines).

[0105] Each of the first initialization control signal GI, the compensation control signal GC, and the second initialization control signal GB may have a gate-off voltage level.

[0106] refer to Figure 4E The second transistor T2 may be turned on in response to the scan signal GW having the gate-on voltage level, and the data voltage DATA may be supplied to the second node N2. The voltage Va of the second node N2 may be changed to the data voltage DATA.

[0107] Since the first node N1 is connected to the second node N2 through the second capacitor C2, the change in the voltage Va of the second node N2 (e.g., "DATA-VREF") can be reflected to the first node N1. Therefore, the voltage Vg of the first node N1 can be changed to "VDD-Vth+(DATA-VREF)".

[0108] The data voltage DATA is written to the pixel PXL in the fifth period P5 allocated separately just before the emission period, so that the transient afterimage can be minimized or reduced. The transient afterimage may be a phenomenon that when pixels (or different display areas including these pixels) are driven with different grayscales in the previous frame, even if these pixels are driven with the same grayscale in the next frame, these pixels emit light with different brightness during a specific time. This will be referred to later. Figure 5A and Figure 5B Describe this instantaneous afterimage.

[0109] Therefore, as in Figure 2A and Figure 3AAs seen in FIG. 1 , in an exemplary embodiment, the scan driver 120 may supply a gate signal (e.g., the first initialization control signal GI) having a gate-on voltage level to the second gate line SSLi-k in the first period P1 and the third period P3, may supply a gate signal (e.g., the compensation control signal GC) having a gate-on voltage level to the first gate line SSLi in the second period P2 and the fourth period P4, and may supply a scan signal GW having a gate-on voltage level to the first scan line SLi in the fifth period P5 (e.g., in the scan period). The first period P1, the second period P2, the third period P3, and the fourth period P4 are sequentially located in one frame.

[0110] Return Reference Figure 3A During the sixth period P6, the second initialization control signal GB may have a gate-on voltage level. That is, the second initialization control signal GB may have a pulse having a gate-on voltage level during the sixth period P6. The second initialization control signal GB may have a waveform in which the scan signal GW is shifted by the fifth period P5 (for example, one horizontal time interval). Therefore, like the width of the pulse of the scan signal GW (or the width of the fifth period P5), the width of the pulse of the second initialization control signal GB (or the width of the sixth period P6) may be one horizontal time interval.

[0111] Each of the first initialization control signal GI, the compensation control signal GC, and the scan signal GW may have a gate-off voltage level.

[0112] refer to Figure 4F The seventh transistor T7 may be turned on in response to the second initialization control signal GB having a gate-on voltage level, and the initialization voltage VINIT may be supplied to the anode electrode of the light emitting element LD. Charge charged in a parasitic capacitor formed in the light emitting element LD (e.g., a parasitic capacitor generated due to the structure of the light emitting element LD) may be initialized by the initialization voltage VINIT, and the pixel PXL may exhibit more uniform luminance characteristics.

[0113] Return Reference Figure 3A , during the seventh period P7, the emission control signal EM may have a gate-on voltage level, and each of the first initialization control signal GI, the compensation control signal GC, the scan signal GW, and the second initialization control signal GB may have a gate-off voltage level.

[0114] The sixth transistor T6 may be turned on in response to the emission control signal EM and form a current path between the third node N3 and the light emitting element LD. A driving current may be supplied to the light emitting element LD, and the light emitting element LD may emit light having brightness corresponding to the driving current.

[0115] As reference Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E and Figure 4F As described, in one frame (or one continuous non-emission period), each of the first initialization control signal GI and the compensation control signal GC may include two pulses having a gate-on voltage level, and the width of each of the pulses may be three horizontal time intervals. Therefore, since the width of the pulse of the compensation control signal GC is set to about 3.2 μs or more, the threshold voltage of the first transistor T1 can be accurately sampled.

[0116] In addition, the first node N1 (or the gate electrode of the first transistor T1) and the second node N2 can be sequentially initialized twice by two pulses of each of the first initialization control signal GI and the compensation control signal GC. Therefore, the component (or influence) of the previous data voltage is removed from the voltage Vg of the first node N1, and the threshold voltage of the first transistor T1 can be more accurately compensated by the voltage Vg of the first node N1 (or the voltage of the gate electrode of the first transistor T1).

[0117] In addition, since the width of the pulse of the scanning signal GW (eg, a pulse having a gate-on voltage level) is one horizontal time interval (eg, since the width of the pulse of the scanning signal GW is the same as that of the gate-on voltage level), Figure 3A ) or three horizontal time intervals (see Figure 3B )'s pulse width of the compensation control signal GC is set differently), so that the instantaneous afterimage can be minimized or reduced.

[0118] Despite Figure 3A and Figure 3B , each of the first initialization control signal GI and the compensation control signal GC includes two pulses having a gate-on voltage level, but the first initialization control signal GI and the compensation control signal GC are not limited thereto. For example, each of the first initialization control signal GI and the compensation control signal GC may include three pulses having a gate-on voltage level.

[0119] like Figure 3A and Figure 3B As shown in , according to an exemplary embodiment, the width of each of the first to fourth periods P1 to P4 may be three times or more the width of the fifth period P5 (e.g., the scanning period), and the width of the fifth period P5 (e.g., the scanning period) may be one horizontal time interval 1H.

[0120] Figure 5A The diagram is included in Figure 2A Graph of a comparative example of characteristics of the first transistor in the pixel shown in . Figure 5B The diagram is included in Figure 2A Graph of an example of characteristics of a first transistor in a pixel shown in FIG.

[0121] refer to Figure 2A and Figure 5A , the first black curve C_B1 represents the voltage-current characteristics of the first transistor T1 (e.g., the relationship between the gate-source voltage Vgs applied between the gate electrode and the source electrode of the first transistor T1 and the driving current Ids) when a voltage (e.g., Black Vgs) corresponding to the minimum grayscale (e.g., black grayscale) is applied to the gate electrode of the first transistor T1 (and when the pixel PXL does not emit light in the emission period).

[0122] The second black curve C_B2 represents the Figure 3A The voltage-current characteristics of the first transistor T1 changed from the first black curve C_B1 by the initialization operation and the compensation operation repeated in the first period P1, the second period P2, the third period P3, and the fourth period P4 are described.

[0123] The reference curve C0 represents the voltage-current characteristic of the first transistor T1 when a voltage (e.g., Gray Vgs) corresponding to a reference grayscale (e.g., grayscale 48 among grayscales in the range of 0 to 255) is applied to the gate electrode of the first transistor T1 (and when the pixel PXL emits light in the emission period).

[0124] The first white curve C_W1 represents voltage-current characteristics of the first transistor T1 when a voltage (eg, White Vgs) corresponding to a maximum grayscale (eg, white grayscale) is applied to the gate electrode of the first transistor T1 (and when the pixel PXL emits light in an emission period).

[0125] The second white curve C_W2 represents the Figure 3A The voltage-current characteristic of the first transistor T1 is changed from the first white curve C_W1 by the repeated initialization operation and compensation operation in the first period P1, the second period P2, the third period P3, and the fourth period P4. That is, the second white curve C_W2 represents the voltage-current characteristic of the first transistor T1 when the on bias in the first period P1 and the third period P3 and the off bias in the second period P2 and the fourth period P4 are repeated.

[0126] According to a comparative example, the data voltage DATA may be written to the pixel PXL while the compensation operation of the pixel PXL is being performed. For example, the data voltage DATA may be written to the pixel PXL at the same time as the compensation operation of the pixel PXL is being performed. Figure 3A The pixel PXL is written in the second period P2 or the fourth period P4 described above.

[0127] After the pixel PXL emits or does not emit light corresponding to a low grayscale (e.g., a grayscale lower than grayscale 48 or black grayscale 0) for a specific time, the pixel PXL may emit light corresponding to a reference grayscale (e.g., grayscale 48). The driving current Ids of the first transistor T1 flowing through the pixel PXL may be changed from a value corresponding to a point on the first black curve C_B1 to a value corresponding to a point on the reference curve C0. That is, when the grayscale value of the pixel PXL is maintained at a low grayscale for a specific time and then changed to a high grayscale, the driving current Ids of the first transistor T1 may be changed to a target current after the specific time.

[0128] In response to the change in the driving current Ids, the luminance LUMINANCE of the pixel PXL may be changed from a luminance higher than the target luminance Target Gray to the target luminance Target Gray over a certain time. That is, a certain time may be required before the luminance LUMINANCE of the pixel PXL equals the target luminance Target Gray.

[0129] Similarly, after the pixel PXL emits light corresponding to a high grayscale (e.g., a grayscale higher than grayscale 48 or white grayscale 255) for a specific time, the pixel PXL may emit light corresponding to a reference grayscale (e.g., grayscale 48). The drive current Ids flowing through the first transistor T1 of the pixel PXL may be changed from a value corresponding to a point on the first white curve C_W1 to a value corresponding to a point on the reference curve C0. That is, when the grayscale value of the pixel PXL is maintained at a high grayscale for a specific time and then changed to a low grayscale, the drive current Ids of the first transistor T1 may be changed to a target current throughout the specific time.

[0130] In response to the change in the driving current Ids, the luminance LUMINANCE may be changed from a luminance lower than the target luminance Target Gray to the target luminance Target Gray within a certain time. That is, a certain time may be required before the luminance LUMINANCE of the pixel PXL is equal to the target luminance Target Gray.

[0131] That is, due to the hysteresis characteristics of the first transistor T1, a change (ΔVth) in the threshold voltage of the first transistor T1 may occur, and a brightness difference between adjacent pixels may occur. For example, since the brightness of a first pixel including the first transistor T1 having the voltage-current characteristic according to the second black curve C_B2 and the brightness of a second pixel including the first transistor T1 having the voltage-current characteristic according to the second white curve C_W2 are different from each other (for example, due to the brightness difference DIFF or the current difference), a momentary afterimage may occur and image quality may be degraded.

[0132] The amount of time required before the instantaneous contrast ratio (or Michelson contrast ratio) becomes less than a reference ratio (or reference value, for example, 0.4%) can be defined as a instantaneous afterimage index (or instantaneous afterimage time) representing the size of the instantaneous afterimage. The instantaneous contrast ratio can be defined as the ratio of the difference between the first brightness (or first current) according to the first brightness curve C_L1 and the second brightness (or second current) according to the second brightness curve C_L2 relative to the sum of the first brightness and the second brightness (for example, "(L1-L2) / (L1+L2)"), (L1 is the first brightness and L2 is the second brightness). The instantaneous afterimage index according to the comparative example can be expressed as approximately 5 seconds to approximately 8 seconds. Therefore, the instantaneous afterimage can be viewed by the user.

[0133] refer to Figure 2A 、 Figure 3A and Figure 5B , in the display device 100 (see Figure 1 ), the data voltage DATA may be written to the pixel PXL in a fifth period P5 (eg, a period different from the first period P1, the second period P2, the third period P3, and the fourth period P4).

[0134] The third black curve C_B3 represents the Figure 3A The voltage-current characteristic of the first transistor T1 is changed from the second black curve C_B2 due to the data writing operation in the fifth period P5 .

[0135] When a voltage (eg, Gray Vgs) corresponding to a reference grayscale (eg, grayscale 48 among grayscales ranging from 0 to 255) is applied to the gate electrode of the first transistor T1, the voltage-current characteristic of the first transistor T1 may be changed to be closer to the reference curve C0.

[0136] The driving current Ids flowing through the first transistor T1 of the pixel PXL may be changed from a value corresponding to a point on the third black curve C_B3 to a value corresponding to a point on the reference curve C0. The difference between the driving current Ids according to the third black curve C_B3 and the driving current Ids according to the reference curve C0 may be smaller than the difference between the driving current Ids according to the second black curve C_B2 and the driving current Ids according to the reference curve C0.

[0137] The third white curve C_W3 represents the Figure 3A The voltage-current characteristic of the first transistor T1 is changed from the second white curve C_W2 due to the data writing operation in the fifth period P5 described.

[0138] When a voltage (eg, Gray Vgs) corresponding to a reference grayscale (eg, grayscale 48 among grayscales ranging from 0 to 255) is applied to the gate electrode of the first transistor T1, the voltage-current characteristic of the first transistor T1 may be changed to be closer to the reference curve C0.

[0139] The driving current Ids flowing through the first transistor T1 of the pixel PXL may be changed from a value corresponding to a point on the third white curve C_W3 to a value corresponding to a point on the reference curve C0. The difference between the driving current Ids according to the third white curve C_W3 and the driving current Ids according to the reference curve C0 may be smaller than the difference between the driving current Ids according to the second white curve C_W2 and the driving current Ids according to the reference curve C0.

[0140] The luminance difference DIFF between the luminance of the first pixel including the first transistor T1 having the voltage-current characteristic according to the third black curve C_B3 and the luminance of the second pixel including the first transistor T1 having the voltage-current characteristic according to the third white curve C_W3 may become relatively small (eg, Figure 5A The first brightness curve C_L1 and the second brightness curve C_L2 are Figure 5B The first luminance curve C_L1′ and the second luminance curve C_L2′ are compared, respectively, and the instantaneous afterimage index can be reduced corresponding to the luminance difference DIFF. For example, the instantaneous afterimage index can be approximately 0.2s or less, or approximately 0.1s or less. Therefore, in an exemplary embodiment, the luminance difference DIFF is not observed by the user.

[0141] As reference Figure 3A 、 Figure 5A and Figure 5BAs described, unlike the initialization period and the compensation period (e.g., the first period P1, the second period P2, the third period P3, and the fourth period P4), the data voltage DATA is written to the pixel PXL (or the gate electrode of the first transistor T1) in the fifth period P5 allocated before the emission period (e.g., the seventh period P7), so that the bias (or operating point) of the first transistor T1 in the fifth period P5 (e.g., the scanning period) can become substantially equal to or similar to the bias (or operating point) of the first transistor T1 in the emission period. Therefore, in an exemplary embodiment, instantaneous afterimages can be reduced or minimized, and image quality can be improved.

[0142] Figure 6A The diagram is included in Figure 2A Graph of a comparative example of the source-gate voltage of the first transistor in the pixel shown in . Figure 6B The diagram is included in Figure 2A Graph of an example of the source-gate voltage of the first transistor in the pixel shown in . Figure 6A and Figure 6B 4 and 5. The pixel is briefly illustrated based on components related to the on-bias of the first transistor T1. Figure 7 It is an icon Figure 2A Graph of the stepping efficiency of the pixels shown in .

[0143] First, refer to Figure 2A and Figure 6A ,and Figure 2A Compared with the pixel PXL shown in , the pixel PXL_C according to the comparative example may further include an eighth transistor T8.

[0144] The eighth transistor T8 may include a first electrode connected to the first power line PL1 , a second electrode connected to the source electrode (or first electrode) of the first transistor T1 , and a gate electrode for receiving the emission control signal EM.

[0145] In reference Figure 3AIn the first and third periods P1 and P3 described above, the fourth transistor T4 may be turned on in response to the first initialization control signal GI having a gate-on voltage level, and the initialization voltage VINIT may be applied to the first node N1. The sixth and eighth transistors T6 and T8 may be turned off in response to the emission control signal EM having a gate-off voltage level, and the source electrode of the first transistor T1 may be floated. The voltage Vs (e.g., source voltage) of the source electrode of the first transistor T1 may be determined by the first parasitic capacitor Cse and the second parasitic capacitor Cgs. The first parasitic capacitor Cse may be a parasitic capacitor formed between the source electrode of the first transistor T1 and the first power line PL1, and the second parasitic capacitor Cgs may be a parasitic capacitor formed between the gate electrode of the first transistor T1 and the source electrode of the first transistor T1.

[0146] The source-gate voltage applied between the source electrode and the gate electrode of the first transistor T1 may be proportional to the difference ΔVg between the first power voltage VDD applied to the first power line PL1 and the voltage of the gate electrode of the first transistor T1 (e.g., the initialization voltage VINIT) and the first parasitic capacitor Cse, and inversely proportional to the second parasitic capacitor Cgs (e.g., "Vsg=Cse / Cgs×ΔVg"). For example, the source-gate voltage Vsg (or on-bias voltage) of the first transistor T1 may be approximately -4V.

[0147] refer to Figure 2A and Figure 6B According to an exemplary embodiment of the present disclosure, the source electrode (or first electrode) of the first transistor T1 may be directly connected to the first power line PL1. That is, the source electrode of the first transistor T1 may be non-floating, and the voltage Vs (e.g., source voltage) of the source electrode of the first transistor T1 may be equal to the first power voltage VDD.

[0148] In reference Figure 3A During the first and third periods P1 and P3 described above, the fourth transistor T4 may be turned on in response to the first initialization control signal GI having a gate-on voltage level, and the initialization voltage VINIT may be applied to the first node N1. Therefore, a source-gate voltage Vsg applied between the source and gate electrodes of the first transistor T1 may be equal to the difference between the first power voltage VDD applied to the first power line PL1 and the initialization voltage VINIT (e.g., Vsg=VDD-VINIT). For example, the source-gate voltage Vsg (or on-bias voltage) of the first transistor T1 may be approximately -8V.

[0149] When the conduction bias voltage (or conduction bias amount) of the first transistor T1 increases, the step efficiency can be improved. The step efficiency can be a phenomenon in which, when a display device that has displayed a black image in a previous frame displays a white image in a subsequent frame, the brightness of the display device is lower than the desired brightness (e.g., target brightness) in the first frame in which the white image is displayed. That is, when the image changes from a black image to a white image, the brightness change does not occur immediately, but the brightness gradually changes in a step-by-step manner throughout a number of frames, and the ratio of the brightness in the first frame to the desired brightness can be defined as the step efficiency.

[0150] refer to Figure 7 , the first step efficiency curve C_SE1 represents that when the image changes from a black image to a white image, Figure 6A luminance of a pixel (eg, pixel PXL_C according to the comparative example) shown in .

[0151] In the first frame of the first step efficiency curve C_SE1, the luminance (or luminance intensity Lum. Intensity) of the pixel PXL_C according to the comparative example is lower than the target luminance (e.g., luminance intensity 6). In the second and third frames, the luminance of the pixel PXL_C according to the comparative example may be relatively close to the target luminance. For example, the step efficiency of the pixel PXL_C according to the comparative example (and the display device including the pixel PXL_C according to the comparative example) may be approximately 85%.

[0152] The second step efficiency curve C_SE2 represents the brightness of the pixel PXL according to an exemplary embodiment of the present disclosure when the image changes from a black image to a white image.

[0153] In the first frame 1st of the second step efficiency curve C_SE2, the luminance (or luminance intensity Lum.Intensity) of the pixel PXL according to the exemplary embodiment of the present disclosure has a value close to the target luminance (for example, luminance intensity 6). Figure 1 The stepping efficiency of the display device 100 shown in FIG may be about 92.6% or higher. In the third frame, the luminance ratio of the pixel PXL (e.g., the ratio of the actual luminance to the target luminance) may be about 93.7%. That is, according to exemplary embodiments, the stepping efficiency of the pixel PXL may be improved.

[0154] As reference Figure 6A 、 Figure 6B and Figure 7As described above, the source electrode of the first transistor T1 is directly connected to the first power line PL1 and is non-floating. Therefore, according to exemplary embodiments, the on-bias voltage (or on-bias amount) of the first transistor T1 can be increased, and the stepping efficiency can be improved.

[0155] Figure 8 The diagram is provided to Figure 2A Another example of a waveform diagram of a pixel signal is shown in FIG. Figure 8 The diagram shows Figure 3A The corresponding figure.

[0156] refer to Figure 2A 、 Figure 3A and Figure 8 The period in which the emission control signal EM has a gate-off voltage level (e.g., a logic high-level off voltage level) (e.g., a non-emission period of the pixel PXL) may further include an eighth period P8 and a ninth period P9. The eighth period P8 and the ninth period P9 may be located between the fourth period P4 and the fifth period P5.

[0157] The operation of the pixel PXL in the first period P1, the second period P2, the third period P3, the fourth period P4, the fifth period P5, the sixth period P6 and the seventh period P7 is similar to the reference period P1. Figure 3A The operation of the described pixel PXL is substantially the same. Therefore, for ease of illustration, further description of previously described aspects will not be repeated.

[0158] During the eighth period P8, the first initialization control signal GI may have a gate-on voltage level. The width of the eighth period P8 may be equal to the width of the first period P1 (and the third period P3). For example, the width of the eighth period P8 may be four horizontal time intervals. Each of the compensation control signal GC, the scan signal GW, and the second initialization control signal GB may have a gate-off voltage level.

[0159] With reference Figure 4C The operation of the pixel PXL described in the third period P3 is similar. The fourth transistor T4 can be turned on in response to the first initialization control signal GI having a gate-on voltage level, and the initialization voltage VINIT can be supplied to the first node N1 for the third time. That is, the first node N1 (or the gate electrode of the first transistor T1) can be initialized by the initialization voltage VINIT in the eighth period P8. The voltage Va of the second node N2 can be maintained equal to the reference voltage VREF by the reference voltage VREF applied in the fourth period P4.

[0160] During the ninth period P9, the compensation control signal GC may have a gate-on voltage level. The width of the ninth period P9 may be equal to the width of the second period P2 (and the fourth period P4). For example, the width of the ninth period P9 may be four horizontal time intervals. Each of the first initialization control signal GI, the scan signal GW, and the second initialization control signal GB may have a gate-off voltage level.

[0161] With reference Figure 4D The operation of the pixel PXL described in the fourth period P4 is similar, the fifth transistor T5 can be turned on in response to the compensation control signal GC having the gate-on voltage level, and the reference voltage VREF can be supplied to the second node N2 for the third time. In addition, the third transistor T3 can be turned on in response to the compensation control signal GC having the gate-on voltage level, and the gate electrode and the drain electrode (or the second electrode) of the first transistor T1 can be connected to each other.

[0162] A voltage corresponding to a difference (or voltage difference) between the first power voltage VDD and the threshold voltage of the first transistor T1 may be sampled at the first node N1. The voltage Vg of the first node N1 may be equal to the difference between the first power voltage VDD and the threshold voltage of the first transistor T1.

[0163] Since the voltage Va of the second node N2 is in a state where the voltage Va is maintained as the reference voltage VREF, the component of the previous data voltage can be completely removed from the voltage Vg of the first node N1. Therefore, the voltage Vg of the first node N1 can be compensated more accurately.

[0164] As reference Figure 8 As described above, each of the first initialization control signal GI and the compensation control signal GC includes three pulses having a gate-on voltage level. Therefore, the component (or influence) of the previous data voltage is more surely removed from the voltage Vg of the first node N1, and the threshold voltage of the first transistor T1 can be more accurately compensated by the voltage Vg of the first node N1 (or the voltage of the gate electrode of the first transistor T1).

[0165] Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D is a diagram showing the driving frequency provided to Figure 2A . For example, in Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D The diagram shows Figure 3A The corresponding figure.

[0166] refer to Figure 1 、 Figure 3A、 Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D , the display device 100 can be driven at different driving frequencies to display images. That is, the display device 100 can be driven at a variable refresh rate (VRR). Hereinafter, for ease of description, a case is described assuming that one frame (or unit frame) corresponds to a frequency of 240 Hz.

[0167] like Figure 9A As shown in , in the first mode, the display device 100 may be driven at a first driving frequency (eg, 48 Hz). For example, the display device 100 may be driven in a period including five frames.

[0168] The operation of the display device 100 in the first frame FRAME1 (or the first frame period) may be the same as that in the reference frame FRAME1. Figure 3A The operation of the display device 100 in the first period P1 to the seventh period P7 is substantially the same. However, the present disclosure is not limited thereto. For example, in the first frame FRAME1, the emission control signal EM, the first initialization control signal GI, the compensation control signal GC, the scanning signal GW, and the second initialization control signal GB may have Figure 3B The waveform shown in Figure 8 The waveform shown in .

[0169] In the first frame FRAME1, since the scan signal GW, the first initialization control signal GI, and the compensation control signal GC have a gate-on voltage level (e.g., a logic low-level turn-on voltage level), a data voltage (or data signal) may be written to the pixel PXL (e.g., Data Programming), and the pixel PXL may emit light having a brightness corresponding to the data voltage in response to the emission control signal EM having the gate-on voltage level.

[0170] In the second frame FRAME2, the third frame FRAME3, the fourth frame FRAME4, and the fifth frame FRAME5, the scan signal GW, the first initialization control signal GI, and the compensation control signal GC may have a gate-off voltage level (e.g., a logic-high-level cut-off voltage level). Therefore, the data voltage is not written to the pixel PXL. The pixel PXL may maintain (e.g., hold) the data voltage written in the first frame FRAME1 during the four frames and emit light having a brightness corresponding to the pre-written data voltage in response to the emission control signal EM having a gate-on voltage level.

[0171] In the non-emission period (e.g., the period in which the emission control signal EM has a gate-off voltage level) of each of the second frame FRAME2, the third frame FRAME3, the fourth frame FRAME4, and the fifth frame FRAME5, the second initialization control signal GB may have a pulse of a gate-on voltage level. The seventh transistor T7 in the pixel PXL may be turned on in response to the second initialization control signal GB, and the anode electrode of the light-emitting element LD may be initialized for each frame. Therefore, as with the first frame FRAME1, the display device 100 may display an image with uniform brightness in the second frame FRAME2, the third frame FRAME3, the fourth frame FRAME4, and the fifth frame FRAME5.

[0172] like Figure 9B As shown in FIG, in the second mode, the display device 100 can be driven at a second driving frequency (eg, 60 Hz). For example, the display device 100 can be driven in a period including four frames. The operation of the display device 100 in the first frame FRAME1 can be the same as that in FIG. Figure 9A The operation of the display device 100 in the first frame FRAME1 is substantially the same as described above, and the operation of the display device 100 in the second frame FRAME2 to the fourth frame FRAME4 can be the same as described above. Figure 9A The operation of the display device 100 described in the second frame FRAME2 is substantially the same. Therefore, for ease of illustration, further description of the previously described aspects will not be repeated.

[0173] That is, the display device 100 may write a data voltage to the pixel PXL in response to the first initialization control signal GI having a gate-on voltage level, the compensation control signal GC, and the scan signal GW in the first frame FRAME1, and maintain the pre-written data voltage in the second and third frames FRAME2 and FRAME3.

[0174] like Figure 9C As shown in , in the third mode, the display device 100 can be driven at a third driving frequency (e.g., 80 Hz). For example, the display device 100 can be driven in a period including three frames. The display device 100 can write a data voltage in the first frame FRAME1 and maintain the pre-written data voltage in the second frame FRAME2 and the third frame FRAME3. Figure 9D As shown in FIG, in the fourth mode, the display device 100 can be driven at a fourth driving frequency (e.g., 120 Hz). For example, the display device 100 can be driven in a period including two frames. The display device 100 can write a data voltage in the first frame FRAME1 and maintain the pre-written data voltage in the second frame FRAME2.

[0175] As reference Figure 9A、 Figure 9B 、 Figure 9C and Figure 9D As described above, the display device 100 may be driven at a variable refresh rate (VRR). The data voltage (or data signal) may be set during a data programming period (eg, Figure 9A The pre-written data voltage in the pixel PXL may be written to the pixel PXL in the first frame FRAME1 shown in FIG. 1 , and the pre-written data voltage in the pixel PXL may be written to the pixel PXL in the first frame FRAME1 shown in FIG. 1 . Figure 9A In the hold frame period, only the emission control signal EM and the second initialization control signal GB periodically have the gate-on voltage level, so that the display device 100 can display an image with completely uniform brightness in the data programming period and the hold frame period.

[0176] Figure 10 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment of the present disclosure.

[0177] refer to Figure 1 、 Figure 2A 、 Figure 3A and Figure 10 , Figure 10 The method shown in Figure 1 is implemented in the display device 100 shown in FIG.

[0178] exist Figure 10 In the method shown in , during a first period P1, an initialization voltage VINIT may be applied to a first node N1 (eg, a gate electrode of a first transistor T1) for the first time (S1010). The width of the first period P1 may be three horizontal time intervals or more.

[0179] As reference Figure 3A and Figure 4A As described, the first initialization control signal GI may have a gate-on voltage level. The fourth transistor T4 may be turned on in response to the first initialization control signal GI, and the initialization voltage VINIT may be supplied to the first node N1 for the first time.

[0180] exist Figure 10 In the method shown in , during the second period P2, the second electrode (or drain electrode) and the gate electrode of the first transistor T1 may be connected to each other, and at the same time, the reference voltage VREF may be applied to the second node N2 for the first time (S1020). The width of the second period P2 may be three horizontal time intervals or more.

[0181] As reference Figure 3A and Figure 4BAs described above, the compensation control signal GC may have a gate-on voltage level, and the third transistor T3 and the fifth transistor T5 may be turned on in response to the compensation control signal GC. The reference voltage VREF may be supplied to the second node N2 for the first time through the turned-on fifth transistor T5, and the second node N2 may be initialized by the reference voltage VREF. In addition, the first transistor T1 is diode-connected through the turned-on third transistor T3, and the threshold voltage of the first transistor T1 may be sampled at the first node N1.

[0182] exist Figure 10 In the method shown in , during the third period P3, the initialization voltage VINIT may be applied to the first node N1 (eg, the gate electrode of the first transistor T1) for the second time (S1030). The width of the third period P3 may be three horizontal time intervals or more.

[0183] As reference Figure 3A and Figure 4C As described above, the first initialization control signal GI may have a gate-on voltage level. The fourth transistor T4 may be turned on in response to the first initialization control signal GI, and the initialization voltage VINIT may be supplied to the first node N1 for the second time. That is, the voltage of the gate electrode of the first transistor T1 may be initialized again.

[0184] exist Figure 10 In the method shown in , during the fourth period P4, the second electrode (or drain electrode) and the gate electrode of the first transistor T1 may be connected to each other, and at the same time, the reference voltage VREF may be applied to the second node N2 for the second time (S1040). The width of the fourth period P4 may be three horizontal time intervals or more.

[0185] As reference Figure 3A and Figure 4D As described, the compensation control signal GC may have a gate-on voltage level, and the third transistor T3 and the fifth transistor T5 may be turned on in response to the compensation control signal GC. The reference voltage VREF may be supplied to the second node N2 for the second time via the turned-on fifth transistor T5, and the second node N2 may be initialized by the reference voltage VREF. In addition, the first transistor T1 may be diode-connected via the turned-on third transistor T3, and the threshold voltage of the first transistor T1 may be sampled at the first node N1. Since the voltage Va of the second node N2 is in a state where the voltage Va is maintained at the reference voltage VREF, the component of the previous data voltage may be removed from the voltage Vg of the first node N1. Therefore, compared to the second period P2, the threshold voltage of the first transistor T1 may be sampled more accurately, and the voltage Vg of the first node N1 may be compensated more accurately.

[0186] In some exemplary embodiments, Figure 10 In the method shown in , the step of applying the initialization voltage VINIT to the first node N1 (e.g., the gate electrode of the first transistor T1) and the step of connecting the second electrode (or drain electrode) of the first transistor T1 to the gate electrode and simultaneously applying the reference voltage VREF to the second node N2 can be additionally repeated one or more times after the fourth period P4.

[0187] That is, in Figure 10 In the method shown in , the initialization operation of initializing the first node N1 and the compensation operation of sampling the threshold voltage of the first transistor T1 can be repeated a total of three or more times. The component (or influence) of the previous data voltage can be more accurately removed from the voltage Vg of the first node N1.

[0188] exist Figure 10 In the method shown in , during the fifth period P5 (or scan period), the data voltage DATA may be applied to the second node N2 (S1050). The width of the fifth period P5 may be one horizontal time interval.

[0189] As reference Figure 3A and Figure 4E As described, the scan signal GW may have a gate-on voltage level. The second transistor T2 may be turned on in response to the scan signal GW, and the data voltage DATA may be supplied to the second node N2.

[0190] After the threshold voltage of the first transistor T1 is compensated (or sampled) and before the emission period, the data voltage DATA is written so that the instantaneous afterimage can be minimized or reduced, as shown in FIG. Figure 5A and Figure 5B Descriptive.

[0191] exist Figure 10 In the method shown in , during the sixth period P6, the initialization voltage VINIT may be applied to the anode electrode of the light emitting element LD (S1060).

[0192] As reference Figure 3A and Figure 4F As described above, the second initialization control signal GB may have a gate-on voltage level. The seventh transistor T7 may be turned on in response to the second initialization control signal GB, and the initialization voltage VINIT may be supplied to the anode electrode of the light-emitting element LD. The parasitic capacitor of the light-emitting element LD is initialized by the initialization voltage VINIT, and the pixel PXL may exhibit more uniform brightness characteristics.

[0193] exist Figure 10In the method shown in , during the emission period (or seventh period P7 ), the sixth transistor T6 (or emission transistor) may be turned on ( S1070 ).

[0194] The emission control signal EM may have a gate-on voltage level. The sixth transistor T6 may be turned on in response to the emission control signal EM, a driving current may flow through the turned-on sixth transistor T6, and the light emitting element LD may emit light having a brightness corresponding to the driving current.

[0195] As reference Figure 10 As described above, in the driving method of the display device according to the exemplary embodiment of the present disclosure, the initialization operation of initializing the first node N1 (e.g., the gate electrode of the first transistor T1) and the compensation operation of sampling the threshold voltage of the first transistor T1 may be repeated three or more times. Therefore, the component (or influence) of the previous data voltage can be removed from the voltage Vg of the first node N1, and the threshold voltage of the first transistor T1 can be more accurately compensated by the voltage Vg of the first node N1 (or the voltage of the gate electrode of the first transistor T1).

[0196] In addition, Figure 10 In the method shown in , independent of the compensation operation, the data voltage can be written to the pixel PXL during a horizontal time interval just before the emission period. As a result, the bias (or operating point) of the first transistor T1 becomes equal to or similar to the bias (or operating point) of the first transistor T1 during the emission period. Therefore, the instantaneous afterimage can be reduced or minimized, and the image quality can be improved.

[0197] In a comparative example, a display device may include a first data line and a second data line corresponding to a pixel column, and a first data signal may be provided to odd-numbered pixels in the pixel column via the first data line, and a second data signal may be provided to even-numbered pixels in the pixel column via the second data line. The number of pixels connected to each of the first and second data lines may be reduced, and the data write time may be increased. As the resolution and driving frequency of the display device increase, such a display device including a plurality of data lines corresponding to a pixel column requires a large number of data lines. As the number of data lines increases, manufacturing costs increase, and the dead zone for arranging the data lines and other components may also increase.

[0198] In a display device and a method of driving the display device according to an exemplary embodiment of the present disclosure, a compensation period in which the threshold voltage of the first transistor (or driving transistor) is sampled (and compensated) and a data writing period in which the data voltage is written to the gate electrode of the first transistor are separated from each other, and a width of the compensation period is set to three or more horizontal time intervals (for example, approximately 3.2 μs or greater).

[0199] In addition, in the display device and the method of driving the display device according to the exemplary embodiment of the present disclosure, the initialization operation of initializing the gate electrode of the first transistor and the compensation operation of sampling (and compensating) the threshold voltage of the first transistor are sequentially repeated three or more times. Therefore, the component (or influence) of the previous data voltage can be removed from the voltage applied to the gate electrode of the first transistor, and the threshold voltage of the first transistor can be compensated more accurately.

[0200] Furthermore, in a display device and a method of driving the display device according to an exemplary embodiment of the present disclosure, the data voltage is written to the pixel during a horizontal time interval immediately preceding the emission period, independently of the compensation operation. Thus, the bias (or operating point) of the first transistor becomes equal to or similar to the bias (or operating point) of the first transistor during the emission period. Consequently, transient afterimages can be reduced or improved, and image quality can be improved.

[0201] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined in the following claims.

Claims

1. A display device, comprising: First Power Line; Second power line; Reference power lines; Initialize powerline; a data line configured to transmit a data signal; a first scan line configured to transmit a scan signal; a first gate line and a second gate line configured to sequentially transmit a gate signal; a transmit control line configured to transmit a transmit control signal; a scan driver configured to supply the gate signal having a gate-on voltage level to the second gate line in a first period and a third period, supply the gate signal having the gate-on voltage level to the first gate line in a second period and a fourth period, and supply the scan signal having the gate-on voltage level to the first scan line in a scan period; as well as Pixels, The pixels include: a first transistor including a first electrode connected to the first power line, a second electrode connected to the third node, and a gate electrode connected to the first node; a first capacitor formed between the first power line and a second node; a second capacitor formed between the first node and the second node; a second transistor comprising a third electrode connected to the data line, a fourth electrode connected to the second node, and a gate electrode connected to the first scan line; a third transistor comprising a fifth electrode connected to the first node, a sixth electrode connected to the third node, and a gate electrode connected to the first gate line; a fourth transistor comprising a seventh electrode connected to the first node, an eighth electrode connected to the initialization power line, and a gate electrode connected to the second gate line; a fifth transistor comprising a ninth electrode connected to the second node, a tenth electrode connected to the reference power line, and a gate electrode connected to the first gate line; a sixth transistor including an eleventh electrode connected to the third node, a twelfth electrode, and a gate electrode connected to the emission control line; and a light emitting element connected between the twelfth electrode of the sixth transistor and the second power line, wherein the first time period, the second time period, the third time period and the fourth time period are sequentially located in one frame, wherein the one frame includes a transmission period and a non-transmission period, and The first period, the second period, the third period, the fourth period and the scanning period are included in the one non-transmission period and do not overlap with each other.

2. The display device according to claim 1, wherein At least one of the second transistor, the third transistor, the fourth transistor, and the fifth transistor is implemented as a double-gate transistor including a plurality of sub-transistors connected in series.

3. The display device according to claim 1, wherein The emission driver provides the emission control signal having the gate-on voltage level to the emission control line in the emission period.

4. The display device according to claim 3, wherein A width of each of the first to fourth periods is three times or more the width of the scanning period.

5. The display device according to claim 4, wherein The width of each of the first to fourth periods is four times the width of the scanning period. The display device according to claim 4 , wherein: The width of the scanning period is one horizontal time interval.

7. The display device according to claim 6, wherein In the second period, the first node has a voltage corresponding to a difference between a first power voltage applied to the first power line and a threshold voltage of the first transistor, wherein the voltage of the first node changes according to a previous data voltage of a previous frame, Here, in the fourth period, the first node has a voltage equal to the difference between the first power voltage and the threshold voltage of the first transistor.

8. The display device according to claim 6, wherein An operating point of the first transistor in the scan period is equal to the operating point of the first transistor in the emission period.

9. The display device according to claim 3, further comprising: a seventh transistor including a thirteenth electrode connected to the initialization power line, a fourteenth electrode connected to the anode electrode of the light emitting element, and a gate electrode connected to the second scan line; The scan driver provides the scan signal having the gate-on voltage level to the second scan line after the scan period.

10. The display device according to claim 9, wherein The scan signal supplied to the second scan line has a waveform in which the scan signal supplied to the first scan line is shifted by the scan period.

11. The display device according to claim 7, wherein The scan driver further sequentially supplies the gate signal having the gate-on voltage level to the second gate line and the first gate line between the fourth period and the scan period.

12. The display device according to claim 1, wherein The gate signal supplied to the first gate line has a waveform in which the gate signal supplied to the second gate line is shifted by the first period.

13. The display device according to claim 1, wherein The gate signal is supplied to the second gate line and the first gate line, and the gate signal supplied to the second gate line includes a plurality of pulses having a gate-on voltage level.

14. The display device according to claim 13, wherein Each of the pulses has the same pulse width, The gate signal supplied to the first gate line has a waveform obtained by shifting the gate signal supplied to the second gate line by the pulse width.

15. A method for driving a display device, comprising: During a first period, an initialization voltage is applied to the first node for the first time, wherein the display device includes a first transistor including a first electrode connected to a first power line, a second electrode connected to a third node, and a gate electrode connected to the first node; During a second period, a reference voltage is applied to a second node for the first time in a state in which the second electrode of the first transistor is connected to the gate electrode of the first transistor, wherein the display device further includes a first capacitor formed between the first power line and the second node and a second capacitor formed between the first node and the second node; During a third period, applying the initialization voltage to the first node for a second time; During a fourth period, the reference voltage is applied to the second node for a second time in a state where the second electrode of the first transistor is connected to the gate electrode of the first transistor; During a scan period, applying a data voltage to the second node; as well as During the emission period, the emission transistor is turned on, The display device further includes the emission transistor and a light emitting element, wherein the emission transistor includes a first electrode connected to the third node, a second electrode, and a gate electrode connected to an emission control line, and the light emitting element is connected to the second electrode of the emission transistor and a second power line. The first to fourth periods are included in one non-transmission period of one frame and do not overlap with each other.

16. The method according to claim 15, wherein A width of each of the first to fourth periods is three times or more the width of the scanning period.

17. The method according to claim 16, wherein The width of the scanning period is one horizontal time interval.

18. The method according to claim 15, further comprising: between the fourth period and the scan period, applying the initialization voltage to the first node for a third time; as well as The reference voltage is applied to the second node for a third time.

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