Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are disclosed. The method includes: providing a carrier substrate, the carrier substrate including a conductive layer; placing a semiconductor die on the carrier substrate; forming an insulating layer to cover the semiconductor die on the carrier substrate; forming a through hole to penetrate the insulating layer at the side of the semiconductor die and expose the conductive layer of the carrier substrate; performing an electroplating process to form a via filling the through hole, in which the conductive layer of the carrier substrate is used as a seed; forming a first redistribution layer on a first surface of the insulating layer; removing the carrier substrate; and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being opposite to each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0012762 filed in the Korean Intellectual Property Office on February 3, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a wafer and panel level semiconductor package. Background Art

[0004] Semiconductor packages are provided to implement integrated circuit chips suitable for use in electronic products. Typically, in a semiconductor package, a semiconductor chip is mounted on a printed circuit board (PCB), and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the recent development of the electronics industry, semiconductor packages have been variously developed to achieve the goals of compact size, light weight, and / or low manufacturing cost. In addition, various semiconductor packages have emerged as their application fields (e.g., large-capacity storage devices) have expanded.

[0005] As semiconductor chips become more and more highly integrated, their size becomes smaller and smaller. However, due to the small size of semiconductor chips, it is difficult to attach, handle, and test solder balls. In addition, problems may arise when obtaining a variety of mounting boards according to the size of semiconductor chips. In order to solve some of these problems, fan-out wafer-level packaging (FO-WLP) and fan-out panel-level packaging (FO-PLP) have been proposed. Summary of the invention

[0006] Some example embodiments of the inventive concepts provide a semiconductor device having reduced defects and a method of manufacturing the same.

[0007] The objects of the inventive concept are not limited to those mentioned above, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0008] According to some example embodiments conceived in the present invention, a method for manufacturing a semiconductor device may include: providing a carrier substrate, the carrier substrate including a conductive layer; placing a semiconductor die on the carrier substrate; forming an insulating layer to cover the semiconductor die on the carrier substrate; forming a through hole to penetrate the insulating layer on the side of the semiconductor die and expose the conductive layer of the carrier substrate; performing an electroplating process to form a via filling the through hole, in which the conductive layer of the carrier substrate is used as a seed; forming a first redistribution layer on a first surface of the insulating layer; removing the carrier substrate; and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being opposite to each other.

[0009] According to some example embodiments of the inventive concept, a method of manufacturing a semiconductor device may include: providing a carrier substrate; placing a semiconductor die on the carrier substrate so that an active surface of the semiconductor die faces the carrier substrate; forming an insulating layer on the carrier substrate, the insulating layer surrounding the semiconductor die; etching the insulating layer to form a through hole penetrating the insulating layer; forming a seed layer to cover the bottom surface and inner side surface of the through hole; forming a via filling the through hole; forming a first redistribution layer over the semiconductor die and the insulating layer; removing the carrier substrate, wherein removing the carrier substrate includes: removing a portion of the seed layer simultaneously when removing the carrier substrate, the portion of the seed layer being located on the bottom surface of the through hole; and forming a second redistribution layer under the semiconductor die and the insulating layer. The bottom surface of the through hole may be located at a level lower than the level of the active surface of the semiconductor die and lower than the level of the bottom surface of the insulating layer.

[0010] According to some example embodiments of the inventive concept, a semiconductor device may include: a lower redistribution layer; a semiconductor die, the semiconductor die being located on the lower redistribution layer; an insulating layer, the insulating layer being located on the lower redistribution layer, the insulating layer surrounding the semiconductor die; a via, the via penetrating the insulating layer and coupled to a redistribution pattern of the lower redistribution layer; a seed layer, the seed layer being located between the via and the insulating layer, the seed layer surrounding a side surface of the via; and an upper redistribution layer, the upper redistribution layer being located on the insulating layer and the semiconductor die, the upper redistribution layer being coupled to the via. A bottom surface of the via is exposed relative to the seed layer. The via may extend into the lower redistribution layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 22 sectional views showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concept, wherein: Fig. 22 Cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts are illustrated.

[0012] Fig.23 Cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts are illustrated.

[0013] Fig.24 Cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts are illustrated. DETAILED DESCRIPTION

[0014] A method for manufacturing a semiconductor device according to the inventive concept will be described below with reference to the accompanying drawings.

[0015] Figures 1 to 22 Cross-sectional views illustrating methods of fabricating a semiconductor device according to some example embodiments of the inventive concepts are shown. Figures 1 to 7 , Figures 9 to 14 , Figures 17 to 19 , Fig.21 and Fig. 22 Cross-sectional views illustrating methods of fabricating a semiconductor device according to some example embodiments of the inventive concepts are shown. Figure 8 Shows Figure 7 An enlarged view of part A of FIG. Fig.15 and Fig.16 Shows Fig.14 An enlarged view of part B. Fig. 20 Shows Fig.19 An enlarged view of portion C of FIG. Fig. 22 Cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts are illustrated.

[0016] Reference Figure 1 , a first carrier substrate 700 may be provided. The first carrier substrate 700 may include a first support substrate 710, a conductive layer 720, and a first release layer 730. The first support substrate 710 may be a carrier or an auxiliary tool disposed on the carrier. The first support substrate 710 may be formed, for example, of glass, plastic, metal, or any other suitable material. The conductive layer 720 may be formed on the first support substrate 710. The conductive layer 720 may be formed by performing a coating or deposition process on the first support substrate 710. The conductive layer 720 may include a metal such as copper (Cu). For example, the conductive layer 720 may be a detachable copper foil. The first release layer 730 may be formed on the conductive layer 720. The first release layer 730 may be a double-sided tape or an adhesive layer. When the first release layer 730 is a double-sided tape, the first release layer 730 may be attached to the conductive layer 720 using a vacuum lamination process. When the first release layer 730 is an adhesive layer, an adhesive material may be applied to form the first release layer 730.

[0017] The first carrier substrate 700 may further include a dam 732 disposed on the first release layer 730. The dam 732 may have a shape protruding upward from the first release layer 730. The dam 732 may define an area on which the semiconductor die 200 is mounted in a subsequent process. The dam 732 may include the same material as that of the first release layer 730. Alternatively, the first carrier substrate 700 may not include the dam 732.

[0018] According to Figure 2 In some other embodiments shown, the first carrier substrate 700' may include a conductive substrate 715 and a first release layer 730. The conductive substrate 715 may be thick enough to serve as a first support substrate (see Figure 1 The first support substrate 710) and the conductive layer (see Figure 1 The conductive substrate 715 may include a material selected from at least one of titanium (Ti) and tantalum (Ta). The first release layer 730 may be formed on the conductive substrate 715. The first release layer 730 may be a double-sided tape or an adhesive layer. Figure 1 Embodiment of the invention.

[0019] Reference Figure 3 , a semiconductor die 200 may be disposed on a first carrier substrate 700. An active surface of the semiconductor die 200 may face the first carrier substrate 700. A plurality of die pads 210 may be disposed on the active surface of the semiconductor die 200. For example, the semiconductor die 200 may be disposed to allow the die pads 210 to contact the first release layer 730 of the first carrier substrate 700. The term "contact" as used herein refers to direct connection (i.e., touching) unless the context otherwise indicates. The die pads 210 may separate the active surface of the semiconductor die 200 from the top surface of the first release layer 730. The die pads 210 may be disposed in an area defined by a barrier 732. For example, the barrier 732 may be positioned along the outer edge of the semiconductor die 200.

[0020] Reference Figure 4 , an insulating layer 300 may be formed on the first carrier substrate 700. The insulating layer 300 may be formed by coating an insulating material on the first carrier substrate 700. An insulating material may be coated on the first carrier substrate 700 to cover the semiconductor die 200. The insulating layer 300 may cover the top surface and the side surface of the semiconductor die 200. The barrier 732 may prevent the insulating material from entering the space between the semiconductor die 200 and the first carrier substrate 700. The insulating layer 300 may have a first surface facing the first carrier substrate 700 and a second surface opposite to the first surface. The insulating material may include an insulating polymer such as epoxy molding compound (EMC).

[0021] In some other embodiments, the first carrier substrate 700 may not include the barrier 732. For example, Figure 5 As shown, the insulating layer 300 may fill the space between the first carrier substrate 700 and the semiconductor die 200. The insulating material may surround the die pad 210. Figure 4 Embodiment of the invention.

[0022] According to some example embodiments of the inventive concepts, the semiconductor die 200 may be placed on the first carrier substrate 700, and then an insulating material may be coated to form the insulating layer 300. Therefore, process defects such as damage of the semiconductor die 200 due to deformation of the insulating layer 300 during the manufacturing process, or delamination of the semiconductor die 200 or the insulating layer 300 from the first carrier substrate 700 may be reduced.

[0023] Reference Figure 6 , a through hole VH may be formed in the insulating layer 300. For example, a mask pattern MP may be formed on the insulating layer 300. When viewed in a top view, the mask pattern MP may have a pattern hole horizontally spaced apart from the semiconductor die 200. An etching process using the mask pattern MP as an etching mask to form a through hole VH in the insulating layer 300 may be performed. The through hole VH may be formed to have a width that gradually decreases as the through hole VH approaches the first carrier substrate 700. During the etching process, the first release layer 730 of the first carrier substrate 700 may be etched together with the insulating layer 300. For example, the through hole VH may be formed to penetrate the insulating layer 300 and extend into the first carrier substrate 700. The through hole VH may penetrate the insulating layer 300 and the first release layer 730, thereby exposing the conductive layer 720.

[0024] Reference Figure 7 , can be obtained from Figure 6 The mask pattern MP is removed from the resulting structure.

[0025] A seed layer SL may be formed on the insulating layer 300. The seed layer SL may conformally cover the insulating layer 300. For example, the seed layer SL may be formed to cover the top surface of the insulating layer 300. In addition, the seed layer SL may be formed along the bottom surface and the inner side surface of the through hole VH. The bottom surface of the through hole VH may correspond to the exposed top surface of the conductive layer 720, and the inner side surface of the through hole VH may correspond to the inner side wall of the insulating layer 300 and the inner side wall of the first release layer 730. For example, as Figure 8As shown, in the through hole VH, a portion SLa of the seed layer SL may be in contact with the top surface of the conductive layer 720. In addition, in the through hole VH, the seed layer SL may be in contact with the inner sidewall of the insulating layer 300 and the inner sidewall of the first release layer 730. The seed layer SL may include a metal material. For example, the seed layer SL may include a material selected from at least one of titanium (Ti) and tantalum (Ta). The boundary between the seed layer SL and the conductive layer 720 may not be visible, but the inventive concept is not limited thereto.

[0026] In some other embodiments, the first carrier substrate 700' may include a conductive substrate 715 and a first release layer 730. In this case, Fig. 9 As shown, in the through hole VH, the seed layer SL may be in contact with the conductive substrate 715, and may also be in contact with the inner sidewall of the insulating layer 300 and the inner sidewall of the first release layer 730. Figure 7 Embodiment of the invention.

[0027] Reference Fig.10 , a resist pattern RP may be formed on the seed layer SL. A trench T may be formed in the resist pattern RP to expose the seed layer SL. At least a portion of the trench T may overlap with the through hole VH. For example, the trench T may be spatially connected to the through hole VH. The trench T may define an area where a first upper redistribution pattern 516 is formed in a subsequent process.

[0028] A via 410 and a first upper redistribution pattern 516 may be formed in the through hole VH and the trench T, thereby covering the seed layer SL. The via 410 and the first upper redistribution pattern 516 may be formed using an electroplating process. For example, an electroplating process may be performed so that the through hole VH and the trench T are filled with a metal material so that the metal material filling the through hole VH may constitute the via 410, and the metal material filling the trench T may constitute the first upper redistribution pattern 516. The electroplating process may include a metal chemical plating process or a metal electroplating process. The electroplating process may use the seed layer SL as an electrode. An external power source for the electroplating process may be connected to the seed layer SL and the conductive layer 720. The conductive layer 720 may be thicker than the seed layer SL, and its resistance may be less than the resistance of the seed layer SL. Therefore, a portion SLa of the seed layer SL located on the bottom surface of the through hole VH may receive external power from the conductive layer 720.

[0029] According to the inventive concept, the portion SLa of the seed layer SL in the through hole VH can receive power from the conductive layer 720 having a low resistance, and thus the electroplating process can be easily performed in the through hole VH. As a result, defects such as the generation of voids in the via 410 in the through hole VH or the failure of conductive material filling in the through hole VH during the electroplating process can be avoided.

[0030] The first upper redistribution pattern 516 may fill the trench T, but may not extend onto the top surface of the resist pattern RP. Therefore, it may not be necessary to perform a planarization process separately. Based on the shape of the through hole VH, the via 410 may be formed to have a width that gradually decreases as the via 410 approaches the first carrier substrate 700. A metal such as copper (Cu) may be selected as a source material used in the electroplating process for forming the via 410 and the first upper redistribution pattern 516.

[0031] According to the inventive concept, a planarization process may not be performed in a process for forming the via 410 and the first upper redistribution pattern 516. Therefore, damage to the semiconductor die 200 caused by the planarization process may be prevented.

[0032] In some other embodiments, the seed layer SL may not be formed. In this way, when the electroplating process is performed, the conductive layer 720 of the carrier substrate 700 exposed by the through hole VH may be used as a seed to form the via 410 filling the through hole VH.

[0033] Reference Fig.11 , the resist pattern RP may be removed to expose the top surface of the seed layer SL and the upper sidewall of the first upper redistribution pattern 516. The exposed portion of the seed layer SL may be removed to expose the top surface of the insulating layer 300. An etching process may be performed to remove the seed layer SL. In the etching process, the first upper redistribution pattern 516 may have an etching selectivity relative to the seed layer SL. Therefore, an unexposed portion of the seed layer SL disposed on the bottom surface of the first upper redistribution pattern 516 may not be removed in the etching process. The first upper seed pattern 514 may be composed of an unexposed portion of the seed layer SL disposed on the bottom surface of the first upper redistribution pattern 516. The via seed layer 420 may be composed of a portion of the seed layer SL located in the through hole VH and between the via 410 and the insulating layer 300. The via seed layer 420 may be interposed between the via 410 and the insulating layer 300, and may have a bottom 422 located between the via 410 and the conductive layer 720.

[0034] Reference Fig.12 , a first upper dielectric layer 512 may be formed on the insulating layer 300. The first upper dielectric layer 512 may cover the top surface of the insulating layer 300 and the first upper redistribution pattern 516. The side surface of the first upper redistribution pattern 516 may be in direct physical contact with the first upper dielectric layer 512. The first upper dielectric layer 512 may include a photosensitive polymer. In the present specification, the photosensitive polymer may include, for example, at least one selected from photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer. The first upper dielectric layer 512, the first upper seed pattern 514, and the first upper redistribution pattern 516 may constitute a first upper redistribution layer 510.

[0035] A second upper redistribution layer 520 may be formed on the first upper redistribution layer 510. The formation of the second upper redistribution layer 520 may be similar to the formation of the first upper redistribution layer 510. For example, a hole may be formed in the first upper dielectric layer 512. The hole may expose the top surface of the first upper redistribution pattern 516. A seed layer may be formed on the first upper dielectric layer 512. The seed layer may be formed along the bottom surface and the inner side surface of the hole while covering the top surface of the first upper dielectric layer 512. A resist pattern may be formed on the seed layer. The resist pattern may have a groove defining an area for forming a second upper redistribution pattern 526. A second upper redistribution pattern 526 may be formed in the hole and the groove of the resist pattern, thereby covering the seed layer. Thereafter, the resist pattern may be removed, and the exposed portion of the seed layer may be removed to form a second upper seed pattern 524. A second upper dielectric layer 522 may be formed on the first upper dielectric layer 512 to cover the second upper redistribution pattern 526. The second upper dielectric layer 522 may have a first recess RS1 exposing a top surface of the second upper redistribution pattern 526. The second upper dielectric layer 522, the second upper seed pattern 524, and the second upper redistribution pattern 526 may constitute a second upper redistribution layer 520. The first upper redistribution layer 510 and the second upper redistribution layer 520 may constitute an upper redistribution substrate 500, and may be electrically connected to the via 410.

[0036] like Fig.13 As shown, it can be Fig.12 The resulting structure is inverted (i.e., "flipped"). Fig.12 In this orientation of the resulting structure, the first carrier substrate 700 is located above the insulating layer 300, and the active surface of the semiconductor die 200 faces upward. In addition, a second carrier substrate 800 can be disposed on the upper redistribution substrate 500. The second carrier substrate 800 may include a second support substrate 810 and a second release layer 820. The second release layer 820 may be used to attach the second support substrate 810 to the second upper redistribution layer 520. The second support substrate 810 may be formed of, for example, glass, plastic, metal, or any other suitable material. The second release layer 820 may be a double-sided tape or adhesive layer.

[0037] For the convenience of describing the relationship between one element or feature shown in the figure and another (more) element or feature, spatial relative terms such as "above", "upper", "below", "below", "lower" and the like may be used in this article. It will be understood that in addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the term "below" can include both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or other directions), and the spatial relative descriptors used in this article are interpreted accordingly.

[0038] The first support substrate 710 of the first carrier substrate 700 may be removed. The first support substrate 710 may be removed using a physical method. The first support substrate 710 may be removed to expose the conductive layer 720.

[0039] Afterwards, the conductive layer 720 of the first carrier substrate 700 may be removed. When the conductive layer 720 includes a detachable copper foil, the conductive layer 720 may be physically removed. Alternatively, a chemical method may be used to remove the conductive layer 720. Removing the conductive layer 720 may expose the first release layer 730.

[0040] like Fig.15 As shown, the via seed layer 420 may have a bottom 422 in contact with the conductive layer 720, and the bottom 422 may be removed simultaneously when the conductive layer 720 is removed. Therefore, the via seed layer 420 may cover the side surface of the via 410, but may not cover the bottom surface 410a of the via 410. One end of the via seed layer 420 may be located at the same level as the bottom surface 410a of the via 410, and the via 410 and the via seed layer 420 may protrude from the first surface 300a of the insulating layer 300.

[0041] According to some other embodiments, Fig.16 As shown, removing the conductive layer 720 may remove a portion of the via seed layer 420 between the via 410 and the first release layer 730. Therefore, the via seed layer 420 may have an end portion located at the same level as the first surface 300a of the insulating layer 300, and the via 410 may protrude from the first surface 300a of the insulating layer 300.

[0042] Reference Fig.17 , the first release layer 730 may be removed. For example, the first release layer 730 may be removed by using a physical method or a chemical treatment. When the first release layer 730 is removed, the barrier 732 may be removed at the same time. Removal of the first release layer 730 may expose the first surface 300a of the insulating layer 300 and the active surface of the semiconductor die 200.

[0043] Or, when using Figure 5 When manufacturing a semiconductor device using the first carrier substrate 700 not including the barrier 732 as shown in the embodiment, the first release layer 730 may be removed to expose the first surface 300 a of the insulating layer 300 and the die pad 210 of the semiconductor die 200 .

[0044] Reference Fig.18 , a first lower dielectric layer 112 may be formed. The first lower dielectric layer 112 may cover the first surface 300a of the insulating layer 300 and the active surface of the semiconductor die 200. The first lower dielectric layer 112 may include a photosensitive polymer. For example, the photosensitive polymer may include at least one selected from photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer.

[0045] The second recess RS2 and the third recess RS3 may be formed on the first lower dielectric layer 112. For example, the first lower dielectric layer 112 may be patterned to form the second recess RS2 and the third recess RS3. The second recess RS2 may expose the bottom surface 410a of the via 410. The third recess RS3 may expose the die pad 210 of the semiconductor die 200. The second recess RS2 may have a width that gradually decreases as it approaches the insulating layer 300. The second recess RS2 may have a bottom surface having a width that is less than the width of the bottom surface 410a of the via 410.

[0046] Reference Fig.19 , a first lower seed pattern 114 and a first lower redistribution pattern 116 may be formed. For example, a seed layer may be formed on the first lower dielectric layer 112. The seed layer may be formed along the bottom surface and the inner side surface of the second recess RS2 and the third recess RS3 while covering the first lower dielectric layer 112. A resist pattern may be formed on the seed layer. The resist pattern may have a groove defining an area in which the first lower redistribution pattern 116 is formed. The first lower redistribution pattern 116 may be formed in the groove of the resist pattern, thereby covering the seed layer. Thereafter, the resist pattern may be removed, and the exposed portion of the seed layer may be removed to form the first lower seed pattern 114. The first lower dielectric layer 112, the first lower seed pattern 114, and the first lower redistribution pattern 116 may constitute the first lower redistribution layer 110.

[0047] like Fig. 20 As shown, based on the shape of the second recess RS2, at the interface between the via 410 and the first lower seed pattern 114, the width of the via 410 may be greater than the width of the first lower seed pattern 114. In addition, the width of the via 410 at the bottom surface 410a may be greater than the width at the bottom surface of the first lower redistribution pattern 116.

[0048] Reference Fig.21 , a second lower redistribution layer 120 and a third lower redistribution layer 130 may be formed on the first lower redistribution layer 110. The formation of the second lower redistribution layer 120 and the third lower redistribution layer 130 may be similar to the formation of the first lower redistribution layer 110. For example, a second lower dielectric layer 122 may be formed on the first lower dielectric layer 112 to cover the first lower redistribution pattern 116 and the first lower seed pattern 114, and then a second lower seed pattern 124 and a second lower redistribution pattern 126 may be formed to be coupled to the first lower redistribution pattern 116. The second lower dielectric layer 122, the second lower seed pattern 124, and the second lower redistribution pattern 126 may constitute the second lower redistribution layer 120. A third lower dielectric layer 132 may be formed on the second lower dielectric layer 122 to cover the second lower redistribution pattern 126 and the second lower seed pattern 124, and then a third lower seed pattern 134 and a third lower redistribution pattern 136 may be formed to be coupled to the second lower redistribution pattern 126. The third lower dielectric layer 132, the third lower seed pattern 134, and the third lower redistribution pattern 136 may constitute a third lower redistribution layer 130. The first lower redistribution layer 110, the second lower redistribution layer 120, and the third lower redistribution layer 130 may constitute a lower redistribution substrate 100. It should be understood that when an element is referred to as being "connected" or "coupled" to another element or being "on" another element, it may be directly connected or coupled to the other element or directly on the other element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0049] like Fig. 22 As shown, Fig.21 The resulting structure can be oriented upside down. Fig. 22 In this orientation of the resulting structure, the lower redistribution substrate 100 is located below the insulating layer 300, and the active surface of the semiconductor die 200 faces downward. A protective layer 142 may be formed on the lower redistribution substrate 100. The protective layer 142 may protect the lower redistribution substrate 100. The protective layer 142 may include a polyamide-based polymer material or an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), but the inventive concept is not limited thereto.

[0050] The terminal pads 144 may be formed on the protective layer 142. The terminal pads 144 may penetrate the protective layer 142 to be coupled to the third lower redistribution pattern 136. The terminal pads 144 may include a conductive material such as metal.

[0051] External terminals 150 may be provided on the protective layer 142. For example, the external terminals 150 may be placed on the terminal pads 144. The external terminals 150 may be provided to allow the semiconductor die 200 mounted on the lower redistribution substrate 100 to be placed on a different substrate. The external terminals 150 may include solder balls or solder bumps.

[0052] Thereafter, the second carrier substrate 800 may be removed. For example, the second release layer 820 may be removed to detach the second support substrate 810 from the upper redistribution substrate 500. The second release layer 820 may be removed by a physical method or a chemical treatment.

[0053] The above-described processes may manufacture semiconductor devices according to some example embodiments of the inventive concepts.

[0054] Fig. 22 and Fig.23 Cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts are illustrated.

[0055] Reference Fig. 22 , the semiconductor device may include a lower redistribution substrate 100 , a semiconductor die 200 , an insulating layer 300 , a via 410 , and an upper redistribution substrate 500 .

[0056] The lower redistribution substrate 100 may include a first lower redistribution layer 110, a second lower redistribution layer 120, and a third lower redistribution layer 130 sequentially disposed from top to bottom. The first lower redistribution layer 110, the second lower redistribution layer 120, and the third lower redistribution layer 130 may include a first lower dielectric layer 112, a second lower dielectric layer 122, and a third lower dielectric layer 132, respectively, and may also include a first lower redistribution pattern 116, a second lower redistribution pattern 126, and a third lower redistribution pattern 136 respectively disposed in the first lower dielectric layer 112, the second lower dielectric layer 122, and the third lower dielectric layer 132, respectively. The first lower redistribution pattern 116 may be disposed in the first lower dielectric layer 112, and the first lower seed pattern 114 is interposed between the first lower redistribution pattern 116 and the first lower dielectric layer 112, the second lower redistribution pattern 126 may be disposed in the second lower dielectric layer 122, and the second lower seed pattern 124 is interposed between the second lower redistribution pattern 126 and the second lower dielectric layer 122, and the third lower redistribution pattern 136 may be disposed in the third lower dielectric layer 132, and the third lower seed pattern 134 is interposed between the third lower redistribution pattern 136 and the third lower dielectric layer 132. The lower redistribution substrate 100 may redistribute signals transmitted to and from the semiconductor die 200 using the first lower redistribution layer 110, the second lower redistribution layer 120, and the third lower redistribution layer 130.

[0057] The protective layer 142 may be disposed under the lower redistribution substrate 100. The protective layer 142 may cover the third lower redistribution layer 130 of the lower redistribution substrate 100. The terminal pad 144 may be disposed on the protective layer 142. The terminal pad 144 may penetrate the protective layer 142 to be coupled to the third lower redistribution pattern 136 of the third lower redistribution layer 130.

[0058] The external terminal 150 may be disposed on the protective layer 142. For example, the external terminal 150 may be placed on the terminal pad 144. The external terminal 150 may include a solder ball or a solder bump.

[0059] The semiconductor die 200 may be mounted on the lower redistribution substrate 100. The semiconductor die 200 may be disposed such that an active surface thereof faces the first lower redistribution layer 110 of the lower redistribution substrate 100.

[0060] The semiconductor die 200 may be coupled to the first lower seed pattern 114 and the first lower redistribution pattern 116 of the first lower redistribution layer 110 through the die pad 210 .

[0061] The first lower dielectric layer 112 of the first lower redistribution layer 110 may have a portion protruding upward below the semiconductor die 200 and in contact with an active surface of the semiconductor die 200 . The first lower dielectric layer 112 may surround the die pad 210 .

[0062] The insulating layer 300 may be disposed on the lower redistribution substrate 100. The insulating layer 300 may cover the top surface of the lower redistribution substrate 100 and may surround the semiconductor die 200. The insulating layer 300 may cover the side surface and the top surface of the semiconductor die 200.

[0063] According to some other embodiments, Fig.23 As shown, the semiconductor die 200 may be spaced apart from the first lower dielectric layer 112 of the lower redistribution substrate 100. The semiconductor die 200 may be coupled to the first lower redistribution pattern 116 through a die pad 210 disposed between the first lower dielectric layer 112 and the semiconductor die 200. The insulating layer 300 may extend between the semiconductor die 200 and the first lower dielectric layer 112 to fill the space between the semiconductor die 200 and the first lower dielectric layer 112. Between the semiconductor die 200 and the first lower dielectric layer 112, the insulating layer 300 may surround the die pad 210. The following will focus on Fig. 22 Embodiment of the invention.

[0064] The via 410 may be disposed in the insulating layer 300. The via 410 may vertically penetrate the insulating layer 300 at the side of the semiconductor die 200. The via 410 may have a width that gradually decreases as it approaches the lower redistribution substrate 100. The via 410 may penetrate the insulating layer 300 and may protrude onto the bottom surface of the insulating layer 300. The via 410 may extend into the first lower dielectric layer 112 of the lower redistribution substrate 100, thereby being coupled to the first lower redistribution pattern 116. The first lower seed pattern 114 may be interposed between the via 410 and the first lower redistribution pattern 116. For example, the via 410 may have a bottom surface that contacts the first lower seed pattern 114. Fig. 20 As shown, at the interface between the via 410 and the first lower seed pattern 114, the width of the via 410 may be greater than that of the first lower seed pattern 114. In addition, the width of the via 410 at the bottom surface may be greater than that of the first lower redistribution pattern 116 at the top surface.

[0065] The via seed layer 420 may be interposed between the insulating layer 300 and the via 410. For example, the via seed layer 420 may surround the side surface of the via 410. The bottom surface of the via 410 may not be covered by the via seed layer 420 but may be exposed with respect to the via seed layer 420. Therefore, the via 410 may directly contact the first lower seed pattern 114.

[0066] The upper redistribution substrate 500 may be disposed on the insulating layer 300. The upper redistribution substrate 500 may include a first upper redistribution layer 510 and a second upper redistribution layer 520 disposed on the insulating layer 300. The first upper redistribution layer 510 and the second upper redistribution layer 520 may include a first upper dielectric layer 512 and a second upper dielectric layer 522, respectively, and may further include a first upper redistribution pattern 516 and a second upper redistribution pattern 526 disposed in the first upper dielectric layer 512 and the second upper dielectric layer 522, respectively. The first upper redistribution pattern 516 may be disposed in the first upper dielectric layer 512, and the first upper seed pattern 514 is interposed between the first upper redistribution pattern 516 and the first upper dielectric layer, and the second upper redistribution pattern 526 may be disposed in the second upper dielectric layer 522, and the second upper seed pattern 524 is interposed between the second upper redistribution pattern 526 and the second upper dielectric layer 522. The first upper redistribution pattern 516 of the first upper redistribution layer 510 may be coupled to the via 410. The second upper dielectric layer 522 of the second upper redistribution layer 520 may cover the second upper redistribution pattern 526. The second upper dielectric layer 522 may have a first recess RS1 exposing a portion of the second upper redistribution pattern 526.

[0067] The semiconductor device may be arranged and configured as described above.

[0068] Or, when using Figure 5 When a semiconductor device is manufactured using the first carrier substrate 700 that does not include the barrier 732 as shown in the embodiment of the present invention, the active surface of the semiconductor die 200 may not contact the lower redistribution substrate 100. Fig.23 As shown, the insulating layer 300 may fill the space between the lower redistribution substrate 100 and the active surface of the semiconductor die 200, and the semiconductor die 200 may be coupled to the lower redistribution substrate 100 through the die pad 210. For example, on the lower redistribution substrate 100, the insulating layer 300 may cover the semiconductor die 200 and may extend between the semiconductor die 200 and the lower redistribution substrate 100.

[0069] Fig.24 Cross-sectional views of semiconductor devices according to some example embodiments of the inventive concepts are illustrated.

[0070] Reference Fig.24 , the semiconductor device may include a lower package 10 and an upper package 20. The lower package 10 may be Fig. 22 The discussed lower redistribution substrate 100, the semiconductor die 200, the insulating layer 300, the via 410 and the upper redistribution substrate 500 are composed.

[0071] The upper package 20 may be disposed on the lower package 10. The upper package 20 may include an upper package substrate 610, an upper semiconductor die 620 mounted on the upper package substrate 610, and an upper molding layer 630 covering the upper semiconductor die 620 on the upper package substrate 610. The upper package substrate 610 may include a printed circuit board (PCB) or a redistribution substrate. The upper semiconductor die 620 may be flip-chip mounted on the upper package substrate 610. For example, the upper semiconductor die 620 may be connected to the upper package substrate 610 by an upper die bump 622. For another example, the upper semiconductor die 620 may be mounted to the upper package substrate 610 by wire bonding. The upper molding layer 630 may include an epoxy molding compound (EMC).

[0072] The upper package 20 may include a connection terminal 614 disposed below the upper package substrate 610. The connection terminal 614 may be coupled to a substrate pad of the upper package substrate 610, and may be coupled to a second upper redistribution pattern 526 of an upper redistribution substrate 500 included in the lower package 10, the second upper redistribution pattern 526 being exposed to the first recess RS1. For example, the upper package 20 may be coupled to the upper redistribution substrate 500 through the connection terminal 614, and the upper redistribution substrate 500 may redistribute the upper package 20 to be electrically connected to the via 410.

[0073] The method of manufacturing a semiconductor device according to some example embodiments of the inventive concept may include placing a semiconductor die on a carrier substrate and then coating an insulating material to form an insulating layer. Therefore, process defects such as damage to the semiconductor die due to deformation of the insulating layer during the manufacturing process or delamination of the semiconductor die or the insulating layer from the carrier substrate may be reduced.

[0074] According to the inventive concept, the seed layer may have a portion located in the through hole, and the portion of the seed layer may receive power from the conductive layer having low resistance, and as a result, the electroplating process may be easily performed in the through hole. As a result, defects such as the formation of voids within the via in the through hole or the failure of conductive material filling in the through hole during the electroplating process may be avoided.

[0075] According to the inventive concept, a planarization process may not be performed in a process for forming a via and an upper redistribution pattern, and thus, damage to a semiconductor die caused by the planarization process may be prevented.

[0076] Although the present invention has been described in conjunction with the exemplary embodiments of the present invention shown in the accompanying drawings, it will be understood by those skilled in the art that changes in form and detail may be made thereto without departing from the spirit and essential features of the present invention. Therefore, the embodiments disclosed above should be considered illustrative rather than restrictive.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: providing a carrier substrate, the carrier substrate comprising a conductive layer; placing a semiconductor die on the carrier substrate; forming an insulating layer to cover the semiconductor die on the carrier substrate; forming a through hole to penetrate the insulating layer at a side of the semiconductor die and expose the conductive layer of the carrier substrate; forming a seed layer covering a bottom surface and an inner side surface of the through hole, wherein the seed layer is in contact with the conductive layer of the carrier substrate; performing an electroplating process to form a via filling the through hole, wherein the conductive layer and the seed layer serve as seeds; forming a first redistribution layer on the first surface of the insulating layer; removing the carrier substrate; and A second redistribution layer is formed on the semiconductor die and the second surface of the insulating layer, the first surface and the second surface facing each other.

2. The method according to claim 1, wherein: The seed layer includes a first portion located on the bottom surface of the through hole and a second portion located on the inner side surface of the through hole, Wherein, when the carrier substrate is removed, the first portion of the seed layer is removed simultaneously.

3. The method according to claim 1, wherein: The electroplating process utilizes power applied to the conductive layer of the carrier substrate.

4. The method according to claim 1, wherein: After removing the carrier substrate, the bottom surface of the via is exposed.

5. The method according to claim 1, wherein: The through-hole extends into the carrier substrate.

6. The method according to claim 5, wherein: A bottom surface of the via protrudes beyond the second surface of the insulating layer.

7. The method according to claim 1, wherein: Forming the second redistribution layer includes: forming a dielectric layer on the semiconductor die and the second surface of the insulating layer; forming a patterned hole to penetrate the dielectric layer and expose a bottom surface of the via; forming a seed pattern in the pattern hole to contact the bottom surface of the via; and A redistribution pattern is formed on the seed pattern.

8. The method according to claim 7, wherein: At an interface between the via and the seed pattern, a width of the via is greater than a width of the seed pattern.

9. The method according to claim 1, wherein: The second surface of the semiconductor die is an active surface, and A plurality of die pads of the semiconductor die are electrically connected to the second redistribution layer.

10. The method according to claim 9, wherein: The carrier substrate includes a barrier on a top surface of the carrier substrate, The insulating layer surrounds the die pad below the semiconductor die before removing the carrier substrate, The bottom surface of the die pad is located at the same level as the bottom surface of the insulating layer, and During the formation of the second redistribution layer, a dielectric layer of the second redistribution layer fills a space between the insulating layer and the die pad.

11. A method for manufacturing a semiconductor device, the method comprising: providing a carrier substrate including a conductive layer; placing a semiconductor die on the carrier substrate such that an active surface of the semiconductor die faces the carrier substrate; forming an insulating layer on the carrier substrate, the insulating layer surrounding the semiconductor die; etching the insulating layer to form a through hole penetrating the insulating layer and exposing the conductive layer of the carrier substrate; forming a seed layer to cover a bottom surface and an inner side surface of the through hole, the seed layer being in contact with the conductive layer of the carrier substrate; performing an electroplating process to form a via filling the through hole, wherein the conductive layer and the seed layer serve as seeds; forming a first redistribution layer over the semiconductor die and the insulating layer; removing the carrier substrate, wherein removing the carrier substrate comprises: removing a portion of the seed layer simultaneously with removing the carrier substrate, the portion of the seed layer being located on the bottom surface of the through hole; and forming a second redistribution layer below the semiconductor die and the insulating layer, The bottom surface of the through hole is located at a level lower than the active surface of the semiconductor die and lower than the bottom surface of the insulating layer.

12. The method according to claim 11, wherein: After removing the carrier substrate, the bottom surface of the via is exposed, and Wherein, the bottom surface of the via contacts the redistribution pattern of the second redistribution layer.

13. The method according to claim 11, wherein: The via protrudes beyond the bottom surface of the insulating layer.

14. The method according to claim 11, wherein: Forming the second redistribution layer includes: forming a dielectric layer to cover the active surface of the semiconductor die and the bottom surface of the insulating layer; etching the dielectric layer to form patterned holes exposing the vias; forming a seed pattern in the pattern hole to contact the via; and A redistribution pattern is formed on the seed pattern.

15. A semiconductor device comprising: Lower redistribution layer; a semiconductor die located on the lower redistribution layer; an insulating layer, the insulating layer being located on the lower redistribution layer, the insulating layer surrounding the semiconductor die; a via penetrating the insulating layer and coupled to the redistribution pattern of the lower redistribution layer; a seed layer, the seed layer being located between the via and the insulating layer, the seed layer surrounding the entire side surface of the via without covering the bottom surface of the via; as well as an upper redistribution layer, the upper redistribution layer being located on the insulating layer and the semiconductor die, the upper redistribution layer being coupled to the via, wherein a bottom surface of the via is exposed relative to the seed layer, and Wherein, the via extends into the lower redistribution layer.

16. The device according to claim 15, wherein The bottom surface of the via is located at a level lower than that of the bottom surface of the insulating layer and lower than that of the bottom surface of the semiconductor die.

17. The device according to claim 15, wherein The lower redistribution layer comprises: a dielectric layer covering a bottom surface of the insulating layer and a bottom surface of the semiconductor die; the redistribution pattern penetrating the dielectric layer and coupled to the via; and A seed pattern is located between the redistribution pattern and the bottom surface of the via, the seed pattern contacting the bottom surface of the via.

Images