Die packaging structure and electronic device

Abstract

The present application relates to the technical field of dies, and provides a die packaging structure and an electronic device, which can satisfy the high-bandwidth density requirement for dies while supporting heterogeneous die integration. The die packaging structure comprises a first die, an electronic element and a hybrid interposer of a novel structure. The hybrid interposer comprises a silicon interposer and a redistribution layer, a metal wiring layer is provided on the front surface of the silicon interposer, and a through silicon via is formed in the silicon interposer. The first die is disposed on the front surface of the silicon interposer and is electrically connected to the metal wiring layer. Alternatively, the hybrid interposer comprises a first redistribution layer, a second redistribution layer, a bridge die located between the two redistribution layers, and a metal connecting structure, and the bridge die achieves interconnection between first dies by means of the first redistribution layer. The second redistribution layer is connected to the first redistribution layer by means of the metal connecting structure. The electronic element is located on the back surface of the redistribution layer, is connected to the redistribution layer or is connected to the redistribution layer by means of a substrate.

Description

Chip packaging structure and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 3, 2023, with application number 202311469345.7 and invention name “Chip packaging structure and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip technology, and in particular to a chip packaging structure and electronic equipment. Background Art

[0003] System-in-a-package (SiP) technology is an integrated circuit packaging technology that integrates multiple dies and passive components into a single package. In the post-Moore era, SiP technology can help increase the integration density of finished chips, reduce their size, and lower power consumption.

[0004] The prior art provides a system-level packaging structure, which cuts out a largest complete continuous square from a wafer as a chip, with an area of ​​up to 46225mm 2 This structure suffers from low yield due to the large wafer area, making it impossible to select and reintegrate known good dies (KGDs) on the wafer, nor can it support the integration of heterogeneous chips. Furthermore, the large chip area requires a large substrate for power supply and signal transmission, complicating the stress risk, power supply, and heat dissipation implementation of the entire system.

[0005] To support KGD selection and heterogeneous chip integration, existing technologies also offer another system-level packaging structure that interconnects multiple dies on the redistribution layer (RDL) through re-constribution. However, because multiple dies are interconnected via RDL in this packaging structure, the bandwidth density between dies cannot be very high, reaching only approximately 0.8Tbps / mm. This cannot support high-density interconnection with higher bandwidth, and therefore cannot meet the requirements of high-bandwidth density between dies.

[0006] Summary of the Invention

[0007] The present application provides a chip packaging structure and an electronic device that can meet the high bandwidth density requirements between chips while supporting heterogeneous chip (die) integration.

[0008] The present application provides a chip packaging structure, which includes a silicon interposer (Siinterposer), at least one first chip, at least one electronic component, and a redistribution layer. The front side of the silicon interposer has a metal wiring layer, and a through silicon via (TSV) is provided in the silicon interposer. The redistribution layer is located on the back side of the silicon interposer and is electrically connected to the TSV. The first chip is located on the front side of the silicon interposer and is electrically connected to the metal wiring layer on the front side of the silicon interposer. The electronic component is located on the side of the redistribution layer away from the first chip and is electrically connected to the redistribution layer or connected to the redistribution layer through a substrate.

[0009] In this chip packaging structure, the metal routing layer on the front of the silicon interposer can be processed using a silicon-based process, so that the line width, line spacing, and line thickness of the metal routing in this metal routing layer can meet the high-bandwidth density interconnection requirements between multiple chips (the first chip), such as interconnection bandwidth density exceeding 2Tbps / mm. The redistribution layer on the back of the silicon interposer can use thick metal layers and thick dielectric layers with better current sharing capabilities, thereby meeting the electronic components' demand for high-speed serdes (serializer / deserializer) drivers with large current sharing capabilities, low impedance, and long distances.

[0010] In some possible implementations, the line width, line spacing, and line thickness of the metal traces in the metal trace layer located on the active surface side of the silicon interposer are all less than 5μm; the line width, line spacing, and line thickness of the metal traces in the redistribution layer are all greater than 5μm.

[0011] In some possible implementations, the at least one first chip may include one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

[0012] In some possible implementations, the at least one electronic component includes one or more of a power supply module, a control module, a connector, a clock device, a rectifier, and a resistor, capacitor, and inductor.

[0013] In some possible implementations, the chip packaging structure includes: a plurality of first chips and a plurality of electronic components.

[0014] In some possible implementations, the multiple electronic components include multiple power supply modules, which are disposed opposite the multiple first chips. The power supply modules are electrically connected to the corresponding first chips via a redistribution layer and a silicon interposer, and supply power to the first chips.

[0015] In some possible implementations, the chip packaging structure includes multiple discrete substrates. The substrates are located between the redistribution layer and the electronic components, and the multiple electronic components are electrically connected to the redistribution layer through multiple discrete substrates. This allows for flexible selection of substrate types based on the electrical requirements of the electronic components to improve the performance of the entire system. Furthermore, the use of multiple discrete substrates can alleviate the mechanical stress caused by thermal mismatch in assembly and service scenarios brought about by a large continuous substrate, making it more user-friendly for system assembly and service reliability.

[0016] In some possible implementations, the multiple substrates are encapsulated in a molding layer to protect the multiple substrates through the molding layer.

[0017] In some possible implementations, the chip packaging structure further includes a first heat sink and a second heat sink. The first heat sink is disposed on a side of the first chip away from the silicon interposer, and the second heat sink is disposed on a side of the electronic component away from the redistribution layer. The first and second heat sinks provide heat dissipation for the chip packaging structure.

[0018] In some possible implementations, the chip packaging structure further includes: a fixing structure; the fixing structure penetrates and fixes the first heat sink, the second heat sink, and the hybrid adapter plate; wherein the hybrid adapter plate includes a silicon interposer and a redistribution layer.

[0019] The present application also provides a chip packaging structure, which includes at least one first chip, at least one electronic component, a first redistribution layer, a second redistribution layer, at least one bridge chip, and a metal connection structure. The bridge chip and the metal connection structure are connected between the first redistribution layer and the second redistribution layer, and the first redistribution layer is located on the active surface of the bridge chip. The first chip is located on a side of the first redistribution layer away from the bridge chip, and the first chip is electrically connected to the bridge chip through the first redistribution layer. The electronic component is located on a side of the second redistribution layer away from the first redistribution layer, and is connected to the second redistribution layer or connected to the second redistribution layer through a substrate.

[0020] In this chip packaging structure, since the bridge chip can be manufactured using a silicon-based process, the line width, line spacing, and line thickness of the metal traces on the surface of the bridge chip can meet the high-bandwidth density interconnection requirements between chips. On this basis, the first redistribution layer can use a thin metal layer and a thin dielectric layer. Through the first redistribution layer, the active surface of the bridge chip can be directly brought out in the area of ​​the bridge chip, thereby achieving the high-bandwidth density interconnection requirements between chips (first chip). The second redistribution layer on the back of the bridge chip can use a thick metal layer and a thick dielectric layer with better current sharing capability, thereby meeting the electronic components' requirements for high-speed serdes driving with large current sharing capability, low impedance, and long distance.

[0021] In some possible implementations, the line width, line spacing, and line thickness of the metal traces in the first redistribution layer are all less than 5 μm; and the line width, line spacing, and line thickness of the metal traces in the second redistribution layer are all greater than 5 μm.

[0022] In some possible implementations, the metal connection structure includes metal pillars; and the bridge chip and the metal pillars are encapsulated in a molding layer.

[0023] In some possible implementations, a glass wafer is disposed between the first redistribution layer and the second redistribution layer, a groove is disposed in the glass wafer, and the bridge chip is embedded in the groove; the metal connection structure includes a through glass via (TGV) penetrating the glass wafer.

[0024] In some possible implementations, the at least one first chip may include one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

[0025] In some possible implementations, the at least one electronic component includes one or more of a power supply module, a control module, a connector, a clock device, a rectifier, and a resistor, capacitor, and inductor.

[0026] In some possible implementations, the chip packaging structure includes: a plurality of first chips and a plurality of electronic components.

[0027] In some possible implementations, a bridge chip may be included in the chip packaging structure. The bridge chip is located between two adjacent first chips, and the bridge chip connects the two adjacent first chips through a first redistribution layer.

[0028] In some possible implementations, the multiple electronic components include multiple power supply modules, which are respectively disposed opposite to the multiple first chips. The power supply modules are electrically connected to the oppositely disposed first chips via a redistribution layer and a bridge chip, and supply power to the first chips.

[0029] In some possible implementations, the chip packaging structure includes multiple discrete substrates. The substrate is located between the second redistribution layer and the electronic components, and the multiple electronic components are electrically connected to the second redistribution layer via multiple discrete substrates. In this way, the types of multiple substrates can be flexibly selected according to the electrical requirements of the electronic components to improve the performance of the entire system. In addition, the use of multiple discrete substrates can also alleviate the mechanical stress caused by thermal mismatch in assembly and service scenarios brought about by a large continuous substrate, which is more friendly to system assembly and service reliability.

[0030] In some possible implementations, the multiple substrates are encapsulated in a molding compound to protect the multiple substrates through the molding layer.

[0031] In some possible implementations, the chip packaging structure further includes: a first heat sink and a second heat sink. The first heat sink is disposed on a side of the first chip away from the first redistribution layer, and the second heat sink is disposed on a side of the electronic component away from the second redistribution layer. The first and second heat sinks are provided to dissipate heat from the chip packaging structure.

[0032] In some possible implementations, the chip packaging structure further includes a fixing structure that penetrates and secures the first heat sink, the second heat sink, and the hybrid adapter plate; wherein the hybrid adapter plate includes a first redistribution layer, a second redistribution layer, and an interposer (including a bridge chip and a metal connection structure) connected between the first and second redistribution layers.

[0033] The present application also provides an electronic device, which includes a circuit board and any possible chip packaging structure as described above, wherein the chip packaging structure is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0035] FIG2 is a schematic diagram of a chip packaging structure provided in Example 1 of the present application;

[0036] FIG3 is a schematic diagram of a chip packaging structure provided in Example 1 of the present application;

[0037] FIG4 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 1 of the present application;

[0038] FIG5 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 1 of the present application;

[0039] FIG6 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 1 of the present application;

[0040] FIG7 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 1 of the present application;

[0041] FIG8 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 1 of the present application;

[0042] FIG9 is a schematic diagram of a chip packaging structure provided in Example 2 of the present application;

[0043] FIG10 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 2 of the present application;

[0044] FIG11 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 2 of the present application;

[0045] FIG12 is a schematic diagram of a chip packaging structure provided in the second embodiment of the present application during the manufacturing process;

[0046] FIG13 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 2 of the present application;

[0047] FIG14 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 2 of the present application;

[0048] FIG15 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 2 of the present application;

[0049] FIG16 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 2 of the present application;

[0050] FIG17 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 2 of the present application;

[0051] FIG18 is a schematic diagram of a chip packaging structure provided in Example 3 of the present application;

[0052] FIG19 is a schematic diagram of a chip packaging structure during the manufacturing process provided in Example 3 of the present application;

[0053] FIG20 is a schematic diagram of a chip packaging structure during the manufacturing process provided by an embodiment of the present application;

[0054] FIG21 is a schematic diagram of a chip packaging structure during the manufacturing process provided by an embodiment of the present application;

[0055] FIG22 is a schematic diagram of a chip packaging structure during the manufacturing process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0057] The terms "first", "second", etc. in the specification, embodiments, claims, and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0058] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc., and the present application does not impose any restrictions on this.

[0059] For example, the above-mentioned consumer electronic products may include mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products may include smart door locks, televisions, smart speakers, refrigerators, robot vacuums, etc. Car-mounted electronic products may include car navigation systems, car displays, etc. Financial terminal products may include automated teller machines (ATMs) and electronic devices for self-service transactions, etc. Communication electronic products may include communication equipment such as servers, storage devices, radars, and base stations.

[0060] The electronic device includes a printed circuit board (PCB) and a chip package structure electrically connected to the PCB. The chip package structure can be a system-in-package (SIP) structure. Referring to FIG1 , the chip package structure employs a novel hybrid adapter board 10. This hybrid adapter board 10 supports heterogeneous die integration while meeting high bandwidth density requirements between chips.

[0061] As an illustration, in some possible implementations, the hybrid adapter plate 10 provided in the embodiment of the present application can achieve an interconnection bandwidth density of more than 2 Tbps / mm.

[0062] This application does not limit the application scenarios of the above chip packaging structure. For example, the chip packaging structure can be used in scenarios such as large servers, high-bandwidth switches, and supercomputers for AI computing.

[0063] The novel hybrid transfer board 10 used in the chip packaging structure provided by the present application is described in detail below in conjunction with specific embodiments.

[0064] Example 1

[0065] Schematically, as shown in FIG2 , this embodiment 1 provides a chip packaging structure, which includes a hybrid transfer board 10a, at least one chip D (also referred to as a first chip), and at least one electronic component 20; the following description is based on multiple chips D and multiple electronic components 20 as examples.

[0066] The chip D may be a central processing unit (CPU), a graphics processing unit (GPU), a memory, an input / output chip (I / O), an integrated passive device (IPD), etc. It may also be an integrated packaged functional module such as HBM (high bandwidth memory), DOI (die on silicon interposer), FOI (fan out RDL interpose), etc. In practice, multiple chips D may be provided as needed.

[0067] The electronic components 20 may include a power supply module, a control module, a connector, a clock device, a rectifier, a resistor, a capacitor, and an inductor. The power supply module may be a voltage regulator module (VRM) or other modules related to electrical transmission, voltage transformation, and rectification. The connector may be an electrical connector for transmitting electrical signals or an optoelectronic converter for transmitting optical signals. In practice, multiple electronic components 20 may be provided as needed.

[0068] 2 , the hybrid interposer 10 a includes a silicon interposer and a redistribution layer (RDL).

[0069] As shown in Figure 2, the silicon interposer includes a silicon wafer a1 and a metal routing layer a2 disposed on the surface of silicon wafer a1 (the surface away from the RDL). Silicon wafer a1 is provided with multiple through silicon vias (TSVs). The metal routing layer a2 is connected to the multiple TSVs. As shown, the aperture of the multiple TSVs can range from 1μm to 30μm.

[0070] In the application, the front side of the silicon interposer is the surface of the silicon interposer on the side where the metal trace layer a2 is provided. The back side of the silicon interposer is the surface of the silicon wafer a1 on the side where the metal trace layer a2 is not provided, that is, the back side of the silicon wafer a1 (the surface away from the metal trace layer a2).

[0071] The redistribution layer RDL (redistribution layer) is located on the back side of the silicon wafer a1 (wafer) (i.e., the surface away from the metal wiring layer a2), and the redistribution layer RDL is connected to the metal wiring layer a2 through multiple silicon vias TSV in the silicon wafer a1.

[0072] The plurality of chips D are disposed on the front surface of a silicon interposer, and connection pads are provided on the front surface of the silicon interposer for electrical connection.

[0073] The plurality of electronic components 20 are disposed below the redistribution layer RDL and are electrically connected to the redistribution layer RDL, thereby achieving electrical connection with the plurality of chips D through the redistribution layer RDL and a silicon interposer.

[0074] In the first embodiment, the metal trace layer a2 on the surface of the silicon interposer (Siinterposer) can be processed using a silicon-based process, so that the metal traces in the metal trace layer a2 have a smaller line width, line spacing, and line thickness, thereby meeting the high-bandwidth interconnection requirements between multiple chips D, such as an interconnection bandwidth density of more than 2Tbps / mm. In some possible implementations, the metal trace layer a2 can be implemented using a damascene process including deposition, exposure, etching, electroplating, and chemical mechanical polishing (CMP).

[0075] As shown, the line width, line spacing and line thickness in the metal routing layer a2 can reach 0.4 μm, and the number of layers can be processed to more than 3 layers.

[0076] Illustratively, in some possible implementations, the line width in the metal wiring layer a2 may be less than 5 μm, but is not limited thereto.

[0077] Illustratively, in some possible implementations, the thickness of the metal wiring layer a2 (ie, the thickness of a single metal layer) may be less than 5 μm, but is not limited thereto.

[0078] Illustratively, in some possible implementations, the line pitch of the metal wiring layer a2 may be less than 5 μm, but is not limited thereto.

[0079] Illustratively, in some possible implementations, the metal routing layer a2 may include 3 to 10 wiring layers (also referred to as metal wiring layers), but is not limited thereto.

[0080] Illustratively, in some possible implementations, the wiring layer in the metal routing layer a2 may be made of copper (Cu), but is not limited thereto.

[0081] In some possible implementations, the dielectric layer in the metal wiring layer a2 can be made of one or more insulating dielectric materials such as polyimide (PI), polybenzoxazoles (PBO), silicon dioxide SiO2, silicon nitride SiN, and silicon carbon nitride SiCN, but is not limited thereto.

[0082] Illustratively, in some possible implementations, the thickness of the dielectric layer in the metal wiring layer a2 may be in the range of 0.1 μm to 5 μm, but is not limited thereto.

[0083] As shown, in some possible implementation methods, the surface of the metal routing layer a2 can be provided with multiple micro pads (solder points), the spacing between the micro pads can be between 10μm and 200μm, and the metal routing layer a2 is welded to multiple chips D through multiple micro pads; in some non-welding connection methods for interconnection, such as HB (Hybrid bonding, hybrid direct bonding), the spacing between the connection points may even be reduced to the order of 1 to 10um.

[0084] In addition, as shown in reference Figure 2, the redistribution layer RDL can adopt thick metal layers and thick dielectric layers with better current sharing capability. For example, the line width, line spacing, and line thickness of the metal traces in the redistribution layer RDL can be above 5μm, thereby being able to meet the electronic component 20's high-speed serdes (serializer / deserializer, serializer / deserializer) driving requirements with large current sharing capability, low impedance, and long distance (such as above 5mm).

[0085] For example, in some possible implementations, the redistribution layer (RDL) may be implemented through a yellow light process including steps such as coating / filming, exposure, development, and curing.

[0086] Illustratively, in some possible implementations, the line width in the redistribution layer (RDL) may be in the range of 5 μm to 30 μm, but is not limited thereto.

[0087] Illustratively, in some possible implementations, the line pitch in the redistribution layer (RDL) may be in the range of 6 μm to 20 μm, but is not limited thereto.

[0088] Illustratively, in some possible implementations, the line thickness of the redistribution layer (RDL) may be in the range of 6 μm to 20 μm, but is not limited thereto.

[0089] Illustratively, in some possible implementations, the redistribution layer RDL may include 3 to 6 wiring layers, but is not limited thereto.

[0090] Illustratively, in some possible implementations, the thickness of the dielectric layer in the redistribution layer (RDL) may be in the range of 10 μm to 40 μm, but is not limited thereto.

[0091] For example, in some possible implementations, the wiring layer in the redistribution layer RDL may be made of copper (Cu), but is not limited thereto.

[0092] For example, in some possible implementations, the dielectric layer in the redistribution layer RDL may be made of one or more dielectric materials such as polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO), but is not limited thereto.

[0093] As shown, in some possible implementations, a plurality of large pads may be provided on the lower surface of the redistribution layer (RDL), and the spacing between the large pads may be between 200 μm and 1500 μm. The redistribution layer (RDL) is electrically interconnected with the plurality of electronic components 20 via the plurality of large pads. The electrical interconnection between the redistribution layer (RDL) and the electronic components 20 may be established by welding, crimping, plugging, or the like.

[0094] In summary, the new hybrid adapter board 10a provided in the first embodiment includes a silicon interposer (Siinterposer) and a redistribution layer RDL. On the one hand, a metal routing layer a2 with a smaller line width / line spacing / line thickness is formed on the surface of the silicon interposer (Siinterposer) to meet the interconnection requirements of high bandwidth density between chips D. On the other hand, the redistribution layer RDL adopts a thick metal layer and a thick dielectric layer, which can meet the requirements of large current sharing and long routing capabilities of the electronic components 20. In other words, the new hybrid adapter board 10a can integrate the medium that realizes high bandwidth density with the two media that realize large current sharing and long routing capabilities. In this way, the packaging structure of the new hybrid adapter board 10a can support high bandwidth density between heterogeneous chips and support long-distance Serdes driving capabilities, thereby meeting the integration requirements of large systems and improving system energy utilization and computing efficiency.

[0095] The present application does not impose any restrictions on the connection method between the multiple electronic components 20 and the redistribution layer RDL. The multiple electronic components 20 and the redistribution layer RDL can be directly connected or indirectly connected through other devices. In practice, they can be set as needed.

[0096] Illustratively, in some possible implementations, the electronic component 20 may be directly connected to the lower surface of the redistribution layer RDL.

[0097] Illustratively, in some possible implementations, a plurality of electronic components 20 may be connected to a lower surface of a redistribution layer (RDL) through a substrate, wherein the substrate may be located between the electronic components 20 and the redistribution layer (RDL).

[0098] The substrate may be manufactured using one or more of a substrate process, a carrier-like process, or a printed circuit board (PCB) process, and this application does not impose any restrictions thereto.

[0099] In order to meet the electrical requirements of multiple electronic components 20, in some possible implementation methods, as shown in Figure 2, multiple discrete substrates 30 can be used, and the number of layers and specifications of the multiple substrates 30 may not be exactly the same. In this case, multiple electronic components 20 can be connected to the redistribution layer RDL through multiple discrete substrates 30. Among them, one electronic component 20 can be installed on a single discrete substrate 30, or multiple electronic components 20 can be installed. This application does not limit this, and it can be set as needed in practice. In this way, the types of multiple substrates 30 can be flexibly selected according to the electrical requirements of the electronic components 20 to improve the performance of the entire system. For example, a multi-layer substrate can be configured only for electronic components 20 that require a complex multi-layer substrate, while a simple substrate can be configured for electronic components 20 that require a simple substrate.

[0100] In addition, the use of multiple discrete substrates 30 can also alleviate the mechanical stress caused by thermal mismatch during assembly and service scenarios brought by a large continuous substrate, which is more friendly to system assembly and service reliability. This application does not restrict the electrical connection method between the substrate 30 and the redistribution layer (RDL), and it can be set as needed in practice.

[0101] Illustratively, in some possible implementations, the plurality of substrates 30 and the redistribution layer RDL may be connected to each other through one or a combination of connection methods such as welding, crimping, and plugging.

[0102] In order to protect the multiple substrates 30, as shown in Figure 3, in some possible implementation methods, a thermosetting material can be used to fill the bottom of the multiple substrates 30 and the gaps between the substrates 30. After filling, the back side of the substrate 30 and the connection structure (such as Cu Stud) can be exposed by grinding to form a mold layer M1 to protect the multiple substrates 30.

[0103] The thermosetting materials involved in this application may include underfill (UF), molded underfill (MUF), epoxy molding compound, etc., which will be described in detail below.

[0104] Similarly, in order to protect multiple chips D, in some possible implementation methods, referring to Figure 2 or Figure 3, a thermosetting material can be used to first fill and protect the bottom of multiple chips D through bottom filling (underfill), and then use molding (molding or molding underfill) to encapsulate the multiple chips D in the mold layer M2 to form protection.

[0105] In addition, in some possible implementations, as shown in FIG2 or FIG3 , a first heat sink 41 and a second heat sink 42 may be further provided in the chip packaging structure. The first heat sink 41 is provided on a side of the plurality of chips D away from the hybrid adapter plate 10 a, and the second heat sink 42 is provided on a side of the plurality of electronic components 20 away from the hybrid adapter plate 10 a. The two heat sinks (41, 42) are provided to meet the heat dissipation requirements of the chip packaging structure.

[0106] As shown, the gap between the chip D and the first heat sink 41 can be filled with thermal interface materials (TIM). The TIM can be a heat dissipation medium such as thermal gel, thermal grease, graphene, or liquid metal, and is not limited here. Similarly, the gap between the electronic component 20 and the second heat sink 42 can also be filled with TIM.

[0107] The present application does not impose any restrictions on the arrangement of the heat dissipation plates (41, 42), which can be arranged as needed in practice.

[0108] For example, in some possible implementations, the heat dissipation plates (41, 42) may be metal cover plates.

[0109] For another example, in some possible implementations, the heat sinks (41, 42) may be hollow structures to support water cooling or liquid cooling.

[0110] For another example, the heat sink (41, 42) may have a hollow structure such as a through-hole structure or a grid. In this case, the heat sink can meet the heat dissipation requirements while supporting the external power supply system to be vertically interconnected with the electrical components 20 on the back of the chip through the hollow area.

[0111] In the packaging structure, the thickness, material, and structure of the first heat dissipation plate 41 and the second heat dissipation plate 42 may be the same or different, and this application does not impose any limitation thereto.

[0112] In addition, referring to FIG3 , in some possible implementations, in order to ensure balanced force inside the chip packaging structure, a support frame 43 may be provided in the chip packaging structure. The support frame 43 is located in the gap between the electronic components 20, and the upper end of the support frame 43 may contact the substrate 30, and the lower end may contact the second heat dissipation plate 42. On this basis, in order to fix the first heat dissipation plate 41, the second heat dissipation plate 42, the support frame 43 and the packaging system, as shown in FIG2 or FIG3 , in some possible implementations, a fixing structure 50 may be provided in the chip packaging structure. The fixing structure 50 passes through the first heat dissipation plate 41, the second heat dissipation plate 42, the support frame 43 and the hybrid adapter plate 10a, and supports and fixes the first heat dissipation plate 41, the second heat dissipation plate 42, the support frame 43 and the hybrid adapter plate 10a.

[0113] Schematically, as shown in Figures 2 or 3, in some possible implementations, the fixing structure 50 may include bolts and nuts. The bolts penetrate the first heat sink 41, the second heat sink 42, and the hybrid adapter plate 10a, and the nuts are fixed at one end of the bolts, thereby securing the first heat sink 41, the second heat sink 42, and the hybrid adapter plate 10a. In this case, the first heat sink 41 and the second heat sink 42 not only provide heat dissipation but also stabilize the structure.

[0114] Of course, the chip packaging structure may also be provided with other devices or component structures according to actual needs.

[0115] The chip packaging structure is further described below in conjunction with a method for manufacturing the chip packaging structure.

[0116] Schematically, this embodiment 1 provides a method for manufacturing a chip packaging structure, which may include:

[0117] First, referring to FIG4 (a), a silicon wafer a1 is provided, and a plurality of through-silicon vias (TSVs) are fabricated on the silicon wafer a1. A damascene process including deposition, exposure, etching, electroplating, CMP and other steps is adopted to fabricate a metal wiring layer a2 on the surface of the silicon wafer a1 to form a silicon interposer.

[0118] After making multiple metal wiring layers in the metal routing layer a2, micro pads will be made on the surface for subsequent welding with the chip D. The spacing between the micro pads can be between 10μm and 200μm. For related instructions, please refer to the previous article and will not be repeated here.

[0119] Next, referring to (b) and (c) in FIG4 , the side of the silicon interposer (Siinterposer) provided with the metal routing layer a2 is fixed on the first carrier 01, and a redistribution layer RDL is made on the back of the silicon wafer a1 to form a hybrid adapter board 10a.

[0120] The carrier plates involved in this application (such as the first carrier plate and the second carrier plate) can be metal plates, glass and other supports. This application does not impose any restrictions on this, and in practice, they can be set as needed.

[0121] Schematically, in some possible implementation methods, the process of forming the redistribution layer RDL may include: referring to FIG4 (a), a temporary bonding method may be used to fix the side of the silicon interposer (Siinterposer) provided with the metal routing layer a2 on the glass carrier (01), and the back side of the silicon wafer a1 is thinned to a desired thickness (e.g., 10 μm to 300 μm) by grinding and chemical mechanical polishing (CMP) processes, and the through silicon vias TSV are exposed; then, a layer of insulating film may be processed by PVD (physical vapor deposition) or CVD (chemical vapor deposition) or suspension coating of liquid glue or film lamination, and the material may be an insulating material such as PI, PBO, SiO2, SiN, etc.; next, referring to FIG4 (b), a metal layer and a dielectric layer are grown on the insulating film to form the redistribution layer RDL. Among them, the specific production process flow of the redistribution layer RDL may include: surface pretreatment, organic material coating-exposure-development-curing-seed layer precipitation-organic material coating-exposure-development-electroplating-photoresist removal-seed layer etching, etc.; after the multi-layer metal wiring layer, large pads will be processed for subsequent welding with electronic components 20, and the spacing between the centers of adjacent large pads may be between 200μm and 1500μm.

[0122] Next, as shown in Figure 5, temporary bonding can be used to secure the side of the hybrid interposer 10a where the redistribution layer (RDL) is located to a second carrier 02 (e.g., glass). Laser ablation, heat treatment, or other methods can then be used to debond and separate the first carrier 01 from the hybrid interposer 10a, exposing the micro-pad interface on the surface of the silicon interposer.

[0123] Next, referring to Figure 6, multiple chips D (such as multiple heterogeneous chips D) can be mounted on the surface of the silicon interposer (Siinterposer), and the chips D can be welded to the micro pads on the surface of the silicon interposer (Siinterposer); then, a thermosetting material can be used to fill the bottom of the chip and the gap between the chips, and then the backside of the multiple chips D can be ground (backside grinding) to expose the backside of the chip, thereby forming a molding layer M2 to protect the multiple chips D.

[0124] Next, referring to FIG7 , the second carrier 02 can be removed to expose the pads on the surface of the redistribution layer (RDL). In some possible implementations, the second carrier 02 can be debonded and separated from the hybrid interposer 10a by laser ablation, heat treatment, or the like, exposing the pad interface on the surface of the RDL.

[0125] Next, as shown in FIG. 7 , a plurality of substrates 30 are soldered to the pads exposed on the surface of the redistribution layer RDL, and a plurality of electronic components 20 are soldered to the other side of the plurality of substrates 30 .

[0126] Next, referring to FIG7 , the non-routing area of ​​the hybrid adapter board 10a is opened to form a via K. The aperture of the via K can be between 2 mm and 8 mm, so that when the system is finally assembled, a fixing structure 50 (such as a bolt) can be passed through the via K to penetrate the hybrid adapter board 10a to form a reliable mechanical support. Of course, in some possible implementation methods, referring to FIG8 , after welding the multiple substrates 30 to the pads on the surface of the redistribution layer RDL, a thermosetting material can be used to fill the bottom of the multiple substrates 30 and the gaps between the substrates 30, and the back of the substrate 30 and the connection structure (such as Cu Stud) are exposed by grinding to form a mold layer M1 to protect the multiple substrates 30. After the mold layer M1 is formed, the non-routing area of ​​the hybrid adapter board 10a is opened to form a via K.

[0127] Of course, in some special scenarios, the electronic components 20 can be directly soldered to the surface of the redistribution layer RDL according to actual needs to form electrical interconnection.

[0128] Next, a support frame 43, whose dimensions match those of the hybrid transfer board system (i.e., the system comprising multiple chips D, hybrid transfer boards 10, multiple electronic components 20, and multiple substrates 30), can be used to support the hybrid transfer board system. Of course, support frame 43 also has holes drilled at the locations where through holes are to be provided in the hybrid transfer board system.

[0129] Next, referring to FIG3 , with the support of the support frame 43, a first heat sink 41 can be mounted on the side of the hybrid adapter plate system located on the chip D, and a second heat sink 42 can be mounted on the side of the electronic component 20. Of course, holes are also drilled at the locations where the through holes are set in the hybrid adapter plate system. Bolts (50) are used to penetrate the hybrid adapter plate system, the support frame, the first heat sink 41, and the second heat sink 42 at the through hole locations and fix them. In this case, the heat sinks (41, 42) not only play a role in heat dissipation, but also play a role in stabilizing the structure.

[0130] At this point, the entire packaging system has been built. As an independent data processing unit, the required power can be provided to the system through an external power supply module, and the system signal can also be brought out through a cable connector.

[0131] Example 2

[0132] The second embodiment of the present invention provides a chip packaging structure. The main difference between this chip packaging structure and the aforementioned first embodiment is the structure of the hybrid adapter board. The settings of other parts (such as chip D, electronic components 20, etc.) are basically the same. The corresponding description of the first embodiment can be referred to and will not be repeated here.

[0133] The structure of the new hybrid adapter plate provided in the second embodiment is described below.

[0134] Schematically, as shown in FIG9 , a new type of hybrid adapter board 10b is used in the chip packaging structure provided in the second embodiment. The hybrid adapter board 10b includes: a first redistribution layer RDL1, a second redistribution layer RDL2, and at least one bridge chip BG (bridge die) and a plurality of metal pillars P (such as copper pillars, Cu posts) connected between the first redistribution layer RDL1 and the second redistribution layer RDL2. The bridge chip BG and the metal pillars P are plastic-encapsulated in the molding layer to form a molding interposer 11. The first redistribution layer RDL1 is arranged on the active surface of the bridge chip BG and is electrically connected to the active surface of the bridge chip BG. The second redistribution layer RDL2 is electrically connected to the first redistribution layer RDL1 through the metal pillars P.

[0135] In addition, according to actual needs, in some possible implementations, the bridge chip BG may be provided with through silicon vias. In this case, the through silicon vias in the bridge chip BG are electrically connected to the second redistribution layer RDL2 below.

[0136] The structure of the bridge chip BG is similar to that of the Siinterposer in Example 1. Since the bridge chip BG can be manufactured through a silicon-based process, the line width, line spacing, and line thickness on the surface of the bridge chip BG can be less than 5μm, thereby meeting the high-bandwidth density interconnection requirements between multiple chips D.

[0137] As shown in Figure 9, multiple chips D are arranged on the upper surface of the first redistribution layer RDL1 (i.e., the surface away from the bridge chip BG) and are electrically connected to the first redistribution layer RDL1. The bridge chip BG is located between two adjacent chips D. In this case, the bridge chip connects the two adjacent chips D through the first redistribution layer. Any two adjacent chips D can be interconnected through the bridge chip BG.

[0138] Multiple electronic components 20 are located below the second redistribution layer RDL2 (i.e., on the side away from the bridge chip BG). The electronic components 20 can be directly connected to the lower surface of the second redistribution layer RDL2, or can be connected to the lower surface of the second redistribution layer RDL2 through the substrate 30. For example, multiple electronic components 20 can be connected to the second redistribution layer RDL2 through different substrates 30. For details, please refer to the corresponding description in Example 1, which will not be repeated here.

[0139] For the first redistribution layer RDL1 and the second redistribution layer RDL2:

[0140] The first redistribution layer (RDL1) can be constructed using thin metal and dielectric layers, with line widths, line spacing, and line thicknesses of less than 5μm. In this case, the first redistribution layer (RDL1) can directly lead to the connection pads on the bridge chip (BG) in the bridge chip (BG) region, enabling the high-bandwidth interconnection requirements between chips D to be met through the bridge chip (BG).

[0141] Illustratively, the first redistribution layer RDL1 may be implemented by a damascene process including deposition, exposure, etching, electroplating, and CMP.

[0142] The second redistribution layer RDL2 can be configured to use a thick metal layer and a thick dielectric layer. For example, the line width / line spacing / line thickness can be above 5 μm, thereby meeting the requirements of large current sharing and long routing capabilities of the electronic component 20.

[0143] Illustratively, the second redistribution layer RDL2 may be implemented by a yellow light process including coating / filming, exposure, development, and curing.

[0144] Illustratively, the first redistribution layer RDL1 may include 1 to 3 wiring layers, but is not limited thereto.

[0145] Illustratively, the second redistribution layer RDL2 may include 3 to 6 wiring layers, but is not limited thereto.

[0146] Regarding other parts of the chip packaging structure, such as the substrate 30, the first heat dissipation plate 41, the second heat dissipation plate 42, the fixing structure 50, etc., reference may be made to the corresponding parts in the aforementioned embodiment 1, and no further details will be given here.

[0147] The chip packaging structure of the second embodiment is further described below in conjunction with a method for manufacturing the chip packaging structure.

[0148] Schematically, this second embodiment provides a method for manufacturing a chip packaging structure, which may include:

[0149] First, referring to FIG10 (a), a metal post P, such as a copper post (Cu post), is made on the front side of a first carrier 01 (such as a glass wafer) as a conductive connector; then, referring to FIG10 (b), at least one bridge chip BG is mounted on the front side of the first carrier 01 (i.e., the side where P is provided); next, referring to FIG10 (c), a thermosetting material is used to perform plastic encapsulation on the front side of the first carrier 01, and the metal post P and the entire body are plastic encapsulated in a molding layer, and the connection structure (such as Cu Stud) on the surface of the metal post P and the bridge chip BG is exposed by grinding, thereby forming a molding interposer 11 (interposer).

[0150] Next, referring to FIG11 , a first redistribution layer RDL1 is fabricated on the upper surface of the molded interposer 11. The interconnect material in the first redistribution layer RDL1 may be Cu, and the insulating dielectric material may be polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) or other materials. Illustratively, the fabrication process for a single-layer routing layer in the first redistribution layer RDL1 includes: surface pretreatment - PI coating - exposure - development - curing - seed layer deposition - photoresist (PR) coating - exposure - development - electroplating - photoresist removal - seed layer etching.

[0151] Next, referring to FIG12(a), multiple heterogeneous chips D can be mounted on the surface of the first redistribution layer RDL1. Then, referring to FIG12(b), a thermosetting material is used to fill the bottoms of the multiple chips and the gaps between the chips. The backsides of the multiple chips D can then be ground (backside grinding) to expose the backsides of the chips, thereby forming a mold layer M2 to protect the multiple chips D.

[0152] Next, referring to FIG13(a), the back side of the plurality of chips D is temporarily bonded to a second carrier plate 02 (e.g., a glass plate, a metal plate, etc.). Then, referring to FIG13(b), the first carrier plate 01 on the other side can be debonded and separated by laser burning, heat treatment, or the like (e.g., laser debonding or thermal debonding), and the metal pillars P and bridge chip BG are exposed by grinding. The grinding process may include rough grinding (grinding) - chemical mechanical polishing (CMP) - Si etching (etching) to expose copper - insulating dielectric material deposition - CMP to expose copper, etc.

[0153] Next, referring to FIG14 , a second redistribution layer RDL2 is fabricated on the back side of the wafer (i.e., the side where the metal pillars P and the bridge chip BG are exposed). The interconnect material in the second redistribution layer RDL2 may be Cu, and the insulating dielectric material may be a polyimide polymer (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) or other materials. Illustratively, the manufacturing process flow of a single-layer routing layer in the second redistribution layer RDL2 includes: surface pretreatment - PI coating - exposure - development - curing - seed layer deposition - photoresist (PR) coating - exposure - development - electroplating - photoresist removal - seed layer etching.

[0154] At this point, the hybrid transfer board 10 b formed by the first redistribution layer RDL1 , the molded interposer 11 embedded with the metal pillars P and the bridge chip BG, and the second redistribution layer RDL2 is completed.

[0155] Next, referring to FIG15(a), multiple substrates 30 can be welded to the pads on the surface of the second redistribution layer RDL2. For example, multiple ABF substrates (ajinomoto build-up film) can be flip-mounted on the surface of the second redistribution layer RDL2. Of course, referring to FIG15(b), after welding the multiple substrates 30, a thermosetting material can be used to fill the bottoms of the multiple substrates 30 and the gaps between the substrates 30 as needed, and the backs of the substrates 30 and the connection structures (such as Cu Stud) can be exposed by grinding to form a mold layer M1 to protect the multiple substrates 30.

[0156] Next, referring to FIG16 , multiple electronic components 20 (such as power modules, clocks, passive components and other functional modules) are respectively soldered to the surfaces of multiple substrates 30 , thereby realizing vertical power supply interconnection between the electronic components 20 and the substrates 30 .

[0157] Next, referring to FIG. 17 , the second carrier plate 02 is debonded and separated by laser burning, heat treatment, or the like.

[0158] After that, the non-routing area of ​​the hybrid adapter board 10b is opened, cut, and the first heat sink 41, the second heat sink 42, the support frame 43, the fixed structure 50 and other manufacturing processes are installed. For details, please refer to the relevant instructions in Example 1, which will not be repeated here.

[0159] Example 3

[0160] The third embodiment provides a chip packaging structure. The hybrid transfer board used in the chip packaging structure is similar to the hybrid transfer board 10b in the second embodiment. The only difference is that the material of the interposer on which the bridge chip BG is provided is different.

[0161] The structure of the new hybrid adapter board provided in the third embodiment is described below.

[0162] Schematically, as shown in FIG18 , a new type of hybrid adapter board 10c is adopted in the chip packaging structure provided in the third embodiment. The hybrid adapter board 10c includes: a first redistribution layer RDL1, a second redistribution layer RDL2, and a glass interposer 12 arranged between the first redistribution layer RDL1 and the second redistribution layer RDL2. Among them, a plurality of through glass vias TGV (through glass via) and at least one groove 100 are provided in the glass interposer 12, and a bridge chip BG (bridge die) is provided in the groove 100. The bridge chip BG and the through glass via TGV are connected between the first redistribution layer RDL1 and the second redistribution layer RDL2. The first redistribution layer RDL1 is provided on the active surface of the bridge chip BG and is electrically connected to the active surface of the bridge chip BG. The second redistribution layer RDL2 is electrically connected to the first redistribution layer RDL1 through the through glass via TGV.

[0163] In addition, according to actual needs, in some possible implementations, the bridge chip BG may be provided with through silicon vias. In this case, the through silicon vias in the bridge chip BG are electrically connected to the second redistribution layer RDL2 below.

[0164] That is, compared to the second embodiment in which the dielectric layer of the bridge chip BG is formed of a molding material (ie, the molding layer 11 ), the dielectric layer of the bridge chip BG in the third embodiment is formed of a glass wafer.

[0165] In the third embodiment, since the bridge chip BG can be manufactured by a silicon-based process, the line width / line spacing / line thickness can be made smaller than 5 μm, thereby meeting the interconnection requirements of multiple chips D with high bandwidth density.

[0166] The first redistribution layer (RDL1) can be constructed using thin metal and dielectric layers, with line widths, line spacing, and line thicknesses of less than 5μm. In this case, the first redistribution layer (RDL1) can extend the connection pads on the bridge chip (BG) surface in the bridge chip (BG) region, meeting the high-bandwidth interconnect requirements between chip D and the bridge chip (BG).

[0167] Schematically, the first redistribution layer RDL1 can be implemented by using a damascene process including deposition, exposure, etching, electroplating, CMP and other processes.

[0168] The second redistribution layer RDL2 can be configured to use a thick metal layer and a thick dielectric layer. For example, the line width / line spacing / line thickness can be above 5 μm, thereby meeting the requirements of large current sharing and long routing capabilities of the electronic component 20.

[0169] Illustratively, the second redistribution layer RDL2 may be implemented by a yellow light process including coating / filming, exposure, development, and curing.

[0170] Regarding other related settings of the bridge chip BG, the first redistribution layer RDL1, and the second redistribution layer RDL2 in the third embodiment, reference may be made to the corresponding parts in the second embodiment, which will not be repeated here.

[0171] Regarding other parts of the chip packaging structure, such as the electronic component 20, the substrate 30, the first heat sink 41, the second heat sink 42, the fixing structure 50, etc., you can refer to the corresponding parts in the aforementioned embodiment 1 and embodiment 2, and will not be repeated here.

[0172] The chip packaging structure of this embodiment is further described below in conjunction with a method for manufacturing the chip packaging structure.

[0173] Referring to FIG. 19 (a), a through glass via (TGV) is fabricated on a glass wafer G, and the glass wafer G with the through glass via (TGV) is mounted on the surface of a first carrier 01. Then, a groove 100 is formed on the glass wafer G using a laser or other method.

[0174] Next, referring to FIG. 19( b ), the bridge chip BG is mounted in the groove body of the trench 100 .

[0175] Next, as shown in FIG19(c), a thermally curable material is used to fill the trench 100 and cover the surface of the glass wafer G. Then, as shown in FIG19(d), the through glass vias TGV and the connection structure (such as Cu stud) on the surface of the bridge chip BG are exposed by grinding, thereby forming a glass interposer 12.

[0176] The subsequent manufacturing process is basically the same as the steps after the molding of the intermediate layer 11 in the second embodiment. For details, please refer to the corresponding parts in the second embodiment and will not be repeated here.

[0177] The chip packaging structure in the aforementioned embodiments is not limited to being manufactured by the manufacturing methods provided in the embodiments, and may also be manufactured by other manufacturing methods.

[0178] For example, in some possible implementations, the chip packaging structure provided in the aforementioned embodiments one, two, and three can first weld multiple substrates 30 on the hybrid adapter board 10 and perform plastic sealing, and finally assemble the chip D and the electronic component 20.

[0179] For example, taking the manufacturing of the chip packaging structure in the first embodiment as an example, the manufacturing method may include:

[0180] First, a hybrid adapter plate 10a is manufactured on the first carrier plate 01. For the specific manufacturing process, please refer to FIG. 4 and the corresponding description in the first embodiment.

[0181] Next, referring to FIG. 20( a ), a plurality of substrates 30 are soldered to the pads on the surface of the redistribution layer RDL in the hybrid interposer 10 a .

[0182] Next, referring to FIG. 20 ( b ), a thermosetting material may be used to fill the bottoms of the plurality of substrates 30 and the gaps between the substrates 30 , and the backs of the substrates 30 and the connection structures (such as Cu Stud) may be exposed by grinding to form a mold layer M1 to protect the plurality of substrates 30 .

[0183] Next, referring to FIG. 20 ( c ), the first carrier 01 and the hybrid transfer board 10 a may be debonded and separated by laser burning, heat treatment, etc., to expose the micro-pad interface on the surface of the silicon interposer.

[0184] Next, as shown in FIG21 , multiple heterogeneous chips D can be mounted on the surface of the first redistribution layer RDL1. A thermosetting material can then be used to fill the bottoms of the multiple chips and the gaps between the chips. The backsides of the multiple chips D can then be ground (backside grinding) to expose the backsides of the chips, thereby forming a mold layer M2 to protect the multiple chips D.

[0185] Next, referring to FIG22 , a plurality of electronic components 20 (such as functional modules such as power modules, clocks, and passive components) can be respectively soldered to the surfaces of a plurality of substrates 30 , thereby realizing vertical power supply interconnection between the electronic components 20 and the substrates 30 .

[0186] After that, the non-routing area of ​​the hybrid adapter board 10b is opened, cut, and the first heat sink 41, the second heat sink 42, the support frame 43, the fixed structure 50 and other manufacturing processes are installed. For details, please refer to the relevant instructions in Example 1, which will not be repeated here.

[0187] It should be understood that the sequence of the production processes in the various embodiments of the present application should be determined by their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0188] For other relevant contents in the manufacturing method in each embodiment, you can refer to the corresponding parts in the chip packaging structure, which will not be repeated here; for other setting structures in the aforementioned chip packaging structure embodiment, you can refer to the above-mentioned manufacturing method and related manufacturing methods for adjustment, which will not be repeated here one by one.

[0189] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that: include: A silicon interposer, wherein the front side of the silicon interposer has a metal wiring layer, and a through silicon via TSV is arranged in the silicon interposer; a redistribution layer formed on the back side of the silicon interposer and electrically connected to the through silicon via; At least one first chip, located on the front side of the silicon interposer and electrically connected to the metal wiring layer; At least one electronic component is located on a side of the redistribution layer away from the first chip and is connected to the redistribution layer or connected to the redistribution layer through a substrate.

2. The chip packaging structure according to claim 1, characterized in that: The at least one first chip includes: one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The at least one electronic component includes: one or more of a power supply module, a control module, a connector, a clock device, a rectifier, and a resistor, capacitor, and inductor.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure includes: a plurality of the first chips and a plurality of the electronic components.

5. The chip packaging structure according to claim 4, characterized in that: The plurality of electronic components include a plurality of power supply modules, and the plurality of power supply modules are respectively arranged opposite to the plurality of first chips; The power supply module is electrically connected to the first chip which is arranged opposite to the first chip through the redistribution layer and the silicon interposer, and supplies power to the first chip.

6. The chip packaging structure according to claim 4 or 5, characterized in that: The chip packaging structure comprises: a plurality of substrates; The substrate is located between the redistribution layer and the electronic components, and a plurality of the electronic components are electrically connected to the redistribution layer through a plurality of the substrates.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The chip packaging structure further includes: a first heat dissipation plate and a second heat dissipation plate; The first heat sink is disposed on a side of the first chip away from the silicon interposer, and the second heat sink is disposed on a side of the plurality of electronic components away from the redistribution layer.

8. A chip packaging structure, characterized in that: include: a first redistribution layer and a second redistribution layer; at least one bridge chip and a metal connection structure connected between the first redistribution layer and the second redistribution layer, and the first redistribution layer is located on the active surface of the bridge chip; at least one first chip, located on a side of the first redistribution layer away from the bridge chip, and the first chip is electrically connected to the bridge chip through the first redistribution layer; At least one electronic component is located on a side of the second redistribution layer away from the first redistribution layer and is connected to the second redistribution layer or connected to the second redistribution layer through a substrate.

9. The chip packaging structure according to claim 8, characterized in that: The line width, line spacing and line thickness of the metal routing in the first redistribution layer are all less than 5 μm; the line width, line spacing and line thickness of the metal routing in the second redistribution layer are all greater than 5 μm.

10. The chip packaging structure according to claim 8 or 9, characterized in that: The metal connection structure includes a metal column; The bridge chip and the metal pillar are encapsulated in a molding layer.

11. The chip packaging structure according to claim 8 or 9, characterized in that: A glass wafer is disposed between the first redistribution layer and the second redistribution layer, and a groove is disposed in the glass wafer; The bridge chip is embedded in the groove, and the metal connection structure includes a through glass via (TGV) penetrating the glass wafer.

12. The chip packaging structure according to any one of claims 8 to 11, characterized in that: The at least one first chip includes: one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

13. The chip packaging structure according to any one of claims 8 to 12, characterized in that: The at least one electronic component includes: one or more of a power supply module, a control module, a connector, a clock device, a rectifier, and a resistor, capacitor, and inductor.

14. The chip packaging structure according to any one of claims 8 to 13, characterized in that: The chip packaging structure includes: a plurality of the first chips and a plurality of electronic components.

15. The chip packaging structure according to any one of claims 8 to 14, characterized in that: The chip packaging structure includes a plurality of bridge chips; The bridge chip is located between two adjacent first chips, and the bridge chip connects the two adjacent first chips through the first redistribution layer.

16. The chip packaging structure according to claim 14 or 15, characterized in that: The plurality of electronic components include a plurality of power supply modules, and the plurality of power supply modules are respectively arranged opposite to the plurality of first chips; The power supply module is electrically connected to the first chip which is arranged opposite to the first chip through the redistribution layer and the bridge chip, and supplies power to the first chip.

17. The chip packaging structure according to any one of claims 14 to 16, characterized in that: The chip packaging structure comprises: a plurality of substrates; The substrate is located between the redistribution layer and the electronic components, and a plurality of the electronic components are electrically connected to the second redistribution layer through a plurality of the substrates.

18. The chip packaging structure according to any one of claims 8 to 17, characterized in that: The chip packaging structure further includes: a first heat dissipation plate and a second heat dissipation plate; The first heat sink is disposed on a side of the first chip away from the first redistribution layer, and the second heat sink is disposed on a side of the electronic component away from the second redistribution layer.

19. An electronic device, characterized in that: It comprises a circuit board and a chip packaging structure as claimed in any one of claims 1 to 18, wherein the chip packaging structure is electrically connected to the circuit board.

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