Three-dimensional semiconductor memory device

Abstract

A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structure extends in a first direction and is spaced apart from each other by a separation region in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes including lowermost electrodes of the plurality of electrodes of the electrode structure, wherein, at a level of the ground select gate electrodes, the separation region includes a first end portion, and at least one ground select gate cut region overlaps the first end portion of the separation region and electrically isolates the ground select gate electrodes from each other.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0013729, filed on February 5, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor memory devices. Background Technology

[0004] To meet consumer demands for superior performance and low cost, the integration density of semiconductor memory devices can be increased. However, in the case of two-dimensional or planar semiconductor memory devices, it is difficult to reduce the area occupied by a single memory cell, thus hindering the improvement of integration density. Therefore, three-dimensional (3D) semiconductor memory devices with memory cells arranged in three dimensions have been proposed. Summary of the Invention

[0005] The present invention provides a three-dimensional (3D) semiconductor memory device with improved reliability and integration.

[0006] According to one aspect of the present invention, a 3D semiconductor memory device is provided, comprising: a semiconductor substrate; an electrode structure including a plurality of electrodes stacked on the semiconductor substrate, the electrode structure extending along a first direction and spaced apart from each other by a separation region in a second direction perpendicular to the first direction; a ground select gate electrode including the lowermost electrode of the plurality of electrodes of the electrode structure, wherein the separation region includes a first end at the level of the ground select gate electrode; and at least one ground select gate cleaving region overlapping the first end of the separation region and electrically isolating the ground select gate electrodes from each other.

[0007] According to another aspect of the present invention, a three-dimensional (3D) semiconductor memory device is provided, comprising: a peripheral logic structure on a semiconductor substrate; a horizontal semiconductor layer on the peripheral logic structure, the horizontal semiconductor layer including a cell array region and a connection region electrically connected to the cell array region; an electrode structure including a plurality of electrodes stacked on the horizontal semiconductor layer in the cell array region and the connection region, the electrode structures extending along a first direction and spaced apart from each other by a separation region in a second direction perpendicular to the first direction; at least one contact region including a through wiring structure in the connection region electrically connecting the electrode structures to the peripheral logic structure; and a ground select gate electrode including the lowermost electrode of the plurality of electrodes of the electrode structure in the cell array region and the connection region, wherein the separation region includes a first end at the level of the ground select gate electrode, and at least one ground select gate cleaving region overlaps with the first end of the separation region, thereby electrically isolating the ground select gate electrodes from each other.

[0008] According to another aspect of the present invention, a three-dimensional (3D) semiconductor memory device is provided, comprising: a peripheral logic structure on a semiconductor substrate; a horizontal semiconductor layer on the peripheral logic structure, the horizontal semiconductor layer including a cell array region and a connection region electrically connected to the cell array region; an electrode structure including a plurality of electrodes stacked on the horizontal semiconductor layer in the cell array region and the connection region, each electrode structure extending along a first direction and spaced apart from each other by at least one separation region in a second direction perpendicular to the first direction; at least one contact region including a through wiring structure in the connection region electrically connecting the electrode structures to the peripheral logic structure; and a ground select gate electrode including the lowermost electrode of the plurality of electrodes of the electrode structure in the cell array region and the connection region, wherein the at least one separation region includes a first end at the level of the ground select gate electrode, and at least one ground select gate cleaving region overlaps with the first end of the at least one separation region, thereby electrically isolating the ground select gate electrodes from each other. Attached Figure Description

[0009] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present invention;

[0011] Figure 2 This is a block diagram illustrating the constituent components of a 3D semiconductor memory device according to an embodiment of the present invention.

[0012] Figure 3 This is a perspective view illustrating the structure of a 3D semiconductor memory device according to an embodiment of the concept of the present invention;

[0013] Figure 4 This is a schematic layout diagram illustrating a 3D semiconductor memory device according to an embodiment of the concept of the present invention;

[0014] Figure 5 This is a schematic layout diagram illustrating a 3D semiconductor memory device according to an embodiment of the concept of the present invention;

[0015] Figure 6 This is a schematic layout diagram illustrating a 3D semiconductor memory device according to an embodiment of the concept of the present invention;

[0016] Figure 7 yes Figure 6 A magnified view of region A in the middle;

[0017] Figure 8 This is a cross-sectional view illustrating a 3D semiconductor memory device according to an embodiment of the concept of the present invention;

[0018] Figure 9A and Figure 9B This is an embodiment of the concept of the present invention. Figure 8 A magnified view of part B;

[0019] Figure 10 This is a schematic diagram illustrating the layout of the ground selection gate electrode disposed in each electrode structure according to an embodiment of the present invention.

[0020] Figures 11A to 11C The diagram illustrates the planar and vertical overlap relationships between the isolation region and the ground select gate dicing region of a 3D semiconductor memory device, according to an embodiment of the present invention.

[0021] Figure 12A and Figure 12B This is a layout diagram illustrating the planar overlap relationship between the isolation region, contact region, and ground select gate dicing region of a 3D semiconductor memory device according to an embodiment of the present invention.

[0022] Figure 13 This is a cross-sectional view illustrating a 3D semiconductor memory device according to an embodiment of the concept of the present invention;

[0023] Figure 14 This is a block diagram illustrating the arrangement relationship between the cell array region and the connection region of a 3D semiconductor memory device according to an embodiment of the present invention.

[0024] Figure 15 This is a schematic layout diagram illustrating a 3D semiconductor memory device according to an embodiment of the concept of the present invention;

[0025] Figure 16 It is along Figure 15 A cross-sectional view of line AB;

[0026] Figure 17 It is along Figure 15 A cross-sectional view taken from line BC;

[0027] Figure 18 It is along Figure 15 A cross-sectional view taken from line DE;

[0028] Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22 and Figure 23 This is a diagram illustrating a method for manufacturing a 3D semiconductor memory device according to an embodiment of the concept of the present invention;

[0029] Figures 24A to 24D This is a cross-sectional view illustrating a method for manufacturing a ground selection gate dicing region of a 3D semiconductor memory device according to an embodiment of the present invention;

[0030] Figures 25A to 25D This is a layout diagram illustrating various overlap relationships between the gate isolation region and the ground select gate dicing region of a 3D semiconductor memory device according to an embodiment of the present invention.

[0031] Figure 26A and Figure 26B This is a layout diagram illustrating various overlap relationships between the gate isolation region, ground gate electrode, and ground select gate dicing region of a 3D semiconductor memory device according to an embodiment of the present invention; and

[0032] Figure 27A and Figure 27B This is a layout diagram illustrating various overlap relationships between the gate isolation region, contact region, ground gate electrode, and ground select gate dicing region of a 3D semiconductor memory device according to an embodiment of the present invention. Detailed Implementation

[0033] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and repeated descriptions may be omitted.

[0034] Figure 1 This is a circuit diagram illustrating a cell array 1 of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present invention.

[0035] The cell array 1 of the 3D semiconductor memory device may include a common source line CSL, a zero bit line BL0 to a second bit line BL2, and a plurality of cell strings CSTRs between the common source line CSL and the zero bit line BL0 to the second bit line BL2.

[0036] Multiple unit strings CSTRs can extend on a plane extending along a first direction (X direction) and a second direction (Y direction) or from it along a third direction (Z direction). The zero bit line BL0 to the second bit line BL2 can be spaced apart from each other along the first direction (X direction) and can extend along the second direction (Y direction).

[0037] Multiple cell strings (CSTRs) can be connected in parallel to each of the zero-th bit line BL0 to the second bit line BL2. Multiple cell strings (CSTRs) can also be connected together to a common source line (CSL). That is, multiple cell strings (CSTRs) can be located between the zero-th bit line BL0 to the second bit line BL2 and a (i.e., the same) common source line (CSL). Multiple common source lines (CSLs) can be arranged in two dimensions.

[0038] In this case, the same voltage can be applied to the common source line CSL, or each common source line CSL can be electrically controlled. In an embodiment, each cell string CSTR may include a first string select transistor SST1 and a second string select transistor SST2 connected in series, a memory cell MCT connected in series, and a ground select transistor GST. Each memory cell MCT may include a data storage element.

[0039] In an embodiment, each cell string CSTR may include a first string select transistor SST1 and a second string select transistor SST2 connected in series. The second string select transistor SST2 may be connected to the zero bit line BL0 to the second bit line BL2, and the ground select transistor GST may be connected to the common source line CSL. The memory cell MCT may be connected in series between the first string select transistor SST1 and the ground select transistor GST.

[0040] Additionally, each cell string CSTR may also include a dummy cell DMC connected between the first string selection transistor SST1 and the memory cell MCT. Although Figure 1 Not shown, but a dummy cell DMC can also be connected between the ground select transistor GST and the memory cell MCT. As another example, in each cell string CSTR, the ground select transistor GST, similar to the first string select transistor SST1 and the second string select transistor SST2, can include multiple metal-oxide-semiconductor (MOS) transistors connected in series. As another example, each cell string CSTR can include one string select transistor.

[0041] In this embodiment, the first string select transistor SST1 can be controlled by the first string select line SSL1, and the second string select transistor SST2 can be controlled by the second string select line SSL2. The memory cell MCT can be controlled by the zero word line WL0 to the nth word line WLn, and the dummy cell DMC can be controlled by the dummy word line DWL. Furthermore, the ground select transistor GST can be controlled by the zero ground select line GSL0 to the second ground select line GSL2. The common source line CSL can be connected to the source of the ground select transistor GST.

[0042] A cell string CSTR may include multiple memory cells MCTs with different distances from the common source line CSL. Furthermore, the zeroth word line WL0 to the nth word line WLn and the dummy word line DWL may be located between the common source line CSL and the zeroth bit line BL0 to the second bit line BL2.

[0043] The gate electrodes of memory cells MCT and dummy cells DMC, which are at approximately the same distance from the common source line CSL, can be connected to one of the zero-word lines WL0 to the nth word line WLn, and therefore can be at the same potential. Unlike this, even when the gate electrodes of memory cells MCT are at approximately the same level from the common source line CSL, the gate electrodes on different rows or columns can be independently controlled. Figure 1 In the diagram, the zero word line WL0 to the nth word line WLn and the dummy word line DWL are shown as being connected to the three gate electrodes respectively, but they can be connected to the corresponding gate electrodes as needed.

[0044] The zero-ground selection lines GSL0 to GSL2, as well as the first selection line SSL1 and the second selection line SSL2, can extend along a first direction (X direction) and can be spaced apart from each other along a second direction (Y direction). The zero-ground selection lines GSL0 to GSL2 can be at substantially the same level from the common source line CSL. The first selection line SSL1 and the second selection line SSL2 can be at substantially different levels from the common source line CSL. The first selection line SSL1 and the second selection line SSL2 can be electrically isolated from each other.

[0045] Figure 2 This is a block diagram illustrating the constituent components of a 3D semiconductor memory device 5 according to an embodiment of the present invention.

[0046] The 3D semiconductor memory device 5 may include a cell array 1 and peripheral circuitry (2, 3, and 4). The peripheral circuitry (2, 3, and 4) may include a row decoder 2, a page buffer 3, and a column decoder 4.

[0047] Cell array 1 may include a 3D cell array, which includes multiple memory cells. (See above reference.) Figure 1The cell array 1 may include a plurality of memory cells, and a plurality of word lines and a plurality of bit lines electrically connected to the plurality of memory cells. In an embodiment, the cell array 1 may include zeroth memory block BLK0 to nth memory block BLKn as data erasure units.

[0048] The line decoder 2 can select word lines of cell array 1. Based on address information, the line decoder 2 can select one of the zeroth memory block BLK0 to the nth memory block BLKn of cell array 1, and then select one of the word lines of the selected memory block from the zeroth memory block BLK0 to the nth memory block BLKn. In response to control by a control circuit (not shown), the line decoder 2 can provide the word line voltage generated by the voltage generation circuit (not shown) to the selected word line and the unselected word line, respectively.

[0049] Page buffer 3 can write information to or read information stored in memory cells. Depending on certain operating modes, page buffer 3 can temporarily store data to be stored in memory cells, or can read data stored in memory cells. Page buffer 3 can operate as a write driver circuit in programming mode and as a read amplifier circuit in read mode.

[0050] Column decoder 4 can be connected to the bit lines of cell array 1. Column decoder 4 can provide a data transfer path between page buffer 3 and external devices (e.g., memory controller).

[0051] Figure 3 This is a perspective view showing the structure of a 3D semiconductor memory device 5 according to an embodiment of the present invention.

[0052] The 3D semiconductor memory device 5 may include a peripheral logic structure PS and a cell array structure CS. The cell array structure CS may be stacked on the peripheral logic structure PS. In a planar view, the peripheral logic structure PS may overlap with the cell array structure CS.

[0053] The cell array structure CS may include zeroth memory blocks BLK0 to nth memory blocks BLKn as data erasure units. Each of the zeroth memory blocks BLK0 to nth memory blocks BLKn may include a cell array with a 3D structure (or a vertical structure). Figure 2 1).

[0054] Cell array 1 may include reference Figure 1The diagram shows a three-dimensional arrangement of multiple memory cells (MTCs) and zero-word lines WL0 to WLn and zero-bit lines BL0 to BL2 electrically connected to the multiple memory cells (MTCs). The peripheral logic structure PS may include peripheral circuitry (2, 3, and 4) of the control unit array 1. Peripheral circuitry (2, 3, and 4) may include... Figure 2 The row decoder 2, page buffer 3, and column decoder 4 are shown, and in addition, control circuitry for controlling memory blocks BLK0 to BLKn can be included.

[0055] In the following description, various layouts and structures of 3D semiconductor memory devices according to embodiments of the present invention are described as examples. The layouts described below do not limit the inventive concept, and the same or similar reference numerals may denote the same or similar elements.

[0056] Figure 4 This is a schematic layout diagram illustrating a 3D semiconductor memory device 5-1 according to an embodiment of the present invention.

[0057] For convenience, the 3D semiconductor memory device 5-1 according to an embodiment of the present invention can be shown as having two memory blocks, a zeroth memory block BLK0 and a first memory block BLK1. Each of the zeroth memory block BLK0 and the first memory block BLK1 may include a plurality of electrode structures ST, but in Figure 4 In the diagram, it is shown as comprising two electrode structures ST.

[0058] The 3D semiconductor memory device 5-1 may include: a peripheral logic structure PS on a semiconductor substrate (not shown); a cell array structure CS on the peripheral logic structure PS; and a through wiring structure THV that electrically connects the cell array structure CS to the peripheral logic structure PS.

[0059] The peripheral logic structure PS may include peripheral logic circuitry that processes data input to / output to / from the cell array. The cell array structure CS may include: a plurality of electrode structures ST disposed on a horizontal semiconductor layer 100 located on a semiconductor substrate (not shown); and a plurality of vertical structures VS penetrating each electrode structure ST. Each electrode structure ST may include multiple electrodes, such as a cell gate electrode and a ground-select gate electrode.

[0060] As described herein, in the electrodes of the electrode structure ST, the ground selection gate electrode may be in the bottom layer of the electrodes or on the bottom layer of the electrodes. The vertical structure VS may include memory cells. In some embodiments, in a planar view, the cell array structure CS may overlap with the peripheral logic structure PS.

[0061] A horizontal semiconductor layer 100 on a semiconductor substrate (not shown) may include a cell array region (CAR) in which memory cells are disposed, and a connection region (CNR) electrically connected to the cell array region (CAR). The connection region (CNR) may include contact plugs and wires connected to the memory cells. A first contact region 120 including a through-wire structure (THV) may be formed in the connection region (CNR). The first contact region 120 may include an insulating layer that was not replaced by metal during the electrode formation process. In other words, the first contact region 120 may include an insulating layer formed in a region that was not replaced by metal during the electrode formation process. In some embodiments, the first contact region 120 may include a silicon oxide layer or a silicon nitride layer.

[0062] Electrode structures ST can extend along a first direction (X direction) on a horizontal semiconductor layer 100. Adjacent electrode structures ST can be spaced apart in a second direction (Y direction) perpendicular to the first direction (X direction) by electrode separation regions ESR disposed between them. The electrode separation regions ESR can be straight patterns, without bending or kinking in the first direction (X direction). The electrode separation regions ESR can be referred to as separation regions. Furthermore, the term "separation region" can refer to (i) multiple electrode separation regions ESR, (ii) multiple gate isolation regions GIR ( Figure 6 (iii) a combination of one or more electrode separation regions (ESR) and one or more gate isolation regions (GIR).

[0063] The 3D semiconductor memory device 5-1 may include at least one ground-select gate dicing region GGIR, which, in a plan view, overlaps with the electrode separation region ESR or the first contact region 120 at the level of the ground-select gate electrode. For example, the ground-select gate dicing region GGIR may overlap with one or more separation regions in the third direction (Z direction).

[0064] A ground-selective gate cut region GGIR can be formed in at least one of the cell array region CAR and the connecting region CNR. The ground-selective gate cut region GGIR can be formed in a first direction (X direction) between the cell array region CAR and the connecting region CNR. The ground-selective gate cut region GGIR can contact or overlap with a first contact region 120 in the connecting region CNR.

[0065] The overlap between the electrode separation region ESR and the first contact region 120, as well as the ground select gate dicing region GGIR, will be described in detail later. The ground select gate dicing region GGIR can electrically isolate the ground select gate electrodes from each other, and thus can improve the reliability of the 3D semiconductor memory device 5-1.

[0066] In some embodiments, each electrode structure ST may include a first wiring portion having a first width W1 and a second wiring portion having a second width W2, the second width W2 being smaller than the first width W1. The second wiring portions of adjacent electrode structures ST may face each other. A pair of adjacent electrode structures ST may be arranged in a mirror-symmetric manner. At least one first contact region 120 exposing a portion of the horizontal semiconductor layer 100 may be arranged in a pair of adjacent electrode structures ST. The first contact region 120 may be between the second wiring portions of the electrode structures ST. In some embodiments, the first contact region 120 may be located between the electrode structures ST in a second direction (Y direction).

[0067] The first contact area 120 can be arranged in various ways as needed. In some embodiments, at least one first contact area 120 may be in either the zeroth memory block BLK0 or the first memory block BLK1. For example, at least one first contact area 120 may be in the zeroth memory block BLK0. In some embodiments, the first contact area 120 may be located inside the electrode structure ST in a first direction (X direction).

[0068] In some embodiments, the first contact region 120 may not be disposed in either the zero storage block BLK0 or the first storage block BLK1. For example, when the first contact region 120 is not disposed in the zero storage block BLK0, the first contact region (not shown) may be formed in a connection region CNR disposed along the -X direction opposite to the X direction.

[0069] The aforementioned 3D semiconductor memory device 5-1 can improve reliability while increasing integration density by including a peripheral logic structure PS, a vertical structure VS including memory cells, and a ground selection gate dicing region GGIR.

[0070] Figure 5 This is a schematic layout diagram illustrating a 3D semiconductor memory device 5-2 according to an embodiment of the present invention.

[0071] In addition to including a plurality of first contact regions 120 in the 3D semiconductor memory device 5-2, the 3D semiconductor memory device 5-2 according to an embodiment of the present invention and Figure 4 The 3D semiconductor memory device 5-1 is the same. Figure 5 In, with Figure 4 The same reference numerals in the figures denote the same components, so their descriptions may be provided briefly or omitted.

[0072] The 3D semiconductor memory device 5-2 may include a plurality of first contact regions 120, wherein a pair of adjacent electrode structures ST are spaced apart in a first direction (X direction). A through-wiring structure THV may be formed in the first contact regions 120. The first contact regions 120 may be disposed between second wiring portions having a second width W2 of the pair of electrode structures ST.

[0073] The 3D semiconductor memory device 5-2 may include at least one ground-selective gate dicing region (GGIR), which, in a plan view, overlaps with the electrode separation region (ESR) and the first contact region 120 at the level of the ground-selective gate electrode. The ground-selective gate dicing region (GGIR) may be formed in a first direction between the cell array region (CAR) and the connection region (CNR). The ground-selective gate dicing region (GGIR) may be formed in the first direction between the first contact regions 120. The ground-selective gate dicing region (GGIR) may contact or overlap with the first contact region 120 in the connection region (CNR).

[0074] Figure 6 This is a schematic layout diagram illustrating a 3D semiconductor memory device 5-3 according to an embodiment of the concept of the present invention; Figure 7 yes Figure 6 A magnified view of region A in the middle; Figure 8 This is a cross-sectional view showing a 3D semiconductor memory device 5-3 according to an embodiment of the present invention; Figure 9A and Figure 9B This is an embodiment of the concept of the present invention. Figure 8 A magnified view of region B; and Figure 10 This is a schematic diagram illustrating the layout of ground selection gate electrodes included in each electrode structure according to an embodiment of the present invention.

[0075] 3D semiconductor memory devices 5-3 may include two electrode structures ST separated by an electrode separation region ESR, such as Figure 6 As shown. Two electrode structures ST can constitute a memory block. In some embodiments, one electrode structure ST can constitute a memory block. Each of the electrode structures ST can include a plurality of sub-electrode structures divided into a first gate isolation region GIR1 and a second gate isolation region GIR2, as described later.

[0076] exist Figure 6In this design, each electrode structure ST may include three first gate isolation regions GIR1 and three second gate isolation regions GIR2, but may include only one first gate isolation region GIR1 and one second gate isolation region GIR2 as needed. When each electrode structure ST includes one first gate isolation region GIR1 and one second gate isolation region GIR2, each electrode structure ST may include two sub-electrode structures. When one first gate isolation region GIR1 and one second gate isolation region GIR2 are located in each electrode structure ST, the first gate isolation region GIR1 and the second gate isolation region GIR2 may be arranged in a linear pattern in a first direction (X direction) without bending or twisting. In the following description, the description of the electrode structure can be understood to include the concept of sub-electrode structures.

[0077] 3D semiconductor memory devices 5-3 may include, for example Figure 8 The peripheral logic structure PS is shown. The peripheral logic structure PS may include a peripheral logic circuit PTR integrated on the front surface of the semiconductor substrate 10, and a lower buried insulating layer 50 on (e.g., covering) the peripheral logic circuit PTR.

[0078] The semiconductor substrate 10 may include a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. As described above, the peripheral logic circuit PTR may include peripheral circuits, such as row decoders, column decoders, page buffers, and control circuits. The peripheral logic circuit PTR may include NMOS transistors and PMOS transistors, low-voltage transistors and high-voltage transistors, capacitors, resistors, etc., integrated on the semiconductor substrate 10.

[0079] The active region can be defined by a device isolation layer 11 formed in the semiconductor substrate 10. A peripheral gate electrode 23 mounted on the gate insulating layer 21 can be located on the semiconductor substrate 10 within the active region. Source / drain regions 25 can be disposed on both sides (e.g., opposite sides) of the peripheral gate electrode 23 on the semiconductor substrate 10. Peripheral circuit wiring 33 can be electrically connected to a peripheral logic circuit PTR via a peripheral circuit contact plug 31. For example, the peripheral circuit plug 31 and the peripheral circuit wiring 33 can be connected to NMOS and PMOS transistors.

[0080] The lower buried insulating layer 50 may cover the peripheral logic circuit PTR, peripheral circuit contact plugs 31, and peripheral circuit wiring 33 on the semiconductor substrate 10. The lower buried insulating layer 50 may include multiple stacked insulating layers. For example, the lower buried insulating layer 50 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0081] The cell array structure CS can be on the lower buried insulating layer 50 and can include a horizontal semiconductor layer 100, an electrode structure ST, and a vertical structure VS. The horizontal semiconductor layer 100 can include a semiconductor material, such as at least one of the following: silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0082] In some embodiments, the horizontal semiconductor layer 100 may include a semiconductor doped with impurities of a first conductivity type and / or an intrinsic semiconductor without impurities. In some embodiments, the horizontal semiconductor layer 100 may have a crystal structure, which includes at least one of a single crystal structure, an amorphous structure, and a polycrystalline structure. In some embodiments, the first horizontal semiconductor layer 100 may include a metallic material. For example, the horizontal semiconductor layer 100 may include tungsten (W), tungsten silicide (WSi), tungsten nitride (WN), cobalt silicide (CoSi), titanium nitride (TiN), etc.

[0083] like Figure 6 and Figure 7 As shown, the horizontal semiconductor layer 100 may include a cell array region CAR and a connection region CNR on one side of the cell array region CAR.

[0084] According to some embodiments, unit string ( Figure 1 The CSTR (Cellular Array Component) can be integrated into the cell array region CAR of the horizontal semiconductor layer 100. Multiple electrode structures ST (Standard Electrode Components) can be mounted on the horizontal semiconductor layer 100. For example... Figure 6 and Figure 7 As shown, the electrode structure ST can extend from the cell array region CAR to the connection region CNR in a first direction (X direction) and can be spaced apart from each other in a second direction (Y direction) perpendicular to the first direction (X direction).

[0085] Each electrode structure ST may include a first stacked insulating layer ILD1, a second stacked insulating layer ILD2, a ground-select gate electrode GGE, a unit gate electrode CGE, and a series-select gate electrode SGE, which are alternately stacked in a third direction (Z direction, i.e., the vertical direction) perpendicular to the first and second directions (X and Y directions).

[0086] Each electrode structure ST may include multiple vertically stacked unit gate electrodes CGE, multiple ground select gate electrodes GGE horizontally spaced from each other by ground select gate cut regions GGIR and arranged below the bottom unit gate electrode CGE, and multiple string select gate electrodes SGE horizontally spaced from each other and arranged on the top unit gate electrode CGE.

[0087] In each electrode structure ST, multiple ground-selective gate electrodes GGE can be at the same level as or at the same level from the top surface of the horizontal semiconductor layer 100, and multiple unit gate electrodes CGE can be at a different level from the top surface of the horizontal semiconductor layer 100.

[0088] In each electrode structure ST, the bottommost ground-select gate electrode GGE can be used as a ground-select transistor. Figure 1 In the GST), its control common source line ( Figure 1 The electrical connection between the CSL (string select transistor) and the vertical structure VS. The topmost string select gate electrode SGE can be used as the first string select transistor and the second string select transistor (string select transistor). Figure 1 The gate electrodes (SST1 and SST2) control the electrical connection between the zero bit line BL0 to the second bit line BL2 and the vertical structure VS. The cell gate electrode CGE can be used as a memory cell ( Figure 1 The control gate electrode of the MCT (e.g., in the MCT) Figure 1 (WL0 to WLn and DWL in the range).

[0089] Multiple vertical structures VS connected to the zero bit line BL0 to the second bit line BL2 and the bit line contact plug BPLG can penetrate the electrode structure ST in the cell array region CAR and connect to the horizontal semiconductor layer 100. In a plan view, the vertical structures VS can be arranged in one direction or in a zigzag pattern. The vertical structures VS can include semiconductor materials such as Si, Ge, or mixtures thereof (i.e., combinations thereof).

[0090] The vertical structure VS can include doped semiconductors or intrinsic semiconductors without impurities. A vertical structure VS comprising semiconductor materials can be used as a reference. Figure 1 The channels of the selection transistors (e.g., SST and GST), memory cells MCT, and dummy cells DMC are described herein. References are made to this document. Figure 9A and Figure 9B A more detailed description of the vertical structure VS.

[0091] Reference Figure 9A Each vertical structure VS may include a lower semiconductor pattern LSP and an upper semiconductor pattern USP. The lower semiconductor pattern LSP may be an epitaxial layer grown from the horizontal semiconductor layer 100. The lower semiconductor pattern LSP may be a columnar shape filling the lower part of the vertical via. The top surface of the lower semiconductor pattern LSP may be located above the top surface of the bottommost ground selection gate electrode GGE. The upper semiconductor pattern USP may be connected to the lower semiconductor pattern LSP and may include Si, Ge, or a mixture thereof.

[0092] The bit-line conductive pads can be disposed on the top of each upper semiconductor pattern USP, and can be impurity regions doped with impurities, or can include conductive material. The upper semiconductor pattern USP can include a first semiconductor pattern SP1 and a second semiconductor pattern SP2. The first semiconductor pattern SP1 can be connected to the lower semiconductor pattern LSP, and can be tubular or tube-shaped with a closed bottom.

[0093] The interior of the first semiconductor pattern SP1 of this type can be filled with a buried insulating pattern V1. The first semiconductor pattern SP1 can electrically connect the second semiconductor pattern SP2 to the lower semiconductor pattern LSP. The second semiconductor pattern SP2 can be a tubular or tube-shaped structure with open top and bottom. The second semiconductor pattern SP2 can be spaced apart from the lower semiconductor pattern LSP without contacting it.

[0094] As another example, see Figure 9B Similar to the above-described upper semiconductor pattern USP, each vertical structure VS may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2. In this case, the first semiconductor pattern SP1 may be in direct contact with the horizontal semiconductor layer 100, and the interior of the first semiconductor pattern SP1 may be filled with a buried insulating pattern VI.

[0095] In addition, refer to Figure 9A and Figure 9B A vertical insulating pattern VP can be located between the electrode structure ST and the vertical structure VS. The vertical insulating pattern VP can be tubular or hollow powder-like with open top and bottom. The vertical insulating pattern VP can extend in the third direction (Z direction) and can surround the sidewalls of each vertical structure VS. When the vertical structure VS comprises a lower semiconductor pattern LSP and an upper semiconductor pattern USP, the vertical insulating pattern VP can surround the sidewalls of the upper semiconductor pattern USP.

[0096] In embodiments of the present invention, the vertical insulating pattern VP can be part of a data storage layer. For example, the vertical insulating pattern VP can include a tunnel insulating layer (TIL), a charge storage layer (CIL), and a barrier insulating layer (BLK) as the data storage layer of a NAND flash memory device. For example, the charge storage layer (CIL) can be an insulating layer including a trap insulating layer, a floating gate electrode, or conductive nanodots.

[0097] The horizontal insulating pattern HP may be located between one of the sidewalls of the ground select gate electrode GGE, the cell gate electrode CGE, and the string select gate electrode SGE and the vertical insulating pattern VP, and may extend to the top and bottom surfaces of each of the ground select gate electrode GGE, the cell gate electrode CGE, and the string select gate electrode SGE. The horizontal insulating pattern HP may include a barrier insulating layer as part of the data storage layer of the NAND flash memory device.

[0098] Refer again Figures 6 to 8 In each electrode structure ST, the ground-selective gate electrode GGE, the unit gate electrode CGE, and the string-selective gate electrode SGE can be stacked to form a stepped structure in the connection region CNR. Therefore, the height of each electrode structure ST can be reduced by moving away from the unit array region CAR. The lengths of the ground-selective gate electrode GGE, the unit gate electrode CGE, and the string-selective gate electrode SGE in the first direction (X direction) of each electrode structure ST can be reduced by moving away from the horizontal semiconductor layer 100. In some embodiments, each electrode structure ST may include a lower stepped structure Sa, an intermediate stepped structure Sb, and an upper stepped structure Sc, which are sequentially disposed on the horizontal semiconductor layer 100 in the first direction (X direction).

[0099] The electrode structure ST can sequentially include a lower region, a middle region, and an upper region in a third direction (Z direction) perpendicular to the top surface of the horizontal semiconductor layer 100. The ground selection gate electrode GGE and the unit gate electrode CGE disposed in the lower region of the electrode structure ST can form a lower stepped structure Sa, and the unit gate electrode CGE disposed in the middle region of the electrode structure ST can form an intermediate stepped structure Sb. The unit gate electrode CGE and the series selection gate electrode SGE disposed in the upper region of the electrode structure ST can form an upper stepped structure Sc.

[0100] As referenced above Figure 4 and Figure 5 Each electrode structure ST may include a first wiring portion having a first width W1 and a second wiring portion having a second width W2. Additionally, a through wiring structure THV may be provided between the second wiring portions of a pair of adjacent electrode structures ST. The through wiring structure THV may be included in the first contact area 120.

[0101] A through-wire structure THV may include: a through-insulation pattern 200 penetrating a portion of the horizontal semiconductor layer 100, extending in a third direction (Z direction), and penetrating some sidewalls of the electrode structure ST; a through-plug TPLG disposed in the through-insulation pattern 200; and a plurality of second conductors CLb connected to the through-plug TPLG. In a narrow sense, the through-wire structure THV may consist only of the through-insulation pattern 200 and the through-plug TPLG. In some embodiments, the through-wire structure THV may be arranged in various ways. For example, the through-wire structure THV may be located inside the electrode structure ST in a first direction (X direction), rather than between the electrode structures ST.

[0102] The through-insulation pattern 200 may extend along a third direction (Z direction) on the underlying buried insulation layer 50. The through-insulation pattern 200 may include an insulating material, such as a silicon oxide layer and a low-k dielectric layer.

[0103] In some embodiments, the through-insulation pattern 200 may be located in a first direction (X direction) between the lower step structure Sa and the upper step structure Sc of each electrode structure ST, and in a second direction (Y direction) between the intermediate step structures Sb of a pair of electrode structures ST. In other words, the upper step structure Sc and the lower step structure Sa of each electrode structure ST may be adjacent to the through-insulation pattern 200 in the first direction (X direction). The through-insulation pattern 200 may use insulating regions that are not replaced by metal during the manufacturing process.

[0104] The through-hole plug TPLG can penetrate the through-insulation pattern 200 and be connected to the peripheral circuit wiring 33 of the peripheral logic structure PS. The through-hole plug TPLG can be connected via wire CLb to the unit gate electrode CGE of the intermediate stepped structure Sb forming the electrode structure ST. In addition, the upper buried insulation layer 150 can cover the electrode structure ST with the stepped structure and the end of the through-insulation pattern 200. The first interlayer insulation layer 151 and the second interlayer insulation layer 153 can be sequentially stacked on the upper buried insulation layer 150 and can be on the top surface of the vertical structure VS (e.g., can cover the top surface of the vertical structure VS).

[0105] The lower contact plug PLGa can penetrate the upper buried insulating layer 150 to be disposed in the lower region of the electrode structure ST, and can be connected to the ground selection gate electrode GGE and the unit gate electrode CGE forming the lower step structure Sa. The lower contact plug PLGa can be connected to the connection contact plug PPLG via a first conductor CLA extending in a first direction (X direction) or a second direction (Y direction). The connection contact plug PPLG can penetrate the upper buried insulating layer 150 and be connected to the peripheral circuit wiring 33 of the peripheral logic structure PS.

[0106] The intermediate contact plug PLGb can penetrate the upper buried insulation layer 150 to be disposed in the intermediate region of the electrode structure ST, and can be connected to the electrode (e.g., GGE) forming the intermediate step structure Sb. The intermediate contact plug PLGb can be connected to the through plug TPLG via a second wire CLb extending in a first direction (X direction) or a second direction (Y direction).

[0107] The lower contact plug PLGa can penetrate the upper buried insulating layer 150 to be disposed in the upper region of the electrode structure ST, and can be connected to the unit gate electrode CGE and the series select gate electrode SGE disposed in the upper region of the electrode structure ST. The upper contact plug PLGc can be connected to the through plug TPLG via a third conductor CLc extending in a first direction (X direction) or a second direction (Y direction).

[0108] According to some embodiments, a first gate isolation region GIR1 penetrating each electrode structure ST in the cell array region CAR and a second gate isolation region GIR2 penetrating each electrode structure ST in the connection region CNR can be provided. The first gate isolation region GIR1 and the second gate isolation region GIR2 can be referred to as isolation regions (or sub-isolation regions) separating the electrode structures ST. According to some embodiments, the string select gate cut region SSIR of the isolation string select gate electrode can be in the cell array region CAR.

[0109] In this configuration, the first gate isolation region GIR1 can extend parallel to each other in the first direction (X direction), and the second gate isolation region GIR2 can extend parallel to each other in the first direction (X direction). A portion of the second gate isolation region GIR2 can be incorporated into a second wiring portion having a second width W2 in the electrode structure ST.

[0110] The first gate isolation region GIR1 may be spaced apart from the second gate isolation region GIR2 in a first direction (X direction). In the example, three first gate isolation regions GIR1 and three second gate isolation regions GIR2 are shown for each electrode structure ST, but the inventive concept is not limited thereto, and the corresponding number of first gate isolation regions GIR1 and second gate isolation regions GIR2 may vary depending on the integration level and process conditions of the 3D semiconductor memory device 5-3.

[0111] In the connection region CNR, a dummy gate isolation region DIR that penetrates the electrode structure ST can be provided. The dummy gate isolation region DIR can have a line shape extending in a first direction (X direction), but can be spaced apart from the second gate isolation region GIR2. The dummy gate isolation region DIR can be provided in a first wiring portion of the electrode structure ST located in the connection region CNR, having a first width W1.

[0112] Electrode separation regions (ESRs) can be disposed between adjacent electrode structures (STs), and one of the ESRs can extend in a straight line from the cell array region (CAR) to the connection region (CNR) in a first direction (X direction). The other ESR can be bent in a second direction (Y direction) to extend from the cell array region (CAR) around the through-insulation pattern 200 and can extend into the connection region (CNR).

[0113] The ground select gate dicing region GGIR can be located in the second direction (Y direction) between the lowest ground select gate electrodes GGE in each electrode structure ST, and each ground select gate dicing region GGIR can be located in the first direction (X direction) between the first gate isolation region GIR1 and the second gate isolation region GIR2.

[0114] As described above, since a first gate isolation region GIR1, a second gate isolation region GIR2, and a ground select gate cut region GIR are provided in each electrode structure ST, the bottommost ground select gate electrode GGE can be spaced apart from each other in the second direction (Y direction) and can be electrically isolated from each other in each electrode structure ST.

[0115] Furthermore, a common source region CSR can be provided in the horizontal semiconductor layer 100 below the first gate isolation region GIR1 of the through electrode structure ST. The common source region CSR can extend parallel to the first gate isolation region GIR1 in a first direction (X direction). The common source region CSR may include a conductivity type impurity opposite to that of the horizontal semiconductor layer 100, such as an N-type impurity (e.g., arsenic (As) or phosphorus (P)).

[0116] In some embodiments, the common source region CSR may not be formed in the horizontal semiconductor layer 100 below the first gate isolation region GIR1, but may be formed as an end of the horizontal semiconductor layer 100.

[0117] Here, refer to Figure 10 Describe the arrangement of the zero-th ground gate electrode GGE0 to the third ground gate electrode GGE3.

[0118] Reference Figure 10 When three first gate isolation regions GIR1 and three second gate isolation regions GIR2 are provided for each electrode structure ST, an electrode structure ST may include the zero ground gate electrode GGE0 to the third ground gate electrode GGE3.

[0119] At the level of the zeroth ground gate electrode GGE0 to the third ground gate electrode GGE3, the zeroth ground gate electrode GGE0 to the third ground gate electrode GGE3 can be electrically isolated by a ground-selective gate cleaving region GGIR. As described above, the ground-selective gate cleaving region GGIR can be formed in at least one of the cell array region CAR and the connection region CNR. The ground-selective gate cleaving region GGIR can be formed in a first direction (X direction) between the cell array region CAR and the connection region CNR.

[0120] The ground select gate cut region GGIR can contact or overlap with the first contact region 120 in the connection region CNR. The ground select gate cut region GGIR can electrically isolate the ground select gate electrodes GGE from each other, and thus can improve the reliability of the 3D semiconductor memory device 5-3.

[0121] Figures 11A to 11C The diagram illustrates the planar and vertical overlap relationships between the isolation region and the ground select gate dicing region of a 3D semiconductor memory device, according to an embodiment of the present invention.

[0122] 3D semiconductor memory devices can be arranged in various ways on the horizontal plane of the ground-selectable gate electrode GGE, with different planar overlaps between the first gate isolation region GIR1 and the second gate isolation region GIR2 and the first ground-selectable gate dicing region GGIR1 and the second ground-selectable gate dicing region GGIR2.

[0123] In some embodiments, such as Figure 11A As shown, a 3D semiconductor memory device may include two of a first gate isolation region GIR1 and a second gate isolation region GIR2 that are spaced apart from each other in a first direction (X direction). Figure 11C This is a cross-sectional view along the centerline CETL. For example... Figure 11A and Figure 11C As shown, the first gate isolation region GIR1 may have a first end EP1. The second gate isolation region GIR2 may include a second end EP2 opposite to the first end EP1.

[0124] The first selected gate cutting region GGIR1 may have a first end ED1 and a second end ED2. The length (LXL or width) of the first selected gate cutting region GGIR1 in the first direction (X direction) may be greater than the length (SXL or width) in the second direction (Y direction).

[0125] The first selected gate dicing region GGIR1 may overlap with the first end EP1 of the first gate isolation region GIR1 and the second end EP2 of the second gate isolation region GIR2, respectively. The first end ED1 and the second end ED2 of the first selected gate dicing region GGIR1 may overlap with the first end EP1 of the first gate isolation region GIR1 and the second end EP2 of the second gate isolation region GIR2 in a planar manner (e.g., in a plan view). The length SXL (or width) of the first selected gate dicing region GGIR1 in the second direction (Y direction) may be greater than the length (or width) of the first gate isolation region GIR1 and the second gate isolation region GIR2 in the second direction (Y direction).

[0126] Additionally, the first selected gate dicing region GGIR1 may overlap with the first gate isolation region GIR1 and the second gate isolation region GIR2, such that the center line CETL passing through the center point CE coincides with the center line CETL of the first gate isolation region GIR1 and the second gate isolation region GIR2 in the first direction (X direction). In some embodiments, the first selected gate dicing region GGIR1 may overlap with the first gate isolation region GIR1 and the second gate isolation region GIR2, such that the center line CETL passing through the center point CE does not coincide with the center line CETL of the first gate isolation region GIR1 and the second gate isolation region GIR2 in the first direction (X direction).

[0127] In some embodiments, the width (or length) of either the first gate isolation region GIR1 or the second gate isolation region GIR2 (e.g., the first gate isolation region GIR1) in the second direction (Y direction) may be equal to or less than the width (SXL, or length) of the first selected gate cut region GGIR1.

[0128] In some embodiments, such as Figure 11B As shown, a 3D semiconductor memory device may include one of a first gate isolation region GIR1 extending in a first direction (X direction). The first gate isolation region GIR1 may include a first end EP1.

[0129] The second selected gate cutting region GGIR2 may include a first end ED1. In the first selected gate cutting region GGIR2, the length LXL2 in the first direction (X direction) may be greater than the length SXL in the Y direction. In the second selected gate cutting region GGIR2, the length LXL2 in the first direction (X direction) may be the sum of a first length LXLa and a second length LXLb. The first length LXLa may be less than or equal to the second length LXLb.

[0130] The second selected gate dicing region GGIR2 may overlap with the first end EP1 of the first isolation region GIR1 in a planar manner. The first end ED1 of the second selected gate dicing region GGIR2 may overlap with the first end EP1 of the first gate isolation region GIR1. The second selected gate dicing region GGIR2 may include: a first length LXLa that overlaps with the first end EP1 of the first gate isolation region GIR1 in a planar manner; and a second length LXLb that does not overlap with the first end EP1 of the first gate isolation region GIR1 in a planar manner.

[0131] exist Figures 11A to 11CThe isolation regions exemplarily show a first gate isolation region GIR1 and a second gate isolation region GIR2, but the first isolation region GIR1 and the second isolation region GIR2 may include an electrode separation region ESR (e.g., may be part of the electrode separation region ESR).

[0132] Figure 12A and Figure 12B This is a layout diagram illustrating the planar overlap relationship between the isolation region, the first contact region, and the ground select gate dicing region of a 3D semiconductor memory device according to an embodiment of the present invention.

[0133] 3D semiconductor memory devices can have various horizontal layouts of ground-selectable gate electrodes GGE, with different planar overlaps between the first gate isolation region GIR1 and the second gate isolation region GIR2, the first contact region 120 including the through wiring structure THV, and the first ground-selectable gate dicing region GGIR1 and the second ground-selectable gate dicing region GGIR2.

[0134] In some embodiments, such as Figure 12A As shown, the 3D semiconductor memory device may include a third ground-select gate dicing region GGIR3 extending in a first direction (X direction). The first gate isolation region GIR1 may include a first end EP1.

[0135] The third-location gate cutting region GGIR3 may include a first end ED1 and a second end ED2. In the third-location gate cutting region GGIR3, the length LXL2 in the first direction (X direction) may be greater than the length SXL in the Y direction. In the third-location gate cutting region GGIR3, the length LXL2 in the first direction (X direction) may be the sum of the first length LXLa and the second length LXLb.

[0136] The third selected gate dicing region GGIR3 can overlap with the first end EP1 of the first gate isolation region GIR1 in a planar manner. The second end ED2 of the first selected gate dicing region GGIR1 can overlap with the first contact region 120 in a planar manner.

[0137] In some embodiments, such as Figure 12B As shown, a 3D semiconductor memory device may include a first gate isolation region GIR1 and a second gate isolation region GIR2. The first gate isolation region GIR1 extends in a first direction (X direction), and the second gate isolation region GIR2 extends in the first direction (X direction) and is spaced apart from the first gate isolation region GIR1 in a second direction (Y direction). The first gate isolation region GIR1 and the second gate isolation region GIR2 may each include a first end EP1 and a second end EP2.

[0138] The fourth selected gate cutting region GGIR4 can be arranged along the second direction (Y direction) and includes a first end ED1 and a second end ED2. In the fourth selected gate cutting region GGIR4, the length LXL2 in the second direction (Y direction) can be greater than the length SXL in the first direction (X direction).

[0139] The fourth selected gate dicing region GGIR4 can overlap in a planar manner with the first end EP1 of the first gate isolation region GIR1 and the second end EP2 of the second gate isolation region GIR2, respectively. The first end ED1 and the second end ED2 of the fourth selected gate dicing region GGIR4 can overlap in a planar manner with the second end EP2 of the second gate isolation region GIR2 and the first end of the first gate isolation region GIR1, respectively.

[0140] exist Figure 12A and Figure 12B The isolation regions exemplarily show a first gate isolation region GIR1 and a second gate isolation region GIR2, but the first isolation region GIR1 and the second isolation region GIR2 may include an electrode separation region ESR (e.g., may be part of the electrode separation region ESR).

[0141] Figure 13 This is a cross-sectional view showing an exemplary embodiment of a 3D semiconductor memory device 5-4 according to the concept of the present invention.

[0142] When with Figures 5 to 10 When comparing with 3D semiconductor memory device 5-3, 3D semiconductor memory device 5-4 can be almost identical to 3D semiconductor memory device 5-3, except that 3D semiconductor memory device 5-4 includes two first contact regions 120 and 120-1. (Referencing...) Figure 13 In the description, you can briefly explain or omit references. Figures 5 to 10 The content being described is the same.

[0143] The 3D semiconductor memory device 5-4 may include: a first contact region 120, including a first through wiring structure THV; and a second contact region 120-1, including a second through wiring structure THV-1. The first contact region 120 and the second contact region 120-1 may be spaced apart from each other.

[0144] The first through-wire structure THV may include: a through-insulation pattern 200 that penetrates a portion of the horizontal semiconductor layer 100, extends in the third direction (Z direction), and penetrates some sidewalls of the electrode structure ST; a through-plug TPLG disposed in the through-insulation pattern 200; and a plurality of second conductors CLb connected to the through-plug TPLG.

[0145] The second through wiring structure THV-1 may include: a through insulation pattern 200 that penetrates a portion of the horizontal semiconductor layer 100, extends in the third direction (Z direction), and penetrates some sidewalls of the electrode structure ST; a through plug TPLG-1 disposed in the through insulation pattern 200; and a plurality of second conductors CLb-1 connected to the through plug TPLG-1.

[0146] The second upper contact plug PLGc-1 can be located between the first contact region 120 and the second contact region 120-1. The second upper contact plug PLGc-1 can penetrate the upper buried insulating layer 150 to be disposed in the second upper region of the electrode structure ST, and can be connected to the ground selection gate electrode GGE forming the second upper stepped structure Sc2. The second upper contact plug PLGc-1 can be connected to the through plug TPLG-1 via the fourth wire CLc-1.

[0147] The first contact region 120 and the second contact region 120-1 can be insulating regions that are not replaced by metal during manufacturing. In some embodiments, the common source region CSR may not be formed in the horizontal semiconductor layer 100 below the first gate isolation region GIR1, but may be formed as an end of the contact horizontal semiconductor layer 100.

[0148] Figure 14 This is a block diagram illustrating the arrangement relationship between the cell array region CAR and the connection region CNR of the 3D semiconductor memory device 5-5 according to an embodiment of the present invention.

[0149] As described above, the 3D semiconductor memory device 5-5 according to an embodiment of the present invention may include a cell array region CAR and a first connection region CNR1 and a second connection region CNR2 electrically connected to the cell array region CAR.

[0150] The cell array region CAR may include (n-1)th storage blocks BLKn-1 to (n+10)th storage blocks BLKn+10 in the second direction (Y direction) (where n is a positive integer of 1 or greater than 1). Twelve storage blocks ((n-1)th storage blocks BLKn-1 to (n+10)th storage blocks BLKn+10) are shown, but this is only an example. The first connection region CNR1 and the second connection region CNR2 may include (n-1)th extension blocks EXTn-1 to (n+10)th extension blocks EXTn+10, which include through-hole cabling structures THV. Twelve extension blocks ((n-1)th extension blocks EXTn-1 to (n+10)th extension blocks EXTn+10) are shown, but this is only an example.

[0151] The first connection region CNR1 can be arranged along the first direction (X direction) on one side of the first storage blocks (BLKn, BLKn+2, BLKn+4, BLKn+6, BLKn+8, and BLKn+10), which are the storage blocks with even-numbered addresses in the second direction (Y direction) from the (n-1)th storage blocks BLKn-1 to the (n+10)th storage blocks BLKn+10. The first connection region CNR1 can include a second sub-extension region group 2GER, a fourth sub-extension region group 4GER, and a sixth sub-extension region group 6GER. The second sub-extension region group 2GER, the fourth sub-extension region group 4GER, and the sixth sub-extension region group 6GER can be regions that are adjacent to each other in the first connection region CNR1 and each includes a storage block between them in the second direction (Y direction).

[0152] The second sub-extension group 2GER may include an nth extension block EXTn and an (n+2)th extension block EXTn+2 connected to the nth memory block BLKn and the (n+2)th memory block BLKn+2, respectively. The fourth sub-extension group 4GER may include an (n+4)th extension block EXTn+4 and an (n+6)th extension block EXTn+6 connected to the (n+4)th memory block BLKn+4 and the (n+6)th memory block BLKn+6, respectively. The sixth sub-extension group 6GER may include an (n+8)th extension block EXTn+4 and an (n+10)th extension block EXTn+10 connected to the (n+8)th memory block BLKn+8 and the (n+10)th memory block BLKn+10, respectively.

[0153] The second connection region CNR2 can be arranged along the first direction (X direction) on one side of the second storage blocks (BLKn-1, BLKn+1, BLKn+3, BLKn+5, BLKn+7, and BLKn+9), which are the odd-numbered storage blocks in the second direction from the (n-1)th storage block BLKn-1 to the (n+10)th storage block BLKn+10. The second connection region CNR2 can include a first sub-extension region group 1GER, a third sub-extension region group 3GER, and a fifth sub-extension region group 5GER. The first sub-extension region group 1GER, the third sub-extension region group 3GER, and the fifth sub-extension region group 5GER can be regions that are adjacent to each other in the second connection region CNR2 and each includes a storage block between them in the second direction (Y direction).

[0154] The first sub-extension group 1GER may include the (n-1) extension block EXTn-1 and the (n+1) extension block EXTn+1, which are connected to the (n-1)th storage block BLKn-1 and the (n+1)th storage block BLKn+1, respectively. The third sub-extension group 3GER may include the (n+3) extension block EXTn+3 and the (n+5) extension block EXTn+5, which are connected to the (n+3)th storage block BLKn+3 and the (n+5)th storage block BLKn+5, respectively. The fifth sub-extension group 5GER may include the (n+7) extension block EXTn+3 and the (n+9) extension block EXTn+9, which are connected to the (n+7)th storage block BLKn+7 and the (n+9)th storage block BLKn+9, respectively. The aforementioned 3D semiconductor memory device 5-5 can improve integration density by efficiently arranging the (n-1)th memory blocks BLKn-1 to (n+10)th memory blocks BLKn+10 and the (n-1)th interconnect blocks EXTn-1 to (n+10)th interconnect blocks EXTn+10 within a unit area. Specifically, each pair of memory blocks BLK in the corresponding sub-extended region group can have another memory block (from a different sub-extended region group) extending between them.

[0155] Figure 15 This is a schematic layout diagram illustrating a 3D semiconductor memory device 5-5 according to an embodiment of the present invention. Figure 16 It is along Figure 15 The cross-sectional view taken from line AB in the diagram. Figure 17 It is along Figure 15 The cross-sectional view of line BC, and Figure 18 It is along Figure 15 The cross-sectional view taken from line DE.

[0156] 3D semiconductor memory devices 5-5 can be used in applications Figure 14 An example of the arrangement relationship between the cell array region CAR and the connection region CNR in a [structure / system]. Figure 15 For convenience, only the connection region CNR located on one side of the cell array region CAR is shown. The 3D semiconductor memory device 5-5 may include: a cell array region CAR, which includes a (n-1)th memory block BLKn-1, an nth memory block BLKn, a (n+1)th memory block BLKn+1, a (n+2)th memory block BLKn+2, and a (n+3)th memory block BLKn+3; and a connection region CNR connected to the nth memory block BLKn and the (n+2)th memory block BLKn+2.

[0157] like Figures 16 to 18As shown, each electrode structure ST may include a first insulating layer ILD1 and a second insulating layer ILD2, a ground select gate electrode GGE, a unit gate electrode CGE, and a series select gate electrode SGE, which are alternately stacked in a third direction (Z direction; i.e., the vertical direction) perpendicular to the first and second directions (X and Y directions).

[0158] Each electrode structure ST may include multiple vertically stacked unit gate electrodes CGE, multiple ground select gate electrodes GGE horizontally spaced from each other by ground select gate cut regions GGIR and arranged below the bottom unit gate electrode CGE, and multiple string select gate electrodes SGE horizontally spaced from each other and arranged on the top unit gate electrode CGE.

[0159] In each electrode structure ST, as described above, multiple ground-selective gate electrodes GGE can be at the same level as / at the same level from the top surface of the horizontal semiconductor layer 100, and multiple unit gate electrodes CGE can be located at a different level from the top surface of the horizontal semiconductor layer 100. An initial insulating layer IO can be formed on the horizontal semiconductor layer 100 as needed / desired.

[0160] refer to Figure 16 and Figure 17 In each electrode structure ST, the ground-selective gate electrode GGE, the unit gate electrode CGE, and the string-selective gate electrode SGE can be stacked to form a stepped structure in the connection region CNR. Therefore, the height of each electrode structure ST can be reduced by moving away from the unit array region CAR. The lengths of the ground-selective gate electrode GGE, the unit gate electrode CGE, and the string-selective gate electrode SGE in the first direction (X direction) of each electrode structure ST can be reduced by moving away from the horizontal semiconductor layer 100.

[0161] In some embodiments, each electrode structure ST may include a lower step structure Sa, an intermediate step structure Sb, a second intermediate step structure Sb2, a first intermediate step structure Sb1, and an upper step structure Sc, which are sequentially disposed on the horizontal semiconductor layer 100 in a first direction (X direction).

[0162] The electrode structure ST can sequentially include a lower region, a middle region, and an upper region in a third direction (Z direction) perpendicular to the top surface of the horizontal semiconductor layer 100. The unit gate electrode CGE and the ground selection gate electrode GGE disposed in the lower region of the electrode structure ST can form a lower stepped structure Sa. The unit gate electrode CGE disposed in the middle region of the electrode structure ST can form a second intermediate stepped structure Sb2 and a first intermediate stepped structure Sb1. The unit gate electrode CGE and the series selection gate electrode SGE disposed in the upper region of each electrode structure ST can form an upper stepped structure Sc.

[0163] The electrode structure ST may include a fourth planarization region FPTHV4, a third planarization region FPTHV3, a second planarization region FPTHV2, a first planarization region FPTHV1, and a select gate planarization region SGPA. In the fourth planarization region FPTHV4, the third planarization region FPTHV3, the second planarization region FPTHV2, the first planarization region FPTHV1, and the select gate planarization region SGPA, the string select gate electrode SGE, the cell gate electrode CGE, and the ground select gate electrode GGE may have their exposed surfaces and thus can be used as string select line pads, word line pads, and ground select line pads, respectively.

[0164] The third flattening region FPTHV3 can be located between the lower stepped structure Sa and the second intermediate stepped structure Sb2. The second flattening region FPTHV2 can be located between the second intermediate stepped structure Sb2 and the first intermediate stepped structure Sb1. The first flattening region FPTHV1 can be located between the upper stepped structure Sc and the first intermediate stepped structure Sb1. The fourth flattening region FPTHV4, the third flattening region FPTHV3, the second flattening region FPTHV2, and the first flattening region FPTHV1 can be regions adjacent to the first contact region 120.

[0165] like Figure 15 As shown, each electrode structure ST may include a first wiring portion having a third width W3 and a second wiring portion having a fourth width W4. A first contact area 120 including multiple through wiring structures THV may be provided in the second wiring portion between the electrode structures ST. (Previously referenced...) Figure 8 , Figure 13 The description of the first contact area 120 is given, and its repeated description can be omitted.

[0166] Furthermore, multiple electrode structures ST can extend from the cell array region CAR to the connection region CNR in a first direction (X direction). The electrode structures ST can be spaced apart from each other in a second direction (Y direction) perpendicular to the first direction (X direction). Adjacent electrode structures ST can be spaced apart from each other in the second direction (Y direction) perpendicular to the first direction (X direction) through an electrode separation region ESR. The electrode separation region ESR can penetrate the electrode structures ST and separate the individual electrode structures ST. The electrode separation region ESR can be referred to as the separation region.

[0167] According to some embodiments, a first gate isolation region GIR1 that penetrates each electrode structure ST in the cell array region CAR and a second gate isolation region GIR2 that penetrates each electrode structure ST in the connection region CNR can be provided. The first gate isolation region GIR1 can extend parallel to each other in a first direction (X direction), and the second gate isolation region GIR2 can extend parallel to each other in the first direction (X direction).

[0168] In some embodiments, two second gate isolation regions GIR2 are shown for each electrode structure ST in the connection region CNR, but the inventive concept is not limited thereto, and the corresponding number of the first gate isolation region GIR1 and the second gate isolation region GIR2 can vary depending on the integration level and process conditions of the 3D semiconductor memory device 5-5.

[0169] In the connected region CNR, such as Figure 18 As shown, in addition to the ground gate electrode GGE, a dummy gate cut region DGIR can be provided through the electrode structure ST. The dummy gate isolation region DIR can be provided in the second wiring portion of the electrode structure ST with a fourth width W4 located in the connection region CNR.

[0170] Electrode separation regions (ESRs) can be positioned between adjacent electrode structures (STs). One of the ESRs can extend along a straight line from the cell array region (CAR) to the connection region (CNR).

[0171] like Figure 18 As shown, a ground selection gate cleaving region GGIR can be provided between the bottommost ground selection gate electrodes GGE in the electrode structure ST in the second direction (Y direction). As described above, since a bottommost ground selection gate cleaving region GIR is provided in each electrode structure ST, the bottommost ground selection gate electrodes GGE in each electrode structure ST can be spaced apart from each other in the second direction (Y direction) and can be electrically isolated from each other.

[0172] Specifically, the ground-selective gate electrodes GGE at the bottommost gate electrode layer of the electrode structure ST can be electrically isolated from each other through ground-selective gate cleaving regions GGIR. As described above, the ground-selective gate cleaving regions GGIR can be formed in at least one of the cell array region CAR and the connection region CNR.

[0173] The ground-select gate dicing region GGIR can be formed in a first direction (X direction) between the cell array region CAR and the connection region CNR. The ground-select gate dicing region GGIR can contact or overlap with the first contact region 120 in the connection region CNR. The ground-select gate dicing region GGIR can electrically isolate the ground-select gate electrodes GGE from each other, and thus can improve the reliability of the 3D semiconductor memory device 5-3.

[0174] Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22 and Figure 23 This is a diagram illustrating a method for manufacturing a 3D semiconductor memory device 5-3 according to an embodiment of the present invention.

[0175] Figure 19A , Figure 20A , Figure 21A , Figure 22 and Figure 23 This illustrates the fabrication of 3D semiconductor memory devices ( Figure 8 The cross-sectional view of method 5-3), and Figure 19B , Figure 20B and Figure 21B It is used to describe the manufacture of 3D semiconductor memory devices ( Figure 8 The layout diagram of method 5-3) is shown. It is described using a memory block comprising two electrode structures ST. Figure 19B , Figure 20B and Figure 21B In some embodiments, an electrode structure ST can constitute a memory block.

[0176] refer to Figure 19A and Figure 19B A peripheral logic structure PS can be formed on the semiconductor substrate 10. Forming the peripheral logic structure PS may include: forming a peripheral logic circuit PTR on the semiconductor substrate 10; forming peripheral wiring structures 31 and 33 connected to the peripheral logic circuit PTR; and forming a lower buried insulating layer 50.

[0177] A horizontal semiconductor layer 100 may be formed on the lower buried insulating layer 50. As described above, the horizontal semiconductor layer 100 may include cell array regions (CAR) and connection regions (CNR). For example, the horizontal semiconductor layer 100 may be formed by depositing a polysilicon layer to cover the entire surface of the lower buried insulating layer 50 and then patterning the polysilicon layer. During the deposition of the polysilicon layer, impurities of a first conductivity type may be doped into the polysilicon layer. The horizontal semiconductor layer 100 may be patterned to expose a portion of the lower buried insulating layer 50.

[0178] Next, a lower sacrificial layer SL1 with a gate opening OP can be formed on the horizontal semiconductor layer 100. The gate opening OP can be formed by etching the lower sacrificial layer SL1 so that a portion of the horizontal semiconductor layer 100 is exposed in the connection region CNR. Figure 19B As shown, the gate openings OP can be spaced apart from each other in the second direction (Y direction). The gate openings OP can also be spaced apart from each other in the first direction (X direction).

[0179] Reference Figure 20A and Figure 20B A ground-selective gate diced region (GGIR) can be formed in the gate opening (OP). The specific formation process of the ground-selective gate diced region (GGIR) will be described later. The ground-selective gate diced region (GGIR) and the lower insulating layer (ILD1) can be formed covering the entire surface of the horizontal semiconductor layer 100. The lower insulating layer (ILD1) can have a planarized top surface.

[0180] Next, a molded structure 110 in which the upper sacrificial layer SL2 and the upper insulating layer ILD2 are vertically and alternately stacked can be formed on the lower insulating layer ILD1. For example, the lower sacrificial layer SL1 and the upper sacrificial layer SL2 may comprise silicon nitride layers.

[0181] By using a trimming process in the connection region CNR of the horizontal semiconductor layer 100, the molded structure 110 can have a stepped structure. Through the trimming process, the molded structure 110 can have a lower stepped structure Sa, an intermediate stepped structure Sb, and an upper stepped structure Sc, which have a downward shape as they move away from the cell array region CAR. Figure 20B As shown, the upper stepped structure Sc of the molded structure 110 can overlap with the ground selection grid cutting region GGIR.

[0182] After the molding structure 110 is formed, an upper buried insulating layer 150 can be formed on the entire surface of the horizontal semiconductor layer 100. The upper buried insulating layer 150 can have a substantially flat top surface. The upper buried insulating layer 150 can be formed by forming a buried insulating layer that is thicker than the molding structure 110 and then performing a planarization process.

[0183] Reference Figure 21A and Figure 21B This allows for the formation of a through-insulating pattern 200 that penetrates a portion of the molded structure 110, a portion of the lower sacrificial layer SL1, and a portion of the horizontal semiconductor layer 100. In this example, the through-insulating pattern 200 may penetrate a portion of the intermediate step structure Sb of the molded structure 110. Figure 21B The through-insulation pattern 200 may be spaced apart from the ground selection gate cut region GGIR formed in the lower sacrificial layer SL1.

[0184] Reference Figure 22 A vertical structure VS can be formed on the horizontal semiconductor layer 100 of the cell array region CAR, consisting of a through-molded structure 110, a lower insulating layer ILD1, and a lower sacrificial layer SL1. Next, a first interlayer insulating layer 151 covering the top surface of the vertical structure VS can be formed on the upper buried insulating layer 150. After forming the first interlayer insulating layer 151, a first gate isolation region GIR1 and a second gate isolation region GIR2 can be formed, exposing the horizontal semiconductor layer 100 through the through-molded structure 110, the lower sacrificial layer SL1, the dummy gate isolation region DIR, and the electrode isolation region ESR.

[0185] In some embodiments, the first gate isolation region GIR1 may extend parallel to each other in the cell array region CAR along a first direction (X direction). The second gate isolation region GIR2 may be spaced apart from the first gate isolation region GIR1 in the first direction (X direction), and the ground selected gate dicing region GGIR is located between the second gate isolation region GIR2 and the first gate isolation region GIR1.

[0186] Reference Figure 23 The electrode structure ST can be formed by performing a process that replaces the lower sacrificial layer SL1 and upper sacrificial layer SL2 exposed in the first gate isolation region GIR1 and the second gate isolation region GIR2, the dummy gate isolation region DIR, and the electrode separation region ESR with a ground selection gate electrode GGE, a unit gate electrode CGE, and a string selection gate electrode SGE.

[0187] A gate region can be formed between the lower insulating layer ILD1 and the upper insulating layer ILD2 by removing the lower sacrificial layer SL1 and the upper sacrificial layer SL2, the dummy gate isolation region DIR, and the electrode isolation region ESR exposed to the first gate isolation region GIR1 and the second gate isolation region GIR2. The lower sacrificial layer SL1 and the upper sacrificial layer SL2 can be isotropically etched using an etch formulation that is etch-selective to the lower insulating layer ILD1 and the upper insulating layer ILD2, the vertical structure VS, and the semiconductor substrate 10. The gate region can extend horizontally between the lower insulating layer ILD1 and the upper insulating layer ILD2 and expose a portion of the sidewalls of the vertical structure VS.

[0188] Next, a horizontal insulating pattern can be formed in the gate region. Figure 9A and Figure 9BThe horizontal insulating pattern HP and the ground select gate electrode GGE, the unit gate electrode CGE, and the series select gate electrode SGE are formed by sequentially forming a horizontal insulating layer, a barrier metal layer (e.g., TiN, tantalum nitride (TaN), or WN), and a metal layer (e.g., W) on a molded structure 110 in which the gate region is formed, and by anisotropically etching the barrier metal layer and the metal layer already deposited inside the trench. In this case, the horizontal insulating pattern HP may be part of the data storage layer of the NAND flash memory transistor and may include a silicon oxide layer and / or a high-k dielectric layer.

[0189] After forming the ground selection gate electrode GGE, the unit gate electrode CGE, and the series selection gate electrode SGE, the first gate isolation region GIR1, the second gate isolation region GIR2, the dummy gate isolation region DIR, and the electrode separation region ESR can be filled with insulating material. Additionally, a common source plug CPLG, connected to the common source region CSR, can be formed in the first gate isolation region GIR1 filled with insulating material.

[0190] After that, as Figure 8 As shown, the second interlayer insulating layer 153 can be formed on the first interlayer insulating layer 151. Next, bit line contact plugs BPLG for the cell array region CAR can be formed; lower contact plugs PLGa, intermediate contact plugs PLGb, and upper contact plugs PLGc connected to the ground select gate electrode GGE, the cell gate electrode CGE, and the series select gate electrode SGE in the connection region CNR; and through contact plugs TPLG and PPLG penetrating through the through insulating pattern 200.

[0191] Figures 24A to 24D This is a cross-sectional view illustrating a method for manufacturing a ground selection gate dicing region (GGIR) of a 3D semiconductor memory device according to an embodiment of the present invention.

[0192] refer to Figure 24A and Figure 24B ,like Figure 24A As shown, a lower sacrificial material layer SL1a can be formed on the horizontal semiconductor layer 100. (As illustrated...) Figure 24B As shown, a mask pattern MP1 can be formed on the lower sacrificial material layer SL1a.

[0193] Next, the lower sacrificial material layer SL1a can be selectively etched using the mask pattern MP1 as an etching mask to form the lower sacrificial layer SL1, which includes the gate opening OP. As described above, the lower sacrificial layer SL1 can be transformed into the ground select gate electrode GGE using a replacement process. Therefore, the shape or form of the ground select gate dicing region GGIR can be changed planarly in subsequent processes based on the planar overlap relationship between the lower sacrificial layer SL1 and the mask pattern MP1.

[0194] Reference Figure 24C and Figure 24D In such Figure 24C After removing the mask pattern MP1 as shown, an insulating layer IL can be formed on the lower sacrificial layer SL1, which includes the gate opening OP. Therefore, the insulating layer IL can fill the gate opening OP.

[0195] like Figure 24D As shown, the ground selection gate cut region GGIR can be formed by planarizing the insulating layer IL. Therefore, the ground selection gate cut region GGIR can be an insulating region that can have a flat upper surface. The ground selection gate cut region GGIR can be cut in one direction by post-processing to cut the ground selection gate electrode GGE. As described above, the shape or form of the ground selection gate cut region GGIR can be changed planarly according to the planar overlap relationship between the lower sacrificial layer SL1 and the mask pattern MP1.

[0196] exist Figures 24A to 24D The method for forming a ground-selective gate cut region (GGIR) is described as an example, but various methods can be used to form a ground-selective gate cut region (GGIR).

[0197] Figures 25A to 25D The illustration shows a layout diagram illustrating various overlap relationships between the gate isolation region and the ground select gate dicing region of a 3D semiconductor memory device according to an embodiment of the present invention.

[0198] As referenced above Figures 11A to 11C The 3D semiconductor memory device can have different overlap relationships between the first isolation region GIR1 and the second isolation region GIR2 and the fifth to eighth ground selection gate dicing regions GGIR5 to GGIR8 at the level of the ground selection gate electrode GGE, depending on various layouts.

[0199] like Figure 25AAs shown, the first gate isolation region GIR1 and the second gate isolation region GIR2 can be spaced apart from each other in a first direction (X direction). The first gate isolation region GIR1 and the second gate isolation region GIR2 can each include a first end EP1 and a second end EP2. The width of the first gate isolation region GIR1 and the second gate isolation region GIR2 can be L1.

[0200] The fifth selected gate dicing region GGIR5 may include a first end ED1 and a second end ED2. The width L2 of the fifth selected gate dicing region GGIR5 may be smaller than the width L1 of the first gate isolation region GIR1 and the second gate isolation region GIR2. The fifth selected gate dicing region GGIR5 may be rectangular or linear. The fifth selected gate dicing region GGIR5 may overlap planarly (e.g., in a planar view) with the first end EP1 of the first gate isolation region GIR1 and the second end EP2 of the second gate isolation region GIR2, respectively. The length (or width) of the fifth selected gate dicing region GGIR5 in the second direction (Y direction) may be smaller than the length (or width) of the first gate isolation region GIR1 and the second gate isolation region GIR2 in the second direction (Y direction).

[0201] like Figure 25B As shown, the sixth selected gate dicing region GGIR6 can overlap with the first end EP1 of the first gate isolation region GIR1 in a planar manner. The sixth selected gate dicing region GGIR6 can be rectangular or linear.

[0202] like Figure 25C As shown, the seventh selected gate dicing region GGIR7 can overlap with the first end EP1 of the first gate isolation region GIR1 in a planar manner. The seventh selected gate dicing region GGIR7 can be I-shaped.

[0203] like Figure 25D As shown, the eighth ground select gate dicing region GGIR8 can overlap with the first end EP1 of the first gate isolation region GIR1 in a planar manner. The eighth ground select gate dicing region GGIR8, including the internal via opening VO, can be rectangular or linear.

[0204] Figure 26A and Figure 26B This is a layout diagram illustrating various overlap relationships between the gate isolation region, ground gate electrode, and ground select gate dicing region of a 3D semiconductor memory device according to an embodiment of the present invention.

[0205] 3D semiconductor memory devices can be separated by electrode separation regions (ESRs) for each memory block (BLK). Multiple ground select gate electrodes (e.g., four ground select gate electrodes, from the zeroth ground select gate electrode GGE0 to the third ground select gate electrode GGE3) can be located within the memory block (BLK). Within the memory block (BLK), the zeroth ground select gate electrode GGE0 to the third ground select gate electrode GGE3 can be separated by a first gate isolation region (GIR1) and a second gate isolation region (GIR2).

[0206] like Figure 26A As shown, at the level of the zero-ground selected gate electrode GGE0 to the third-ground selected gate electrode GGE3, the ninth-ground selected gate dicing region GGIR9 can overlap with the first gate isolation region GIR1 and the second gate isolation region GIR2 with a relatively wide width W5. In other words, at the level of the zero-ground selected gate electrode GGE0 to the third-ground selected gate electrode GGE3, the ninth-ground selected gate dicing region GGIR9 can overlap with the first gate isolation region GIR1, the second gate isolation region GIR2, and the zero-ground selected gate electrode GGE0 to the third-ground selected gate electrode GGE3.

[0207] like Figure 26B As shown, at the levels of the zero-ground selected gate electrode GGE0 to the third-ground selected gate electrode GGE3, the tenth-ground selected gate dicing region GGIR10 can overlap with the first gate isolation region GIR1 and the second gate isolation region GIR2 with a narrower width W6. In other words, at the levels of the zero-ground selected gate electrode GGE0 to the third-ground selected gate electrode GGE3, the tenth-ground selected gate dicing region GGIR10 can overlap only with the first gate isolation region GIR1 and the second gate isolation region GIR2.

[0208] Figure 27A and Figure 27B This is a layout diagram illustrating various overlap relationships between the gate isolation region, contact region, ground gate electrode, and ground select gate dicing region of a 3D semiconductor memory device according to an embodiment of the present invention.

[0209] The electrode separation region (ESR) of each memory block BLK can separate multiple ground gate electrodes (e.g., three ground gate electrodes, from the zeroth ground gate electrode GGE0 to the second ground gate electrode GGE2) in the 3D semiconductor memory device. Within the memory block BLK, the zeroth ground gate electrode GGE0 to the second ground gate electrode GGE2 can be separated by the first gate isolation region GIR1 and the second gate isolation region GIR2.

[0210] like Figure 27AAs shown, at the level from the zero-ground selected gate electrode GGE0 to the second-ground selected gate electrode GGE2, the eleventh-ground selected gate dicing region GGIR11 can overlap with the first gate isolation region GIR1 and the second gate isolation region GIR2 with a relatively wide width W7. In other words, at the level from the zero-ground selected gate electrode GGE0 to the second-ground selected gate electrode GGE2, the eleventh-ground selected gate dicing region GGIR11 can overlap with the first gate isolation region GIR1, the second gate isolation region GIR2, and the zero-ground selected gate electrode GGE0 to the second-ground selected gate electrode GGE2. Furthermore, the first end ED1 and the second end ED2 of the eleventh-ground selected gate dicing region GGIR11 can overlap with the first end EP1 of the first gate isolation region GIR1 and the second end EP2 of the second gate isolation region GIR2, respectively.

[0211] like Figure 27B As shown, at the levels from the zero-select gate electrode GGE0 to the second-select gate electrode GGE2, the twelfth-place-select gate dicing region GGIR12 may overlap with the first gate isolation region GIR1 and the first contact region 120 including the through-wiring structure THV. Multiple (e.g., two) ground-select gate dicing regions GGIR12 may overlap with the first contact region 120 in a planar manner. The number of overlapping regions between the first contact region 120 and the twelfth-place-select gate dicing region GGIR12 may vary depending on the size of the first contact region 120.

[0212] Additionally, the first end ED1 of the twelfth selected gate dicing region GGIR12 can overlap with the first end EP1 of the first gate isolation region GIR1 in a planar manner. The second end ED2 of the twelfth selected gate dicing region GGIR12 can overlap with the first contact region 120 in a planar manner.

[0213] Additionally, at the level of the zero-selection gate electrode GGE0 to the second-selection gate electrode GGE2, one end EG of the zero-selection gate electrode GGE0 to the second-selection gate electrode GGE2 can contact the first contact region 120 and have a curved profile CRP. For example, at the level of the zero-selection gate electrode GGE0 to the second-selection gate electrode GGE2 (i.e., at this level), one end EG of the zero-selection gate electrode GGE0 to the second-selection gate electrode GGE2 with a curved profile CRP can be obtained by replacing the zero-selection gate electrode GGE0 to the second-selection gate electrode GGE2.

[0214] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the scope of the appended claims.

Claims

1. A three-dimensional semiconductor memory device, comprising: Semiconductor substrate; An electrode structure includes a plurality of electrodes stacked on the semiconductor substrate, the electrode structure extending along a first direction and spaced apart from each other by separation regions in a second direction perpendicular to the first direction; A ground selection gate electrode, including the lowermost electrode of the plurality of electrodes of the electrode structure, wherein the separation region includes a first end at the level of the ground selection gate electrode; as well as At least one ground selection gate cutting region overlaps with the first end of the separation region and electrically isolates the ground selection gate electrodes from each other.

2. The three-dimensional semiconductor memory device according to claim 1, wherein, The semiconductor substrate includes a cell array region and a connection region, the electrode structure extends from the cell array region to the connection region in the first direction, and the at least one ground-selected gate dicing region is located in the cell array region or the connection region.

3. The three-dimensional semiconductor memory device according to claim 1, in, The separation region also includes a second end spaced apart from and opposite to the first end, and Wherein, the at least one selected grid cutting region overlaps with both the first end and the second end of the separation region.

4. The three-dimensional semiconductor memory device according to claim 1, wherein, The length of the at least one selected gate cutting region in the second direction is greater than the length of the separation region in the second direction.

5. The three-dimensional semiconductor memory device according to claim 1, wherein, The length of the at least one selected gate cutting region in the second direction is less than the length of the separation region in the second direction.

6. The three-dimensional semiconductor memory device according to claim 1, in, The separation region includes: a first isolation region including a first end; and a second isolation region including a second end, the second isolation region being spaced apart from the first isolation region in the first direction, and Wherein, the at least one selected gate cutting region overlaps with the first end of the first isolation region and the second end of the second isolation region in a third direction perpendicular to the first direction and the second direction.

7. The three-dimensional semiconductor memory device according to claim 1, wherein, The first length of the at least one selected gate cutting region in the first direction is less than the second length of the at least one selected gate cutting region in the second direction.

8. The three-dimensional semiconductor memory device according to claim 1, wherein, The first length of the at least one ground-selected gate cutting region in the first direction is greater than the second length of the at least one ground-selected gate cutting region in the second direction.

9. The three-dimensional semiconductor memory device according to claim 1, wherein, The at least one selected grid cutting region is linear, I-shaped, or linear with internal through-hole openings.

10. The three-dimensional semiconductor memory device according to claim 1, wherein, The separation region includes an electrode isolation region or a gate isolation region.

11. A three-dimensional semiconductor memory device, comprising: The peripheral logic structure is located on a semiconductor substrate. A horizontal semiconductor layer, on the peripheral logic structure, includes a cell array region and a connection region electrically connected to the cell array region; An electrode structure includes a plurality of electrodes stacked on the horizontal semiconductor layer in the cell array region and the connection region, the electrode structure extending along a first direction and spaced apart from each other by a separation region in a second direction perpendicular to the first direction; At least one contact area, including a through wiring structure in the connection area electrically connecting the electrode structure to the peripheral logic structure; and The selected gate electrode includes the lowest electrode among the plurality of electrodes in the electrode structure of the cell array region and the connection region. The separation region includes a first end at the level of the ground-selective gate electrode, and In this configuration, at least one ground selection gate cutting region overlaps with the first end of the separation region, and the ground selection gate electrodes are electrically isolated from each other.

12. The three-dimensional semiconductor memory device of claim 11, wherein the at least one ground select gate dicing region overlaps with the at least one contact region at the level of the ground select gate electrode.

13. The three-dimensional semiconductor memory device according to claim 11, in, The at least one contact area includes a plurality of contact areas spaced apart from each other in the first direction, and The at least one selected grid cutting region is located between the plurality of contact regions.

14. The three-dimensional semiconductor memory device according to claim 11, in, The separation region includes a first portion and a second portion spaced apart from the at least one contact region in the second direction, and The first and second portions of the separated regions are parallel to each other in a straight line shape in the first direction.

15. The three-dimensional semiconductor memory device according to claim 11, wherein, At the level of the ground selection gate electrode, the profile of a side surface of the ground selection gate electrode adjacent to the at least one contact area and the at least one ground selection gate cutting area is curved.

16. A three-dimensional semiconductor memory device, comprising: The peripheral logic structure is located on a semiconductor substrate. A horizontal semiconductor layer, on the peripheral logic structure, includes a cell array region and a connection region electrically connected to the cell array region; An electrode structure includes a plurality of electrodes stacked on the horizontal semiconductor layer in the unit array region and the connection region, each electrode structure extending along a first direction and spaced apart from each other by at least one separation region in a second direction perpendicular to the first direction; At least one contact area, including a through wiring structure in the connection area electrically connecting the electrode structure to the peripheral logic structure; and The selected gate electrode includes the lowest electrode among the plurality of electrodes in the electrode structure of the cell array region and the connection region. Wherein, the at least one separation region includes a first end at the level of the ground-selective gate electrode, and In this embodiment, at least one ground selection gate cutting region overlaps with the first end of the at least one separation region, and the ground selection gate electrodes are electrically isolated from each other.

17. The three-dimensional semiconductor memory device according to claim 16, wherein, The unit array region has a first length in the second direction, and the connection region has a second length in the second direction, the second length being greater than the first length.

18. The three-dimensional semiconductor memory device according to claim 16, in, The cell array region includes multiple storage blocks in the second direction. The plurality of storage blocks are divided into a first storage block group and a second storage block group. The connection region includes a first connection region and a second connection region, and The first storage block group and the second storage block group are electrically connected to the first connection area and the second connection area along the first direction on the first side and the second side of the cell array area, respectively.

19. The three-dimensional semiconductor memory device according to claim 16, in, The connection region includes the stepped regions of the plurality of electrodes, and Wherein, the at least one selected gate cutting region is located in the cell array region or in the connection region.

20. The three-dimensional semiconductor memory device according to claim 16, wherein, The at least one selected grid cutting region overlaps with the second end of the at least one separated region or with a portion of the through wiring structure.

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