Semiconductor device and method of manufacturing the same

Abstract

A method of fabricating a semiconductor device includes providing a substrate defining a logic region and a memory region; depositing a bottom electrode layer on the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region. Embodiments of the invention also relate to semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Semiconductors are used in integrated circuits for electronic applications including radios, televisions, cell phones, and personal computing devices. One type of well-known semiconductor device is a semiconductor memory device such as dynamic random access memory (DRAM) or flash memory, both of which use electrical charge to store information.

[0003] Recent developments in semiconductor memory devices involve magnetoresistive random access memory (MRAM) using spintronic devices. MRAM combines semiconductor technology with magnetic materials and devices. Rather than the electron's charge, the electron's spin polarization is used to indicate a "1" or "0" state. One such spintronic device is a magnetic tunnel junction (MTJ) device that uses spin torque transfer (STT). Summary of the Invention

[0004] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate comprising a logic area and a memory area; depositing a bottom electrode layer on the logic area and the memory area; depositing a magnetic tunnel junction (MTJ) layer above the bottom electrode layer; depositing a first conductive layer above the magnetic tunnel junction layer; depositing a sacrificial layer above the first conductive layer; etching the sacrificial layer in the memory area to expose the first conductive layer in the memory area while keeping the first conductive layer in the logic area covered; depositing a second conductive layer in the memory area and the logic area; patterning the second conductive layer to expose the magnetic tunnel junction layer in the memory area; and etching the patterned second conductive layer and the magnetic tunnel junction layer to form a top electrode and a magnetic tunnel junction, respectively, in the memory area.

[0005] Another embodiment of the invention provides a method of fabricating a semiconductor device, comprising: providing a substrate, the substrate including a logic region and a memory region; depositing a bottom electrode layer and a magnetic tunnel junction (MTJ) layer over the substrate; depositing a first conductive layer over the magnetic tunnel junction layer; depositing an etch buffer layer over the first conductive layer; etching the etch buffer layer in the memory region to expose the first conductive layer in the memory region while leaving the first conductive layer in the logic region covered; depositing a second conductive layer over the first conductive layer and the etch buffer layer in the memory region and the logic region, respectively; depositing a mask layer over the second conductive layer; patterning the mask layer to form a pattern of a top electrode in the memory region; patterning the first conductive layer and the second conductive layer by transferring the pattern to the first conductive layer and the second conductive layer; and etching the mask layer, the patterned first conductive layer and the patterned second conductive layer, the magnetic tunnel junction layer, and the bottom electrode layer using an etching operation to form the top electrode, magnetic tunnel junction, and bottom electrode in the memory region.

[0006] Yet another embodiment of the invention provides a semiconductor device, comprising: a substrate, the semiconductor device defining a memory region and a logic region; and a memory device arranged in the memory region over the substrate, the memory device including: a bottom electrode via arranged over the substrate; a bottom electrode arranged over the bottom electrode via; a magnetic tunnel junction (MTJ) arranged over the bottom electrode; and a top electrode arranged over the magnetic tunnel junction, the top electrode including an upper portion and a lower portion separated from the upper portion. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the invention can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various components have not been drawn to scale. In fact, the dimensions of the various components can be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the invention.

[0009] Figure 1B is a close-up perspective view of an MRAM structure of a semiconductor structure in Figure 1A

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 ​、 Figure 9 、 Figure 10A 、 Figure 10B 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 and Figure 25 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments of the present invention.

[0011] Figure 26 、 Figure 27 、 Figure 28 、 Figure 29 、 Figure 30 and Figure 31 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments of the present invention.

[0012] Figure 32 、 Figure 33 、 Figure 34 、 Figure 35 and Figure 36 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments of the present invention. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or during operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] Although the numerical ranges and parameters setting forth the broad scope of the present invention are approximate, the numerical values ​​set forth in the specific examples are reported as accurately as possible. However, any numerical value inherently contains certain errors, which are necessarily due to the deviations typically found in the corresponding test measurements. Similarly, as used herein, the terms "about," "substantially," or "substantially" generally refer to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, when considered by one of ordinary skill in the art, the terms "about," "substantially," or "substantially" refer to within an acceptable standard error of the mean. Except in the operating / working examples, or unless otherwise expressly stated, all numerical ranges, quantities, values, and percentages (such as the amount of material disclosed herein, duration, temperature, operating conditions, quantitative ratios, etc.) should be understood to be modified by the terms "about," "substantially," or "substantially" in all cases. Therefore, unless otherwise indicated, the numerical parameters set forth in the present invention and the appended claims are approximate values ​​that can be varied as needed. At a minimum, each numerical parameter should be interpreted based on the number of reported significant figures and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to the other endpoint or between two endpoints.Unless otherwise stated, all ranges disclosed herein include the endpoints.

[0016] An MTJ device typically includes a free layer, a tunnel layer, and a pinned layer. The magnetization direction of the free layer can be reversed by applying a current through the tunnel layer, which causes the injected polarized electrons in the free layer to exert a so-called spin torque on the magnetization of the free layer. For reference, the pinned layer has a fixed magnetization direction. When current flows from the free layer to the pinned layer, electrons flow in the opposite direction, from the pinned layer to the free layer. After passing through the pinned layer, the electrons are polarized to the same magnetization direction as the pinned layer; flow through the tunnel layer; and then enter and accumulate in the free layer. Ultimately, the magnetization of the free layer becomes parallel to that of the pinned layer, and the MTJ device will be in a low-resistance state. Electron injection caused by current is called primary injection.

[0017] When a current is applied from the pinned layer to the free layer, electrons flow in the direction from the free layer to the pinned layer. Electrons with the same polarization as the magnetization direction of the pinned layer can flow through the tunnel layer and enter the pinned layer. On the contrary, electrons with a polarization different from the magnetization of the pinned layer will be reflected (blocked) by the pinned layer and will accumulate in the free layer. Eventually, the magnetization of the free layer becomes antiparallel to the magnetization of the pinned layer, and the MTJ device will be in a high resistance state. The corresponding electron injection caused by the current is called secondary injection.

[0018] Embedded MRAM cells in CMOS structures have been continuously developed. A semiconductor circuit with an embedded MRAM cell defines a memory region and a logic region separated from the memory region. For example, the memory region may be located in the center of the semiconductor circuit, while the logic region may be located at the periphery of the semiconductor circuit. Note that the foregoing description is not intended to be limiting. Other arrangements of the memory region and the logic region are within the contemplated scope of the present invention.

[0019] In the memory region, a transistor structure may be provided below the MRAM structure. In some embodiments, the MRAM cell is embedded in a metallization layer or interconnect layer that is prepared in a back-end-of-line (BEOL) operation of a CMOS manufacturing technology. For example, in some embodiments, the transistor structures in the memory region and the logic region are provided in a common semiconductor substrate that is prepared in a front-end-of-line (FOL) operation of a CMOS manufacturing technology and are substantially identical to each other in the two regions. The MRAM cell may be embedded in any position in the metallization layer, for example, between adjacent metal wire layers that are horizontally distributed parallel to the surface of the semiconductor substrate. For example, the embedded MRAM cell may be located between the fourth metal wire layer and the fifth metal wire layer in the memory region. Horizontally offset to the logic region, the metal wires in the fourth metal wire layer are connected to the metal wires in the fifth metal wire layer via metal vias in a fourth metal via layer located between the fourth metal wire layer and the fifth metal wire layer. In other words, taking into account the memory region and the logic region, the embedded MRAM cell occupies at least a portion of the thickness of the fifth metal wire layer. Throughout the present invention, the term "metal line layer" refers to a collection of metal lines in the same Nth metal line layer, where N is an integer greater than or equal to 1. Similarly, throughout the present invention, the term "metal via layer" refers to a collection of metal vias in the same Nth metal via layer, where N is an integer greater than or equal to 1. Typically, the MRAM cell is located between the Nth metal line layer and the (N+1)th metal line layer. It will be understood by those skilled in the art that the number of metal line layers and the arrangement of the MRAM in the metallization layer described herein are not limiting.

[0020] The embedded MRAM includes a magnetic tunnel junction (MTJ) composed of a ferromagnetic material. A bottom electrode and a top electrode are electrically coupled to the MTJ for signal / biasing applications. In accordance with the example provided previously, the bottom electrode is further connected to the Nth metal line layer, while the top electrode is further connected to the (N+l)th metal line layer.

[0021] Referring Figure 1A , Figure 1A is a cross-section of a semiconductor structure 10 in accordance with some embodiments of the present invention. The semiconductor structure 10 can be a semiconductor circuit including a memory region 100A and a logic region 100B. Each of the memory region 100A and the logic region 100B has a transistor structure 101 located in a semiconductor substrate 100 and a metallization structure 102 arranged above the semiconductor substrate 100.

[0022] In some embodiments, the semiconductor substrate 100 can be, but is not limited to, for example, a silicon substrate. In embodiments, the semiconductor substrate 100 is provided or formed to include a semiconductor material such as a silicon substrate, but it can include other semiconductor materials such as silicon germanium, silicon carbide, gallium arsenide, etc. In the present embodiment, the semiconductor substrate 100 is a p-type semiconductor substrate (P-substrate) or an n-type semiconductor substrate (N-substrate) composed of silicon. Optionally, the semiconductor substrate 100 includes another elemental semiconductor such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In yet another optional embodiment, the semiconductor substrate 100 is a semiconductor-on-insulator (SOI). In other optional embodiments, the semiconductor substrate 100 can include a doped epitaxial layer, a graded semiconductor layer, and / or a semiconductor layer on another semiconductor layer of a different type such as a silicon layer on a silicon germanium layer. The semiconductor substrate 100 can or can not include a doped region such as a P-well, an N-well, or a combination thereof.

[0023] In some embodiments, a shallow trench isolation (STI) 111 is provided in the semiconductor substrate 100. The STI 111 is provided to electrically isolate the transistor structure from adjacent semiconductor devices such as other transistor structures. The STI 111 is formed of a suitable dielectric material including an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO2), a nitrogen-containing oxide (e.g., nitrogen-containing SiO2), a nitrogen-doped oxide (e.g., N2-implanted SiO2), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. x O y N z) etc. STI 111 is also formed of any suitable "high dielectric constant" or "high K" material, where K is greater than or equal to about 8, such as titanium oxide (Ti x O y , such as TiO2), tantalum oxide (Ta x O y , for example, Ta2O5), barium strontium titanate (BST, BaTiO3 / SrTiO3), etc. Alternatively, the STI 111 may also be formed of any suitable "low dielectric constant" or "low-K" dielectric material, where K is less than or equal to about 3.8.

[0024] In some embodiments, the transistor structure 101 includes a gate region 107, a source region 103, and a drain region 105. The source region 103 and the drain region 105 are at least partially disposed in the semiconductor substrate 100. In some embodiments, the gate region 107 of the semiconductor structure 10 includes a polysilicon gate or a metal gate. The gate region 107 is disposed above the top surface of the semiconductor substrate 100 and between the source region 103 and the drain region 105. The semiconductor substrate 100 defines a memory region 100A and a logic region 100B, and the memory region 100A and the logic region 100B include the transistor structure 101. In some embodiments, the transistor structure 101 has a similar configuration in the memory region 100A and the logic region 100B. Note that for illustrative purposes, Figure 1A Only a planar transistor structure 101 is shown in FIG. However, the present invention is not limited thereto. Any non-planar transistor structure, such as a FinFFT transistor structure, is within the intended scope of the present invention.

[0025] The semiconductor structure 10 may further include a contact plug 108 disposed in an interlayer dielectric (ILD) 109 and may be electrically coupled to the gate region 107 of the transistor structure 101. In some embodiments, the ILD 109 is formed over the semiconductor substrate 100. The ILD 109 may be formed using various techniques, such as chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), sputtering and physical vapor deposition (PVD), thermal growth, and the like. The ILD 109 over the semiconductor substrate 100 may be formed of a variety of dielectric materials and may be, for example, an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO2), a nitrogen-containing oxide (e.g., nitrogen-containing SiO2), a nitrogen-doped oxide (e.g., N2-implanted SiO2), or a silicon oxynitride (SiO2). x O y N z )wait.

[0026] The metallization structure 102 is disposed above the transistor structure 101. Referring to the logic region 100B, the metallization structure 102 includes a plurality of metal line layers, for example, an Nth metal line layer 121L and an (N+1)th metal line layer 123L, and an Nth metal via layer 122L and an (N+1)th metal via layer 162L. The metal lines 121 and 123 in the respective metal line layers 121L and 123L are interconnected through metal vias 122 in the Nth metal via layer 122L. The metal line 123 in the metal line layer 123L is electrically connected to the upper component through metal vias 162 in the (N+1)th metal via layer 162L. The metal lines 121 and 123 and the metal vias 122 and 162 are conductive lines and vias, respectively, and are formed of a conductive material such as copper, tungsten, aluminum, gold, silver, or alloys thereof. Referring to memory region 100A, metal line 123 has a reduced height compared to metal line 123 of logic region 100B. Exemplary MRAM cell structure 100_1A is arranged between Nth metal line 121 and (N+1)th metal line 123 of memory region 100A. Because Nth metal line layer 121L may not be the first metal line layer located above transistor structure 101, portions of metallization structure 102 are omitted and represented by dots. In some embodiments, N is any integer from 3 to 10.

[0027] In some embodiments, the metal lines or metal vias are laterally surrounded by dielectric layers 115, 125, 186, or 145, respectively. Each of dielectric layers 115, 125, 186, or 145 may be an intermetallic dielectric (IMD) layer and formed of an oxide such as undoped silicate glass (USG), fluorinated silicate glass (FSG), a low-k dielectric material, or the like. The low-k dielectric material may have an k value lower than 3.8, but the dielectric material of IMD layers 115, 125, 186, or 145 may also be close to 3.8. In some embodiments, the k value of the low-k dielectric material is less than approximately 3.0 and may be less than approximately 2.5.

[0028] In some embodiments, the metal lines or metal vias are further formed by a barrier layer or a stack of barrier layers 141, 142, and 143, respectively (see Figure 3) is laterally surrounded. In some embodiments, barrier layers 141 to 143 include dielectric materials and serve as etch stop layers for etching trenches or grooves in corresponding metal line layers or metal via layers, wherein conductive materials can be deposited in these trenches or grooves to form metal lines and metal vias. In some embodiments, two or more of barrier layers 141 to 143 are selected to have different materials, different materials have different etching selectivities, and are arranged in a stack to improve etching performance. For example, in some embodiments, barrier layer 141 is formed of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. In some embodiments, barrier layer 142 is aluminum oxide. In some embodiments, barrier layer 143 is formed of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0029] exist Figure 1A In the MRAM structure 100_1A, at least a bottom electrode via (BEVA) 132, a bottom electrode 131, an MTJ 135, and a top electrode 158 are included. In some embodiments, the BEVA 132 is formed above and electrically coupled to the Nth metal line 121. In some embodiments, the BEVA 132 is laterally surrounded by the IMD layer 125 and a dielectric stack formed by barrier layers 141 and 142. The BEVA 132 can be formed in a trench having a trapezoidal recess. In some embodiments, the BEVA 132 can include a conductive material such as TiN, TaN, Ta, or other suitable materials.

[0030] In some embodiments, a liner layer 161 is formed on the sidewalls of the trench of BEVA 132. In some embodiments, liner layer 161 is a seed layer for a material electroplated thereon. For example, if the material constituting BEVA includes copper, liner layer 161 may be a seed layer for electroplating copper. In some other embodiments, liner layer 161 may include TaN or Ta.

[0031] In some embodiments, the BEVA 132 of the MRAM structure 100_1A is electrically coupled to a doped region of the transistor structure 101 , where the doped region is the drain region 105 or the source region 103 . In other embodiments, the BEVA 132 of the MRAM structure 100_1A is electrically coupled to the gate region 107 of the transistor structure 101 .

[0032] The bottom electrode 131 is disposed above the BEVA 132. In some embodiments, the bottom electrode 131 may include a conductive material such as TiN, TaN, Ti, Ta, or Ru. The MTJ 135 is disposed above the bottom electrode 131. In some embodiments, the MTJ 135 includes a layer stack (not separately shown) such as a free layer, a tunnel layer, and a pinned layer disposed above each other. A top electrode 158 is disposed above the MTJ 135. In some embodiments, the top electrode 158 may include a conductive material such as TiN, TaN, Ti, Ta, or Ru. In some embodiments, the top electrode 158 and the bottom electrode 131 are made of the same material. In some embodiments, the material of the top electrode 158 is different from the material of the BEVA 132. In some embodiments, the top electrode 158 includes a multilayer structure.

[0033] like Figure 1A As shown, sidewalls of the bottom electrode 131, MTJ 135, and top electrode 158 are laterally surrounded by a protective layer or spacer 127. The protective layer 127 has a top surface level that is the same as a top surface level of the top electrode 158. In some embodiments, the protective layer 127 includes silicon nitride (SiN).

[0034] In some embodiments, dielectric layer 129 is disposed over and laterally surrounds protective layer 127. Dielectric layer 129 may have a top surface flush with a top surface of top electrode 158 and a top of protective layer 127. Dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0035] Figure 1B The MRAM structure 100_1A of the semiconductor structure 10 according to some embodiments of the present invention is Figure 1A FIG1 is an enlarged perspective view of portion 12 in FIG1 . Top electrode 158 includes lower portion 133 and upper portion 154, with upper portion 154 located above and separated from lower portion 133. Lower portion 133 and upper portion 154 can comprise the same conductive material. In some embodiments, each of lower portion 133 and upper portion 154 has a height between about 50 angstroms and about 300 angstroms, or between about 10 angstroms and about 250 angstroms. In some embodiments, top electrode 158 includes an interface region 164 located between lower portion 133 and upper portion 154. In some embodiments, interface region 164 is an oxide form of lower portion 133 and can include TiO2 or other metal oxides. In some embodiments, the thickness of interface region 164 is between about 1 angstrom and about 5 angstroms.

[0036] Figures 2 to 33 are semiconductor structures (e.g., Figure 1A It should be understood that in Figures 2 to 33 Additional stages may be provided before, during, and after the stages shown in the order shown, and in other embodiments, some of the stages described below may be replaced or eliminated. The order of the stages may be interchanged.

[0037] exist Figure 2 In some embodiments, a semiconductor structure having a predetermined memory region 100A and a logic region 100B is formed or provided. Figure 2 (not shown) in advance to form a transistor structure. Figure 1A The integrated circuit device of the transistor structure 101 shown may be further processed using CMOS or MOS technology to form various components known in the art.

[0038] Figure 2 Also shown Figure 1A , at least a portion of the metallization structure 102 shown in is formed. An Nth metal line 121 is patterned in the IMD layer 115 above the transistor structure. The metal line 121 is a conductive line and includes a conductive material such as copper, tungsten, aluminum, gold, silver, alloys thereof, or the like. In some embodiments, the Nth metal line 121 can be formed by an electroplating operation in which a seed layer is deposited over the patterned IMD layer 115. In other embodiments, the Nth metal line 121 can be formed by various techniques, such as electroless plating, high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or the like. A planarization operation is performed to expose the top surface of the Nth metal line 121 and the top surface of the IMD layer 115.

[0039] exist Figure 3 In the embodiment of the present invention, a layer stack 140 formed of dielectric layers 141, 142, and 143 and IMD layer 125 is blanket deposited over the top surface of the N-th metal line 121 and the top surface of the IMD layer 125 of the N-th metal line layer in the memory region 100A and the logic region 100B. In some embodiments, the barrier layers 141 to 143 are formed of SiC, aluminum oxide, and SiC, respectively, and the IMD layer 125 is formed of TEOS (tetraethyl orthosilicate). The layer stack 140 can be formed by various techniques, such as chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition (PVD), thermal growth, etc.

[0040] exist Figure 4In the embodiment, a photoresist layer (not shown) is patterned over the layer stack 140 to expose one or more BEVA holes 132H of the MRAM structure 100_1A. Figure 4 As shown, two BEVA holes 132H are formed in the layer stack 140 by a suitable dry etching operation. In some embodiments, the dry etching in this operation includes reactive ion etching (RIE) using a fluorine-containing gas. Referring to the logic region 100B, the layer stack 140 is protected by a photoresist layer (not shown) so that the top surface of the N-th metal line 121 is not exposed compared to the layer stack 140 in the memory region 100A.

[0041] exist Figure 5 In the embodiment, a liner layer 161 is blanket formed over the BEVA holes 132H in the memory region 100A and over the layer stack 140 in the logic region 100B. Figure 6 As shown, BEVA 132 is deposited to be disposed over liner layer 161 and layer stack 140. BEVA 132 can be composed of a conductive material such as a metal. In some embodiments, BEVA 132 can be electroplated copper. Liner layer 161 and BEVA 132 can be formed using various techniques, such as high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. In some embodiments, BEVA 132 is overfilled during the electroplating operation to a thickness T1 above the horizontal surface of liner layer 161. This overfill may be desirable to effectively minimize any indentations that may appear above BEVA hole 132H after the electroplating operation.

[0042] exist Figure 7The liner layer 161 and the deposited BEVA 132 are then etched back to be flush with the top surface of the IMD layer 125. A multi-step chemical mechanical polishing (CMP) process can be performed to form a planar top surface of the BEVA 132 and liner layer 161. In some embodiments, a multi-step CMP process using slurries with different selectivities is used to achieve a planar top surface. Initially, a first selective removal process involves utilizing a first slurry that has a higher selectivity for copper than for the liner layer 161. In some embodiments, the first slurry comprises H2O2, benzotriazole (BTA), a carboxylic acid, and an abrasive. The first slurry consumes copper faster than the liner layer 161, resulting in a recess in the copper fill of the BEVA 132. Subsequently, a second selective removal process involves utilizing a second slurry that has a higher selectivity for the liner layer 161 than for copper. In some embodiments, the second slurry comprises H2O2, benzotriazole (BTA), a pH adjuster, a carboxylic acid, and an abrasive. The second slurry consumes liner layer 161 faster than copper, allowing liner layer 161 to be removed without consuming a significant amount of exposed copper. The third selective removal includes utilizing a third slurry that has a higher selectivity for liner layer 161 than for copper. In some embodiments, the third slurry includes H2O2, a suppressant, a pH adjuster, a carboxylic acid, and an abrasive. The third slurry, for example, consumes one of the dielectric stack elements faster than copper, allowing barrier layer 141 to be removed without consuming a significant amount of exposed copper.

[0043] exist Figure 8 In the embodiment of the present invention, a bottom electrode layer 131L is deposited on the planarized BEVA 132 and the liner layer 161. The bottom electrode layer 131L may include TiN, TaN, Ta, or Ru. In some embodiments, the thickness of the bottom electrode layer 131L ranges from about 50 angstroms to about 500 angstroms. The deposited bottom electrode layer 131L may be formed by various techniques, such as high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, a planarization operation such as CMP is performed to make the top surface of the bottom electrode layer 131L flush.

[0044] Then, a plurality of material stacks ( Figure 8The MTJ layer 135L is deposited in the form of a substrate (not shown). In some embodiments, the thickness of the MTJ layer 135L ranges from about 50 angstroms to about 500 angstroms, or from about 100 angstroms to about 350 angstroms. In some embodiments, the roughness of the top surface of the MTJ layer 135L is between about 2 angstroms and about 10 angstroms. In some embodiments, the MTJ layer 135L may include a ferromagnetic layer, a spacer, and a capping layer. The ferromagnetic layer may serve as a free layer, the magnetic polarity or magnetic orientation of which may change during a write operation of its associated MRAM cell. The ferromagnetic layer and the spacer may serve as a fixed layer or pinned layer, the magnetic orientation of which may not change during operation of its associated MRAM cell. The capping layer is formed on the ferromagnetic layer and may reduce the write current of its associated MRAM cell. Each ferromagnetic layer may include a ferromagnetic material, which may be a metal or a metal alloy, such as Fe, Co, Ni, CoFeB, FeB, CoFe, FePt, FePd, CoPt, CoPd, CoNi, TbFeCo, CrNi, etc. The spacer may include a non-ferromagnetic metal, such as Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, etc. Another material for the spacer may also include an insulator, such as Al2O3, MgO, TaO, RuO, etc. The capping layer may include a non-ferromagnetic material, which may be a metal or an insulator, such as Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, Ir, Re, Os, Al2O3, MgO, TaO, RuO, etc. It is contemplated that according to other embodiments, the MTJ layer 135L may include an antiferromagnetic layer.

[0045] The MTJ layer 135L can be formed by various techniques, such as high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc.

[0046] A first top electrode layer 133L is deposited over the MTJ layer 135L. In some embodiments, the first top electrode layer 133L is a conductive layer and includes a conductive material such as TiN, TaN, Ti, Ta, or Ru. In some embodiments, the thickness of the first top electrode layer 133L is about 50 angstroms to about 1000 angstroms. The first top electrode layer 133L can be formed by various techniques, such as high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), DC or RF PVD, pulsed DC sputtering, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0047] In some embodiments, the first top electrode layer 133L is deposited at a chamber process pressure between approximately 10 mTorr and approximately 400 mTorr and a chamber backside pressure between 0.1 mTorr and 10 mTorr. In some embodiments, the first top electrode layer 133L is deposited at a temperature between approximately 200°C and approximately 450°C. In some embodiments, deposition of the first top electrode layer 133L is performed with a DC power between approximately 1 kW and approximately 30 kW and an AC power between approximately 0 W and approximately 1000 W. The applied voltage can be between approximately 500 V and approximately 900 V, and the applied current can be between approximately 5 A and approximately 35 A. The AC frequency can be equal to or greater than 13.56 MHz, such as 2 GHz. A magnet disposed in the process chamber can be positioned at a distance between 38 mm and approximately 46 mm from the deposition target and configured to operate at a rotation rate between approximately 50 rpm and approximately 70 rpm. A gas mixture of N2 and argon is introduced during deposition of the first top electrode layer 133L at a gas flow rate between approximately 0 sccm and approximately 1500 sccm.

[0048] refer to Figure 9, a sacrificial layer 152L is formed over the first top electrode layer 133L. The sacrificial layer 152L can be patterned to serve as a mask layer or etch buffer structure for subsequent etching operations. In some embodiments, the sacrificial layer 152L is formed of a dielectric material such as an oxide, nitride, oxynitride, or other suitable dielectric material. In some embodiments, the sacrificial layer 152L includes TEOS or a nitrogen-free anti-reflective layer (NR-ARL). In some embodiments, the sacrificial layer 152L is doped with silicon or carbon to enhance film stress. In some other embodiments, the sacrificial layer 152L includes a conductive material different from the first top electrode layer 133L, such as TiN, TaN, W, or other suitable conductive materials. In some embodiments, the thickness of the sacrificial layer 152L is from about 50 angstroms to about 1000 angstroms. In some embodiments, the thickness of the sacrificial layer 152L is from about 100 angstroms to about 800 angstroms or between about 200 angstroms and about 500 angstroms.

[0049] The sacrificial layer 152L can be formed by various techniques, such as high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0050] exist Figure 10A In the embodiment of the present invention, the sacrificial layer 152L is patterned into a patterned sacrificial layer 152P, so that the portion of the first top electrode layer 133L located in the memory region 100A is exposed. The portion of the first top electrode layer 133L in the logic region 100B remains covered by the patterned sacrificial layer 152P. In some embodiments, the sacrificial layer 152L is patterned by a photolithography operation, followed by an etching operation to remove undesired portions of the sacrificial layer 152L.

[0051] In some embodiments, the etching operation is a wet etch, a dry etch, or a combination thereof, such as reactive ion etching (RIE). In embodiments where the etching operation is a dry etch, a fluorine-based etching gas may be utilized to assist in the selective etching of the sacrificial layer 152L. In some embodiments, a portion of the sacrificial layer 152L in the logic region 100B remains substantially intact or is consumed at a relatively slow rate, such that the underlying first top electrode layer 133L remains covered by the patterned sacrificial layer 152P. In some embodiments, the patterned sacrificial layer 152P in the logic region 100B serves as an etch buffer structure that can assist in protecting underlying metal lines or metal vias in the metallization layers in the logic region 100B from damage during subsequent etching operations. In some embodiments, the thickness of the first top electrode layer 133L in the memory region 100A is etched by the patterning operation, such that the first top electrode layer 133L is thinned but not completely removed.

[0052] In some embodiments, the vacuum is not broken. Figure 10A Therefore, the surface of the first top electrode layer 133L can be kept away from oxygen in the ambient air, and the surface of the first top electrode layer 133L can be prevented from being oxidized. Figure 10A The etching operations shown are performed in different chambers. Figure 10A The result is as follows: Figure 10B As shown, the first top electrode layer 133L is likely to be exposed to oxygen, and the interface layer 164L grows on the upper surface of the first top electrode layer 133L. The interface layer 164L may be an oxide of the conductive material of the first top electrode layer 133L. Figure 10A The sequence of steps following this is shown in reference Figures 11 to 25 In the embodiment, the first top electrode layer 133L is formed without any interface layer thereon. However, it will be understood by those skilled in the art that the reference Figures 11 to 25 The interface layer 164L is grown on the surface of the first top electrode layer 133L. Figure 1B As shown, the final top electrode 158 includes an interface region 164 between the lower portion 133 and the upper portion 154 of the top electrode 158 .

[0053] refer to Figure 11A second top electrode layer 154L is deposited over the first top electrode layer 133L and the patterned sacrificial layer 152P. In some embodiments, the second top electrode layer 154L is a conductive layer and includes a conductive material such as TiN, TaN, Ti, Ta, or Ru. The second top electrode layer 154L can be made of the same material as the first top electrode layer 133L. In some embodiments, the second top electrode layer 154L has a thickness of approximately 50 angstroms to approximately 1500 angstroms. In some embodiments, the second top electrode layer 154L has a thickness of approximately 100 angstroms to approximately 1200 angstroms.

[0054] In some embodiments, a mask layer 156L is formed over the second top electrode 154L. The mask layer 156L is used to pattern the underlying top electrode layers 154L and 133L, the MTJ layer 135L, and the bottom electrode layer 131L, thereby forming Figure 1A One or more MRAM structures 100_1A are shown. Mask layer 156L may include TEOS or silicon oxide. Optionally, mask layer 156L may have a multilayer structure, which may include, for example, an oxide layer, an advanced patterning film (APF) layer, and an oxide layer. In some embodiments, the thickness of mask layer 156L ranges from approximately 50 angstroms to approximately 500 angstroms.

[0055] The second top electrode layer 154L, the oxide layer, the APF layer and each of the oxide layers can be formed by various techniques, for example, high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc.

[0056] exist Figure 12 , the mask layer 156L is patterned to form a patterned mask layer 156 that corresponds to the pattern of the top electrode 158 of the MRAM structure 100_1A from a top view perspective in the memory region 100A. Figure 12 The patterning operation in removes portions of the mask layer 156L in the logic region 100B. In some embodiments, the patterning operation may involve photolithography and etching operations. The etching operation may be wet etching, dry etching, or a combination thereof, such as RIE.

[0057] refer to Figure 13The second top electrode layer 154L and the first top electrode layer 133L are patterned using the patterned mask layer 156 as an etch mask. The pattern of the patterned mask layer 156 is transferred to the underlying second top electrode layer 154L and first top electrode layer 133L. Accordingly, one or more second top electrode portions 154U and the lower portion 133 of the top electrode 158 are formed for the corresponding MRAM structure 100_1A or 100_2A. Through the patterning operation, the material of the second top electrode layer 154L and the first top electrode layer 133L in the logic region 100B is removed. During the patterning operation, the MTJ layer 135L and the patterned sacrificial layer 152P are exposed in the memory region 100A and the logic region 100B, respectively.

[0058] In some embodiments, the patterning operation can be performed by a selective etching operation 172 such as wet etching, dry etching, or a combination thereof (such as RIE). In embodiments where dry etching is performed, a fluorine-based etchant is used to facilitate the selective etching operation 172, such that etching proceeds through the second top electrode layer 154L and the first top electrode layer 133L and stops at the patterned sacrificial layer 152P or the MTJ layer 135L. In some embodiments, the MTJ layer 135L remains substantially intact during the selective etching operation 172. In some embodiments, a relatively thin portion of the patterned sacrificial layer 152P is consumed by the selective etching operation 172.

[0059] Figure 14 An etching operation 174 is shown that completely removes the patterned mask layer 156 and partially removes the second top electrode portion 154U to leave the upper portion 154 of the top electrode 158. Throughout the present disclosure, the lower portion 133 and the upper portion 154 refer to the lower portion and the upper portion of the top electrode 158 of the corresponding MRAM structure 100_1A or 100_2A, respectively. In some embodiments, Figure 14 The etching operation 174 performed in FIG. 1 is a non-selective etching operation, such as ion bombardment etching (IBE), which removes the entire patterned mask layer 156 and an upper portion of the second top electrode layer 154L.

[0060] During the etching operation 174, while the patterned mask layer 156 and the second top electrode layer 154L are consumed, the remaining material of the patterned mask layer 156 and the second top electrode portion 154U serves as an etching mask for the etching operation 174 in etching the MTJ layer 135L and the bottom electrode layer 131L, thereby forming the patterned MTJ 135 and the patterned bottom electrode 131 of the corresponding MRAM structure 100_1A or 100_2A. In some embodiments, when viewed in cross section, the sidewalls of the lower portion 133 and the upper portion 154, the MTJ 135, and the bottom electrode 131 have a trapezoidal shape. In some embodiments, when viewed in cross section, the MRAM structures 100_1A and 100_2A have different widths.

[0061] In some embodiments, etching operation 174 stops at the IMD layer 125 at the level of BEVA 132 in memory region 100A. Simultaneously, etching operation 174 consumes the remaining patterned sacrificial layer 152P, first top electrode layer 133L, MTJ layer 135L, and bottom electrode layer 131L in logic region 100B, exposing the IMD layer 125 at the level of BEVA 132. In some embodiments, etching operation 174 proceeds further downward and removes the thickness of IMD layer 125, such that the remaining thickness of IMD layer 125 in logic region 100B is less than the remaining thickness of IMD layer 125 in memory region 100A. A height difference H1 is formed between the surfaces of IMD layer 125 in memory region 100A and logic region 100B. In some embodiments, height H1 is between approximately 50 angstroms and approximately 1000 angstroms. In some embodiments, IMD layer 125 has a first lower surface 125A in memory region 100A, first lower surface 125A being at the same level as a second lower surface 125B in logic region 100B, and a first upper surface 125C in memory region 100A being higher than a second upper surface 125D in logic region 100B by a height difference H1. In some embodiments, etching removes the entire IMD layer 125 and exposes barrier layer 142 or 141. In some embodiments, metal line 121 of the N-th metal line layer in logic region 100B remains covered by at least one or more barrier layers 141 and 142.

[0062] Conventional patterning operations for forming MRAM structures 100_1A and 100_2A using a non-selective etching operation can simultaneously remove material from top electrode layers 133L and 154L, MTJ layer 135L, and bottom electrode layer 131L in logic region 100B. However, because logic region 100B occupies the majority of the die area—for example, approximately 95% of the die area compared to 5% occupied by memory region 100A—the plasma density in logic region 100B can be greater than that in memory region 100A, leading to over-etching in logic region 100B and exposure / damage to N-th metal line 121 in the N-th metal line layer of logic region 100B. The conductive material removed from N-th metal line 121 by the over-etching operation can also become a source of contamination. Thus, the proposed etch buffer structure including the sacrificial layer 152P and the first top electrode layer 133L in the logic region 100B can help increase the etch margin of the etching operation 174 during the patterning of the MRAM structures 100_1A and 100_2A. Therefore, device defects caused by over-etching can be eliminated or reduced in the logic region 100B.

[0063] Figure 15 The deposition of the protective layer 127 over the bottom electrode 131, the MTJ 135, and the top electrode 158 is shown. In some embodiments, the protective layer 127 has a thickness of about 50 angstroms to about 300 angstroms. Note that the sidewalls of the MTJ 135 and the sidewalls of the top electrode 158 are surrounded by the protective layer 127 to prevent oxidation or other contamination. Then, as shown in FIG. Figure 16 As shown, the protection layer 127 is patterned to expose the top surface of the IMD layer 125 .

[0064] exist Figure 17 In the embodiment of the present invention, a dielectric layer 129 is conformally deposited over the protective layer 127 and the IMD layer 125 of the memory region 100A and the logic region 100B. In some embodiments, the dielectric layer 129 is composed of TEOS. In some embodiments, the dielectric layer 129 is composed of a high-density plasma oxide (HDP-oxide). However, this is not a limitation of the present invention. A stop layer 137 is formed over the dielectric layer 129. In some embodiments, the stop layer 137 is a silicon nitride (SiN) stop layer. Another dielectric layer 138 is conformally formed over the stop layer 137. In some embodiments, the dielectric layer 138 has a different material than the dielectric layer 125 and can be a USG layer.

[0065] A planarization operation such as CMP is performed to remove dielectric layer 138. Since logic region 100B occupies most of the die area, the depth of the CMP operation is strongly related to the indication of stop layer 137 in logic region 100B. Figure 18As shown, the CMP operation stops at the level of the stop layer 137 over the logic region 100B, and removes portions of the dielectric layer 138 and the dielectric layer 129 over the memory region 100A.

[0066] The CMP operation described above makes the surface of the dielectric layer 129 relatively smooth and helps ensure exposure of the top electrode 158 of each MRAM structure 100_1A in the memory region 100A in a subsequent thinning operation. In Figure 19 In the memory region 100A, a thinning operation such as an etching process is performed on the smooth dielectric layer 129 so that the top surface of the dielectric layer 129 is substantially planar over the memory region 100A. As shown in Figure 19 As shown, after the thinning operation, the top surface of the top electrode 158 is exposed from the dielectric layer 129.

[0067] In Figure 20 In the memory region 100A, a thinning operation such as an etching process is performed on the smooth dielectric layer 129 so that the top surface of the dielectric layer 129 is substantially planar over the memory region 100A. As shown in Figure 20 The height difference H2 can be observed in Figure 21 As shown, a back-etching operation is performed to obtain a substantially planar top surface for subsequent trench formation in the memory region 100A and the logic region 100B. Note that after the planarization operation, the dielectric layer 188 of the stack 180 remains in the logic region 100B. The dielectric layer 188 is intentionally left to serve as a protective layer for subsequent trench formation. The dielectric layer 188 can prevent acidic solution from damaging the low-k dielectric layer 186 during a photoresist lift-off operation.

[0068] In Figure 22 In the memory region 100A, a thinning operation such as an etching process is performed on the smooth dielectric layer 129 so that the top surface of the dielectric layer 129 is substantially planar over the memory region 100A. As shown in

[0069] In Figure 23 and Figure 24In some embodiments, the conductive metal fills the metal line trenches / metal via trenches (hereinafter referred to as "trenches") by, for example, a single damascene or dual damascene operation. The patterned trenches are filled with a conductive material by an electroplating operation, and excess portions of the conductive material are removed from the surface using a CMP operation, an etching operation, or a combination thereof.

[0070] In some embodiments, the (N+1)th metal line 123 can be formed from tungsten (W) or copper (Cu), and can include AlCu (collectively referred to as Cu). In one embodiment, the (N+1)th metal line 123 is formed using a damascene operation. In some embodiments, a seed layer of Cu is plated in the trenches 123A and 123B. Note that a seed layer of Cu can be plated over the top surface of the top electrode 158. A copper layer is then deposited in the trenches, and then planarized down to the top surface of the IMD layer 186, such as by CMP. The dielectric layer 188 over the trench 123B is removed, and the exposed copper surface and the upper surface of the IMD layer 186 can be coplanar. After the planarization operation, as shown, a cap layer of conductive metal is removed, forming the (N+1)th metal line 123 in both the memory region 100A and the logic region 100B, and the Nth metal via 122 in the logic region 100B. Figure 24

[0071] In some embodiments, the (N+1)th metal line 123 can be formed from tungsten (W) or copper (Cu), and can include AlCu (collectively referred to as Cu). In one embodiment, the (N+1)th metal line 123 is formed using a damascene operation. In some embodiments, a seed layer of Cu is plated in the trenches 123A and 123B. Note that a seed layer of Cu can be plated over the top surface of the top electrode 158. A copper layer is then deposited in the trenches, and then planarized down to the top surface of the IMD layer 186, such as by CMP. The dielectric layer 188 over the trench 123B is removed, and the exposed copper surface and the upper surface of the IMD layer 186 can be coplanar. After the planarization operation, as shown, a cap layer of conductive metal is removed, forming the (N+1)th metal line 123 in both the memory region 100A and the logic region 100B, and the Nth metal via 122 in the logic region 100B. Figure 25 In some embodiments, the (N+1)th metal line 123 can be formed from tungsten (W) or copper (Cu), and can include AlCu (collectively referred to as Cu). In one embodiment, the (N+1)th metal line 123 is formed using a damascene operation. In some embodiments, a seed layer of Cu is plated in the trenches 123A and 123B. Note that a seed layer of Cu can be plated over the top surface of the top electrode 158. A copper layer is then deposited in the trenches, and then planarized down to the top surface of the IMD layer 186, such as by CMP. The dielectric layer 188 over the trench 123B is removed, and the exposed copper surface and the upper surface of the IMD layer 186 can be coplanar. After the planarization operation, as shown, a cap layer of conductive metal is removed, forming the (N+1)th metal line 123 in both the memory region 100A and the logic region 100B, and the Nth metal via 122 in the logic region 100B.

[0072] Figures 26 to 31 is a cross-sectional view of an intermediate stage of fabricating the semiconductor structure 10 according to some embodiments of the present application. In Figure 7 the operation shown in Figures 26 to 31 is performed directly after the operation shown in Figures 8 to 14 is replaced with the operation shown in Figures 15 to 25 is performed. Unless otherwise noted, Figures 26 to 31 the configuration of materials, fabrication methods, and operations in Figures 2 to 9 , Figure 10A , Figure 10B and​ Figures 11 to 25 , and for the sake of brevity, repeated descriptions are omitted.

[0073] refer to Figure 26 A bottom electrode layer 131L is deposited on the planarized BEVA 132 and the liner layer 161. In some embodiments, a planarization operation such as CMP is performed to level the top surface of the bottom electrode layer 131L. The MTJ layer 135L is deposited above the bottom electrode layer 131L. A sacrificial layer 152L is deposited directly above the MTJ layer 135L in both the memory region 100A and the logic region 100B. Figure 26 The patterning operation shown in Figure 8 and Figure 9 , except that the first top electrode layer 133L does not exist, and repeated descriptions are omitted for brevity.

[0074] Figure 27 The sacrificial layer 152L is patterned to expose the MTJ layer 135L in the memory region 100A while keeping the MTJ layer 135L in the logic region 100B covered. In this regard, an etch buffer structure of the patterned sacrificial layer 152P is correspondingly formed over the logic region 100B. Figure 27 The patterning operation shown is similar to Figure 10A For the sake of brevity, repeated descriptions are omitted.

[0075] refer to Figure 28 , then forming a top electrode layer 158L and a mask layer 156L over the MTJ layer 135L and the patterned sacrificial layer 152P. The top electrode layer 158L is a conductive layer and may include a conductive material similar to the first top electrode layer 133L or the second top electrode layer 154L. The thickness of the top electrode layer 158L may be substantially equal to the sum of the thicknesses of the first top electrode layer 133L and the second top electrode layer 154L. In some embodiments, the thickness of the top electrode layer 158L is between approximately 50 angstroms and approximately 2000 angstroms, or between approximately 200 angstroms and approximately 1400 angstroms. Figure 28 The layers shown in FIG are formed to Figure 8 and Figure 9 The same manner as shown is performed, and repeated descriptions are omitted for the sake of brevity.

[0076] Figure 29 A patterning operation of mask layer 156L is shown. Figure 29 The patterning operation shown in Figure 12 The method shown in FIG is performed, and for the sake of brevity, repeated descriptions are omitted. Figure 30As shown, the top electrode portion 158U is formed by etching the top electrode layer 158L using an etching operation 172. During the patterning operation, the MTJ layer 135L in the memory region 100A and the patterned sacrificial layer 152P in the logic region 100B are exposed. Figure 30 The patterning operation 172 shown in FIG is similar to Figure 13 , and repeated descriptions are omitted for brevity.

[0077] refer to Figure 31 An etching operation 174 is performed to etch the MTJ layer 135L and the bottom electrode layer 131L to form discrete units of the top electrode 158 , the MTJ 135 , and the bottom electrode 131 of the corresponding MRAM structure 100_1A. Figure 31 The etching operation 174 shown in FIG is similar to Figure 14 The height difference H2 between the surface of the IMD layer 125 in the memory region 100A and the surface of the IMD layer 125 in the logic region 100B is formed by etching operation 174. In some embodiments, the height difference H2 is different from Figure 14 The height difference H1 shown in the reference Figure 14 and Figure 31 , through, 26 to Figure 31 The top electrode 158 obtained by the operation is formed of a single layer, which is produced by a single deposition operation of the conductive material of the top electrode layer 158L, and no interface layer is formed in the top electrode 158.

[0078] Figures 32 to 36 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments of the present invention. Figures 32 to 35 The operation shown follows Figure 7 The operations shown are then performed and replaced Figures 8 to 14 operation, then proceed Figures 15 to 25 Unless otherwise stated, Figures 32 to 36 The materials, manufacturing methods and operation configurations in Figures 2 to 9 、 Figure 10A 、 Figure 10B and Figures 11 to 25 , and for the sake of brevity, repeated descriptions are omitted.

[0079] refer to Figure 32, a bottom electrode layer 131L is deposited on the planarized BEVA 132 and the pad layer 161. In some embodiments, a planarization operation such as CMP is performed to level the top surface of the bottom electrode layer 131L. The MTJ layer 135L is deposited over the bottom electrode layer 131L. Subsequently, a top electrode layer 158L and a mask layer 156L are formed over the MTJ layer 135L. The thickness of the top electrode layer 158L may be substantially equal to the sum of the thicknesses of the first top electrode layer 133L and the second top electrode layer 154L (see FIG. 1 ). Figure 11 In some embodiments, the thickness of the top electrode layer 158L is between about 50 angstroms and about 2000 angstroms, or between about 200 angstroms and about 1400 angstroms. Figure 32 The layers shown in FIG are formed to resemble Figure 8 , except that the thickness of the top electrode layer 158L is different, and for the sake of brevity, repeated description is omitted.

[0080] Figure 33 The formation of a patterned sacrificial layer 152P over the mask layer 156L in the logic region 100B is shown. The mask layer 156L is exposed through the patterned sacrificial layer 152P. In some embodiments, the material of the patterned sacrificial layer 152P can be the same as or different from the material of the mask layer 156L. The patterned sacrificial layer 152P can be formed by photolithography and etching operations similar to Figure 10A The method shown is formed, and repeated description is omitted for the sake of brevity.

[0081] Figure 34 A patterning operation of the mask layer 156L is shown to form a mask pattern 156 in the memory region 100A. Figure 34 The patterning operation shown in Figure 12 In some embodiments, the method shown in FIG. Figure 34 The patterned sacrificial layer 152P remains during the patterning operation shown in FIG. In this regard, the patterned sacrificial layer 152P and the patterned mask layer 156R in the logic region 100B serve as an etch buffer structure to prevent subsequent over-etching from damaging the underlying Nth metal line 121 .

[0082] Alternatively, another form of the etch buffer structure is obtained by directly patterning the mask layer 156L to form the patterned mask layer 156R without the additional step of depositing the sacrificial layer 152L. In this regard, a single patterned mask layer 156R serves as the etch buffer structure, and the patterned mask layer 156R may be omitted. Figure 33 operation.

[0083] Then, if Figure 35As shown, top electrode portion 158U is formed by etching top electrode layer 158L using etching operation 172. MTJ layer 135L in memory region 100A is exposed during patterning operation 172. Patterned sacrificial layer 152P and patterned mask layer 156R in logic region 100B are removed. An upper portion of top electrode layer 158L in logic region 100B is removed, and a lower portion of top electrode layer 158R adjacent to MTJ layer 135L remains during etching operation 172 due to the presence of an etch buffer structure formed by patterned sacrificial layer 152P and / or patterned mask layer 156R. Figure 35 The patterning operation 172 shown in FIG. Figure 13 , and duplicate descriptions are omitted for brevity.

[0084] refer to Figure 36 An etching operation 174 is performed to etch the MTJ layer 135L and the bottom electrode layer 131L to form discrete units of the top electrode 158 , the MTJ 135 , and the bottom electrode 131 of the corresponding MRAM structure 100_1A. Figure 36 The etching operation 174 shown in FIG is similar to Figure 14 Those shown in , and for the sake of brevity, repeated descriptions are omitted. Figure 36 The etching operation 174 performed in the embodiment also removes the remaining top electrode layer 158R and then removes the underlying MTJ layer 135, the bottom electrode layer 131L, and optionally the thickness of the IMD layer 125 or the barrier layer 142. The etching operation 174 forms a height difference H3 between the surface of the IMD layer 125 in the memory region 100A and the surface of the IMD layer 125 in the logic region 100B. In some embodiments, the height difference H3 is different from the height difference H1 ( Figure 14 ) and H2( Figure 31 ). refer to Figure 14 and Figure 36 ,pass Figures 32 to 36 The top electrode 158 obtained by the operation is formed of a single layer, which is produced by a single deposition operation of the conductive material, and there is no interface layer in the top electrode 158.

[0085] According to an embodiment, a method for manufacturing a semiconductor device includes: providing a substrate, wherein the substrate defines a logic region and a memory region; depositing a bottom electrode layer on the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer above the bottom electrode layer; depositing a first conductive layer above the MTJ layer; depositing a sacrificial layer above the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while leaving the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and MTJ layer in the memory region to form a top electrode and an MTJ, respectively. In one or more of the foregoing and following embodiments, before depositing the bottom electrode layer, a metal line layer having metal lines is formed, a first dielectric layer is deposited in the memory region and the logic region above the metal lines, and a bottom electrode via is formed within the first dielectric layer in the memory region. In one or more of the foregoing and following embodiments, etching the patterned second conductive layer and MTJ layer in the memory region to form the top electrode and the MTJ, respectively, includes reducing the thickness of the first dielectric layer in the logic region. In one or more of the foregoing and following embodiments, after etching the thickness of the first dielectric layer is completed, the metal line is covered by the first dielectric region in the logic region. In one or more of the foregoing and following embodiments, patterning the second conductive layer to expose the MTJ layer in the memory region includes removing the second conductive layer in the logic region. In one or more of the foregoing and following embodiments, a mask layer is also deposited above the second conductive layer. Patterning the second conductive layer to expose the MTJ layer in the memory region includes patterning the mask layer, and patterning the second conductive layer using the patterned mask layer as an etching mask. In one or more of the foregoing and following embodiments, the mask layer includes the same material as the material in the sacrificial layer. In one or more of the foregoing and following embodiments, etching the patterned second conductive layer and the MTJ layer in the memory region to form a top electrode and an MTJ, respectively, includes performing ion bombardment etching to remove the entire mask layer and a portion of the second conductive layer in the memory region. In one or more of the foregoing and following embodiments, the ion bombardment etching uses at least the second conductive layer as an etching mask to etch the MTJ layer to form an MTJ in the memory region. In one or more of the foregoing and following embodiments, the ion bombardment etching further etches the bottom electrode layer using the second conductive layer as an etching mask to form a bottom electrode. In one or more of the foregoing and following embodiments, the ion bombardment etching removes the mask layer and the second conductive layer in the logic region. In one or more of the foregoing and following embodiments, spacers are further formed that laterally surround the top electrode and the sidewalls of the MTJ.

[0086] According to an embodiment, a method for manufacturing a semiconductor structure includes: providing a substrate, wherein the substrate defines a logic region and a memory region; depositing a bottom electrode layer and a magnetic tunnel junction (MTJ) layer over the substrate; depositing a first conductive layer over the MTJ layer; depositing an etch buffer layer over the first conductive layer; etching the etch buffer layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer covered in the logic region; depositing a second conductive layer over the first conductive layer and the etch buffer layer in the memory region and the logic region, respectively; depositing a mask layer over the second conductive layer; patterning the mask layer to form a pattern of a top electrode in the memory region; patterning the first conductive layer and the second conductive layer by transferring the pattern to the first conductive layer and the second conductive layer; and etching the mask layer, the patterned first conductive layer and the patterned second conductive layer, the MTJ layer, and the bottom electrode layer using an etching operation to form a top electrode, an MTJ, and a bottom electrode in the memory region. In one or more of the foregoing and following embodiments, patterning the first conductive layer and the second conductive layer includes removing the second conductive layer in the logic region. In one or more of the foregoing and following embodiments, the first conductive layer includes a conductive material that is the same as the conductive material in the second conductive layer. In one or more of the foregoing and following embodiments, an interfacial layer is grown on the first conductive layer prior to depositing the second conductive layer. In one or more of the foregoing and following embodiments, a dielectric layer is formed above the substrate over the memory region and the logic region prior to depositing the bottom electrode layer, and a bottom electrode via is formed within the dielectric layer. The bottom electrode layer is electrically connected to the bottom electrode via, and the etching operation stops at the dielectric layer in the memory region while removing the thickness of the dielectric layer in the logic region. In one or more of the foregoing and following embodiments, the dielectric layer in the logic region is completely removed after the etching operation.

[0087] According to an embodiment, a semiconductor device includes a substrate and a memory device. The semiconductor device includes a memory region and a logic region. The memory device is arranged in the memory region above the substrate and includes: a bottom electrode via arranged above the substrate; a bottom electrode arranged above the bottom electrode via; a magnetic tunnel junction (MTJ) arranged above the bottom electrode; and a top electrode arranged above the MTJ. The top electrode includes an upper portion and a lower portion separated from the upper portion. In one or more of the foregoing and following embodiments, the top electrode further includes an interface layer located between the upper portion and the lower portion.

[0088] The features of several embodiments have been summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent configurations do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate comprising a logic region and a memory region; depositing a bottom electrode layer on the logic region and the memory region; depositing a magnetic tunnel junction layer above the bottom electrode layer; depositing a first conductive layer over the magnetic tunnel junction layer; depositing a sacrificial layer over the first conductive layer; removing the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; After removing the sacrificial layer, growing an interface layer on the first conductive layer in the memory region; After growing the interface layer, depositing a second conductive layer in the memory region and the logic region, wherein in the memory region, the first conductive layer and the second conductive layer are separated by the interface layer; patterning the second conductive layer and the first conductive layer to expose the magnetic tunnel junction layer in the memory region; and Portions of the patterned second conductive layer and the magnetic tunnel junction layer are etched to form a top electrode and a magnetic tunnel junction, respectively, in the memory region.

2. The method according to claim 1, further comprising: Prior to depositing the bottom electrode layer: forming a metal line layer having metal lines; depositing a first dielectric layer in the memory region and the logic region over the metal lines; as well as A bottom electrode via is formed in the first dielectric layer in the memory region.

3. The method according to claim 2, wherein: Etching portions of the patterned second conductive layer and the magnetic tunnel junction layer to form the top electrode and the magnetic tunnel junction, respectively, in the memory region includes reducing a thickness of the first dielectric layer in the logic region.

4. The method according to claim 3, wherein: After reducing the thickness of the first dielectric layer in the logic region, the metal lines in the logic region are covered by the first dielectric layer.

5. The method according to claim 1, wherein Patterning the second conductive layer to expose the magnetic tunnel junction layer in the memory region includes removing the second conductive layer in the logic region.

6. The method according to claim 1, further comprising: A mask layer is deposited over the second conductive layer, wherein patterning the second conductive layer to expose the magnetic tunnel junction layer in the memory region includes patterning the mask layer, and wherein the second conductive layer is patterned using the patterned mask layer as an etch mask.

7. The method according to claim 6, wherein: The mask layer includes the same material as that in the sacrificial layer.

8. The method according to claim 6, wherein: Etching the portion of the patterned second conductive layer and the magnetic tunnel junction layer to form the top electrode and the magnetic tunnel junction, respectively, in the memory region includes performing ion bombardment etching to remove the entire mask layer and the portion of the second conductive layer in the memory region.

9. The method according to claim 8, wherein The ion bombardment etching etches the magnetic tunnel junction layer using at least the second conductive layer as an etching mask to form the magnetic tunnel junction in the memory region.

10. The method according to claim 9, wherein: The ion bombardment etching also etches the bottom electrode layer using the second conductive layer as an etching mask to form a bottom electrode.

11. The method according to claim 8, wherein The ion bombardment etching removes the mask layer and the second conductive layer in the logic region. 12 . The method of claim 1 , further comprising forming spacers laterally surrounding the top electrode and sidewalls of the magnetic tunnel junction.

13. A method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate comprising a logic region and a memory region; depositing a bottom electrode layer and a magnetic tunnel junction layer over the substrate; depositing a first conductive layer over the magnetic tunnel junction layer; depositing an etching buffer layer over the first conductive layer; etching the etch buffer layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; growing an interface layer on the first conductive layer in the memory region; Depositing a second conductive layer over the interface layer and the etching buffer layer in the memory region and the logic region, respectively, wherein in the memory region, the first conductive layer and the second conductive layer are separated by the interface layer; depositing a mask layer over the second conductive layer; patterning the mask layer to form a pattern of a top electrode in the memory region; patterning the first conductive layer and the second conductive layer by transferring the pattern to the first conductive layer and the second conductive layer; and The mask layer, the patterned second conductive layer, the magnetic tunnel junction layer, and the bottom electrode layer are etched using an etching operation to form the top electrode, the magnetic tunnel junction, and the bottom electrode in the memory region.

14. The method according to claim 13, wherein Patterning the first conductive layer and the second conductive layer includes removing the second conductive layer in the logic region.

15. The method according to claim 13, wherein The first conductive layer includes the same conductive material as that in the second conductive layer.

16. The method according to claim 13, wherein The interface layer includes oxide.

17. The method according to claim 13, further comprising: Prior to depositing the bottom electrode layer: forming a dielectric layer on the memory region and the logic region over the substrate, and forming a bottom electrode via in the dielectric layer, wherein the bottom electrode layer is electrically connected to the bottom electrode via, The etching operation stops at the dielectric layer in the memory region while removing the thickness of the dielectric layer in the logic region.

18. The method according to claim 17, further comprising: After the etching operation, the dielectric layer in the logic area is completely removed.

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