A zero current shutdown circuit and method

Abstract

The invention belongs to the technical field of power switches, and provides a zero current shutdown circuit, which samples the Vds voltage of a field effect tube and restores a clock signal through the Vds voltage; at the same time, the Vds voltage is converted in the order of a level signal, a current signal, a voltage signal, and a pulse width signal to form a feedback loop for adjusting and controlling the pulse width. The time error of the current zero-crossing shutdown by the feedback circuit is controlled within the range of 0.1ns-2ns, and the supported power supply frequency can reach 30MHZ-300MHZ.

Description

Technical Field

[0001] The invention belongs to the technical field of power switches, and in particular relates to a zero-point current shutdown circuit and method for a high-frequency switch. Background Art

[0002] In power supply design, it is necessary to shut down the switch at zero current. Zero current shutdown is required. During a certain period of time, when the current flows from one end of the switch element (recorded as end A) to the other end (recorded as end B), the switch is turned on to provide a low-resistance path. Due to the presence of inductive loads, such as inductors, transformers, electromagnetic relays, adjustable inductors, etc., when the current flowing through the switch decreases from a large value to 0, the current will continue to flow in the opposite direction after passing through the zero point, that is, the current tries to flow from end B of the switch to end A. At this time, the switch needs to be disconnected when the current decreases to 0 to prevent the current from flowing in the opposite direction to complete the normal operation of the circuit.

[0003] Existing designs often use diodes to complete this function, such as Schottky diodes. Since Schottky diodes conduct in one direction, their reverse blocking characteristics prevent the current from flowing in the reverse direction after passing through zero. The diode conducts when the current flows from end A to end B, but the voltage drop is large, about 0.4V-0.9V, resulting in high power consumption and device heating.

[0004] In order to improve the power consumption problem, MOSFET has been used to replace diodes in existing synchronous rectification circuits. However, since MOSFET is a 3-port device, a circuit needs to be designed to control the gate of MOSFET. In low-speed power supplies, zero-current shutdown can be achieved by detecting the voltage zero-crossing point on Vds. Although there is a certain shutdown delay, it can also meet the requirements in low-speed application scenarios.

[0005] However, with the evolution and innovation of power supply structure, the switching speed is getting faster and faster. For example, in some cases, the switching frequency reaches 30MHz-300MHz, which puts higher requirements on the gate circuit of controlling MOSFET. For example, it is required to realize the switch shutdown within the range of 0.1nS-2nS near the current zero crossing point. In this way, the existing technology 2 cannot meet the requirements. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a zero current shutdown circuit, which samples the field effect tube Vds voltage and generates a clock signal through the Vds voltage drive; at the same time, the Vds voltage is converted in the order of level signal, current signal, voltage signal, and pulse width signal; and a feedback loop for adjusting the control pulse width is formed.

[0007] Specifically, the zero current shutdown circuit comprises:

[0008] The first field effect transistor and the second field effect transistor are used to control the inductive load loop in the circuit to be turned on or off according to the gate signal;

[0009] A clock recovery circuit uses the Vds signal of the first field effect tube and the Vds signal of the second field effect tube as input signals to recover a clock signal;

[0010] A sampling and comparison circuit samples the gate pulse signal of the first field effect tube and the Vds signal of the first field effect tube, compares the sampled Vds value of the first field effect tube with the zero voltage at the falling edge of the gate pulse signal of the first field effect tube, and outputs a level signal indicating the comparison result;

[0011] A charge pump, which controls the output direction of the current signal according to the level signal output by the sampling and comparison circuit;

[0012] a low-pass filter, receiving an output current of the charge pump and outputting a voltage signal related to a direction of the current signal;

[0013] A pulse generating circuit is used to generate a gate pulse signal for controlling the first field effect transistor and the second field effect transistor; the pulse generating circuit receives a clock signal generated by a clock recovery circuit, receives a voltage signal output by the low-pass filter, determines a rising edge of the gate pulse signal according to the clock signal, and determines a width of the gate pulse signal according to the voltage signal.

[0014] As a further improvement of one embodiment of the present invention, the sampling and comparison circuit outputs a high level signal when the gate pulse signal of the first field effect transistor is greater than zero, and outputs a low level signal when the gate pulse signal of the first field effect transistor is less than zero.

[0015] As a further improvement of one embodiment of the present invention, when the level signal is at a high level, the output current of the charge pump flows from the charge pump to the low-pass filter; when the level signal is at a low level, the output current of the charge pump flows from the low-pass filter to the low-pass filter.

[0016] As a further improvement of one embodiment of the present invention, the voltage signal output by the low-pass filter increases when the current signal flows from the charge pump into the low-pass filter; the voltage signal output by the low-pass filter decreases when the current signal flows from the low-pass filter into the charge pump.

[0017] As a further improvement of one embodiment of the present invention, the gate pulse signal width generated by the pulse generating circuit becomes larger when the voltage signal increases; the gate pulse signal width generated by the pulse generating circuit becomes smaller when the voltage signal decreases.

[0018] As a further improvement of one embodiment of the present invention, the clock recovery circuit includes a first inverter, a second inverter, a third inverter and a trigger; the output ends of the first inverter and the second inverter are connected to the input end of the third inverter, and the output end of the third inverter is connected to the signal input end of the trigger; the first input end of the first inverter is connected to the clock signal, and the second input end is connected to the Vds signal of the first field effect transistor; the first input end of the second inverter is connected to the inverted clock signal, and the second input end is connected to the Vds signal of the second field effect transistor.

[0019] As a further improvement of one embodiment of the present invention, the circuit module composed of the charge pump and the low-pass filter includes a first current source, a second current source, a P-type field effect transistor, an N-type field effect transistor, and a filter capacitor; the first current source is connected to the source of the P-type field effect transistor, and the second current source is connected to the source of the N-type field effect transistor; the drain of the P-type field effect transistor is connected to the drain of the N-type field effect transistor, and the gates of both are respectively connected to the level signal input terminal; the first plate of the filter capacitor is connected to the drain of the P-type field effect transistor and the drain of the N-type field effect transistor, and the second plate of the filter capacitor is connected to the reference ground.

[0020] The present invention also provides a universal zero-current shutdown method for different circuit implementations, the method comprising:

[0021] a. Sample the Vds signal of the field effect tube switch;

[0022] b. recovering a clock signal according to the Vds signal of the field effect tube, the clock signal is used to determine the rising edge of the gate pulse signal of the field effect tube;

[0023] c. Compare the Vds signal with the zero value at the falling edge of the field effect tube pulse signal, and generate a level signal indicating the comparison result;

[0024] d. Converting the level signal generated in step c into a current signal associated with the level signal;

[0025] e. converting the current signal generated in step d into a voltage signal;

[0026] f. Determine the rising edge of the gate pulse signal according to the clock signal in step b, and determine the width of the gate pulse signal according to the voltage signal in step e.

[0027] As a further improvement of an embodiment of the present invention, in step c, a high level signal is generated when the Vds signal of the field effect tube is greater than zero, and a low level signal is generated when the Vds signal of the field effect tube is less than zero.

[0028] As a further improvement of an embodiment of the present invention, in step c, when the level signal is a high level signal, the current signal is in the first direction; when the level signal is a low level signal, the current signal is in the second direction.

[0029] As a further improvement of an embodiment of the present invention, in step e, when the current signal is in the first direction, the voltage signal increases; when the current direction is in the second direction, the voltage signal decreases.

[0030] Compared with the prior art, the present invention can be applied to higher frequency power supply control, and its control frequency can reach 30MHZ-300MHZ. And it can adaptively adjust the width of the gate control pulse signal of the field effect tube according to the Vds voltage, so that the zero-crossing time point of the current shutdown is controlled within 0.1ns-2ns of the current zero-crossing point. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is the zero current shutdown circuit architecture diagram.

[0032] Figure 2 This is a schematic diagram of the clock recovery circuit.

[0033] Figure 3 Shown is the schematic diagram of the charge pump and low-pass filter.

[0034] Figure 4 Schematic diagram of zero current shutdown method.

[0035] Figure 5 This is a schematic diagram of the timing of each signal in the clock recovery circuit.

[0036] Figure 6 It is a timing diagram of various types of sampling and comparison circuits.

[0037] Figure 7 It is the timing diagram of low-pass filter and charge pump signals.

[0038] Figure 8 It is the timing diagram of each signal of the sampling and comparison circuit.

[0039] Fig. 9 This is the timing diagram of each signal in the pulse generating circuit. DETAILED DESCRIPTION

[0040] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings to help those skilled in the art understand the technical solutions of the present invention.

[0041] Reference Figure 1 It shows the composition of each module of the zero current shutdown circuit 100 and the relationship between the modules, wherein the arrow indicates the signal direction, the arrow pointing to the module is the input signal, and the arrow away from the module is the output signal.

[0042] The zero current shutdown circuit 100 includes a first field effect transistor MOSFET1, a second field effect transistor MOSFET2, a clock recovery circuit 110, a sampling and comparison circuit 102, a charge pump 104, a low pass filter 106, and a pulse generating circuit 108. The first input end of the clock recovery circuit 110 is coupled to the first field effect transistor MOSFET1, and the second input end is coupled to the second field effect transistor MOSFET2; the output end of the clock recovery circuit 110 is coupled to the first input end of the pulse generating circuit 108; the first input end of the sampling and comparison circuit 102 is coupled to the first field effect transistor MOSFET1, the second input end of the sampling and comparison circuit 102 is coupled to the gate of the first field effect transistor MOSFET1, and the output end of the sampling and comparison circuit 102 is coupled to the input end of the charge pump 104; the output of the charge pump 104 is coupled to the input end of the low pass filter 106, the output end of the low pass filter 106 is coupled to the second input end of the pulse generating circuit 108, and the output end of the pulse generating circuit 108 is coupled to the gates of the first field effect transistor MOSFET1 and the second field effect transistor MOSFET2.

[0043] The first field effect transistor MOSFET1 and the second field effect transistor MOSFET2 are used to turn on or off a load loop (not shown in the figure) in the control circuit according to a gate signal. The load is an inductive load, such as a motor winding or a transformer. The first field effect transistor MOSFET1 and the second field effect transistor MOSFET2 can be connected to the upper end and the lower end of the inductive load respectively. The first field effect transistor MOSFET1 and the second field effect transistor MOSFET2 are connected to turn on or off at the same time. In a preferred solution, the first field effect transistor MOSFET1 is preferably a PMOS tube and the second field effect transistor MOSFET2 is an NMOS tube.

[0044] Figure 2 FIG. 1 is a schematic diagram of a preferred clock recovery circuit 110 .

[0045] The clock recovery circuit 110 recovers the clock signal by taking the Vds signal Vds1 of the first field effect transistor MOSFET1 and the Vds signal Vds2 of the second field effect transistor MOSFET2 as input signals. The clock recovery circuit 110 includes a first inverter 202, a second inverter 204, a third inverter 206 and a trigger 210; the output ends of the first inverter 202 and the second inverter 204 are connected to the input end of the third inverter 206, and the output end of the third inverter 206 is connected to the signal input end of the trigger 210; the first input end of the first inverter 202 is connected to the clock signal Vclk, and the second input end is connected to the Vds signal Vds1 of the first field effect transistor MOSFET1; the first input end of the second inverter 204 is connected to the inverted clock signal Clk_b, and the second input end is connected to the Vds signal Vds2 of the second field effect transistor MOSFET2. The inverted clock signal Clk_b is obtained after the clock signal Clk is processed by the fourth inverter 208.

[0046] Figure 3 The schematic diagram of the structure of the charge pump 104 and the low-pass filter 106 is shown, which is equivalent to Figure 1 The charge pump 104 module and the low-pass filter 106 module are combined modules.

[0047] The circuit module composed of the charge pump 104 and the low-pass filter 106 includes a first current source Iup, a second current source Idn, a P-type field effect transistor MP, an N-type field effect transistor MN, and a filter capacitor Clpf; the first current source Iup is connected to the source of the P-type field effect transistor MP, and the second current source Iup is connected to the source of the N-type field effect transistor MN; the drain of the P-type field effect transistor MP is connected to the drain of the N-type field effect transistor MN, and the gates of the two are respectively connected to the input end of the level signal Dflag, and the input end of the level signal Dflag is coupled to the sampling and comparison circuit 102; the first plate of the filter capacitor Clpf is connected to the drain of the P-type field effect transistor MP and the drain of the N-type field effect transistor, and the second plate of the filter capacitor Clpf is connected to the reference ground. The first plate of the filter capacitor Clpf serves as the output end of the low-pass filter 106.

[0048] The sampling and comparison circuit 102 has multiple implementations, and those skilled in the art can implement multiple implementations according to the functional requirements of the comparator. For example, the output terminal of the comparator is connected to the first input terminal of the AND gate circuit, and the second input terminal of the AND gate circuit is connected to the gate pulse signal Vgs. The input terminal of the comparator is connected to the zero reference potential and the first field effect tube Vds voltage.

[0049] Those skilled in the art know that the sampling and comparison circuit 102 can select appropriate accuracy and speed. For example, the sampling rate can be reduced to improve accuracy. For another example, sampling can be performed only once during multiple gate pulses Vgs, and a high-precision sampling and comparison circuit 102 can be used to achieve high-precision zero-current shutdown. The pulse generating circuit 108 has multiple implementations, and those skilled in the art can implement multiple implementations according to the functional requirements of the pulse signal. The function of the pulse generating circuit 108 is: according to the clock signal Vclk recovered by the clock recovery circuit 110 and the voltage signal Vcp output by the low-pass filter 106, a gate pulse signal Vgs is output, and the gate pulse signal Vgs is connected to the gate of the field effect transistor.

[0050] Figure 4 The flowchart of the zero current shutdown method is shown in FIG. 1 . In addition to the above circuit scheme, those skilled in the art can also design circuit executions with different implementations. Figure 4 The zero current shutdown method shown in the figure includes steps a to f, wherein steps ab and cf are performed in time sequence, and steps ab and cf are performed simultaneously.

[0051] Figure 5-8 The signal timings involved in the corresponding steps af are plotted, and the following content describes each step in combination with the timings and circuits.

[0052] Step a: sampling the Vds signals Vds1 and Vds2 of the field effect tube switch. The sampled Vds signals are used to recover the clock signal Vclk and to compare with the zero value. The step of sampling the signals Vds1 and Vds2 can be performed as follows: Figure 1 The clock recovery circuit 110 and the sampling and comparison circuit 102 shown in the figure can sample separately, or an intermediate module can be used to sample and send the samples to the clock recovery circuit 110 and the sampling and comparison circuit 102.

[0053] Step b recovers the clock signal Vclk according to the Vds signal of the field effect tube, and the clock signal Vclk is used to determine the rising edge 402 of the gate pulse signal Vgs of the field effect tube. The clock recovery circuit 110 takes the Vds1 signal of the first field effect tube and the Vds2 signal of the first field effect tube as input signals, and recovers the clock signal Vclk according to Vds1 and Vds2.

[0054] Reference Figure 5The Vds1 signal of the first field effect tube and the Vds2 signal of the second field effect tube are processed by inverters 202, 204, and 206 to generate a phase difference CK_dff signal. The phase difference signal CK_dff is used to drive the trigger 210 so that the output state of the trigger 210 periodically jumps. The pulse sequence formed by the multiple phase differences CK_dff causes the trigger 210 to output a clock signal Vclk. The clock signal Vclk is the same as the clock cycle of the power supply of the load, so the time point of zero current of the power supply can be determined by the clock signal Vclk. The pulse generation circuit aligns the rising edge of the gate pulse signal Vgs of the field effect tube with the rising edge of the clock signal Vclk 402 (refer to Figure 7 ), and then adjusting the width of the gate pulse signal Vgs to determine the falling edge 404 position of the gate control signal.

[0055] Step c compares the Vds signal with a zero value at the falling edge of the gate pulse signal Vgs, and generates a level signal representing the comparison result.

[0056] In step c, the sampling and comparison circuit 102 samples the gate pulse signal Vgs of the first field effect transistor MOSFET1, samples the Vds1 voltage at the end edge of the Vgs pulse, compares the sampled Vds value of the first field effect transistor with the zero voltage at the falling edge of the gate pulse signal Vgs of the first field effect transistor MOSFET1, and outputs a level signal representing the comparison result.

[0057] Reference Figure 6 In the first clock cycle t1, the sampling and comparison circuit 102 samples the Vds1 voltage at the falling edge of the gate pulse signal Vgs. At this time, the Vds1 voltage Vsamp is greater than zero, and the sampling and comparison circuit 102 outputs a high-level signal h, which indicates that the turn-off time of the field effect tube is earlier than the zero current point. In the second clock cycle t2, at the falling edge of the gate pulse signal Vgs, the value of Vsamp is less than 0, and the output is a low-level signal l.

[0058] Step d converts the level signal generated in step c into a current signal related to the level signal. The charge pump 104 outputs a current signal Icp under the control of the level signal Dflag. When the level signal is a high level signal, the current signal Icp is in a first direction, and when the level signal is a low level signal, the current signal Icp is in a second direction.

[0059] Reference Figure 3 , Figure 7When the level signal Dflag is at a low level, the P-type field effect transistor MP in the charge pump 104 is turned on, and the first current source Iup is turned on so that the current signal Icp flows from the charge pump 104 to the filter capacitor Clpf; when the level signal Dflag is at a high level, the N-type field effect transistor MN is turned on, and the current signal Icp flows from the filter capacitor Clpf to the second current source Iup. Overall, when the level signal Dflag is at a low level, the current flows from the charge pump 104 to the filter, and when the level signal Dflag is at a high level, the current flows from the filter to the charge pump 104.

[0060] Step e converts the current signal Icp generated in step d into a voltage signal. As described above, when the level signal is low, the current signal Icp flows from the charge pump 104 into the low-pass filter 106, and the low-pass filter 106 receives the current signal Icp, and its output voltage signal Vcp increases; when the level signal is high, the current signal Icp flows from the low-pass filter 106 into the charge pump 104, and the output voltage signal Vcp of the low-pass filter 106 decreases.

[0061] Reference Figure 7 After the conversion of the current signal Icp and the voltage signal Vcp, the level signal Dflag is converted into a changing sawtooth voltage signal Vcp, and this voltage change is accompanied by the charging and discharging process of the capacitor Clpf. When the level signal Dflag is at a low level, the charging voltage of the capacitor Clpf increases, and when the level signal Dflag is at a high level, the discharging voltage of the capacitor Clpf decreases. The voltage signal is used to control the pulse width Vgs of the pulse generating circuit 108, so as to bring the falling edge of the field effect tube closer to the zero point of the current.

[0062] Step f determines the rising edge 402 of the gate pulse signal Vgs according to the clock signal in step b, and determines the width d of the gate pulse signal Vgs according to the voltage signal in step e. The input signal of the pulse generating circuit 108 is the recovered Vclk and the output signal Vcp of the low-pass filter 106, and outputs the gate pulse signal Vgs, and the gate pulse signal Vgs is connected to the gates of the field effect transistors MOSFET1 and MOSFET2. The pulse generating circuit generates a rising edge 402 of a pulse signal Vgs driven by the rising edge of the clock signal Vclk, and the width d of the pulse signal is controlled by the output signal Vcp of the low-pass filter: when Vcp increases, the pulse width d of the gate pulse signal Vgs increases; when the output signal Vcp of the low-pass filter decreases, the pulse width of the gate pulse signal Vgs decreases. The falling edge 404 of the gate pulse signal Vgs is made closer to the zero point by adjusting the width of the pulse signal Vgs.

[0063] and Fig. 9The following two cases are listed to illustrate the adjustment process of the gate pulse signal Vgs in steps af. Because the circuit starts working from an initial state or for some reason, the falling edge of the gate pulse signal Vgs will deviate from the zero current switching point.

[0064] Reference Figure 5 , 6 8. Assume that the pulse width of the gate pulse signal vgs is too small, causing the vds1 value sampled at the falling edge of the gate pulse signal vgs to be less than 0, indicating that at the sampling moment, the current flows from the S terminal to the D terminal, and the sampling and comparison circuit 102 outputs the level signal Dflag as a low level 1; the charge pump 104 receives the low level 1, and the current signal Icp flows from the charge pump 104 to the low-pass filter 106; the low-pass filter 106 receives the input current signal Icp from the charge pump 104 into the low-pass filter 106, and the output voltage signal Vcp increases; the pulse generating circuit 108 receives the voltage signal Vcp increase, and outputs a pulse signal Vgs under the action of the rising edge of Vclk. Since the Vcp voltage signal increases, the pulse width increases, so that the falling edge of Vgs is closer to the zero current switching point. Figure 8 As shown, after 3 clock cycles of adjustment, the pulse width of the gate pulse signal Vgs gradually increases, so that the falling edge of the gate pulse signal Vgs gradually aligns with the zero current point.

[0065] Reference Figure 5 , 6 9. Assume that the pulse width of the gate pulse signal vgs is too large, and the vds1 value sampled at the falling edge of the gate pulse signal vgs is greater than 0, indicating that at the sampling moment, the current flows from the D terminal to the S terminal, and the sampling and comparison circuit 102 outputs Dflag as a high level h; the charge pump 104 receives Dflag as a high level, and the output current signal Icp flows from the low-pass filter 106 to the charge pump 104; the low-pass filter 106 receives the input current signal Icp from the low-pass filter 106 into the charge pump 104, and the output voltage signal Vcp decreases; the pulse generating circuit 108 receives the voltage signal Vcp decreases, and outputs a pulse signal Vgs under the action of the rising edge of Vclk. Since the Vcp voltage signal decreases, the pulse width decreases, so that the falling edge of Vgs is closer to the zero current switching point. Fig. 9 As shown, after 3 clock cycles of adjustment, the pulse width of the gate pulse circuit gradually decreases, so that the falling edge of the gate pulse signal Vgs gradually aligns with the zero current point.

[0066] Compared with the prior art, the present invention can be applied to power supply control at a higher frequency, and can adapt to the changes of the power supply zero point and pulse width through the feedback loop, and can adaptively adjust the width of the gate control pulse signal of the field effect tube according to the Vds voltage. The zero-crossing time point of the current shutdown is controlled at 0.1ns-2ns of the current zero-crossing point. And the supported power supply frequency can reach 30MHZ-300MHZ.

[0067] Any equivalent changes to the technical solutions made by those skilled in the art without departing from the concept of the present invention shall fall within the protection scope of the present invention. For example, those skilled in the art know the high and low level settings of the level signal Dflag, the flow direction settings of the Icp current signal, the increase and decrease settings of the Vcp voltage signal, the increase or decrease settings of the pulse width of Vgs, etc., and the input-output relationship can be adjusted and changed.

Claims

1. A zero current shutdown circuit, characterized in that: include: The first field effect transistor and the second field effect transistor are used to control the inductive load loop in the circuit to be turned on or off according to the gate signal; A clock recovery circuit uses the Vds signal of the first field effect transistor and the Vds signal of the second field effect transistor as input signals to recover a clock signal; A sampling and comparison circuit, sampling a gate pulse signal of the first field effect tube and a Vds signal of the first field effect tube; Comparing the Vds value of the first field effect tube with the zero voltage at the falling edge of the gate pulse signal of the first field effect tube, and outputting a level signal indicating the comparison result; A charge pump, which controls the output direction of the current signal according to the level signal output by the sampling and comparison circuit; a low-pass filter, receiving an output current signal of the charge pump and outputting a voltage signal related to a direction of the current signal; A pulse generating circuit, used for generating a gate pulse signal for controlling the first field effect transistor and the second field effect transistor; A pulse generating circuit receives a clock signal generated by a clock recovery circuit, receives a voltage signal output by the low-pass filter, determines a rising edge of the gate pulse signal according to the clock signal, and determines a width of the gate pulse signal according to the voltage signal; The clock recovery circuit includes a first inverter, a second inverter, a third inverter and a trigger; the output ends of the first inverter and the second inverter are connected to the input end of the third inverter, and the output end of the third inverter is connected to the signal input end of the trigger; the first input end of the first inverter is connected to the clock signal, and the second input end is connected to the Vds signal of the first field effect tube; The first input terminal of the second inverter is connected to the inverted clock signal, and the second input terminal is connected to the Vds signal of the second field effect transistor; The circuit module composed of the charge pump and the low-pass filter includes a first current source, a second current source, a P-type field effect transistor, an N-type field effect transistor, and a filter capacitor; the first current source is connected to the source of the P-type field effect transistor, and the second current source is connected to the source of the N-type field effect transistor; The drain of the P-type field effect transistor is connected to the drain of the N-type field effect transistor, and the gates of both are connected to the level signal input terminal respectively; The first plate of the filter capacitor is connected to the drain of the P-type field effect transistor and the drain of the N-type field effect transistor, and the second plate of the filter capacitor is connected to the reference ground.

2. A zero current shutdown circuit according to claim 1, characterized in that: The sampling and comparison circuit outputs a high level signal when the gate pulse signal of the first field effect tube is greater than zero, and outputs a low level signal when the gate pulse signal of the first field effect tube is less than zero.

3. A zero current shutdown circuit according to claim 2, characterized in that: When the level signal is at a high level, the output current of the charge pump flows from the charge pump to the low-pass filter; when the level signal is at a low level, the output current of the charge pump flows from the low-pass filter to the low-pass filter.

4. A zero current shutdown circuit according to claim 3, characterized in that: The voltage signal output by the low-pass filter increases when the current signal flows from the charge pump into the low-pass filter; the voltage signal output by the low-pass filter decreases when the current signal flows from the low-pass filter into the charge pump.

5. A zero current shutdown circuit according to claim 4, characterized in that: The gate pulse signal width generated by the pulse generating circuit increases when the voltage signal increases; the gate pulse signal width generated by the pulse generating circuit decreases when the voltage signal decreases.

6. A zero current shutdown method for the zero current shutdown circuit as claimed in claim 1, characterized in that: include: a. Sample the Vds signal of the field effect tube switch; b. recovering a clock signal according to the Vds signal of the field effect tube, the clock signal is used to determine the rising edge of the gate pulse signal of the field effect tube; c. Comparing the Vds signal of the field effect tube with the zero value at the falling edge of the gate pulse signal, and generating a level signal indicating the comparison result; d. Converting the level signal generated in step c into a current signal associated with the level signal; e. converting the current signal generated in step d into a voltage signal; f. Determine the rising edge of the gate pulse signal according to the clock signal in step b, and determine the width of the gate pulse signal according to the voltage signal in step e.

7. A zero current shutdown method according to claim 6, characterized in that: In step c, when the Vds signal of the field effect tube is greater than zero, a high level signal is generated; when the Vds signal of the field effect tube is less than zero, a low level signal is generated.

8. A zero current shutdown method according to claim 7, characterized in that: In step c, when the level signal is a high level signal, the current signal is in the first direction; when the level signal is a low level signal, the current signal is in the second direction.

9. A zero current shutdown method according to claim 8, characterized in that: In step e, when the current signal is in the first direction, the voltage signal increases; when the current signal is in the second direction, the voltage signal decreases.

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