Merged data path for triangle and box intersection testing in ray tracing

Abstract

A merged data path unit is described herein, having elements that are configurable to switch between different instruction types. The merged data path unit is a pipeline unit having multiple stages. A multiplexer layer is located between different stages, and the multiplexer layer is configurable to route data from a functional block in a previous stage to a next stage. The manner in which the multiplexer layer is configured for a particular stage is based on the type of instruction executed at the stage. In some embodiments, the control unit may also configure the functional blocks in different stages to change the operations performed. In addition, in some embodiments, the control unit has a sideband storage device that stores data for "skipped stages." An example of a merged data path for performing ray-triangle intersection testing and ray-box intersection testing is also described herein.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Patent Application No. 16 / 219,802, filed December 13, 2018, the contents of which are hereby incorporated herein by reference. Background Art

[0003] Ray tracing is a graphics rendering technique in which simulated light rays are cast to test for object intersection, and pixels are shaded based on the results of the ray casting. Ray tracing is computationally more expensive than rasterization-based techniques, but produces more physically accurate results. Ray tracing operations are continually being improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] A more detailed understanding may be obtained from the following description given by way of example in conjunction with the accompanying drawings, in which:

[0005] Figure 1 is a block diagram of an exemplary apparatus in which one or more features of the present disclosure may be implemented;

[0006] Figure 2 is a block diagram of an apparatus according to an example, showing Figure 1 Additional details about the accelerated processing device performing the processing task;

[0007] Figure 3 shows details of a merged data path unit according to an example;

[0008] Figure 4 An example of a merged datapath unit that implements both a ray box test and a ray triangle test is shown; and

[0009] Figure 5 is a flow chart of a method for processing data via a merged data path unit according to an example. DETAILED DESCRIPTION

[0010] A merged data path unit is described herein, which has elements that can be configured to switch between different instruction types. The merged data path unit is a pipeline unit with multiple stages. A multiplexer layer is located between different stages, and the multiplexer layer can be configured by a control unit to route data from functional blocks of the stage before the multiplexer layer to the stage after the multiplexer layer. The manner in which the multiplexer layer is configured for a particular stage is based on the type of instruction executed at the stage. In some embodiments, the control unit can also configure functional blocks in different stages to change the operations performed. (For example, a combined multiplier / adder can be set to a multiplier or an adder based on the instruction type). In addition, in some embodiments, the control unit has a sideband storage device that stores data of "skipped stages". An example of a merged data path for performing ray-triangle intersection testing and ray-box intersection testing is described herein. Additional details are provided below.

[0011] Figure 1 1 is a block diagram of an exemplary device 100 in which one or more features of the present disclosure may be implemented. Device 100 includes, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 also optionally includes an input driver 112 and an output driver 114. It should be understood that device 100 includes devices not described in Figure 1 Additional components shown in FIG.

[0012] In various alternatives, the processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU on the same die, or one or more processor cores, where each processor core can be a CPU or a GPU. In various alternatives, the memory 104 is located on the same die as the processor 102, or is located separately from the processor 102. The memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or cache.

[0013] Storage device 106 includes fixed or removable storage devices, such as hard disk drives, solid state drives, optical disks, or flash drives. Input device 108 includes, but is not limited to, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless LAN card for transmitting and / or receiving wireless IEEE 802 signals). Output device 110 includes, but is not limited to, a display device 118, a speaker, a printer, a tactile feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless LAN card for transmitting and / or receiving wireless IEEE 802 signals).

[0014] The input driver 112 communicates with the processor 102 and the input device 108 and allows the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110 and allows the processor 102 to send output to the output device 110. It should be noted that the input driver 112 and the output driver 114 are optional components, and if the input driver 112 and the output driver 114 are not present, the device 100 will operate in the same manner. The output driver 114 includes an accelerated processing device ("APD") 116 coupled to the display device 118. The APD 116 is configured to accept computational commands and graphics rendering commands from the processor 102, process those computational commands and graphics rendering commands, and provide pixel outputs to the display device 118 for display. As described in further detail below, the APD 116 includes one or more parallel processing units that are configured to perform computations according to a single instruction multiple data ("SIMD") paradigm. Thus, while various functionality is described herein as being performed by or in conjunction with APD 116, in various alternatives, functionality described as being performed by APD 116 is additionally or alternatively performed by other computing devices having similar functionality that are not driven by a host processor (e.g., processor 102) and are not configured to provide (graphic) output to display device 118. For example, it is contemplated that any processing system that performs processing tasks according to the SIMD paradigm may be configured to perform the functionality described herein. Alternatively, it is contemplated that computing systems that do not perform processing tasks according to the SIMD paradigm perform the functionality described herein.

[0015] Figure 21 is a block diagram of device 100 showing additional details related to performing processing tasks on APD 116. Processor 102 maintains one or more control logic modules in system memory 104 for execution by processor 102. The control logic modules include operating system 120, driver 122, and application program 126. These control logic modules control various features of the operation of processor 102 and APD 116. For example, operating system 120 communicates directly with the hardware and provides an interface to the hardware for other software executing on processor 102. Driver 122 controls the operation of APD 116 by, for example, providing an application programming interface ("API") to software executing on processor 102 (e.g., application program 126) to access various functionalities of APD 116. In some embodiments, driver 122 includes a just-in-time compiler that compiles programs for execution by a processing component of APD 116 (such as SIMD unit 138 discussed in further detail below). In other implementations, a just-in-time compiler is not used to compile the program, and a normal application compiler compiles the shader program for execution on the APD 116 .

[0016] APD 116 executes commands and programs for selected functions, such as graphics operations and non-graphics operations suitable for parallel processing and / or out-of-order processing. APD 116 is used to perform graphics pipeline operations such as pixel operations, geometric calculations, and rendering images to display device 118 based on commands received from processor 102. APD 116 also performs computational processing operations not directly related to graphics operations, such as operations related to video, physics simulations, computational fluid dynamics, or other tasks, based on commands received from processor 102.

[0017] The APD 116 includes a computing unit 132, which includes one or more SIMD units 138, which perform operations in parallel according to the request of the processor 102 according to the SIMD paradigm. The SIMD paradigm is a paradigm in which multiple processing elements share a single program control flow unit and program counter and thus execute the same program but can execute the program with different data. In one example, each SIMD unit 138 includes sixteen channels, each of which executes the same instruction simultaneously with other channels in the SIMD unit 138, but executes the instruction with different data. If not all channels need to execute a given instruction, the channel can be closed using an assertion. Assertions can also be used to execute programs with divergent control flows. More specifically, for programs with conditional branches or other instructions in which the control flow is based on calculations performed by a single channel, assertions of channels corresponding to control flow paths that are not currently executed and serial execution of different control flow paths allow arbitrary control flows. In one embodiment, each of the computing units 132 can have a local L1 cache. In one embodiment, multiple computing units 132 share an L2 cache.

[0018] The basic execution unit in the computing unit 132 is a work item. Each work item represents a single instance of a program to be executed in parallel in a specific channel. Work items can be executed as "wavefronts" on a single SIMD processing unit 138 at the same time. One or more wavefronts are included in a "work group", which includes a set of work items designated to execute the same program. The work group is executed by executing each of the wavefronts that constitute the work group. In an alternative, the wavefront is executed sequentially on a single SIMD unit 138, or partially or completely in parallel on different SIMD units 138. The wavefront can be regarded as the maximum set of work items that can be executed simultaneously on a single SIMD unit 138. Therefore, if the command received from the processor 102 indicates that a specific program will be parallelized to the extent that the program cannot be executed on a single SIMD unit 138 at the same time, the program is decomposed into wavefronts that are parallelized on two or more SIMD units 138 or serialized on the same SIMD unit 138 (or parallelized and serialized as needed). Scheduler 136 is configured to perform operations related to scheduling the various wavefronts across compute units 132 and SIMD units 138 .

[0019] The parallelism provided by the compute units 132 is suitable for graphics-related operations such as pixel value calculations, vertex transformations, and other graphics operations. Thus, in some examples, the graphics pipeline 134 that receives graphics processing commands from the processor 102 provides computing tasks to the compute units 132 for parallel execution.

[0020] Compute unit 132 is also used to perform computational tasks that are not graphics related or that are not performed as part of the "normal" operation of graphics pipeline 134 (e.g., custom operations performed to supplement processing performed for operation of graphics pipeline 134). Application 126 or other software executing on processor 102 transmits programs defining such computational tasks to APD 116 for execution.

[0021] Each compute unit 132 includes one or more merge data path units 139. The merge data path unit 139 is a unit having functional blocks shared between different operations. In one example, the merge data path unit 139 performs ray-box and ray-triangle hit detection for a ray casting shader program executed in the SIMD unit 138. The functional blocks within the merge data path unit 139 include blocks such as various adders and multipliers. In the merge data path unit 139, some of these functional blocks are used for two or more of the different operations. It should be noted that although the merge data path unit 139 is described as being included in the APD 116, it should be understood that the merge data path unit 139 can be used in or in conjunction with any type of processing unit. In one example, a program executed in the SIMD unit 138 requests the merge data path unit 139 to execute a specific instruction, and in response, the merge data path unit 139 configures itself according to the requested instruction type and executes the requested instruction.

[0022] Figure 3 Details of a merged datapath unit 139 according to an example are shown. The merged datapath unit 139 includes a plurality of opcode specific blocks 304 arranged in stages, a multiplexer layer 306 and shared functional blocks 308, and a sideband storage and block control unit 310 (also referred to herein as "control unit 310"). The merged datapath unit 139 is considered "merged" because different types of instructions can be executed in the merged datapath unit 139 using at least some of the same functional blocks ("shared functional blocks 308").

[0023] The term "function block" refers to both opcode-specific blocks 304 and shared function blocks 308. An opcode-specific block 304 is a function block (i.e., a circuit that performs operations such as addition or multiplication, determines a minimum or maximum value, performs logical operations such as AND operations and / or OR operations, or performs a specific sequence of the above) that is used only by a specific data path 302 (and therefore only by a specific instruction type defined by its opcode). A shared function block 308 is a function block used by two or more data paths 302 (and therefore two or more instruction types). In some embodiments, a shared function block 308 performs a fixed operation (such as addition) regardless of which instruction type the function block is executing. In other embodiments, the control unit 310 can configure the shared function block 308 to perform different operations for different instruction types.

[0024] The start and end of any function block are defined by timing elements, such as flip-flops. From the flip-flops, signals propagate through the logic of the function block at the input of the function block, without encountering any timing elements until the output of the function block, to provide a result at the output of the function block. At the output, the result is stored in an output flip-flop for use in subsequent stages. Typically, the propagation delay for each function block is less than the cycle period multiplied by the number of stages spanned by the function block. (Typically, this number is 1, but some function blocks may span multiple stages where the propagation delay across the function block is greater than the cycle period, but less than a certain multiple of the cycle period).

[0025] The multiplexer layer 306 includes one or more multiplexers that receive data from an immediately preceding stage or control unit 310 and provide data to an immediately following stage or control unit 310 based on a control signal set by the control unit 310 .

[0026] At the input of the merge datapath unit 139, the merge datapath unit 139 accepts an opcode specifying an instruction type and one or more operands for the instruction type. The instruction is processed through a series of stages to produce and output one or more results. Because the merge datapath unit 139 is pipelined, each stage performs a sub-operation on a different instruction in any particular cycle.

[0027] The control unit 310 configures each stage to perform a sub-operation on a specific instruction type based on which instruction type the stage is to execute in any given cycle. More specifically, in each clock cycle, each stage performs a sub-operation on a specific instruction type. The term "sub-operation" refers to any intermediate calculation or operation for an instruction type performed by a specific functional block of the merge data path unit 138. In one example, for an instruction involving a series of multiplication-addition operations, one sub-operation is the addition of two values, another sub-operation is the multiplication of two values, another sub-operation is the addition of two values, and so on. The specific order of the sub-operations to be performed on any given instruction depends on the opcode of the instruction.

[0028] The control unit 310 controls the multiplexer layer 306 based on the opcode of the instruction to route data for a particular instruction to a particular functional block. In addition, the control unit 310 acts as a temporary storage device for instructions that do not perform any operations in a particular stage. For example, such storage may be performed if a particular instruction type is at least partially serialized by the merge data path unit 139, as described in more detail below.

[0029] For any given stage, in any particular cycle, the functional blocks of the stage are configured to perform sub-operations on a single instruction type. However, a stage can change which instruction type is executed at the stage on each cycle. Thus, in any particular cycle, one stage may be configured to execute instructions of a first type, while in the same cycle, the immediately next (or immediately previous) stage executes instructions of a second type.

[0030] One purpose of using a merged datapath unit 139 is to reduce the amount of silicon area used by only one type of instruction, because doing so reduces the total amount of silicon on the chip. Thus, one way to design a merged datapath unit is to design it for the instructions that require the largest amount of silicon area, and then use the functional blocks that take up that silicon area for other instruction types that require less silicon. The functional blocks that are used by more than one instruction are the shared functional blocks 308 described above. Of course, different instruction types may require unique functional units that cannot be shared with different instruction types, or require more specific shared functional blocks 308 than other instruction types.

[0031] By increasing the throughput of instruction types that require less silicon, the difference in the amount of silicon area required for different instruction types can be exploited. The increase in throughput of a first instruction type compared to a second instruction type means that more instructions of the first instruction type are processed by the merged data path unit 139 than the second instruction type in the same number of cycles. The increase in throughput can be achieved by parallelizing the sub-operations of the instruction type in a specific level or serializing the sub-operations of the instruction type across multiple levels. Parallelizing the sub-operations of the instruction type refers to using functional blocks to perform sub-operations corresponding to multiple instances of a given instruction type in a single level. Serializing the sub-operations refers to performing the same sub-operations on different instruction instances of the same type in different levels of the merged data path unit 139. Since it is required for instructions that require a larger amount of silicon than the instructions being parallelized, parallel sub-operations can be performed when a large number of functional blocks already exist in a specific level. In the case, sub-operations of multiple instances of instructions that require a smaller amount of silicon can be performed in the specific level in the same cycle. By parallelizing and serializing one or both of the lower-level silicon instructions, a high percentage of the large amount of silicon used for higher-level silicon instructions is used for lower-level silicon instructions.

[0032] Figure 3 An example of the above features of the merged datapath unit 139 is shown. The first datapath 302(1) processes instructions of a first type, and the second datapath 302(2) processes instructions of a second type. The first type requires more silicon area than the second type. Specifically, each instruction of the first type requires the following units: an opcode specific block 304(1), four shared functional blocks 308(1) to 308(4) in level 1, two shared functional blocks 308(5) to 308(6) in level 2, two shared functional blocks 308(7) to 308(8) in level 3, and an opcode specific block 304(6) in level 4. The opcode specific block 304(1) is also used for each instruction of the first type. Each instruction of the second type requires the following units: two shared functional blocks 308 and one opcode specific block 304. The opcode specific block 304(2) is shared between multiple instances of instructions of the second type. Instructions of the second type use opcode specific blocks 304(3), 304(4), 304(5), and 304(7), but do not use 304(6). Note that each instruction of the first instruction type requires eight shared function blocks 308, while each instruction of the second instruction type requires only two shared function blocks 308. Thus, there are enough shared function blocks 308 to output the results of one instruction of the first type per cycle or four instructions of the second type per cycle.

[0033] For the first instruction type, the operation of the merge datapath unit 139 proceeds in the following manner. In the first cycle, data for instructions of the first instruction type is input to the opcode specific block 304(1) in stage 0. In addition, the opcode of the instruction is provided to the sideband storage and block control unit 310 (again sometimes referred to simply as "control unit 310"). The opcode specific block 304(2) is not used during this cycle because it is used for instructions of the second type. The result of the opcode specific block 304(1) is output to the multiplexer layer 306(1).

[0034] In the next cycle, the control unit 310 configures the multiplexer layer 306(1) to distribute values ​​from the opcode specific block 304(1) to each of the shared function blocks 308 in the first level, all of which are used to process a single instruction of the first type. The shared function blocks 308 in the first level process the values ​​and output the results to the multiplexer layer 306(2). The control unit 310 configures the multiplexer layer 306(2) to output the values ​​to one of the shared function blocks 308(5) or the shared function blocks 308(6). These blocks process the data and output the results to the multiplexer layer 306(3). The control unit 310 configures the multiplexer layer 306(3) to output the results to one of the shared function blocks 308(7) or the shared function blocks 308(8). These blocks process the results and output the results to the multiplexer layer 306(4). The control unit 310 controls the multiplexer layer 306 (4) to output the result to the opcode specific block 304 (6), which processes the result and outputs the result for the instruction.

[0035] Instructions of the second type are processed in the following manner. Values ​​for four different instructions of the second type are input to opcode specific block 304(2). Opcode specific block 304(2) processes those results and outputs those values ​​to multiplexer layer 306(1). Control unit 310 configures multiplexer layer 306(1) to output values ​​for two instructions to shared function blocks 308(1) to 308(4) and to output values ​​for the other two instructions to control block 310 for temporary storage. Shared function blocks 308(1) and 308(2) process values ​​for the first instruction and output those values ​​to multiplexer layer 306(2). Shared function blocks 308(3) and 308(4) process values ​​for the second instruction and output those values ​​to multiplexer layer 306(2). Control unit 310 configures multiplexer layer 306(2) to provide the value of the third instruction to stage 2 for the same sub-operation as the sub-operation performed on the first and second instructions in stage 1, the value being stored in control unit 310 and not processed in stage 1. Control unit 310 configures multiplexer layer 306(2) to provide the value of instruction 1 output from stage 1 to the first opcode specific block 304(3) in stage 2, and configures multiplexer layer 306(2) to provide the value of instruction 2 output from stage 1 to the second opcode specific block 304(4) in stage 2. The blocks in stage 2 process these values ​​and output the results to multiplexer layer 306(3). The control unit 310 configures the multiplexer layer 306(3) to provide the output of the shared function block 308 of the second level to the opcode specific block 304(5) of the third level, to provide the output of instruction 4 to the shared function block 308 of the third level, and to provide the output of the opcode specific block 304 of the second level to the control unit 310. The shared function block 308 of the third level and the opcode specific block 304 output the results to the multiplexer layer 306(4). The control unit configures the multiplexer layer 306(4) to output the result of instruction 4 to the opcode specific block 304(7) in the fourth level. After the fourth level, the control unit 310 causes the results of all four instructions of the second type to be output in the same cycle. Because the merge data path unit 139 is pipelined, the results of up to four instructions of the second type can be output per cycle. Of course, the instruction type can also be different in different cycles, so that the results of one instruction of the first type or four instructions of the second type are output from the merge data path unit 139 per cycle.

[0036] It should be understood that in any given cycle, any particular stage may be operating on one type of instruction, while different stages are operating on different types of instructions. It should be understood that although specific details of the merged datapath unit 139 are shown, such as the number and interconnectivity of functional blocks, many variations in such details are possible and fall within the scope of the present disclosure.

[0037] An exemplary implementation of the merged data path unit is now described with respect to ray tracing operations. Typically, ray tracing renders an image by casting a ray from a camera point through an image plane, determining whether the ray hits an object, and if so, shading a pixel in the image plane based on the hit (or miss). The determination of whether a ray hits an object is referred to herein as a "ray intersection test."

[0038] Ray intersection testing involves sending a ray from the origin and determining whether the ray hits a triangle, and if so, determining the distance from the origin at which the triangle is hit. For efficiency, ray tracing tests use a spatial representation, called a bounding box hierarchy. In the bounding box hierarchy, each non-leaf node represents an axis-aligned bounding box that defines the geometry of all of the node's child nodes. In one example, the base node represents the maximum extent of the entire area for which the ray intersection test is being performed. In this example, the base node has two child nodes, each of which represents a mutually exclusive axis-aligned bounding box that subdivides the entire area. Each of the two child nodes has two child nodes that represent axis-aligned bounding boxes that subdivide the space of its parent node, and so on. Leaf nodes represent triangles that can be ray traced.

[0039] This data structure allows the number of ray-triangle intersections to be reduced (triangle intersections are complex and therefore expensive in terms of processing resources) compared to the case where the bounding box hierarchy data structure is not used and all triangles in the scene would therefore have to be tested against the ray. Specifically, if a ray does not intersect a particular bounding box, and that bounding box defines a large number of triangles, all triangles in that bounding box can be eliminated from the test. Thus, ray intersection testing is performed as a series of ray tests against axis-aligned bounding boxes and then against triangles.

[0040] Figure 4 An example of a merged datapath unit 400 that implements both a ray box test and a ray triangle test is shown. This particular merged datapath unit 400 is capable of outputting the results of four box tests per cycle or one triangle test per cycle. The merged datapath unit 400 parallelizes and serializes the operations of the box test to achieve this box test rate. Each stage is shown as having multiple functional blocks. Most of the functional blocks are adders (indicated by a plus sign "+") that add two scalar values ​​or multipliers (indicated by an "x") that multiply two scalar values. Both the triangle datapath 402(1) and the box datapath 402(2) use most of the multipliers and adders. In addition, opcode specific blocks are shown. These opcode specific blocks include a box min / max unit and a triangle comparison unit.

[0041] The merged data path unit 400 is divided into multiple stages, each of which performs a specific function for one or both of the ray box test and the ray triangle test. The first stage includes twelve adders. As shown in the figure, twelve of these adders are used for two box tests, and nine adders are used for one triangle test.

[0042] When the calculations of stage 0 are completed for either the box test or the triangle test, the results are provided to multiplexer layer 406(0). Control unit 410 configures multiplexer layer 406(0) to provide these results to the multipliers of stage 1 for further operations.

[0043] At level 1, twelve multipliers are used for two box tests or one triangle test. The results are output to the multiplexer layer 406 (1), and the control unit 410 configures the results to be forwarded to the next level according to the instruction being executed. Levels 2 and 3 include six adders and six multipliers, respectively. The six adders and multipliers are used for one box test or one triangle test. Box min / max units are also shown between levels 2 and 3. These units are operation specific units, each of which is used by one box test. After level 3, the results of the two box tests are completed and stored in the control unit 410. At levels 2 and 3, for the third box test, the results from the adders and multipliers are provided to the box min / max units of levels 4 and 5.

[0044] The 4th level and the 5th level include six adders and six multipliers, respectively. The six adders and multipliers are used for a triangle test or a box test (fourth box test). The 6th level and the 7th level each include two adders, and the two adders are used for a triangle test. The box min / max unit is used for the fourth box test. In each cycle, the merged data path unit 400 outputs the results of the four box tests (wherein the results of the three box tests are stored in the control unit 910, and wherein the results of the one box test come from the box min / max units of the 6th level and the 7th level) or the result of the one triangle test (the result comes from the 7th level).

[0045] Figure 51 is a flow chart of a method 500 for processing data via a merged data path unit 139 according to an example. At step 502, the control unit 310 of the merged data path unit 139 sets the configuration of multiplexers for each stage based on the sub-operations to be performed at each stage of the merged data path unit 139. As described elsewhere herein, the merged data path unit 139 is pipelined. Such a pipeline means that different instructions perform different sub-operations at different stages. The merged data path unit 139 is "merged" in the sense that different stages can be configured in different ways to perform sub-operations of different types of instructions. The sub-operations of a stage are defined at least by feeding data from a previous stage (or input) into a specific functional block of the stage. For example, for one instruction type, the output of a specific functional block from a previous stage can be fed to a first functional block of a subsequent functional stage, while for a different instruction type, the output of a specific functional block from a previous stage can be fed to a second functional block of a subsequent functional stage. Values ​​from the functional blocks can also be output to a sideband storage device controlled by the control unit 310, and / or values ​​can be read from the sideband storage device into the functional blocks. Whether this happens, which values ​​are read into and out of the sideband storage, and into and from which functional blocks these values ​​are read depends on the instruction type. The control unit 310 therefore controls the multiplexer layer to move data between stages based on the instruction type.

[0046] At step 504, the control unit 310 sets the configuration of the functional blocks for the stage based on the sub-operations to be performed by each stage. This step is considered "optional" because some embodiments of the merge datapath unit 139 perform this step while other embodiments do not. In embodiments that perform this step, at least some of the functional blocks can change the operations they perform. For example, instead of the functional block being an adder or a multiplier, it can be switched between the functional block being an adder and the functional block being a multiplier. In such embodiments, the control unit 310 controls which functional blocks perform which operations based on the type of instructions executed in a particular cycle at the stage.

[0047] At step 506, the control unit 310 configures a multiplexer to store data in a sideband storage device of the control unit 310 for instruction types that use this functionality. Specifically, for some instruction types, some data is stored in the sideband to be processed in a level that is not the next level in which the data is generated. In one example, this feature is used to facilitate the output of multiple instructions per cycle by serializing the data processing through the data path. In one example, an instruction is processed in the first two levels, and the result of the instruction is then stored in the sideband memory. Then, the data of the second instruction is obtained from the sideband memory and provided to the next two levels. Finally, the output of the two instructions is provided in the same cycle. At step 508, the control unit configures a multiplexer to forward data from the sideband storage device of the control unit 310 to the functional unit of the level for reading from the sideband storage device. Steps 506 and 508 are optional because not all embodiments of the merged data path 139 use the sideband storage feature. At step 510, each stage performs an operation using the data provided by the previous multiplexer layer, and if the embodiment performs step 504 to change the operation performed by the functional block, each stage performs the operation configured by the control unit. After step 510, the method 500 returns to step 1002 to perform the operation of the next cycle. For steps 502 to 508, the specific manner in which the control unit 310 configures the multiplexer layer and / or the functional block is based on the instruction type at a particular cycle. At any particular cycle, different stages can be configured to execute instructions of different instruction types. It should be noted that the method can be used to perform operations related to Figure 4 Describes the operation.

[0048] It should be understood that, based on the disclosure of this article, many variations are possible. In one example, any level can be configured to execute different instruction types in the same cycle. In one example, in any specific level, a functional unit in the level can be configured to process data of a first instruction type in a specific cycle, and different functional units in the same level are configured to process data of a second different instruction type in the same specific cycle. As described above, any level can be configured to process different instruction types in the same cycle. Although the features and elements are described above in a specific combination, each feature or element can be used alone without other features and elements, or with various combinations with or without other features and elements.

[0049] The provided methods can be implemented in a general purpose computer, a processor, or a processor core. Suitable processors include, for example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine. Such processors can be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data (including netlists) (such instructions can be stored on a computer readable medium). The result of such processing can be a mask work, which is then used in a semiconductor manufacturing process to manufacture a processor that implements various aspects of the embodiments.

[0050] The methods or flow charts provided herein can be implemented in a computer program, software or firmware incorporated into a non-transitory computer-readable storage medium so as to be executed by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

[0051] ***

Claims

1. A merged data path circuit for executing at least two different types of instructions, the merged data path circuit comprising: a plurality of stages, the plurality of stages including a first stage and a second stage, each stage including one or more functional units, at least one of the functional units being a shared functional unit that performs operations on more than one of the one or more instruction types; and a plurality of multiplexers disposed between the stages of the plurality of stages, wherein, in a first cycle, the first functional unit of the first level is configured to execute a first instruction of a first instruction type; wherein, in a second cycle following the first cycle, the plurality of stages and the multiplexer are configured to perform operations comprising: executing the first instruction in a first functional unit of the second stage, the executing comprising selecting data generated in the first cycle from the first functional unit of the first stage as input to the first functional unit of the second stage via the plurality of multiplexers, and executing a second instruction of a second instruction type in a second functional unit of the first stage; and wherein, in a third cycle after the second cycle, the plurality of stages and the multiplexer are configured to perform operations including: The second instruction is executed in the first functional unit of the second stage, the execution comprising selecting data generated in the second cycle from the second functional unit of the first stage as input to the first functional unit of the second stage through the plurality of multiplexers.

2. The merged data path circuit of claim 1 , wherein the one or more functional units include at least one opcode-specific block that is used by one instruction type of the at least two different types of instructions but not another instruction type of the at least two different types of instructions. 3 . The merged datapath circuit of claim 1 , wherein at least one of the plurality of stages is configured to process multiple instances of an instruction type of the one or more instruction types in parallel in a single cycle. 4 . The merged datapath circuit of claim 1 , wherein the plurality of stages are configured to execute multiple instances of an instruction type of the one or more instruction types via serializing operation of the multiple instances through the plurality of stages.

5. The merged data path circuit of claim 1 , further comprising a control unit configured to configure the plurality of multiplexers to route the data for the different functional units of the plurality of stages based on the type of instruction executed at the stage. 6 . The merged data path circuit of claim 5 , wherein the control unit is further configured to store data from at least one stage for use in a next stage. 7 . The merged data path circuit of claim 1 , wherein at least one of the one or more functional units comprises a functional unit that spans multiple stages.

8. The merged data path circuit of claim 1, wherein at least one of the one or more functional units receives an input from an input timing element and outputs a value to an output timing element, and there is no timing element between the input timing element and the output timing element.

9. The merge data path circuit of claim 1, wherein the two different types of instructions include ray-triangle intersection test and ray-box intersection test.

10. A method for operating a merged datapath circuit for executing at least two different types of instructions, the merged datapath circuit comprising: a plurality of stages, the plurality of stages including a first stage and a second stage, each stage including one or more functional units, at least one of the functional units being a shared functional unit that performs operations on more than one instruction type; and a plurality of multiplexers disposed between the stages in the plurality of stages, the method comprising: configuring the plurality of stages to execute instructions of one or more instruction types by controlling the plurality of multiplexers to route data between functional units of the stages based on the instruction types executed at the plurality of stages; as well as configuring the plurality of stages such that in at least one cycle, a first stage of the plurality of stages is configured for a first instruction type and a second stage of the plurality of stages is configured for a second instruction type, In a first cycle, configuring a first functional unit of the first stage to execute a first instruction of a first type; In a second loop after the first loop, performing operations including: executing the first instruction in a first functional unit of the second stage, the executing comprising selecting data generated in the first cycle from the first functional unit of the first stage as input to the first functional unit of the second stage via the plurality of multiplexers, and executing a second instruction of a second instruction type in a second functional unit of the first stage; and In a third loop after the second loop, operations including the following are performed: The second instruction is executed in the first functional unit of the second stage, the execution comprising selecting data generated in the second cycle from the second functional unit of the first stage as input to the first functional unit of the second stage through the plurality of multiplexers.

11. The method of claim 10, wherein the one or more functional units include at least one opcode-specific block, the at least one opcode-specific block being used by one instruction type of the at least two different types of instructions but not another instruction type of the at least two different types of instructions.

12. The method according to claim 10, further comprising: Multiple instances of an instruction type of the one or more instruction types are processed in parallel in a single cycle by at least one stage of the plurality of stages.

13. The method according to claim 10, further comprising: Multiple instances of an instruction type of the one or more instruction types are executed through the multiple stages via serializing operation of the multiple instances through the multiple stages.

14. The method according to claim 10, further comprising: Data from at least one stage is stored for use by a control unit in a next stage.

15. The method of claim 10, wherein at least one of the one or more functional units comprises a functional unit that spans multiple stages.

16. The method according to claim 10, further comprising: receiving input from an input timing element via at least one of the one or more functional units; as well as The value is output to an output timing element by the at least one of the one or more functional units.

17. The method according to claim 10, further comprising: Data is output through the multiple stages to a single instruction multiple data unit for graphics processing.

18. The method of claim 10, wherein the two different types of instructions include ray-triangle intersection testing and ray-box intersection testing.

19. An accelerated processing device, comprising: Processing unit; and A merged data path circuit for executing at least two different types of instructions according to a request of the processing unit, the merged data path circuit comprising: a plurality of stages, the plurality of stages including a first stage and a second stage, each stage including one or more functional units, at least one of the functional units being a shared functional unit that performs operations on more than one instruction type; and a plurality of multiplexers disposed between the stages of the plurality of stages, wherein, in a first cycle, the first functional unit of the first level is configured to execute a first instruction of a first instruction type; wherein, in a second cycle following the first cycle, the plurality of stages and the multiplexer are configured to perform operations comprising: executing the first instruction in a first functional unit of the second stage, the executing comprising selecting data generated in the first cycle from the first functional unit of the first stage as input to the first functional unit of the second stage via the plurality of multiplexers, and executing a second instruction of a second instruction type in a second functional unit of the first stage; and wherein, in a third cycle after the second cycle, the plurality of stages and the multiplexer are configured to perform operations including: The second instruction is executed in the first functional unit of the second stage, the execution comprising selecting data generated in the second cycle from the second functional unit of the first stage as input to the first functional unit of the second stage through the plurality of multiplexers.

20. An accelerated processing device according to claim 19, wherein the one or more functional units include at least one opcode-specific block, and the at least one opcode-specific block is used by one instruction type of the at least two different types of instructions but not another instruction type of the at least two different types of instructions.

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