Thin film transistors and related manufacturing technologies

Abstract

The present application relates to thin film transistors and related manufacturing techniques. The thin film transistors can access two or more memory cell levels arranged in a cross-point architecture. The manufacturing techniques can use one or more via patterns formed at the top layer of a composite stack, which can facilitate the construction of the thin film transistor within the composite stack while using a reduced number of processing steps. By utilizing different groups of the vias, the manufacturing techniques can be used to construct different configurations of the thin film transistor. In addition, the thin film transistors described herein and the related via-based manufacturing techniques can be used to construct circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays).

Description

[0001] Cross Reference

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 064599, filed by Castro et al. on December 5, 2019, entitled “THIN FILM TRANSISTORS AND RELATED FABRICATION TECHNIQUES,” which claims priority to U.S. Patent Application No. 16 / 223,595, filed by Castro et al. on December 18, 2018, entitled “THIN FILMTRANSISTORS AND RELATED FABRICATION TECHNIQUES,” each of which is assigned to the assignee of this patent application and each of which is expressly incorporated herein by reference in its entirety. Background Art

[0003] The following relates generally to forming memory arrays, and more specifically, to thin film transistors and related fabrication techniques.

[0004] Memory devices are widely used to store information in a variety of electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by a logical "1" or a logical "0". In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read or sense the stored state in the memory device. To store information, a component of the electronic device may write or program a state into the memory device.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash, phase change memory (PCM), and others. Memory devices may include volatile memory cells or non-volatile memory cells. Non-volatile memory cells can retain their stored logic state for a long time, even without external power. Volatile memory cells lose their stored state over time unless they are periodically refreshed by an external power source.

[0006] Improvements to memory devices may generally include increased memory cell density, increased read / write speeds, increased reliability, enhanced data retention, reduced power consumption, or reduced manufacturing costs, among other criteria. It may be desirable to build more memory cells per unit area to increase memory cell density and reduce cost per bit without increasing the size of the memory device. Improved techniques (e.g., faster, lower cost) for manufacturing memory devices, including memory devices with increased memory cell density or other beneficial features, may also be desirable. Summary of the invention

[0007] A method is described. The method may include: forming a first plurality of vias and a second plurality of vias through a top layer of a stack including a first layer, a second layer, and a third layer; using the first plurality of vias to form a gate electrode of a transistor, the gate electrode being located at the second layer; using the second plurality of vias to form a second electrode of the transistor, the second electrode being located at the first layer; and using a via common to the first plurality of vias and the second plurality of vias to form a third electrode of the transistor, the third electrode extending through at least the third layer.

[0008] An apparatus is described. The apparatus may include: a conductive plug extending through a stack including a first layer, a second layer, and a third layer; a semiconductor material located at the first layer and the second layer, the semiconductor material surrounding the conductive plug; an oxide material located at the second layer and in contact with the semiconductor material; and a gate electrode located at the second layer and in contact with the oxide material.

[0009] Another method is described. The method may include: forming a first via, a second via, and a third via through a top layer of a stack including a first layer and a second layer; using the first via to form a gate electrode of a transistor; using the second via to form a second electrode of the transistor, the second electrode extending through the first layer and the second layer; and using at least the first via and the third via to form a third electrode of the transistor.

[0010] Another apparatus is described. The apparatus may include: a dielectric plug extending through a stack including a first layer and a second layer; a semiconductor material at the first layer, the semiconductor material surrounding the dielectric plug; a gate electrode at the second layer, the gate electrode surrounding the dielectric plug; and an oxide material between the semiconductor material and the gate electrode.

[0011] Another method is described. The method may include: forming a first plurality of vias, a second plurality of vias, and a third via through a top layer of a stack including a first layer, a second layer, and a third layer; using the first plurality of vias to form a gate electrode of a transistor, the gate electrode being located at the second layer; using the second plurality of vias to form a second electrode of the transistor, the second electrode being located at the first layer; using the third via to form a third electrode of the transistor, the third electrode extending at least through the third layer.

[0012] Another apparatus is described. The apparatus may include: a conductive plug extending through a stack including a first layer, a second layer, and a third layer; a gate electrode located at the second layer; a second electrode located at the first layer; and a semiconductor material located at the first layer and the second layer, the semiconductor material coupled to the second electrode via a first segment of the ohmic material at the first layer and coupled to the conductive plug via a second segment of the ohmic material at the third layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An example memory device including a three-dimensional array of memory cells supporting thin film transistors and related fabrication techniques according to an embodiment of the present disclosure is described.

[0014] Figure 2 An example of a three-dimensional memory array supporting thin film transistors and related manufacturing techniques according to an embodiment of the present disclosure is described.

[0015] Figures 3A to 3L Exemplary manufacturing techniques supporting thin film transistors and related manufacturing techniques according to embodiments of the present disclosure are described.

[0016] Figures 4A to 4AA Exemplary manufacturing techniques supporting thin film transistors and related manufacturing techniques according to embodiments of the present disclosure are described.

[0017] Figures 5A to 5N Exemplary manufacturing techniques supporting thin film transistors and related manufacturing techniques according to embodiments of the present disclosure are described.

[0018] Figures 6A to 6R Exemplary manufacturing techniques supporting thin film transistors and related manufacturing techniques according to embodiments of the present disclosure are described.

[0019] Figures 7A to 7D Diagram illustrating an exemplary memory array including an active array region and a socket region supporting thin film transistors and related manufacturing techniques according to an embodiment of the present disclosure.

[0020] Figures 8A to 8CDiagram illustrating an exemplary socket area and decoding scheme to support thin film transistor and related manufacturing techniques according to an embodiment of the present disclosure.

[0021] Fig. 9 Diagram illustrating an exemplary decoding scheme supporting thin film transistor and related manufacturing techniques according to an embodiment of the present disclosure.

[0022] Fig. 10A and 10B Diagram illustrating exemplary crossover regions supporting thin film transistors and related manufacturing techniques according to embodiments of the present disclosure.

[0023] Fig.11 Diagrams illustrating exemplary memory devices supporting thin film transistors and related fabrication techniques according to embodiments of the present disclosure.

[0024] Figures 12 to 14 A method of supporting a thin film transistor and related manufacturing techniques according to an embodiment of the present disclosure is described.

[0025] Fig.15 and 16 A method of supporting a thin film transistor and related manufacturing techniques according to an embodiment of the present disclosure is described. DETAILED DESCRIPTION

[0026] Constructing more memory cells per unit area can increase the areal density of memory cells within a memory device. The increased areal density of memory cells can promote a lower per-bit cost and / or a larger memory capacity at a fixed cost for the memory device. The three-dimensional (3D) integration of two or more two-dimensional (2D) memory cell arrays can increase the areal density while also alleviating the difficulties associated with shrinking the various feature sizes of the memory cells. In some cases, a 2D memory cell array can be referred to as a memory cell level. In some cases, a memory device including multiple memory cell levels can be referred to as a 3D memory device. Each memory cell level of a 3D memory device can be selected (e.g., activated) or inhibited (e.g., deactivated, not selected) by a circuit system, which can be configured to determine which level is selected and to perform access operations for one or more memory cells of the selected level. In some cases, the circuit system can include complementary metal oxide semiconductor (CMOS) transistors formed in or on a substrate, and the 3D integration level of the memory cell can be positioned above the CMOS circuit system (e.g., fabricated on top of the CMOS circuit system). In some cases, the level of memory cells and associated components positioned above the substrate may be included in a set of layers (which may be collectively referred to as array layers).

[0027] The CMOS circuitry may determine a particular level of the 3D memory device to be selected based on an access command from a host device, such as by decoding addresses of memory cells associated with the access command and included in the particular level. In some implementations, as the number of levels in a 3D memory device increases (e.g., 4 levels, 8 levels, 16 levels, 32 levels) to increase areal density, the CMOS circuitry may increase in size to support decoding (e.g., determining which level to select from the increased levels) and driving the additional levels (e.g., providing sufficient current to access the memory cells of the selected level). This increase in the size of the CMOS circuitry (e.g., increasing the substrate area occupied by the CMOS circuitry) may offset the benefits otherwise associated with the 3D integration of two or more 2D memory cell arrays.

[0028] The manufacturing techniques, methods, and related devices described herein can facilitate the construction of thin film transistors (TFTs) that can be positioned within a layer of a 3D memory device (e.g., within an array layer that collectively includes two or more memory cell layers). In some cases, multiple groups of TFTs can be fabricated simultaneously within an array layer (e.g., two or more array layers that each include a group of TFTs). The TFTs positioned within the array layer can be configured to select (e.g., activate) or inhibit (e.g., deactivate) the corresponding memory cell layer. In some cases, the TFTs can be part of a memory layer decoder (which can also be referred to as a memory layer selector) that can be coupled to a CMOS circuit system in a substrate. Thus, the TFTs can be coupled to the CMOS circuit system to facilitate the CMOS circuit system to perform its functions (e.g., determine a specific layer of multiple layers of 3D integration to be selected and drive current to access memory cells of a specific layer). In this way, the TFTs positioned in the array layer can facilitate accommodating additional memory cell layers of a 3D memory device while mitigating the effects associated with the substrate area occupied by the CMOS circuit system. For example, in some cases, the CMOS circuit system can support one or more additional memory cell layers in conjunction with TFTs while occupying approximately the same area. In some cases, TFTs positioned in the array layer can mitigate the effects of various array parasitic components, such as leakage currents, parasitic capacitances.

[0029] In some cases, the TFTs may be configured to perform additional functions (e.g., functions other than selecting or inhibiting a level of memory cells, such as a full decoding function) so that the area of ​​the CMOS circuitry below the array layer may be reduced, such as by delegating at least some aspects of its decoding functions to a TFT located in the array layer. Additionally, because the TFTs may provide individual levels isolated from the rest of the levels (e.g., the TFTs may select individual levels while inhibiting the rest of the levels) current requirements (e.g., drive current requirements) during access operations may be relaxed. Relaxing current requirements may have several benefits associated with CMOS circuitry over alternative approaches, where the CMOS circuitry may be configured to provide current to multiple levels during access operations. For example, relaxing current requirements may facilitate the CMOS circuitry to occupy a smaller area, use (have) a simpler circuit configuration, or provide one or more additional functions without increasing the occupied area.

[0030] The fabrication techniques, methods, and related devices described herein may be based on techniques, methods, and related devices that use via (e.g., access via) patterns to facilitate simultaneous construction of multiple memory cell levels and associated array electrodes (e.g., a set of array layers and associated array electrodes that each include a memory cell level), as described elsewhere. That is, aspects of constructing multiple memory cell levels and associated array electrodes are described in U.S. Patent Application No. 15 / 961,540 to Castro et al., entitled “Cross-Point Memory Arrays and Related Fabrication Techniques,” U.S. Patent Application No. 15 / 961,547 to Castro et al., entitled “Cross-Point Memory Arrays and Related Fabrication Techniques,” and U.S. Patent Application No. 15 / 961,550 to Castro et al., entitled “Buried Lines and Related Fabrication Techniques,” each of which is expressly incorporated herein by reference in its entirety. A via may be formed at the top layer of a composite stack that may be used to construct multiple memory cell levels and array electrodes in an area and TFTs in a different area. As used herein, a via may refer to an opening or an opening that may be used to form associated via holes and other structures beneath a material (layer, surface) that includes the opening, including an opening that is later filled with a material that includes a material that may not be conductive.

[0031] Thus, the manufacturing techniques, methods, and related apparatus described herein can facilitate a flexible sequence of constructing TFTs relative to constructing multiple memory cell levels and array electrodes. This flexibility can provide for optimizing process steps to mitigate various undesirable factors associated with various processing conditions, such as thermal effects on memory cells, cross-contamination risks with materials used for memory cells (e.g., chalcogenide materials), and the like. As an example, TFTs can be formed prior to constructing memory cells to reduce the thermal budget for maintaining the memory cells (e.g., the sum of durations of processing steps at various temperatures). In some cases, the manufacturing techniques, methods, and related apparatus described herein can provide for reducing the cost of manufacturing 3D memory devices because the same composite stack of materials can be used to construct TFTs and to construct multiple memory cell levels and array electrodes.

[0032] The manufacturing techniques, methods, and related devices described herein may support selection (or suppression) of memory cell levels disposed in a cross-point architecture. For example, each memory cell level in the cross-point architecture may include a set of first access lines (e.g., word lines, first array electrodes) in a first plane and a set of second access lines (e.g., bit lines, second array electrodes) in a second plane, the first access lines and the second access lines extending in different directions, for example, the first access lines may be substantially perpendicular to the second access lines. Each topological intersection of the first access lines and the second access lines may correspond to a memory cell. Thus, a memory cell level in the cross-point architecture may include a memory array having a set of memory cells placed at a topological intersection of the access lines (e.g., a 3D grid structure of the access lines). As described herein, a TFT (e.g., a memory level selector / suppressor) may be constructed in an array layer including multiple memory cell levels and array electrodes. Thus, the TFT may be coupled to the access lines (e.g., word lines, bit lines, first array electrodes, second array electrodes) and thus support selection (and access) of multiple memory cell levels disposed in the cross-point architecture.

[0033] In addition, the TFT may support various cross-point architectures, such as a stuffing architecture or derivatives thereof. A stuffing architecture in the context of a memory device may refer to a memory cell array comprising a set of memory tiles, each of which comprises a similar configuration of components (e.g., word line decoders, bit line decoders, sensing components, subsets of the memory cell array) arranged similarly to the patch blocks in a patch. Memory tiles may be viewed as building blocks (e.g., modular building blocks) of a memory cell array of a memory device employing a stuffing architecture. In this way, the memory cell array of a memory device may be expanded or contracted by increasing or decreasing the number of memory tiles. In other words, a cross-point architecture may refer to a memory array comprising a topological intersection of a first access line and a second access line, wherein each topological intersection corresponds to a memory cell, and a stuffing architecture may refer to constructing an array by arranging a set of memory tiles that each form a subset of the memory cell array.

[0034] The configuration of the TFT may be varied (e.g., the associated geometry and structure may be varied) to meet various constraints or requirements. In some cases, the relevant constraints and requirements of the TFT may be based on the selection function and the inhibition (e.g., deselection) function provided by one or more TFTs. For example, the TFT may be configured to provide a specific current drive capability (e.g., selection function) when activated. Additionally or alternatively, the TFT may be configured to maintain an acceptably low leakage current (e.g., inhibition function) when deactivated. In some cases, multiple (e.g., two) groups of TFTs may be constructed for each array electrode within the memory cell level. For example, one group of TFTs may be configured to actively drive the array electrodes of the memory cell level (e.g., provide the desired or required drive current) when the memory cell level is selected. Additionally or alternatively, another group of TFTs may be configured to drive an inhibition level (e.g., maintain a low leakage current) when the memory cell level is inhibited (e.g., not accessed, deselected). In some cases, multiple groups of TFTs present in a single device may be processed differently from one another to optimize for current drive capabilities and voltage ranges that the multiple groups of TFTs can collectively support (e.g., one group of TFTs may be optimized for drive current capability, while another group of TFTs may be optimized for low leakage current capability).

[0035] In some cases, a control gate (e.g., a gate electrode) of a TFT may be formed in the same layer in which a memory element (e.g., an element that may be configured to store information, such as a chalcogenide element) is formed. The control gate of the TFT may determine a path for current to flow within the TFT between a first electrode (e.g., a drain) of the TFT and a second electrode (e.g., a source) of the TFT. In some cases, the path for current flow may be vertical, horizontal, or a combination of both, based on how the channel of the TFT is formed relative to the gate electrode, first electrode, and second electrode of the TFT. In some cases, the channel of the TFT may be coupled to a bulk connection of a node of an underlying CMOS circuitry to control electrical characteristics of the channel that may be different based on various functions that the TFT may perform (e.g., a selection function, an inhibition function, or other functions).

[0036] Furthermore, the fabrication techniques, methods, and related devices described herein may facilitate the construction of one or more composite circuits, such as circuits including various combinations of TFTs within a layer of an array layer, such as TFT-based decoder cells. For example, a TFT-based decoder cell may perform cluster-level decoding to activate (or deactivate) a particular tile within a tile cluster. Additionally or alternatively, another TFT-based decoder cell may perform tile-level decoding to activate a particular access line from a set of access lines included in a tile. The fabrication techniques and methods described herein may also be used to construct a crossover region, where a first set of electrodes of a first TFT group may cross over a second set of electrodes of a second TFT group without causing a short between the first set of electrodes and the second set of electrodes.

[0037] The features of the present disclosure introduced above are further described herein in the context of various TFT structures and TFT-based circuits in composite stacks of construction materials (which can also be used to construct memory arrays in cross-point architectures). Next, specific examples of structures and techniques for fabricating TFT structures and TFT-based circuits are described. These and other features of the present disclosure are further illustrated and described with reference to equipment diagrams, formation method diagrams, and flow diagrams related to TFTs and related fabrication techniques.

[0038] Figure 1 An example memory device 100 including a three-dimensional array of memory cells supporting thin film transistors and related fabrication techniques according to an embodiment of the present disclosure is illustrated. The memory device 100 may also be referred to as an electronic memory apparatus. Figure 1 is an illustrative diagram of various components and features of memory device 100. Thus, it should be understood that the components and features of memory device 100 are shown to illustrate functional interrelationships rather than their actual physical locations within memory device 100.

[0039] exist Figure 1In the illustrative example of , memory device 100 includes a three-dimensional (3D) memory array 102. 3D memory array 102 includes memory cells 105 that are programmable to store different states. In some embodiments, each memory cell 105 is programmable to store two states represented as logic 0 and logic 1. In some embodiments, memory cell 105 can be configured to store more than two logic states (e.g., multi-level cells). In some embodiments, memory cell 105 can include self-select memory cells. It should be understood that memory cell 105 can also include another type of memory cell, such as 3D XPoint TM A memory cell, a PCM cell, a bridge RAM (CBRAM) cell or a FeRAM cell comprising a storage element and a selection element. Figure 1 Some of the elements included therein are labeled with numerical indicators, while other corresponding elements are not labeled but are the same or should be understood to be similar in an attempt to improve visibility and clarity of the depicted features.

[0040] The 3D memory array 102 may include two or more two-dimensional (2D) memory arrays (e.g., array layers including two or more memory cell levels and array electrodes) stacked one on top of the other. This may increase the number of memory cells that may be placed or produced on a single die or substrate compared to a single 2D array, which in turn may reduce production costs or increase performance of the memory device, or both. Figure 1 In the depicted example, memory array 102 includes two levels of memory cells 105 (e.g., memory cell 105-a and memory cell 105-b) and thus may be considered a 3D memory array; however, the number of levels may not be limited to 2, and other examples may include additional levels (e.g., 4 levels, 8 levels, 16 levels, 32 levels). Each level may be aligned or positioned so that memory cells 105 may be aligned (completely, overlapping, or approximately) with each other across each level to thereby form a memory cell stack 145. In some cases, the memory cell levels may be referred to as memory cell planes.

[0041] In some embodiments, each row of memory cells 105 is connected to a word line 110, and each column of memory cells 105 is connected to a bit line 115. Both word lines 110 and bit lines 115 may also be collectively referred to as access lines. Furthermore, an access line may serve as a word line 110 for one or more memory cells 105 at a level of the memory device 100 (e.g., memory cells 105 below the access line) and a bit line 115 for one or more memory cells 105 at another level of the memory device (e.g., memory cells 105 above the access line). Thus, references to word lines and bit lines, or the like, may be interchanged without loss of understanding or operation. Word lines 110 and bit lines 115 may be substantially perpendicular to each other and may support an array of memory cells.

[0042] One memory cell 105 may generally be located at the intersection of two access lines, such as a word line 110 and a bit line 115. This intersection may be referred to as the address of the memory cell 105. A target memory cell 105 may be a memory cell 105 located at the intersection of a powered (e.g., activated) word line 110 and a powered (e.g., activated) bit line 115; that is, both the word line 110 and the bit line 115 may be powered to read or write to the memory cell 105 at their intersection. Other memory cells 105 that are in electronic communication with (e.g., connected to) the same word line 110 or bit line 115 may be referred to as non-target memory cells 105.

[0043] like Figure 1 , two memory cells 105 in a memory cell stack 145 may share a common conductive line, such as a bit line 115. That is, the bit line 115 may be coupled with an upper memory cell 105-b and a lower memory cell 105-a. Other configurations may be possible, for example, a third layer (not shown) may share a word line 110 with an upper memory cell 105-b.

[0044] In some cases, an electrode may couple the memory cell 105 to a word line 110 or a bit line 115. The term electrode may refer to an electrical conductor and may include a trace, a wire, a conductive line, a conductive layer, or the like that provides a conductive path between elements or components of the memory device 100. Thus, the term electrode may refer in some cases to an access line (e.g., a word line 110 or a bit line 115) and in some cases to an additional conductive element that serves as an electrical contact between the access line and the memory cell 105. In some embodiments, the memory cell 105 may include a chalcogenide material positioned between a first electrode and a second electrode. The first electrode may couple the chalcogenide material to the word line 110, and the second electrode couples the chalcogenide material to the bit line 115. The first electrode and the second electrode may be the same material (e.g., carbon) or different materials. In other embodiments, the memory cell 105 may be directly coupled to one or more access lines, and electrodes other than the access lines may be omitted.

[0045] Operations such as reading and writing can be performed on the memory cell 105 by activating or selecting the word line 110 and the digit line 115. Activating or selecting the word line 110 or the digit line 115 can include applying a voltage to the corresponding line. The word line 110 and the digit line 115 can be made of a conductive material, such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, a conductive doped semiconductor or other conductive material, alloy, compound, or the like.

[0046] In some architectures, the logic storage device of the cell (e.g., a resistive component in a CBRAM cell, a capacitive component in a FeRAM cell) can be electrically isolated from the digital line by a selection component. The word line 110 can be connected to the selection component and can control the selection component. For example, the selection component can be a transistor and the word line 110 can be connected to the gate of the transistor. Alternatively, the selection component can be a variable resistance component, which can include a chalcogenide material. Activating the word line 110 results in an electrical connection or closed circuit between the logic storage device of the memory cell 105 and its corresponding digital line 115. The digital line can then be accessed to read or write the memory cell 105. After selecting the memory cell 105, the resulting signal can be used to determine the stored logic state. In some cases, the first logic state can correspond to no current or a weak current through the memory cell 105, while the second logic state can correspond to a limited current.

[0047] In some cases, memory cell 105 may include a self-select memory cell having two terminals, and a separate selection component may be omitted. Thus, one terminal of the self-select memory cell may be electrically connected to word line 110 and the other terminal of the self-select memory cell may be electrically connected to digit line 115.

[0048] Access to the memory cells 105 may be controlled by a row decoder 120 and a column decoder 130. For example, the row decoder 120 may receive a row address from the memory controller 140 and activate the appropriate word line 110 based on the received row address. In some cases, the row decoder 120 may include multiple sets of TFTs for selecting a particular level of the 3D memory array 102. For example, the row decoder 120 may include a first set of TFTs associated with a lower level (e.g., a memory level including the memory cells 105-a) to select the lower level and a second set of TFTs associated with an upper level (e.g., a memory level including the memory cells 105-b) to inhibit (e.g., deselect) the upper level. In some cases, the TFTs may be co-located in an array layer including the 3D memory array 102. In some cases, the TFTs located in the array layer may be coupled to the row decoder 120, which may be located in a substrate above which the 3D memory array 102 is located. Similarly, the column decoder 130 may receive a column address from the memory controller 140 and activate the appropriate digital line 115. In some cases, similar to the row decoder 120, the column decoder 130 may include additional sets of TFTs for selecting specific levels of the 3D memory array 102. For example, the memory array 102 may include a plurality of word lines 110 labeled WL_1 to WL_M and a plurality of digit lines 115 labeled DL_1 to DL_N, where M and N depend on the array size. Thus, the memory cells 105 at their intersections may be accessed by activating the word lines 110 and digit lines 115 (e.g., WL_2 and DL_3).

[0049] After access, the memory cell 105 may be read or sensed by the sensing component 125 to determine the storage state of the memory cell 105. For example, a voltage may be applied to the memory cell 105 (using the corresponding word line 110 and bit line 115), and the presence of a resulting current through the memory cell 105 may depend on the applied voltage and the threshold voltage of the memory cell 105. In some cases, more than one voltage may be applied. In addition, if the applied voltage does not cause current to flow, other voltages may be applied until current is detected by the sensing component 125. The storage logic state of the memory cell 105 may be determined by evaluating the voltage that causes current to flow. In some cases, the voltage may be ramped up in magnitude until current flow is detected. In other cases, predetermined voltages may be applied sequentially until current is detected. Likewise, a current may be applied to the memory cell 105 and the magnitude of the voltage that produces the current may depend on the resistance or threshold voltage of the memory cell 105.

[0050] In some cases, the memory cell 105 (e.g., a self-selected memory cell) may include a chalcogenide material. The chalcogenide material of the self-selected memory cell may remain in an amorphous state during the operation of the self-selected memory cell. In some cases, operating the self-selected memory cell may include applying programming pulses of various shapes to the self-selected memory cell to determine a specific threshold voltage of the self-selected memory cell, that is, the threshold voltage of the self-selected memory cell may be modified by changing the shape of the programming pulse, which may change the local composition of the chalcogenide in the amorphous state. The specific threshold voltage of the self-selected memory cell may be determined by applying read pulses of various shapes to the self-selected memory cell. For example, when the applied voltage of the read pulse exceeds the specific threshold voltage of the self-selected memory cell, a limited amount of current may flow through the self-selected memory cell. Similarly, when the applied voltage of the read pulse is less than the specific threshold voltage of the self-selected memory cell, no appreciable amount of current may flow through the self-selected memory cell.

[0051] In some embodiments, the sensing component 125 can read the information stored in the memory cell 105 by detecting the flow of current or no current through the selected memory cell 105. In this manner, the memory cell 105 (e.g., a self-selected memory cell) can store one bit of data based on the threshold voltage levels (e.g., two threshold voltage levels) associated with the chalcogenide material, where the threshold voltage levels when current flows through the memory cell 105 indicate the logic state stored by the memory cell 105. In some cases, the memory cell 105 can exhibit a particular number of different threshold voltage levels (e.g., three or more threshold voltage levels) to thereby store more than one bit of data.

[0052] The sensing component 125 may include various transistors or amplifiers to detect and amplify the signal difference associated with the sensed memory cell 105, which may be referred to as a latch. The detected logic state of the memory cell 105 may then be output as an output 135 by the column decoder 130. In some cases, the sensing component 125 may be part of the column decoder 130 or the row decoder 120. Alternatively, the sensing component 125 may be connected to or in electronic communication with the column decoder 130 or the row decoder 120. Figure 1 An alternative option of arranging the sense component 125-a (in a dashed box) is also shown.One of ordinary skill in the art will appreciate that the sense component 125 may be associated with either a column decoder or a row decoder without losing its functional purpose.

[0053] Memory cell 105 may be set or written by similarly activating associated word line 110 and digit line 115, and at least one logic value may be stored in memory cell 105. Column decoder 130 or row decoder 120 may accept data written to memory cell 105, such as input / output 135.

[0054] In some memory architectures, accessing the memory cell 105 degrades or destroys the stored logic state, and a rewrite or refresh operation may be performed to restore the memory cell 105 to the original logic state. For example, in a DRAM, a capacitor may be partially or fully discharged during a sensing operation to destroy the stored logic state, so the logic state may be rewritten after the sensing operation. Additionally, in some memory architectures, activating a single word line 110 causes all memory cells in a row (e.g., coupled to the word line 110) to discharge; therefore, some or all memory cells 105 in the row may need to be rewritten. However, in non-volatile memory (e.g., self-select memory, PCM, CBRAM, FeRAM, or NAND memory), accessing the memory cell 105 does not destroy the logic state, so the memory cell 105 may not need to be rewritten after access.

[0055] The memory controller 140 may control the operation (e.g., reading, writing, rewriting, refreshing, discharging) of the memory cell 105 through various components (e.g., row decoder 120, column decoder 130, and sensing component 125). In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 may generate row and column address signals to activate the desired word lines 110 and digit lines 115. The memory controller 140 may also generate and control various voltages or currents used during operation of the memory device 100. In general, the amplitude, shape, polarity, and / or duration of the applied voltages or currents discussed herein may be adjusted or varied and may differ for the various operations discussed in operating the memory device 100. Furthermore, one, multiple, or all memory cells 105 within memory array 102 may be accessed simultaneously; for example, multiple or all cells of memory array 102 may be accessed simultaneously during a reset operation in which all memory cells 105 or groups of memory cells 105 are set to a single logic state.

[0056] In some cases, the lower word line 110 ( Figure 1 WL_B1), upper word line 110 ( Figure 1 In addition, both the lower word line 110 and the upper word line 110 may be disposed (formed) in a layer initially comprising the same dielectric material, and a single via pattern may be used to simultaneously form one or more processing steps of the lower level word line 110 and the upper level word line 110 at their respective layers, such as removing portions of the dielectric material and replacing them with conductive material. Similarly, the lower memory cell 105 (e.g. Figure 1 The memory cell 105-a illustrated as a solid black circle in FIG. 1 may be connected to the upper memory cell 105 (eg Figure 1 105 - b) and any number of additional levels of memory cells (not shown) are formed simultaneously. In some cases, the 3D memory array 102 can be positioned above a substrate including various circuitry such as row decoders 120, sensing components 125, column decoders 130, or the like.

[0057] Figure 2 An example of a 3D memory array 202 supporting thin film transistors and related manufacturing techniques according to an embodiment of the present disclosure is described. The 3D memory array 202 may be a reference Figure 1An example of a memory array 102 or portion of a 3D memory device including two or more levels of memory cells is described. The 3D memory array 202 can include a first array or level 205-a of memory cells positioned above a substrate 204 and a second array or level 205-b of memory cells on top of the first array or level 205-a. The 3D memory array 202 can also include word lines 110-a and word lines 110-b and bit lines 115-a, which can be reference lines. Figure 1 Examples of line 110 and bit line 115 are described. Figure 2 , the memory cells of the first level 205-a and the second level 205-b may each include self-select memory cells. In some examples, the memory cells of the first level 205-a and the second level 205-b may each include another type of memory cell that may be suitable for a cross-point architecture, such as a CBRAM cell or a FeRAM cell. Figure 2 Some of the elements included therein are labeled with numerical indicators, while other corresponding elements are not labeled but are the same or should be understood to be similar in an attempt to improve visibility and clarity of the depicted features.

[0058] In some cases, the memory cells of the first level 205-a may each include a first electrode 215-a, a chalcogenide material 220-a, and a second electrode 225-a. Additionally, the memory cells of the second level 205-b may each include a first electrode 215-b, a chalcogenide material 220-b, and a second electrode 225-b. In some embodiments, the access lines (e.g., word lines 110, bit lines 115) may include an electrode layer (e.g., a conformal layer) in place of electrodes 215 or 225 and thus may include a multi-layer access line. In such embodiments, the electrode layer of the access line may interface with the memory material (e.g., chalcogenide material 220). In some embodiments, the access lines (e.g., word lines 110, bit lines 115) may directly interface with the memory material (e.g., chalcogenide material 220) without an electrode layer or electrodes in between.

[0059] In some embodiments, the memory cells of the first layer 205-a and the second layer 205-b may have a common conductive line, so that corresponding (e.g., vertically aligned along the y direction) memory cells of each layer 205-a and 205-b may share a bit line 115 or a word line 110, as shown in FIG. Figure 1 For example, both the first electrode 215-b of the second level 205-b and the second electrode 225-a of the first level 205-a may be coupled to the bit line 115-a so that the bit line 115-a is shared by vertically aligned and adjacent memory cells (in the y-direction).

[0060] In some embodiments, the 3D memory array 202 may include additional bit lines (not shown) such that the first electrode 215-b of the second level 205-b may be coupled to the additional bit line and the second electrode 225-a of the first level 205-a may be coupled to the bit line 115-a. The additional bit line may be electrically isolated from the bit line 115-a (e.g., an insulating material may be inserted between the additional bit line and the bit line 115-a). Thus, the first level 205-a and the second level 205-b may be separated and may operate independently of each other. In some cases, the access line (e.g., word line 110 or bit line 115) may include a selection component (e.g., a two-terminal selector device, which may be configured as one or more thin film materials integrated with the access line) for the corresponding memory cell at each intersection. Thus, the access line and the selection component may together form a composite material layer that acts as both the access line and the selection component.

[0061] In some cases, the architecture of the 3D memory array 202 may be referred to as an example of a cross-point architecture because memory cells may be formed at topological cross-points between word lines 110 and bit lines 115, such as Figure 2 This cross-point architecture can provide relatively high density data storage at a lower production cost than some other memory architectures. For example, a memory array with a cross-point architecture can have memory cells with reduced area and thus can support increased memory cell density than some other architectures. For example, compared with a 6F 2 Compared to other architectures (such as those with three-terminal selection elements), the cross-point architecture can have a 4F 2 Memory cell area, where F is the minimum feature size (e.g., minimum feature size). For example, a DRAM memory array may use a transistor (e.g., a thin film transistor) (which is a three-terminal device) as a select element for each memory cell, and therefore, a DRAM memory array including a given number of memory cells may have a larger memory cell area than a memory array having a cross-point architecture including the same number of memory cells.

[0062] although Figure 2The example of shows two memory levels, but other configurations may include any number of levels (e.g., 4 levels, 8 levels, 16 levels, 32 levels). In some embodiments, one or more memory levels may include self-select memory cells that include chalcogenide materials 220. In other embodiments, one or more memory levels may include FeRAM cells that include ferroelectric materials. In other embodiments, one or more memory levels may include CBRAM cells that include metal oxide or chalcogenide materials. For example, chalcogenide material 220 may include chalcogenide glass, such as, for example, an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some embodiments, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy.

[0063] In some cases, the lines 110-a, word lines 110-b, and bit lines 115-a of the 3D memory array 202 may be referred to as array electrodes. As described herein, a group of TFTs may be constructed in an array layer such that a subset of the group of TFTs may be coupled to array electrodes (e.g., word lines 110, bit lines 115) of a layer of the memory array (e.g., a first layer of memory cells 205-a, a second layer of memory cells 205-b). In some cases, the group of TFTs may be coupled to circuitry in the substrate 204 (e.g., CMOS circuitry below the array layer) to facilitate various functions of the circuitry. For example, the group of TFTs may select a particular layer of the memory array (e.g., a select function) and simultaneously deselect two or more layers of the memory array (e.g., an inhibit function) based on input from the circuitry (e.g., a decode result associated with an access command). In some cases, the group of TFTs may perform a higher level function (e.g., a full decode function) to offload one or more functions that would otherwise be implemented by the circuitry.

[0064] Figures 3 to 6 illustrate various aspects of the manufacturing techniques of the present disclosure. For example, various cross-sectional views may illustrate the parallel nature of producing specific structures of a TFT (e.g., source, drain, gate, and channel of a TFT) at one or more buried target layers of a composite stack, each target layer comprising a target material. As described herein, in some cases, a via (e.g., an access via) may be used to produce a structure in a target material at a target buried layer. Various top views may illustrate how a set of specific vias may be used to produce various structures of a TFT. The manufacturing techniques described herein may facilitate the simultaneous formation of identical structures at different underlying layers, such as a set of gate electrodes of a TFT or a set of channel material elements of a TFT. Thus, the manufacturing techniques described herein may facilitate the simultaneous formation of a set of TFTs in an array layer comprising two or more memory cell levels, each level comprising access lines (e.g., word lines, bit lines, array electrodes) and a 3D cross-point structure of a memory cell.

[0065] Figures 3A to 3L Exemplary manufacturing techniques according to the present disclosure are described. Figures 3A to 3L Aspects of several process steps for simultaneously constructing two or more TFTs (e.g., TFTs that may be referred to as vertical TFTs and in which current flows in a vertical direction relative to a horizontal substrate when the TFTs are activated) are described. In some cases, such TFTs may be fabricated in a socket region of an array layer. In some cases, the TFTs may be referred to as array electrode drivers. The socket region may refer to the region where various interconnects (e.g., TFTs and underlying circuitry (e.g., reference electrodes) may be formed. Figure 2 The logic circuitry in the substrate 204 described above, the interconnections between the row decoder 120, the TFTs and the array electrodes (eg, reference Figure 2 The area of ​​the array layer of the interconnects between the ends of the lines 110 and / or bit lines 115 is depicted. Figures 3A to 3L A top view of a portion of a socket area is included (eg, a layout of the socket area) to illustrate that different via groups may be used to simultaneously construct various structures of TFTs. Figures 3A to 3L A cross-sectional side view of a portion of the socket area is also included to illustrate aspects of process features during several process steps used to simultaneously construct the TFT.

[0066] Figure 3A 305 may include a plurality of different layers of various materials. In some cases, the stack may be referred to as a composite stack. In some cases, the stack 305 may be positioned on a substrate (e.g., a substrate having a plurality of layers of various materials). Figure 2 The specific material of stack 305 may be selected based on a number of factors, such as the desired type of memory technology (e.g., self-select memory, FeRAM, CBRAM), the desired number of memory cell levels (e.g., two or more memory cell levels). Figure 3A As depicted in the illustrative example of FIG. 2 , the stack 305 may include a first layer 205-a of memory cells positioned above the substrate 204 and a second array or layer 205-b of memory cells on top of the first array or layer 205-a, as described with reference to FIG. Figure 2 An initial layer stack (described above) is provided.

[0067] Stack 305 may include layer 310, which may be the top layer of stack 305. In some embodiments, layer 310 includes a dielectric material. In some embodiments, layer 310 includes a hard mask material, such that layer 310 may be referred to as a hard mask (HM) layer. A via pattern may be formed in layer 310 as a result of, for example, a photolithography step. In some cases, this photolithography step may form a first set of vias (e.g., Figure 3BThe third group of paths 340-c) and the second group of paths (eg Figure 3B Path 340-b of the second group shown in FIG.

[0068] The stack 305 may also include a layer 315. Figure 3A In the illustrative example of , stack 305 includes two layers 315 (i.e., layer 315-a and layer 315-b), but any number of layers is possible. In some embodiments, layers 315 may each include a first dielectric material (which may also be referred to as D1). As described herein, each layer 315 may be modified to include a set of first array electrodes (e.g., electrode sheets or segments, conductive lines, access lines, word lines). In some cases, each layer 315 may be referred to as a first layer, a first electrode layer, or a D1 layer.

[0069] The stack 305 may also include a layer 320. Figure 3A In the illustrative example of , stack 305 includes two layers 320 (i.e., layer 320-a and layer 320-b), but any number of layers 320 is possible. In some embodiments, each layer 320 may include a placeholder material that may later be partially removed and replaced by a desired material (e.g., memory material, gate electrode material, semiconductor material). In some embodiments, each layer 320 may initially include a memory material that may be processed to form one or more memory elements. In some cases, layer 320 may be referred to as a second layer, a memory layer, or a DM layer.

[0070] The stack 305 may also include a layer 325. Figure 3A In the illustrative example of , stack 305 includes a single layer 325, but any number of layers 325 is possible. In some embodiments, each layer 325 may include a second dielectric material (which may be referred to as D2). As described herein, layer 325 may be modified to include a set of second array electrodes (e.g., electrode sheets, conductive lines, access lines, bit lines). In some cases, each layer 325 may be referred to as a third layer, a second electrode layer, or a D2 layer.

[0071] Stack 305 can include layer 330. In some cases, layer 330 can include an etch stop material to withstand the various etching processes described herein. In some cases, layer 330 can include the same hard mask material as layer 310, or can include a different material. In some cases, layer 330 can provide a hard mask material relative to a substrate (e.g., a substrate having a substrate surface formed thereon). Figure 2 204) or other layers (not shown) that may be located below layer 330. In some cases, layer 330 may provide a buffer layer relative to one or more memory cell levels fabricated in an earlier processing step.

[0072] Figure 3BA top view of a stack 305 illustrating where a socket area including two or more TFTs (eg, vertical TFTs) may be constructed, as described herein. Figure 3B A set of vias 340 (depicted as white, grey or cross-hatched squares) are illustrated in an array pattern. Figure 3B It is also illustrated that different groups of vias (e.g., first group of vias 340-a, second group of vias 340-b, third group of vias 340-c) may be used to simultaneously form various structures within stack 305. For example, Figure 3B Illustrated are a set of array electrodes 350, a set of electrode sheets 355 (depicted as dark shaded rectangles), and a set of gate electrodes 360 (one of which is depicted in top view), each of which may be formed at a different junction of the process sequence to construct a TFT.

[0073] As described elsewhere, a first subset of vias (e.g., vias 340-a of the first group) may be used to construct a set of array electrodes 350 (e.g., array electrodes 350-c and 350-d). In addition, a second subset of vias (e.g., vias 340-b of the second group depicted as gray squares) may be used to construct a set of electrode patches (e.g., electrode patches 355-b). In some cases, electrode patches 355-b may be a second electrode (e.g., a drain) of a TFT at the first layer 315-a. In some cases, an electrode patch may be constructed by forming a channel (e.g., a series of merged cavities in a row) at a first layer (e.g., D1 layer 315-a, D1 layer 315-b) using vias 340-b of the second group, for example, the channel being aligned with vias 340-b of the second group. The channel at the first layer may be filled with an electrode material (e.g., a conductive material). Subsequently, a set of dielectric plugs corresponding to the second group of vias 340-b may be formed to separate an electrode piece within D1 layer 315-a from another electrode piece within D1 layer 315-b. The dielectric plugs may extend through the electrode material filling the trenches at the first layer.

[0074] Additionally, a set of gate electrodes 360 may be constructed using a third subset of vias (eg, a third group of vias 340-c), as described herein with reference to Figures 3C to 3F As described. In addition, one or more vias (e.g., vias depicted as cross-hatched squares, which include vias 340-d, vias 340-e) may be used to divide an array electrode (e.g., array electrode 350-f) into two or more segments. Therefore, in some cases, an electrode sheet (e.g., electrode sheet 355-b) may be coupled to a single array electrode (e.g., array electrode 350-e). In some cases, the electrode sheet (and therefore the one or more TFTs constructed therein) may be positioned between the two ends of a single array electrode. For example, an electrode sheet (e.g., electrode sheet 355-b) may be positioned approximately in the middle region of a single array electrode (e.g., array electrode 350-e).

[0075] In some cases, array electrode 350 may be an access line (e.g., a word line, a bit line, a conductive line) coupled to a group of memory cells in an active array region of an array layer or may be part of an access line. An active region may refer to a region of an array layer where an access line and a group of memory cells form an array of memory cells. In some cases, an array of memory cells (e.g., an access line and a group of memory cells) may be constructed according to a cross-point architecture in an active array region. In this manner, a group of TFTs formed in a socket region of an array layer may be coupled to array electrode 350 (and therefore a group of memory cells associated with array electrode 350) in an active array region of an array layer.

[0076] Figures 3C to 3F A fabrication technique is illustrated for forming a set of gate electrodes 360 of a TFT within stack 305 using third group of vias 340-c. In some cases, a set of array electrodes 350 and a set of electrode pads 355 may have been formed within stack 305 prior to forming a set of gate electrodes 360 at layer 320.

[0077] Figure 3C The following diagram illustrates the traversal of the via hole formed using the third group of vias 340-c. Figure 3B The cross-sectional side view of the stack 305 shown in the dashed line AA. The cross-sectional side view may correspond to an electrode sheet (e.g., Figure 3B A portion of the electrode sheet 355-a) is shown in FIG. Figure 3C The electrode sheet depicted in Figure 3C The electrode sheets 355-c and 355-d shown in FIG. 3 may have been previously formed in the D1 layer. Figure 3A The shading pattern of the original D1 layer (e.g., layer 315-a, layer 315-b) is used to depict Figure 3C The electrodes 355-c and 355-d indicate Figure 3C The portion of the D1 layer shown in FIG. 3 has been replaced by electrode material that forms a set of electrode sheets 355 . Figure 3C Also illustrated is an opening 341 that may correspond to a cross-sectional side view of a via hole, such as a via hole corresponding to via 340 - f included in the third group of vias 340 - c .

[0078] In some cases, the photolithography step may transfer the shape of via 340 onto stack 305. In some cases, the photolithography step may include forming a photoresist layer (not shown) having the shape of via 340 (e.g., defined by the absence of photoresist material within via 340) on top of layer 310. In some examples, the photolithography step may be followed by an etching process step to transfer the shape of via 340 onto layer 310, so that the shape of via 340 established within layer 310 may be reused as an access via during subsequent processing steps, i.e., layer 310 including the shape of via 340 may act as a hard mask layer that provides an access via in the shape of via 340 for subsequent processing steps.

[0079] In some cases, the anisotropic etching process step may form an opening 341 through the stack 305 and the width of the opening 341 may be substantially the same as the width of the via (e.g., via 340-f). The anisotropic etching step may remove the target material in one direction (e.g., an orthogonal direction relative to the substrate) by applying an etchant (e.g., a mixture of one or more chemical elements) to the target material. In addition, the etchant may exhibit selectivity (e.g., chemical selectivity) for removal of only the target material (e.g., the hard mask material at layer 310) while retaining other materials (e.g., photoresist) exposed to the etchant. When removing one or more layers of material (e.g., the first dielectric material at the D1 layer 315, the placeholder material at the DM layer 320, the second dielectric material at the D2 layer 325), the anisotropic etching step may use one or more etchants during a single anisotropic etching step. In some cases, an anisotropic etching step may use an etchant that exhibits selectivity for groups of materials that are desired to be removed (eg, oxides and nitrides) while preserving other groups of materials (eg, metals) exposed to the etchant.

[0080] Figure 3D The invention illustrates the use of via holes (eg, openings 341) already formed in stack 305 (see reference Figure 3C A cross-sectional side view of the stack 305 crossing dashed line AA after performing at least one etching process step and a deposition process step as described above.

[0081] In some cases, the etching process step may include an isotropic etching step that can remove the target material in all directions. In some cases, the isotropic etching step may apply an etchant that exhibits selectivity (e.g., chemical selectivity) for the removal of only the target material (e.g., the placeholder material in the DM layer 320) while retaining other materials (e.g., the electrode material of the electrode sheet 355-c or 355-d, the second dielectric material of the D2 layer, the hard mask material of the HM layer) exposed to the etchant (e.g., a mixture of one or more chemical elements). When removing one or more layers of material, the isotropic etching step may employ different etchants during a single isotropic etching step. In some cases, the isotropic etchant (e.g., the etchant used in the isotropic etching step) may be chemically selective between the first dielectric material and at least one other material in the stack. In this way, the etching process step may form a series of cavities within each DM layer, such as a series of cavities 342 corresponding to the vias 340-c of the third group. When overlapping cavities (e.g., adjacent cavities, such as cavity 342-a and the next cavity (not shown) within DM layer 320-a) completely overlap, the overlapping cavities can merge to form a channel at the DM layer. In this way, the channels can be connected to the first set of vias (e.g., Figure 3B A channel is formed at a second layer (eg, layer 320 - a, layer 320 - b ) aligned with the third group of vias 340 - c ) shown in FIG.

[0082] Still refer to Figure 3D , a deposition process step may be performed after the etching process step to form a layer of insulating material (e.g., insulating layer 365) on the surface of cavity 342 (and therefore the channel) and via hole (e.g., opening 341). In some cases, insulating layer 365 may conform to (e.g., maintain substantially the same thickness) the uneven surface across at least two layers (e.g., across electrode pad 355-c and recessed DM layer 320-a and then D2 layer 325). In some cases, insulating layer 365 may facilitate crossover region formation, as described herein. In some cases, the deposition process step may form insulating layer 365 that is conformal to the channel.

[0083] Figure 3E A cross-sectional side view of the stack 305 across dashed line AA is illustrated after completion of at least one deposition process step. The deposition process step may be based on the use of via holes (e.g., as described in reference Figure 3DThe insulating layer 365 is partially filled with the opening 341 described above to form the insulating layer 365 to fill the trenches formed at the DM layers (e.g., DM layers 320-a and 320-b). In some cases, the deposition process step may deposit electrode material 361. The electrode material 361 may form a set of gate electrodes 360. In some cases, the electrode material 361 may include polysilicon, a refractory metal element (e.g., tungsten, titanium, tantalum) or its nitride or a combination thereof. In some cases, additional electrode material 361 that may be present above the HM layer 310 may be removed by using a chemical mechanical polishing (CMP) process step or an etch back process step.

[0084] Figure 3F A cross-sectional side view of the stack 305 across dashed line AA is illustrated after at least one etching process step using the third group of vias 340 - c to remove electrode material 361 from the via holes. Figure 3F Also illustrated is an opening 341-a that may correspond to a cross-sectional side view of a via hole (e.g., a via hole corresponding to via 340-f included in the third group of vias 340-c). In some cases, the anisotropic etching process step may form the opening 341-a and the width of the opening 341-a may be substantially the same as the width of the via (e.g., via 340-f). Because the anisotropic etching process step removes the electrode material 361 from the via hole, the electrode material within a DM layer (e.g., electrode material 361-a within DM layer 320-a) may be separated from the electrode material within another DM layer (e.g., electrode material 361-b within DM layer 320-b). In this manner, two or more gate electrodes (e.g., a set of gate electrodes 360) may be formed simultaneously within the stack 305.

[0085] Figure 3G The invention illustrates the use of a via hole (eg, opening 341-a) formed in the stack 305 to perform at least one etching process step and a deposition process step (eg, referring to FIG. 3 ). Figure 3F A cross-sectional side view of the stack 305 across the dashed line AA after being described).

[0086] In some cases, the etching process step may include a selective isotropic etching step that can selectively remove electrode material 361 while leaving the rest of stack 305 exposed to the isotropic etching process. Due to the isotropic etching step, electrode material 361 (e.g., electrode materials 361-a and 361-b) within the DM layer can be recessed, such as Figure 3G341 -a. In some cases, the isotropic etching may remove a portion of the gate electrode (e.g., gate electrode 360 ​​including electrode material 361) to form a cavity at the second layer (e.g., layer 320). In some cases, the etching process step may also include an anisotropic etching step that selectively removes a portion of layer 330 (e.g., hard mask material at layer 330) to create a hole through layer 330 (e.g., opening 341 -b at layer 330). In some cases, the width of opening 341 -b may be substantially the same as the width of opening 341 -a. Opening 341 -b may be coupled to a conductive element 385 that may be part of a logic circuitry layer. For example, conductive element 385 may represent a node of circuitry in the substrate (e.g., row decoder 120 constructed in substrate 204). In another example, conductive element 385 may be coupled to a node of row decoder 120 (e.g., a node where a select signal is present) to activate one or more levels of the array layer.

[0087] Still refer to Figure 3G , the deposition step may use the via (e.g., via hole 341-a) to form oxide material 370 over the exposed surface of electrode material 361. In this way, oxide material 370 may be formed in the cavity at the second layer (e.g., layer 320), wherein oxide material 370 may be in contact with gate electrode 360 ​​including electrode material 361. In some cases, oxide material 370 may be referred to as a gate oxide that may be present between the gate electrode and the active channel region of the TFT. The deposition step may be a selective oxidation step or a selective deposition step that may be configured to form oxide material 370 only over the exposed surface of electrode material 361.

[0088] Figure 3H The invention illustrates the use of the via hole (eg, opening 341-a) formed in the stack 305 to perform at least one first etching process step, a deposition process step, and a second etching process step (eg, referring to FIG. 1 ). Figure 3G 341-a). The first etching process step may include an isotropic etching step that removes a portion of the electrode sheet 355 (e.g., the second electrode of the TFT), such as selectively removing exposed electrode material of the electrode sheet 355 within the via hole 341-a. The isotropic etching step may form one or more cavities at the first layer (e.g., layer 315).

[0089] Subsequently, ohmic material 375 may be formed to fill via hole 341-a and spaces (e.g., cavities) associated with via hole 341-a, such as cavities at D1 layer (e.g., layer 315) created by removing portions of electrode sheet 355, spaces at DM layer (e.g., layer 320) created by removing electrode material 361. Thus, ohmic material 375 may contact the second electrode (e.g., electrode sheet 355). In some cases, ohmic material 375 may provide a connection between electrode material (e.g., electrode sheet 355-c or 355-d) and a semiconductor material (e.g., reference 361) to be formed later. Fig. 3I Ohmic contact between the semiconductor materials 380) described.

[0090] The ohmic material may be a material configured to provide a current path between a conductive material (e.g., electrode sheet 355-c or 355-d) and a semiconductor material (e.g., semiconductor material 380) having a bidirectional uniform or at least substantially uniform resistance. That is, the current path from the conductive material through the ohmic material to the semiconductor material may exhibit the same or substantially the same resistance as the current path from the semiconductor material through the transition material to the ohmic material. Thus, the ohmic material may avoid a rectifying junction or other non-ohmic or directional contact or current path between the conductive material (e.g., electrode sheet 355-c or 355-d) and the semiconductor material (e.g., semiconductor material 380). In some cases, the ohmic material 375 may be referred to as a transition material. The ohmic material 375 may include various compounds including transition metal elements (e.g., titanium, cobalt, nickel, copper, tungsten, tantalum). The second etching process step may include an anisotropic etching step that uses the opening 341-a to remove the ohmic material 375 in the vertical direction within the via hole. In this way, the ohmic material outside the via hole (eg, ohmic material 375 - a , ohmic material 375 - b ) may remain intact.

[0091] Fig. 3I The invention illustrates the use of the via hole (eg, opening 341-a) formed in the stack 305 to perform at least one first etching process step, a first deposition process step, a second etching process step, and a second deposition step (see reference 341-a). Figure 3H341 -a). The first etching process step may include an isotropic etching step that selectively removes a portion of the ohmic material 375 exposed within the opening 341 -a (e.g., a portion of the ohmic material 375-a at the D1 layer, the ohmic material 375-b at the DM layer). In this way, the isotropic etching step may form a cavity spanning the first layer (e.g., layer 315) and the second layer (e.g., layer 320). The first etching process step may also include an etching step that selectively removes the insulating layer 365 exposed by removing a portion of the ohmic material 375. The first deposition process step may use the semiconductor material 380 to fill the via hole (e.g., the opening 341 -a) and the space created by the first etching process step (e.g., the cavity spanning the first layer and the second layer). The second etching process step may use the opening 341 -a to remove the semiconductor material 380 in the vertical direction within the via hole. The second deposition step may selectively form insulating material 390 over the exposed surface of semiconductor material 380 within the via hole so that insulating material 390 may contact semiconductor material 380. In some cases, the thickness of insulating material 390 may be determined based on the second gate effect (e.g., to avoid the second gate effect).

[0092] Figure 3J The invention illustrates the use of the via hole (eg, opening 341-a) formed in the stack 305 to perform at least one first etching process step, a deposition process step, and a second etching process step (eg, referring to FIG. 1 ). Fig. 3I 3. A cross-sectional side view of stack 305 across dashed line AA after the first etching process step may include an anisotropic etching step that selectively removes a portion of the third layer (e.g., layer 325, D2 layer) to create a cavity therein. Subsequently, a deposition process step may fill the via hole and the cavity with ohmic material 375 (e.g., ohmic material 375-e). A second etching process step may remove ohmic material 375 from the via hole in a vertical direction so that ohmic material (e.g., ohmic material 375-e) remains in the cavity at the third layer. The remaining ohmic material at the third layer (e.g., ohmic material 375-e) may contact the third electrode (e.g., reference electrode 325). Figure 3K and 3L The conductive plug 396 described above contacts the substrate.

[0093] Figure 3K The method of performing at least one deposition process step (such as referring to FIG. 1 ) using a via hole (such as opening 341 - a ) formed in stack 305 is described. Figure 3J390-a). A cross-sectional side view of stack 305 across dashed line AA after deposition of the stack 305 (as described above). The deposition process step may fill the via hole with electrode material 395. In some cases, electrode material 395 may be the same electrode material as electrode pad 355 or array electrode 350. As a result of using electrode material 395 to fill the via hole (e.g., to form conductive plug 396), conductive element 385 (e.g., a node associated with a logic circuit system layer) may be coupled with ohmic material 375-e, which is in contact with semiconductor material 380-a. Semiconductor material 380-a, which is further coupled to electrode material 361-a of gate electrode 360 ​​(e.g., gate electrode 360 ​​in contact with oxide material 370-a) through oxide material 370-a, may form an active channel to allow current to flow based on a voltage applied to gate electrode 360. In addition, semiconductor material 380-a is in contact with ohmic material 375-a, which is in contact with electrode pad 355-c.

[0094] thus, Figure 3K A cross-sectional side view of TFTs (e.g., two vertical TFTs 335-a and 335-b) constructed in a socket region of an array layer including stack 305 may be illustrated. A conductive plug 396 (e.g., a via hole filled with electrode material 395) may serve as a common source of the TFTs, such as a third electrode extending through a third layer (e.g., layer 325). Conductive plug 396 may be further coupled to conductive element 385 (e.g., a node associated with logic circuitry). Semiconductor material 380-a surrounding conductive plug 396 may serve as an active channel of an upper TFT 335-a. Similarly, semiconductor material 380-b surrounding conductive plug 396 may serve as an active channel of a lower TFT 335-b. Electrode pad 355-c coupled to semiconductor material 380-a (e.g., through ohmic material 375-a) may serve as a drain of the upper TFT 335-a. Similarly, electrode plate 355 - d coupled to semiconductor material 380 - b (eg, via ohmic material 375 - d ) may serve as a drain for lower TFT 335 - b .

[0095] In some cases, Figure 3K (Given that Figure 3L ) depicts an ohmic material 375 - a at a first layer (eg, D1 layer 315 ), wherein the ohmic material 375 - a surrounds and contacts a semiconductor material 380 - a at the first layer. Figure 3K Also depicted is an insulating material 390 - a interposed between the conductive plug 396 and the semiconductor material 380 - a. Figure 3KA portion of an ohmic material (e.g., ohmic material 375-e) at a third layer (e.g., D2 layer 325) is depicted, where ohmic material 375-e is in contact with semiconductor material 380-a so that conductive plug 396 can be coupled with semiconductor material 380-a. In some cases, ohmic material 375-e can surround conductive plug 396.

[0096] Figure 3K Current path 345 is depicted to illustrate some operational aspects of the TFT. For example, a first signal at conductive element 385 (e.g., a select signal from logic circuitry) may provide a first voltage (e.g., 0V) to a conductive plug (e.g., a common source of both upper TFT 335-a and lower TFT 335-b). In addition, a second voltage (e.g., 1V) applied to a gate electrode (e.g., upper gate electrode 360 ​​including electrode material 361-a) may be greater than a threshold voltage (e.g., 0.2V) of the TFT to form a conductive path (e.g., an active channel region) within semiconductor material 380-a. In addition, a third voltage (e.g., 0.5V) may be applied to electrode patch 355-c (e.g., a drain of upper TFT 335-a) such that current may flow from the source of the TFT (e.g., conductive plug 396 coupled to a node of logic circuitry) to the drain of the TFT (e.g., electrode patch 355-c coupled to an array electrode (i.e., a word line)), which is indicated as upper current path 345-a. Similarly, the lower current path 345-b can be established when the second voltage is applied to the lower gate electrode including the electrode material 361-b and the third voltage is applied to the electrode piece 355-d (e.g., the drain of the lower TFT 335-b). In some cases, the voltages associated with the TFT (e.g., the first voltage, the second voltage, the third voltage) may not be independent of each other, such as during the TFT performing a decoding function or a selection function. In some cases, if there is a separate circuit (e.g., a circuit that drives the voltage to the TFT, an activated memory cell that conducts current), the voltages associated with the TFT may be independent of each other.

[0097] Figure 3K The TFT illustrated in FIG. 3 may depict a word line socket region because the electrode pad 355 in the D1 layer may be coupled to an array electrode (eg, a word line) constructed in the D1 layer. In addition, Figure 3K The TFT illustrated in is operable to activate or deactivate one of the two memory cell levels in the active cell region that constitutes the array layer of stack 305. In some cases, the drain of the TFT (e.g., the drain of the upper TFT 335-a connected to electrode pad 355-c) can be driven to a voltage related to the voltage present at the conductive element 385 through a conductive pathway (e.g., an active channel region) as described herein.

[0098] Figure 3LA top view of a stack 305 including two or more TFTs (eg, vertical TFTs) including all gate, source, and drain electrodes is illustrated. Figure 3L Various structures for forming a socket region (e.g., a word line socket region) of an array layer are also described. Figure 3L Illustrated are a set of array electrodes 350 , a set of electrode patches 355 (depicted as dark shaded rectangles), and a set of gate electrodes 360 described herein.

[0099] For example, Figure 3L A top view of a conductive plug 396 (e.g., via hole 341-a filled with electrode material 395) extending through a stack 305 including a first layer (e.g., D1 layer 315), a second layer (e.g., DM layer 320), and a third layer (e.g., D2 layer 325) may be used. A via shared between two groups of vias (e.g., via 340-f shared between vias 340-b of the second group and vias 340-c of the third group, as shown in FIG. Figure 3B ) to form a conductive plug 396. Figure 3L Semiconductor material 380 - a at the first layer (eg, D1 layer 315 ) and the second layer (eg, DM layer 320 ) is further depicted, wherein semiconductor material 380 - a surrounds conductive plug 396 . Figure 3L Also depicted is an oxide material 370-a located at a second layer (eg, DM layer 320) and in contact with semiconductor material 380-a. Figure 3L The gate electrode 360-a at the second layer (eg, DM layer 320) is depicted. The gate electrode 360-a including the electrode material 361-a is in contact with the oxide material 370-a. Figure 3K In some cases, the combination of semiconductor material 380-a, oxide material 370-a, and electrode material 361-a can form an active channel within semiconductor material 380-a of a TFT (e.g., a vertical TFT), where current can flow through the active channel based on a voltage applied to gate electrode 360-a.

[0100] In some cases, Figure 3L A portion of an ohmic material (eg, ohmic material 375-a) at a first layer (eg, D1 layer 315) is depicted, wherein the ohmic material 375-a is in contact with the semiconductor material 380-a and surrounds the conductive plug 396, and also as shown in FIG. Figure 3K As shown in . Figure 3L Also depicted is insulating material 390 - a interposed between conductive plug 396 and semiconductor material 380 - a .

[0101] Figures 4A to 4AA Exemplary manufacturing techniques according to the present disclosure are described. Figures 4A to 4AAAspects of several process steps for simultaneously constructing two or more TFTs (e.g., TFTs that may be referred to as planar TFTs and in which current flows in a horizontal (parallel) direction relative to a horizontal substrate when the TFTs are activated) are described. In some cases, such TFTs may be fabricated in a socket region of an array layer, as described herein. In some cases, the TFTs may be referred to as array electrode drivers. Figures 4A to 4AA A top view of a portion of a socket area is included (eg, a layout of the socket area) to illustrate various structures in which TFTs may be constructed simultaneously using different via groups. Figures 4A to 4AA A cross-sectional side view of a portion of the socket area is also included to illustrate aspects of process features during several process steps used to simultaneously construct the TFT.

[0102] Figures 4A to 4AA Instructions for constructing a composite stack (e.g., reference Figures 3A to 3L The exemplary fabrication techniques for constructing a planar TFT in a stack 305 of vertical TFTs described herein are described. Thus, the composite stack can be used to construct a vertical TFT or a planar TFT, or both, in a socket region of an array layer. The composite stack can also be used to construct a 3D cross-point array of memory cells and associated electrodes in an active array region of an array layer as described herein. In this manner, the composite stack can provide array layers that each include a memory cell layer and an electrode, wherein the electrode (and therefore the memory cell) can be further coupled to a TFT (e.g., a vertical TFT, a horizontal TFT, a combination of a vertical TFT and a horizontal TFT).

[0103] Figure 4A A top view of a stack 405 illustrating a socket region in which a socket region including two or more TFTs (eg, horizontal TFTs) may be constructed, as described herein. The stack 405 may be a reference Figures 3A to 3L An example of a stack 305 is described. Figure 4A A set of vias 440 (depicted as white, gray, or cross-hatched squares) in an array pattern is illustrated. The set of vias 440 may be formed through a top layer (e.g., layer 310 of stack 305) of stack 405 including a first layer (e.g., layer 315 of stack 305) and a second layer (e.g., layer 320 of stack 305). The set of vias 440 may be a reference Figures 3A to 3L An example of a set of pathways 340 is depicted. Figure 4A It is also illustrated that different groups of vias (e.g., first group of vias 440-a, second group of vias 440-b) may be used to simultaneously form various structures within stack 405. For example, Figure 4A A set of array electrodes 450 (which may be referenced Figures 3A to 3L An example of an array electrode 350 described herein) and a set of gate electrodes 460 (which may be reference Figures 3A to 3LExamples of gate electrode 360 ​​are described), each of which can be formed at a different junction in the process sequence to construct a TFT.

[0104] As described elsewhere, a first subset of vias (e.g., first group of vias 440-a) can be used to construct a set of array electrodes 450 (e.g., array electrodes 450-a and 450-b). In some cases, the array electrodes can serve as a third electrode of the TFT. Additionally, a second subset of vias (e.g., second group of vias 440-b) can be used to construct a set of gate electrodes 460 (e.g., gate electrode 460-a), as described herein with reference to Figures 3C to 3F described.

[0105] In some cases, a via (e.g., a via depicted as a gray square that includes via 440-z) that can form a cavity (e.g., cavity 442-z corresponding to via 440-z) can be used to divide a subset of array electrodes 450 (e.g., array electrodes 450-b, array electrodes 450-c) into segments. Subsequently, an etching process step can remove the portion of array electrode 450 exposed within the cavity to divide the subset of array electrodes 450 into two or more segments. As described herein with reference to Figure 4Y As described, dividing the subset of array electrodes can facilitate the TFT subset formed in the socket area to drive a single array electrode (e.g., array electrode 450-a, array electrode 450-d). In some cases, the TFT subset can be positioned between the two ends of a single array electrode. For example, the TFT subset can be positioned approximately in the middle region of a single array electrode.

[0106] Figure 4B Instructions for using a third channel group (e.g. Figure 4A The vias depicted as cross-hatched squares in FIG. 4 include vias 440-c and 440-d) to form via holes (eg, openings 441-d corresponding to vias 440-d) after traversing Figure 4A 4. The cross-sectional side view of stack 405 shown in FIG. 4 may correspond to a portion of a socket region including gate electrodes 460-a and 460-b. Electrode material 461 (which may be reference Figures 3A to 3L The examples of electrode material 361 described) may have been previously formed in the DM layer of stack 405, as described herein. Figure 4B The electrode material 461 depicted in FIG. Figure 4A In the gate electrode 460 depicted in FIG. 4 , for example, electrode material 461 - a forms gate electrode 460 - a , and electrode material 461 - b forms gate electrode 460 - b . Figure 4B The insulating layer 465 (which may be a reference Figures 3A to 3L4. The example of insulating layer 365 depicted) partially surrounds electrode material 461. In some cases, an etching process (eg, an anisotropic etching process) can remove a portion of insulating layer 465 that is exposed to the etching process that forms the via hole.

[0107] Figure 4C Instructions for using a third channel group (e.g. Figure 4A The vias depicted as cross-hatched squares in FIG. 4 include vias 440-c and 440-d) to form via holes (eg, openings 441-d) after traversing Figure 4A 4 is a cross-sectional side view of the stack 405 shown in dashed line BB. Figure 4C Describe and Figure 4B Different cross-sectional side views of the stack 405 at the same process steps as depicted in FIG. 4 are provided to highlight various aspects of the manufacturing techniques used to form the TFTs. Figure 4C The cross-sectional side view of also corresponds to a portion of the socket region including gate electrodes 460 - a and 460 - b . Figure 4C It is illustrated that an insulating layer (eg, insulating layer 465 - a ) surrounds electrode material 461 - c (which may form gate electrode 460 - b ) because Figure 4C The insulating layer 465 captured in the cross-sectional side view of FIG. 4 remains intact when forming the via hole, for example, the anisotropic etching process may not reach the insulating layer 465-a. In addition, Figure 4C It is illustrated that the array electrode 450 may have been formed in the D1 layer of the stack 405 , such as the array electrode 450 - d1 and the array electrode 450 - d2 .

[0108] Figure 4D The invention illustrates performing at least one etching process step and a deposition process step (such as referring to FIG. 4 ) using a via hole (such as opening 441 - d ) formed in stack 405 . Figure 4A and 4B A top view of the stack 405 after the above description. Figure 4D Describe the specific pathways used (e.g., reference Figure 4A The described passage 440-z and corresponding cavity 442-z) are used to remove part of the array electrode (e.g., array electrode 450-b, array electrode 450-c). Therefore, some array electrodes (e.g., array electrode 450-b, array electrode 450-c) may be disconnected from the array electrodes in the active array area of ​​the array layer.

[0109] Figure 4E Explain the traversal after the etching process step and the deposition process step Figure 4D 4 is a cross-sectional side view of the stack 405 shown in dashed line AA. Similarly, Figure 4F Explain the traversal after the etching process step and the deposition process step Figure 4D405 is a cross-sectional side view of the stack 405 shown in dashed line BB. In this way, Figures 4D to 4F Various aspects of structural features formed within stack 405 as a result of etching process steps and deposition process steps are described.

[0110] In some cases, the etching process step may include a first isotropic etching process that uses a via hole (e.g., opening 441-d) to reach layers below a top layer (e.g., a hard mask layer) of stack 405. The first isotropic etching process may selectively remove the first dielectric material of the D1 layer within stack 405. The first isotropic etching process may leave other materials exposed in the via hole (e.g., materials other than the first dielectric material of the D1 layer) substantially unchanged, such as insulating layer 465, electrode material 461, and a second dielectric material in the D2 layer. As a result of the first isotropic etching process, via cavity 442 (e.g., Figure 4D The passage cavity 442-b corresponding to the passage 440-d depicted in FIG. Figure 4E and 4F Via cavity 442-c and via cavity 442-d) depicted in FIG. 4 corresponding to via 440-d may be formed at the D1 layer. Figure 4D It is illustrated that via cavities (eg, via cavities 442 - a and 442 - b depicted as light gray squares in the top view) can reach array electrodes 450 (eg, array electrodes 450 - c and 450 - d ) to expose array electrodes 450 at the D1 layer.

[0111] In some cases, the etching process may further include a second isotropic etching process, which may selectively remove portions of the array electrode 450 at the D1 layer, such as portions of the array electrode 450 exposed to the second isotropic etching process due to the first isotropic etching process. The second isotropic etching process may leave other materials (e.g., materials other than the array electrode 450 at the D1 layer) exposed in the via holes and via cavities substantially unchanged, such as the insulating layer 465, the electrode material 461, the first dielectric material at the D1 layer, and the second dielectric material at the D2 layer. Due to the second isotropic etching process, Figure 4F It is explained that a portion of the array electrode 450 (eg, the array electrode 450-d1, the array electrode 450-d2) has been removed to form (eg, expand) a via cavity (eg, via cavity 442-c, via cavity 442-d). In addition, Figure 4D It is illustrated that the second isotropic etching process may remove portions of the array electrodes, such as the overlapping regions between the via cavities (such as the via cavities 442 - a ) and the array electrodes (such as the array electrodes 450 - c , 450 - d ).

[0112] In some cases, the etching process may also include a third isotropic etching process that may selectively remove the insulating layer 465 at the DM layer exposed in the via hole and the via cavity. The third isotropic etching process may leave other materials (e.g., materials other than the insulating layer 465) exposed in the via hole and the via cavity substantially unchanged, such as the electrode material 461, the first dielectric material in the D1 layer, the second dielectric material in the D2 layer, the array electrode 450 at the D1 layer. Due to the third isotropic etching process, portions of the electrode material 461 may become exposed to the deposition process.

[0113] In some cases, the deposition process step may selectively form oxide material 470 (which may be referenced to FIG. 1 ) over the exposed surface of electrode material 461. Figures 3A to 3L 4. In some cases, oxide material 470 may serve as a gate oxide for a TFT.

[0114] In some cases, using vias (e.g., via 440-d) of the second group of vias 440-b that have been used to form gate electrodes (e.g., gate electrode 460-b) of the TFT, the second isotropic etching process may form cavities (e.g., cavities 442-c, cavities 442-d) at the first layer to expose a portion of the gate electrodes (e.g., electrode material 461-b1, electrode material 461-b2). Using the vias (e.g., via 440-d), a deposition process step may form an oxide material (e.g., oxide material 470-e, oxide material 470-f) in contact with the gate electrodes (e.g., electrode material 461-b1, electrode material 461-b2).

[0115] Figure 4G The invention illustrates the use of via holes (eg, Figure 4E The opening 441-d) and the passage cavity (eg Figure 4E and 4F 442) to perform at least one deposition process step (as shown in reference Figures 4D to 4F A top view of stack 405 after being described). Figure 4H Describes the traversal after the deposition process step Figure 4G 4 is a cross-sectional side view of the stack 405 shown in dashed line AA. Similarly, Fig. 4I Describes the traversal after the deposition process step Figure 4G 4 is a cross-sectional side view of the stack 405 shown in dashed line BB.

[0116] In some cases, the deposition process step may use semiconductor material 480 (which may be reference Figures 3A to 3L The examples of semiconductor material 380 described above are used to fill the via holes and via cavities. Figure 4GA top view of a via cavity (eg, via cavity 442 - a depicted as a dark grey square) filled with semiconductor material 480 is depicted. Figure 4H It is depicted that semiconductor material 480 may be in contact with oxide material 470 (eg, gate oxide). Fig. 4I It is depicted that semiconductor material 480 may fill the cavity and may be in contact with oxide material 470 (eg, gate oxide).

[0117] In some cases, the deposition step may be performed in a chamber (eg, via 440-d) using vias (eg, via 440-d) of the second group of vias 440-b that have been used to form a gate electrode (eg, gate electrode 460-b) of a TFT. Figure 4E and 4F A semiconductor material (eg, semiconductor material 480) is formed in cavity 442-c, cavity 442-d) shown in FIG. 1 , and the semiconductor material may be in contact with an oxide material (eg, oxide material 470-e).

[0118] Figure 4J The third via group (eg, Figure 4J The vias depicted as cross-hatched squares in FIG. 4 include vias 440-c and vias 440-d) perform at least one etching process step and a deposition process step (as shown in FIG. Figures 4G to 4I A top view of stack 405 after being described). Figure 4K Explain the traversal after the etching process step and the deposition process step Figure 4J 4 is a cross-sectional side view of the stack 405 shown in dashed line AA. Similarly, Figure 4L Describes the traversal after the deposition process step Figure 4J 4 is a cross-sectional side view of the stack 405 shown in dashed line BB.

[0119] In some cases, the etching process may include a first anisotropic etching process that may selectively remove semiconductor material 480 within via holes (e.g., via holes corresponding to the third via group) along a vertical direction (e.g., a vertical direction relative to a horizontal substrate). In some cases, the etching process may include a second anisotropic etching process that may selectively remove oxide material 470 in the via holes. Due to the etching process that removes semiconductor material 480 in the via holes, semiconductor material at the upper D1 layer (e.g., semiconductor material 480-a) may be separated from semiconductor material at the lower D1 layer (e.g., semiconductor material 480-b), as shown in FIG. Figure 4K As shown in .

[0120] In some cases, the deposition process step may include filling the via hole with a dielectric material (eg, an insulating material). In some cases, a CMP process or an etch-back process may be used to remove additional dielectric material on top of the stack 405 . Figure 4KA via hole filled with a dielectric material (e.g., dielectric plug 444-a, dielectric plug 444-b) is depicted that separates semiconductor material 480-a at an upper D1 layer from semiconductor material 480-b at a lower D1 layer. Semiconductor material (e.g., semiconductor material 480-a) at a first layer (e.g., D1 layer of stack 405) may surround the dielectric plug (e.g., dielectric plug 444-b). Furthermore, a gate electrode (e.g., electrode material 461-b1, electrode material 461-b2) at a second layer (e.g., DM layer of stack 405) may surround the dielectric plug (e.g., dielectric plug 444-b). Additionally, an oxide material (e.g., oxide material 470-e) may be located between the semiconductor material (e.g., semiconductor material 480-a) and the gate electrode (e.g., electrode material 461-b1). Figure 4L The structural features depicted in Fig. 4I The structural features described in Figure 4L The structural features depicted in FIG. 1 are positioned away from the via hole, for example, the etching process steps and the deposition process steps do not affect the Figure 4L The structural features described in .

[0121] Figure 4M The fourth channel group (eg Figure 4M 4 is a top view of the stack 405 after at least one etching process step is performed on the vias 440-e to 440-i as depicted as dot-filled square vias. Some vias of the fourth group (e.g., vias 440-e and 440-f) are adjacent to via cavities filled with semiconductor material (e.g., via cavity 442-a filled with semiconductor material 480), as shown in FIG. Figures 4J to 4L described. Figure 4N Explain the traverse after the etching process step Figure 4M 4 is a cross-sectional side view of the stack 405 shown in dashed line AA. Similarly, Fig.4O Explain the traverse after the etching process step Figure 4M 4 is a cross-sectional side view of the stack 405 shown in dashed line BB.

[0122] In some cases, the etching process step may include an anisotropic etching process that removes various materials along a vertical direction (e.g., along a vertical direction relative to a horizontal substrate) to form via holes corresponding to the fourth via group, such as via holes 441-e to 441-i corresponding to vias 440-e to 440-i, respectively. In some cases, the various materials that the anisotropic etching process may remove include the HM layer (top layer) and the D1 layer of the stack 405, the insulating layer 465, the electrode material 461, and the D2 layer of the stack 405. In some cases, the anisotropic etching process may stop at the bottom layer of the stack 405, such as Figure 4N As shown in . Fig.4OThe structural features depicted in Figure 4L The structural features described in Fig.4O The structural features depicted in FIG. 1 are positioned away from the third via hole group (eg, via holes 441 - e to 441 - i), for example, the anisotropic etching process does not affect Fig.4O The structural features described in .

[0123] Figure 4P The description uses the method corresponding to the fourth path group (eg Figure 4P 4 and 5. The vias depicted as dot-filled square vias in FIG. 4 include via holes (eg, via holes 441-e to 441-i) from via 440-e to via 440-i to perform at least one etching process step (eg, as shown in FIG. 4) on stack 405. Figure 4M and 4N A top view of stack 405 after being described). Figure 4Q Explain the traverse after the etching process step Figure 4P 4 is a cross-sectional side view of the stack 405 shown in dashed line AA. Similarly, Figure 4R Explain the traverse after the etching process step Figure 4P 4 is a cross-sectional side view of the stack 405 shown in dashed line BB.

[0124] In some cases, the etching process step may include a first isotropic etching process. The first isotropic etching process may selectively remove a portion of the first dielectric material at the D1 layer to create a cavity (eg, cavity 442-e, cavity 442-f), such that the cavity may expose the array electrode 450 at the D1 layer, as shown in FIG. Figure 4P and 4R In addition, Figures 4P to 4R Two or more cavities may be adjacent to form a channel (eg, channel 443-a). In some cases, the etching process may include a second isotropic etching process. The second isotropic etching process may selectively remove the exposed array electrodes 450 (eg, array electrodes 450-d1, array electrodes 450-d2) at the D1 layer, such as Figure 4P and 4R Described in.

[0125] In some cases, the etching process step can remove any exposed oxide material 470 (e.g., gate oxide) while removing portions of the dielectric material at the D1 layer or the exposed array electrodes 450 at the D2 layer. The etching process can leave substantially intact semiconductor material (e.g., semiconductor material 480). Additionally, the etching process can leave substantially intact the second dielectric material of the D2 layer of the stack 405. Figure 4RThe etching process step is depicted extending the cavity to reach the array electrode 450 at the D1 layer and removing a portion of the array electrode (eg, array electrode 450 - d1 , array electrode 450 - d2 ), while the semiconductor material remains substantially intact.

[0126] In some cases, at least via 440-g (which may be used to form a second electrode of a transistor, such as Figure 4Y to 4AA ), an etching process step (e.g., a first isotropic etching process) may form a second cavity (e.g., channel 443-a1) at the first layer (e.g., D1 layer), so that a portion of the third electrode (e.g., electrode 450-d) and the semiconductor material (e.g., semiconductor material 480-a, semiconductor material 480-c) may be exposed. In addition, using at least a third via (e.g., via 440-i), an etching process step (e.g., a first isotropic etching process) may form a third cavity (e.g., cavity 442-e1) at the first layer, so that the semiconductor material (e.g., semiconductor material 480-c) may be exposed.

[0127] Figure 4S The description uses the method corresponding to the fourth path group (eg Figure 4S 4. The vias depicted as dot-filled squares in FIG. 4 include via holes (e.g., via holes 441-e to 441-i) from via 440-e to via 440-i to perform at least one first deposition process step and a second deposition process step (e.g., as shown in FIG. 4). Figures 4P to 4R A top view of stack 405 after being described). Figure 4T Explain the traversal after the first deposition process step and the second deposition process step Figure 4S 4 is a cross-sectional side view of the stack 405 shown in dashed line AA. Similarly, Figure 4U Explain the traversal after the first deposition process step and the second deposition process step Figure 4S 4 is a cross-sectional side view of the stack 405 shown in dashed line BB.

[0128] In some cases, the first deposition process step may include selectively forming an insulating layer 466 over the exposed surface of the electrode material 461, such as Figure 4N and 4Q In some cases, the insulating layer 466 may be a reference Figures 3A to 3L An example of an insulating layer 365 is depicted. The insulating layer 466 can provide electrical isolation between the electrode material 461 (eg, upper level gate electrode 460 including electrode material 461-a1, lower level gate electrode 460 including electrode material 461-a2) and the ohmic material deposited during the second deposition process step.

[0129] In some cases, the second deposition process step may include using an ohmic material 475 (which may be a reference Figures 3A to 3L375) to fill the cavities and channels formed in the stack 405 (eg, reference Figures 4P to 4R The cavity 442 and channel 443 described above). Figure 4S A top view illustrating cavities and channels filled with ohmic material 475 (eg, ohmic material 475 - a , ohmic material 475 - b , ohmic material 475 - c ). Figure 4T and 4U A cross-sectional side view of a cavity and a channel filled with an ohmic material 475 (eg, ohmic material 475 - a , ohmic material 475 - b , ohmic material 475 - c ) is illustrated. In addition, Figure 4U The semiconductor material (eg, semiconductor material 480 - a1 ) is in contact with the ohmic material (eg, ohmic material 475 - a1 ), and the ohmic material is in contact with the array electrode (eg, array electrode 450 - d1 ). Figure 4Y and 4Z It is described that when the TFT is fully constructed, the combination of the semiconductor material, the ohmic material and the array electrode can form a current path of the TFT, and the current path is along a horizontal direction (eg, a parallel direction relative to a horizontal substrate).

[0130] In some cases, the second deposition process step may use an ohmic material (eg, ohmic material 475-b1, ohmic material 475-c1) to fill the second cavity (eg, reference 475) at the first layer (eg, D1 layer). Figure 4Q and 4R The channel 443-a1 described above and the third chamber (eg, reference Figure 4Q and 4R Cavity 442-e1) is described.

[0131] Figure 4V The fourth via group (eg, Figure 4V The vias depicted as dot-filled squares in FIG. 4 include vias 440-e to 440-i) perform at least one etching process step and a deposition process step (as shown in FIG. Figure 4S to 4U A top view of stack 405 after being described). Figure 4W Explain the traversal after the etching process step and the deposition process step Figure 4V 4 is a cross-sectional side view of the stack 405 shown in dashed line AA. Similarly, Figure 4X Explain the traversal after the etching process step and the deposition process step Figure 4V 4 is a cross-sectional side view of the stack 405 shown in dashed line BB.

[0132] In some cases, the etching process may include an anisotropic etching process that removes the ohmic material in a vertical direction (e.g., a vertical direction relative to a horizontal substrate). Due to the etching process that removes the ohmic material, via holes (e.g., via holes 441-e to 441-i corresponding to vias 440-e to 440-i, respectively) may be formed to separate the ohmic material at the upper D1 layer (e.g., ohmic material 475-a1, ohmic material 475-c1) from the ohmic material at the lower D1 layer (e.g., ohmic material 475-a2, ohmic material 475-c2). Subsequently, a deposition process may fill the via holes with a dielectric material. Figure 4W Via holes (eg, via holes 441 - e to 441 - i) filled with dielectric material are illustrated. Additional dielectric material over the HM layer of stack 405 may be removed by a CMP process or an etch-back process. Figure 4X The structural features depicted in Figure 4U The structural features described in Figure 4X The structural features depicted in FIG. 1 are positioned away from the third via hole group (eg, via holes 441 - e to 441 - i), for example, the anisotropic etching process and the subsequent deposition process will not affect Figure 4X The structural features described in .

[0133] Figure 4Y The fifth group of vias (eg, vias depicted as dark gray squares, including via 440-g) that have been filled with dielectric material are illustrated as performing at least one etching process step and a deposition process step (as shown in FIG. 4A ). Figure 4V to 4X A top view of stack 405 after being described). Figure 4Z Explain the traversal after the etching process step and the deposition process step Figure 4Y 4 is a cross-sectional side view of the stack 405 shown in dashed line AA. Similarly, Figure 4AA Explain the traversal after the etching process step and the deposition process step Figure 4Y 4 is a cross-sectional side view of the stack 405 shown in dashed line BB.

[0134] In some cases, the etching process step may include an anisotropic etching process. The anisotropic etching process may remove dielectric material from a via hole (e.g., via hole 441-g corresponding to via 440-g). In addition, the anisotropic etching process may selectively remove a portion of a bottom layer (e.g., an etch stop layer, an HM layer) of stack 405 to form a hole (e.g., opening 441-j) through the bottom layer of stack 405. In some cases, the width of opening 441-j may be substantially the same as the width of opening 441-g. Opening 441-j may be coupled to a conductive element 485 that may be part of a logic circuitry layer. For example, conductive element 485 may represent a node of a circuitry in a substrate (e.g., a row decoder 120 constructed in substrate 204). In another example, conductive element 485 may be coupled to a node of row decoder 120 (e.g., a node where a select signal is present) to activate one or more levels of the array layer. In some cases, the etching process step may include an isotropic etching process that may follow the anisotropic etching. The isotropic etching process may selectively remove the ohmic material exposed in the via hole, such as the ohmic material at the recessed etching D1 layer (eg, ohmic material 475 - b1 , ohmic material 475 - b2 ).

[0135] In some cases, the deposition process may use electrode material 495 (which may be reference Figures 3A to 3L The via hole (e.g., via hole 441-g) may be filled with an example of electrode material 395 as described above. Additional electrode material 495 above a top layer (e.g., HM layer) of stack 405 may be removed by a CMP process or an etch-back process. As a result of using electrode material 495 to fill the via hole (e.g., to form conductive plug 496), conductive element 485 (e.g., a node associated with a logic circuitry layer) may be coupled with an ohmic material (e.g., ohmic material 475-b1), as shown in FIG. Figure 4Z In some cases, conductive plug 496 (eg, via hole 441-g corresponding to via 440-g, which has been filled with electrode material 495) can serve as a second electrode of the TFT. Figure 4AA The structural features depicted in Figure 4X The structural features described in Figure 4AA The structural features depicted in FIG. 1 are positioned away from the fifth via group, for example, the etching process and the subsequent deposition process will not affect Figure 4AA The structural features described in .

[0136] As referenced in this article Figure 4Y to 4AAAs illustrated, the conductive element 485 may be coupled to an ohmic material (e.g., ohmic material 475-b1, ohmic material 475-b2), which is in contact with a semiconductor material (e.g., semiconductor material 480-a1, semiconductor material 480-a2). The semiconductor material (e.g., semiconductor material 480-a1, semiconductor material 480-a2) is in contact with an ohmic material (e.g., ohmic material 475-a1, ohmic material 475-b2), which is in contact with an array electrode (e.g., array electrode 450-d1, array electrode 450-d2), as shown. Figure 4AA In this way, a current path between the conductive element 485 and the array electrode (e.g., array electrode 450-d1, array electrode 450-d2) can be established based on a voltage applied to the gate electrode (e.g., upper-level gate electrode 460 including electrode material 461-a1, lower-level gate electrode 460 including electrode material 461-a2) to form a current path that allows current to flow (e.g., Figure 4Y and 4Z An active channel within a semiconductor material (eg, semiconductor material 480 - a1, semiconductor material 480 - a2) of the semiconductor material 480 - a1 or 480 - a2.

[0137] Figure 4Y to 4AA Explain various features of planar TFTs. For example, Figure 4Z The planar TFT depicted in may include a dielectric plug (e.g., dielectric plug 444-a, dielectric plug 444-b) extending through a stack including a first layer and a second layer (e.g., stack 405 including a D1 layer and a DM layer). The planar TFT may also include a semiconductor material (e.g., semiconductor material 480-a1) at a first layer surrounding the dielectric plug (e.g., dielectric plug 444-a). In addition, the planar TFT may include a gate electrode (e.g., electrode material 461-a1 forming gate electrode 460-a) at a second layer surrounding the dielectric plug (e.g., dielectric plug 444-a). In addition, the planar TFT may include an oxide material (e.g., oxide material 470-a) between the semiconductor material 480-a1 and the gate electrode (e.g., electrode material 461-a1 forming gate electrode 460-a).

[0138] Figure 4Z The planar TFT depicted in FIG. 1 may include a conductive plug (e.g., conductive plug 496) extending through the stack and an ohmic material (e.g., ohmic material 475-b1, ohmic material 475-b2) at a first layer surrounding the conductive plug. The ohmic material (e.g., ohmic material 475-b1) surrounding the conductive plug contacts a semiconductor material (e.g., semiconductor material 480-a1) surrounding a dielectric plug (e.g., dielectric plug 444-a), as shown in FIG. Figure 4Y to 4AAThe planar TFT may also include a second dielectric plug (e.g., dielectric plug 444-b) extending through the stack, and the semiconductor material (e.g., semiconductor material 480-a1) at the first layer surrounding the dielectric plug (e.g., dielectric plug 444-a) includes a first segment of the semiconductor material, and the ohmic material (e.g., ohmic material 475-b1) surrounding the conductive plug (e.g., conductive plug 496) is in contact with a second segment of the semiconductor material (e.g., semiconductor material 480-b1) surrounding the second dielectric plug (e.g., dielectric plug 444-b), as shown in FIG. Figure 4Y to 4AA Described in.

[0139] Figures 5A to 5N Exemplary manufacturing techniques according to the present disclosure are described. Figures 5A to 5N Aspects of several process steps for simultaneously constructing two or more TFTs (e.g., TFTs that may be referred to as wraparound TFTs and in which current flows in a direction along the outer surface of a gate electrode when the TFT is activated) are described. In some cases, such TFTs may be fabricated in a socket region of an array layer, as described herein. Figures 5A to 5N A top view of a portion of a socket area is included (eg, a layout of the socket area) to illustrate various structures in which TFTs may be constructed simultaneously using different via groups. Figures 5A to 5N A cross-sectional side view of a portion of the socket area is also included to illustrate aspects of process features during several process steps used to simultaneously construct the TFT.

[0140] Figures 5A to 5N Instructions for constructing a composite stack (e.g., reference Figures 3A to 3L The stack 305 described for constructing a vertical TFT, reference Figures 4A to 4AA The exemplary fabrication techniques for constructing a wraparound TFT within a stack 405 of planar TFTs described herein are described. Thus, the composite stack can be used to construct a vertical TFT, a planar TFT, a wraparound TFT, or any combination thereof, in a socket region of an array layer. The composite stack can also be used to construct a 3D cross-point array of memory cells and associated electrodes in an active array region of an array layer as described herein. In this manner, the composite stack can provide an array layer that each includes a memory cell layer and an electrode, wherein the electrode (and therefore the memory cell) can be further coupled to a TFT (e.g., a vertical TFT, a horizontal TFT, a wraparound TFT, or any combination thereof).

[0141] Figure 5A A top view of a stack 505 illustrating a socket region including two or more TFTs (e.g., wraparound TFTs) may be constructed as described herein. As an example, Figure 5ATwo groups of TFTs are described, each of which includes two TFT subgroups. Each group of TFTs can drive a single group of array electrodes. In addition, each group of TFTs can include a first TFT subgroup coupled to a first node associated with a logic circuit system layer and a second TFT subgroup coupled to a second node associated with the logic circuit system layer. In some cases, the first node can correspond to a node of a first circuit configured to supply current to an activated memory cell level. Thus, the first node can be referred to as a selection node and the first circuit can be referred to as a selection driver. In some cases, the second node can correspond to a node of a second circuit configured to maintain a leakage current associated with one or more deactivated memory cell levels below a threshold. Thus, the second node can be referred to as an inhibition node and the second circuit can be referred to as an inhibition driver. Figure 5N Further aspects of TFT operation are described.

[0142] Stack 505 can be used as a reference Figures 3A to 3L An example of a stack 305 is described. Figure 5A A set of vias 540 (depicted as white squares, squares with ×, squares with ○) in an array pattern is illustrated. The set of vias 540 may be formed through a top layer (e.g., layer 310, HM layer) of the stack 505 including a first layer (e.g., layer 315, D1 layer), a second layer (e.g., layer 320, DM layer) and a third layer (e.g., layer 325, D2 layer). The set of vias 540 may be a reference Figures 3A to 3L An example of a set of pathways 340 is depicted. Figure 5A It is also illustrated that different via groups can be used to simultaneously form various structures within stack 505. For example, Figure 5A A set of gate electrodes 560 of a TFT (which may be a reference Figures 3A to 3L An example of a gate electrode 360 ​​described above), a set of array electrodes 550 (which may be reference Figures 3A to 3L An example of an array electrode 350 is described), each of which may be formed at a different junction of the process sequence used to construct the TFT.

[0143] A set of gate electrodes 560 (eg, gate electrodes 560-a through 560-d) may be constructed using a first subset of vias (eg, first group of vias 540-a), as described herein with reference to Figures 3C to 3F As described elsewhere. In addition, as described elsewhere, a set of array electrodes 550 (e.g., array electrodes 550-a to 550-j) may be constructed using vias depicted as squares with x's. In addition, a set of electrode sheets (e.g., electrode sheet 555-a, electrode sheet 555-b) may be constructed using vias depicted as squares with o's. In some cases, the second set of vias may include vias depicted as squares with x's and vias depicted as squares with o's. As described elsewhere. Figure 5AAs depicted in FIG. 1 , each electrode sheet (e.g., electrode sheet 555-a) can connect two array electrodes (e.g., electrode 550-a and electrode 550-c), and thus, the array electrode group can include the electrode sheet group. In some cases, the array electrode can serve as the second electrode of the TFT. In addition, a third via (e.g., via 540-b1, via 540-b2) can be used to construct a conductive plug, as described herein with reference to Figure 5L and 5M In some cases, the conductive plug can serve as a third electrode of the TFT and the conductive plug (eg, third electrode) can extend at least through the third layer (eg, layer 325, D2 layer of stack 305). Figure 5A Also illustrated is a third group of vias (eg, vias 540 - c1 , 540 - c2 , 540 - c3 ) formed through the top layer of stack 505 .

[0144] Figures 5B to 5M A cross-sectional side view may correspond to Figure 5A The dashed line AA in FIG. extends through the socket area of ​​fourteen (14) vias. For example, Figure 5B The 14 vias (e.g., vias depicted as white or gray squares, vias depicted as squares with ×, vias depicted as squares with ○) above the cross-sectional side view of stack 505 are illustrated to match various structural features (e.g., via holes, via cavities, trenches (i.e., adjacent via cavities), dielectric plugs, conductive plugs) formed within stack 505 using one or more specific vias to form such structural features in stack 505. Additionally, arrows are added to indicate one or more specific vias at different junctions of the process sequence used to construct the TFT.

[0145] Figure 5B A cross-sectional side view of stack 505 is illustrated after forming via holes (e.g., vias corresponding to the vias indicated by arrows) using a third group of vias (e.g., vias 540-c1, 540-c2, 540-c3). In some cases, an anisotropic etching process may form the via holes, as described herein. Figure 5B It is also explained that the electrode material 561 (which may be a reference) may have been previously formed in the second layer (eg, DM layer) of the stack 505. Figures 3A to 3L Examples of electrode materials 361 described herein) as referenced herein Figures 3C to 3F described. Figure 5B The electrode material 561 depicted in FIG. Figure 5A In the gate electrode 560 depicted in FIG. 1 , for example, electrode material 561 - a forms gate electrode 560 - a , and electrode material 561 - b forms gate electrode 560 - b . Figure 5B The insulating layer 565 (which may be a reference Figures 3A to 3LAn example of an insulating layer 365 is depicted) that partially surrounds the electrode material 561. Figure 5B It is also described that the electrode sheets (eg, electrode sheets 555 - a , electrode sheets 555 - b ) may have been formed in advance in the first layer (eg, D1 layer) of the stack 505 .

[0146] Figure 5C The method of performing at least one etching process step (such as referring to FIG. 1 ) using via holes (such as via holes corresponding to vias indicated by arrows) that have been formed using the third via group (such as vias 540-c1, 540-c2, and 540-c3) is described. Figure 5B 542-a1, via cavity 542-a2, via cavity 542-a3). Via cavity 542 may span a first layer (e.g., D1 layer in which array electrode 550 is present), a second layer (e.g., DM layer in which gate electrode 560 is present), and a third layer (e.g., D2 layer). In addition, via cavity (e.g., via cavity 542-b1, via cavity 542-b2) may expose array electrodes (e.g., array electrodes 550-k1, array electrodes 550-k2). Additionally, the via cavity 542 may expose the insulating layer 565 conforming to the gate electrode 560 .

[0147] Figure 5D The method of performing at least one etching process step (such as referring to FIG. 1 ) using the formed third via group (such as via 540-c1, via 540-c2, via 540-c3) and the corresponding via holes and via cavities is described. Figure 5C 5. In some cases, the etching process step may include an isotropic etching process that selectively removes the array electrodes at the D1 layer exposed to the isotropic etching process (e.g., referring to Figure 5C The isotropic etching may leave other materials (e.g., materials other than the array electrodes at the D1 layer) exposed in the via holes and via cavities substantially unchanged, such as the insulating layer 565, the electrode material 561, the first dielectric material at the first layer, the placeholder material at the second layer, and the second dielectric material at the third layer.

[0148] Figure 5EThe method of performing at least one etching process step and a deposition process step (using reference 540) using the formed third via group (eg, via 540-c1, via 540-c2, via 540-c3) and corresponding via holes and via cavities is described. Figure 5D 5. A cross-sectional side view of the stack 505 after the deposition process step (described in detail in the drawings) is shown. In some cases, the etching process step may include an isotropic etching process that selectively removes a portion of the insulating layer 565 in contact with the gate electrode. The isotropic etching may leave other materials exposed in the via hole and the via cavity (e.g., materials other than the insulating material at the DM layer) substantially unchanged, such as the electrode material 561 that forms the gate electrode 560, the first dielectric material at the first layer, the placeholder material at the second layer, and the second dielectric material at the third layer. In some cases, the deposition process step may form an oxide material 570 (which may be a reference to the oxide material 570) in contact with the gate electrode. Figures 3A to 3L 3. An example of oxide material 370 is described herein.) In some cases, the oxide material may be referred to as a gate oxide of the TFT.

[0149] Fig. 5F The method of performing at least one deposition process step (using reference 5) using the formed third via group (eg, via 540-c1, via 540-c2, via 540-c3) and corresponding via holes and via cavities is described. Figure 5D 505 after the deposition process step may use semiconductor material 580 (which may be a reference Figures 3A to 3L The semiconductor material 580 may be in contact with the oxide material 570, and the oxide material 570 may be in contact with the gate electrode, as shown in FIG. Figure 5E described.

[0150] Figure 5G A cross-sectional side view of the stack 505 is illustrated after performing at least one etching process step and a deposition process step using a fourth group of vias (eg, a fourth set of vias including the vias indicated by arrows). Figure 5A , the fourth via group may include vias shared by the first via group (e.g., via 540-a1, via 540-a2, via 540-a3, via 540-a4) and the third via group (e.g., via 540-c1, via 540-c2, via 540-c3). In some cases, the etching process step may include an anisotropic etching process to remove the semiconductor material 580 that has filled the via hole and the via cavity, as shown in reference Fig. 5FThe anisotropic etching process may remove the semiconductor material 580 in a vertical direction (e.g., a vertical direction relative to a horizontal substrate) to form via holes corresponding to the fourth via group (e.g., via holes to be later filled with a dielectric material). Removing the semiconductor material 580 within the via holes corresponding to the fourth via group may remove the parasitic current path having a shorter channel length of the TFT, so that the main current path of the TFT may have a longer channel length, as described in reference to FIG. Figure 5M In some cases, the deposition process step may fill the via hole with a dielectric material. In some cases, the via hole filled with a dielectric material may be referred to as a dielectric plug (e.g., dielectric plug 544-a, dielectric plug 544-b) that extends through a gate electrode (e.g., gate electrode 560-a including electrode material 561-a).

[0151] Figure 5H A cross-sectional side view of stack 505 is illustrated after performing at least one etching process step using a fifth via group (eg, a fifth via group including the via indicated by the arrow). Figure 5A , the fifth via group may include via 540-e (e.g., via 540-e1 including via 540-b1, via 540-e2 including via 540-b2, via 540-e3, via 540-e4). In some cases, the etching process may include an anisotropic etching process that removes a first dielectric material of a first layer (e.g., D1 layer), a placeholder material of a second layer (e.g., DM layer), and a second dielectric material of a third layer (e.g., D2 layer) (e.g., forming a via hole corresponding to via 540-b1). The anisotropic etching process may also remove dielectric material that has filled via holes used to form array electrodes (e.g., via holes corresponding to vias depicted as squares with × (which include via 540-b2)). The anisotropic etching process may leave other materials exposed in the via holes substantially unchanged, such as insulating layer 565.

[0152] In some cases, the etching process step may further include an isotropic etching process that selectively removes the first dielectric material of the first layer (e.g., D1 layer). The isotropic etching process may leave other materials exposed in the via hole substantially unchanged, such as the placeholder material of the second layer (e.g., DM layer), the second dielectric material of the third layer (e.g., D2 layer), and the insulating layer 565. The isotropic etching process using the fifth via group (e.g., the fifth via group including vias 540-b1, 540-b2) may form via cavities (e.g., via cavities 542-c1, 542-c2) to expose the semiconductor material (e.g., semiconductor material 580-a) and the second electrode (e.g., electrode pads 555-a1, 555-a2) of the TFT at the first layer (e.g., D1 layer).

[0153] Fig.5I A cross-sectional side view of stack 505 after performing at least one deposition process step using via holes formed based on a fifth set of vias (e.g., a fifth set of vias including the vias indicated by arrows). In some cases, the deposition process step may use ohmic material 575 (which may be reference Figures 3A to 3L The example of the ohmic material 375 described above) is used to fill the reference Figure 5H The via cavities described (e.g., via cavities 542-c1, 542-c2) allow the ohmic material (e.g., ohmic material 575-a) to contact the semiconductor material (e.g., semiconductor material 580-a) and the second electrode (e.g., array electrode 555-a1). The extra ohmic material on the top of the stack 505 can be removed using a CMP process or an etch-back process.

[0154] Figure 5J A cross-sectional side view of stack 505 after performing at least one etching process step and a deposition process step using a fifth group of vias (e.g., a fifth group of vias including vias indicated by arrows). In some cases, the etching process step may include an anisotropic etching process that may remove a portion of the ohmic material along a vertical direction (e.g., a vertical direction relative to a horizontal substrate) to form a via hole (e.g., a via hole corresponding to the fifth group of vias). The anisotropic etching process may leave other materials exposed in the via hole substantially unchanged, such as a placeholder material of the second layer (e.g., the DM layer), a second dielectric material of the third layer (e.g., the D2 layer), and insulating layer 565. In some cases, after the anisotropic etching process, a deposition process step using the via hole (e.g., the via hole corresponding to the fifth group of vias) may form and maintain a via cavity (e.g., via cavity 542-c1 that has been filled with the ohmic material, as shown in reference Fig.5I Insulating material 566 that contacts an ohmic material (eg, ohmic material 575-a1, ohmic material 575-a2) within the ohmic material (described above). In some cases, insulating material 566 may be a reference Figures 3A to 3L Examples of materials that may form insulating layer 365 are described. In some cases, the deposition process step may include a selective deposition process that may deposit insulating material 566 only on exposed surfaces of ohmic material 575.

[0155] Figure 5K The method of performing at least one etching process step (such as referring to FIG. 1 ) using via holes formed based on a fifth set of vias (such as a fifth set of vias including vias indicated by arrows) is described. Figure 5J542-d) after the stack 505 is formed. In some cases, the etching process step may include an isotropic etching process, which may selectively remove the second dielectric material at the third layer (e.g., D2 layer). The isotropic etching process may leave other materials exposed in the via hole (e.g., materials other than the second dielectric material of the D2 layer) substantially unchanged, such as insulating material 566, insulating layer 565, semiconductor material 580, and placeholder material at the second layer (e.g., DM layer). Due to the isotropic etching process, a via cavity (e.g., via cavity 542-d) may be formed so that the semiconductor material 580-a may be exposed to subsequent process steps.

[0156] Figure 5L A cross-sectional side view of stack 505 after performing at least one deposition process step and an etching process step using a fifth set of vias (e.g., a fifth set of vias including the vias indicated by arrows). In some cases, the deposition process step can fill via holes (e.g., via holes corresponding to the fifth set of vias) with an ohmic material. The ohmic material can also fill via cavities (e.g., reference 1 to the via holes) formed at a third layer (e.g., D2 layer). Figure 5K 542-d) as described, such that an ohmic material (e.g., ohmic material 575-b) can be in contact with semiconductor material 580-a. In some cases, the etching process step can include an anisotropic etching process that can remove a portion of the ohmic material from the via hole in a vertical direction (e.g., a vertical direction relative to a horizontal substrate). In some cases, the anisotropic etching process can produce a hole (e.g., opening 541-a) at a bottom layer (e.g., layer 330) of stack 505. The hole can be coupled to a conductive element (e.g., conductive element 585-a to conductive element 585-d) that can be part of a logic circuit system layer. In some cases, conductive element 585-a can be coupled to an inhibit node of an inhibit driver. In some cases, conductive element 585-b can be coupled to a select node of a select driver.

[0157] Figure 5M 5. A cross-sectional side view of stack 505 is shown after performing at least one deposition process step using a fifth set of vias (e.g., a fifth set of vias including the vias indicated by arrows). In some cases, the deposition step may fill via holes (e.g., via holes corresponding to the fifth set of vias) and holes (e.g., reference 5) at the bottom layer with electrode material 595. Figure 5L The via hole filled with electrode material 595 may be referred to as a conductive plug (e.g., conductive plug 596). The conductive plug may couple the conductive element 585 with the semiconductor material of the TFT (e.g., semiconductor material 580-a) through an ohmic material (e.g., ohmic material 575-b) and may complete the construction of the TFT.

[0158] In some cases, Figure 5M The TFT described in can include a conductive plug extending through a stack, the stack including a first layer, a second layer, and a third layer, a gate electrode at the second layer, a second electrode at the first layer, and semiconductor materials at the first and second layers, the semiconductor material being coupled to the second electrode via a first segment of the ohmic material at the first layer and coupled to the conductive plug via a second segment of the ohmic material at the third layer. In some cases, the semiconductor material at the first and second layers extends into the third layer. In some cases, the TFT can include a dielectric plug extending through the gate electrode.

[0159] Figure 5M Two groups of TFTs (e.g., first group of TFTs 535-a, second group of TFTs 535-b) are illustrated. Each group of TFTs may include a first subgroup of TFTs (e.g., a subgroup of TFTs including an upper TFT and a lower TFT) coupled to a first node associated with the logic circuitry layer (e.g., via a conductive element 585-a coupled to an inhibit node of an inhibit driver) and a second subgroup of TFTs (e.g., a subgroup of TFTs including an upper TFT and a lower TFT) coupled to a second node associated with the logic circuitry layer (e.g., via a conductive element 585-b coupled to a select node of a select driver). As shown in reference Figure 5N As described, each group of TFTs can drive (e.g., activate, inhibit) a single group of array electrodes (e.g., array electrode 550-a1 connected to array electrode 550-d1 in the upper layer, array electrode 550-a2 connected to array electrode 550-d2 in the lower layer). In some cases, the two groups of TFTs can be processed in different ways to adapt their operating characteristics accordingly, for example, the first TFT subgroup can be processed to provide low leakage current characteristics within a specific operating voltage range and the second TFT subgroup can be processed to provide high drive current characteristics.

[0160] Figure 5M The current paths (e.g., current paths 545-a, current paths 545-b) of the TFTs (e.g., the upper TFTs of the first group of TFTs 535-a) are also illustrated. The current paths illustrate how a particular TFT can couple a node of the logic circuitry layer with an array electrode to access memory cells in an active array region of the array layer when the TFT is activated. For example, the conductive element 585-b can be coupled with a select node of a select driver. The conductive element 585-b is coupled with a conductive plug 596 that can serve as a common source of the TFTs (e.g., the upper TFTs and the lower TFTs of the second TFT subset of the first group of TFTs 535-a). The conductive plug 596 contacts the semiconductor material 580-b through the ohmic material 575-c. The semiconductor material 580-b can form an active channel that allows current to flow based on a voltage applied to the gate electrode 560 (e.g., the gate electrode 560-b1 including the electrode material 561-b1).

[0161] In addition, semiconductor material 580-b is connected to array electrode 555-a1 through ohmic material 575-b1. Array electrode 555-a1 can serve as a common drain of the upper TFTs of the first group of TFTs 535-a. In this way, when an active channel is formed in the semiconductor material (e.g., semiconductor material 580-b) (when a voltage applied to a gate electrode (e.g., gate electrode 560-b1 including electrode material 561-b1) is greater than a threshold voltage of the upper TFT and when there is a voltage difference between the source (which is coupled to a node of the logic circuit system layer) and the drain (which is coupled to the array electrode) of the upper TFT), current can flow (e.g., current path 545-b) between the source and drain of the upper TFT (e.g., the upper TFT of the second TFT subset of the first group of TFTs 535-a).

[0162] Similarly, when another current path (e.g., current path 545-a) is activated (e.g., when the upper TFT of the first TFT subgroup of the first group of TFTs 535-a is activated), the array electrode 555-a1 can be coupled with the conductive element 585-a, which can be coupled with a different node (e.g., the inhibition node) of the logic circuit system layer. In this way, the array electrode (e.g., the array electrode 555-a1 in the upper layer) can be coupled with two or more nodes (e.g., the inhibition node, the selection node) of the logic circuit system layer using the upper TFT of the first group of TFTs 535-a. More generally, one of the four TFTs of the first group of TFTs 535-a can be activated to couple a node of the logic circuit system layer (e.g., the selection node or the inhibition node connected to the source of the TFT) with the array electrode (e.g., the array electrode connected to the drain of the TFT).

[0163] The current flowing in the TFT flows in a manner surrounding the gate electrode and the TFT may be called a wraparound TFT. Figure 5M As described in FIG. 1 , the channel length of the wraparound TFT (eg, the distance between the source and drain of the TFT) may be greater than that of the vertical TFT (eg, the distance between the source and drain of the TFT). Figure 3K described) or horizontal TFT (as described in reference Figure 4Z This increased channel length can benefit some aspects of TFT operation, such as being less susceptible to leakage current problems related to channel length.

[0164] Figure 5N A top view illustrating a stack 505 in which the socket area includes two sets of TFTs (eg, wrap-around TFTs), as described herein. Figure 5M The cross-sectional side view may correspond to a cross-sectional side view in which the dashed line AA extends (eg Figure 5N Socket area shown in . Figure 5NAspects of structural features that have been constructed using the manufacturing techniques described herein are described. For example, Figure 5N The bulk region 581 of the TFT (eg, the bulk region 581 - a including the semiconductor material 580 - a ) is depicted. The bulk region 581 may correspond to the reference Figure 5A and 5F A third group of vias is depicted (eg, bulk region 581-a corresponds to the third group of vias 540-c1).

[0165] Figure 5N The fifth via group is also depicted as squares with horizontal lines (e.g., a via including via 540-b1) or squares with vertical lines (e.g., a via including via 540-b2). The vias depicted as squares with horizontal lines may correspond to vias coupled to conductive element 585-a or conductive element 585-d. The vias depicted as squares with vertical lines may correspond to vias coupled to conductive element 585-b or conductive element 585-c. In some cases, conductive element 585-a (or conductive element 585-d) may be coupled to an inhibition node of an inhibition driver and conductive element 585-b (or conductive element 585-c) may be coupled to a selection node of a selection driver. Each via of the fifth via group may include an insulating material 576 (e.g., an insulating material deposited on a surface of ohmic material 575 at the D1 layer, as shown in reference to FIG. 1 ). Figure 5J A conductive plug (eg, as described) surrounded by Figure 5M However, the conductive plug may be coupled to the corresponding bulk region 581 at the second layer of the stack through an ohmic material, as shown in FIG. Figure 5M described.

[0166] Figure 5N Also depicted is an ohmic material (e.g., ohmic material 575-a) positioned between a bulk region (e.g., bulk region 581-a) and an electrode pad (e.g., electrode pad 555-a connected to array electrode 550-a and array electrode 550-d). The ohmic material provides a low resistance path for current to flow between a bulk region (e.g., where a channel for current flow may be formed) and an electrode pad (e.g., electrode pad 555-a) or a conductive plug (e.g., conductive plug 596).

[0167] Figure 5N Current paths (e.g., current path 545-e, current path 545-f) are also depicted. Current path 545-e may correspond to reference Figure 5MThe current path 545-a or current path 545-b described above. In other words, the current flow following the current path 545-a (or current path 545-b) can reach the electrode sheet 555-b and continue to flow using the array electrode 550-a and the array electrode 550-c. Similarly, the current path 545-f can correspond to the reference electrode 550-c. Figure 5M Depicted current path 545 - c or current path 545 - d .

[0168] Figure 5N It is also described that more than one TFT can be connected in series (e.g., a wraparound TFT) to provide more current than a single TFT can provide. For example, Figure 5N Depicting that array electrodes can be stitched together when an array electrode (e.g., array electrode 550-a) is connected to an electrode patch (e.g., electrode patch 555-a) which is further connected to another array electrode (e.g., array electrode 550-c). As an example, Figure 5N Depicting five (5) single TFTs connected in series into one TFT (e.g., indicated by five conductive plugs arranged in a single column connected to a single electrode sheet 555-a), which can supply four times more current than a single TFT. Any number of TFTs may be connected in series to provide any amount of current that may be needed or desired, as described herein.

[0169] Figure 5N The TFT configuration described in can facilitate providing an electrical connection dedicated to the bulk region 581. Such an electrical connection dedicated to the bulk region can benefit aspects of the TFT operation, such as avoiding problems associated with the floating body of the TFT. For example, the bulk region 581-b can be expanded to include additional rows of vias (e.g., including three rows of vias instead of one row of vias between the gate electrode 560-b and the gate electrode 560-c), so that one or more vias of the additional vias (e.g., one or more vias in the middle row of the three rows of vias) can be coupled to nodes of the logic circuit system layer using the manufacturing techniques described herein. In some cases, one or more holes (e.g., via holes corresponding to the one or more vias) can be formed through the bulk region (e.g., bulk region 581-b including semiconductor material 580) to the logic circuit system layer and the one or more holes can be formed by electrode material (e.g., reference Figure 5M The bulk region 581-a may be filled with the electrode material 595 described above to form a fourth electrode of the transistor (e.g., the base of the TFT). Additionally or alternatively, the bulk region 581-a may be expanded to include additional vias (e.g., vias located to the left boundary of the bulk region 581-a) and the additional vias may be coupled to the logic circuitry layer. In this way, the logic circuitry may provide specific voltages to the bulk region based on various operating modes of the TFT (e.g., operating in an inhibit mode or a select mode).

[0170] Figures 6A to 6RExemplary manufacturing techniques according to the present disclosure are described. Figures 6A to 6R Aspects of several process steps for simultaneously constructing two or more TFTs, such as hybrid TFTs in which current flows in a combination of vertical and horizontal directions when the TFTs are activated, are described. In some cases, such TFTs can be fabricated in a socket region of an array layer, as described herein. Figures 6A to 6R A top view of a portion of a socket area is included (eg, a layout of the socket area) to illustrate that various structures of TFTs may be constructed simultaneously using different via groups. Figures 6A to 6R A cross-sectional side view of a portion of the socket area is also included to illustrate aspects of process features during several process steps used to simultaneously construct the TFT.

[0171] Figures 6A to 6R Instructions for constructing a composite stack (e.g., reference Figures 3A to 3L The stack 305 described for constructing a vertical TFT, reference Figures 4A to 4AA The stack 405 described for constructing a planar TFT, reference Figures 5A to 5N An exemplary fabrication technique for hybrid TFTs within a stack 505) described for constructing a wraparound TFT is described. Thus, the composite stack can be used to construct a vertical TFT, a planar TFT, a wraparound TFT, a hybrid TFT, or any combination thereof in a socket region of an array layer. The composite stack can also be used to construct a 3D cross-point array of memory cells and associated electrodes in an active array region of an array layer as described herein. In this manner, the composite stack can provide array layers that each include a memory cell layer and electrodes, wherein the electrodes (and therefore the memory cells) can be further coupled to a TFT (e.g., a vertical TFT, a horizontal TFT, a wraparound TFT, a hybrid TFT, or any combination thereof).

[0172] Fig. 6A A top view of a stack 605 illustrating a socket region containing two or more TFTs (e.g., a hybrid TFT) may be constructed as described herein. As an example, Fig. 6AFour groups of TFTs are described. Each group of TFTs can drive a single group of array electrodes from one end of the array electrodes or the other end. In some cases, two groups of TFTs can drive a single group of array electrodes, such as a first group of TFTs from one end and a second group of TFTs from the other end. In addition, the first group of TFTs can couple the array electrodes to a first node associated with a logic circuit system layer and the second TFT subgroup can couple the array electrodes to a second node associated with the logic circuit system layer. In some cases, the first node can correspond to a selection node and the first circuit can be referred to as a selection driver. In some cases, the second node can correspond to an inhibition node and the second circuit can be referred to as an inhibition driver. In some cases, the two groups of TFTs can be processed in different ways to adapt their operating characteristics accordingly, for example, the first group of TFTs can be processed to provide high drive current characteristics and the second TFT subgroup can be processed to provide low leakage current characteristics within a specific operating voltage range.

[0173] Stack 605 can be used as a reference Figures 3A to 3L An example of a stack 305 is described. Fig. 6A A set of vias 640 (depicted as white squares, squares with ×, squares with ○) in an array pattern is illustrated. The set of vias 640 may be formed through a top layer (e.g., layer 310, HM layer) of the stack 605 including a first layer (e.g., layer 315, D1 layer), a second layer (e.g., layer 320, DM layer) and a third layer (e.g., layer 325, D2 layer). The set of vias 640 may be a reference Figures 3A to 3L An example of a set of pathways 340 is depicted. Fig. 6A It is also illustrated that different via groups can be used to simultaneously form various structures within stack 605. For example, Fig. 6A A set of gate electrodes 660 of a TFT (which may be a reference Figures 3A to 3L An example of a gate electrode 360 ​​described above), a set of array electrodes 650 (which may be reference Figures 3A to 3L An example of an array electrode 350 is described), each of which may be formed at a different junction of the process sequence used to construct the TFT.

[0174] A set of gate electrodes 660 (eg, gate electrodes 660-a, gate electrodes 660-b) may be constructed using a first subset of vias (eg, first group of vias 640-a), as described herein with reference to Figures 3C to 3F As described elsewhere, a set of array electrodes 650 (e.g., array electrodes 650-a to 650-d) may be constructed using vias depicted as squares with x's (e.g., the second via group). In addition, a set of electrode sheets (e.g., electrode sheets 655-a, electrode sheets 655-b) may be constructed using a subset of the second via group (e.g., vias 640-b1, vias 640-b2). Fig. 6A As depicted in FIG. 1 , each electrode sheet (eg, electrode sheet 655 - b ) may be connected to an array electrode (eg, array electrode 650 - a ), and thus, the array electrode group may include a group of electrode sheets.

[0175] In some cases, according to the manufacturing techniques described herein, a subset of array electrodes (e.g., array electrodes 650-b, array electrodes 650-c) can be cut (e.g., separated, disconnected) from the rest of the array electrodes by using a subset of vias (e.g., vias 640-x). In some cases, the array electrodes can serve as the second electrodes of the TFTs. In addition, a third via (e.g., vias 640-c1, vias 640-c2) can be used to construct a conductive plug, as described herein with reference to Figure 6P and 6Q In some cases, the conductive plug can serve as a third electrode of the TFT and the conductive plug (eg, third electrode) can extend at least through the third layer (eg, layer 325, D2 layer of stack 305). Fig. 6A Also illustrated is a third group of vias (eg, depicted as square vias with o's) formed through the top layer of stack 605.

[0176] Figures 6B to 6Q A cross-sectional side view may correspond to Fig. 6A The dashed line AA in FIG. extends through the socket area of ​​the via. For example, Figure 6B Nine (9) vias (e.g., vias depicted as white squares, vias depicted as squares with ×, vias depicted as squares with ○) above the cross-sectional side view of stack 605 are illustrated to match various structural features (e.g., via holes, via cavities, trenches (i.e., adjacent via cavities), dielectric plugs, conductive plugs) formed within stack 605 using one or more specific vias to form such structural features in stack 605. Additionally, arrows are added to indicate one or more specific vias at different junctions of the process sequence used to construct the TFT.

[0177] Figure 6B A cross-sectional side view of stack 605 is shown, as shown in FIG. Fig. 6A described. Figure 6B The electrode material 661 (which may be a reference) may have been previously formed in the second layer (eg, DM layer) of the stack 605. Figures 3A to 3L Examples of electrode materials 361 described herein) as referenced herein Figures 3C to 3F described. Figure 6B The electrode material 661 depicted in FIG. Fig. 6A , for example, the electrode material 661 - a forms the gate electrode 660 - a . Figure 6B The insulating layer 665 (which may be a reference Figures 3A to 3LAn example of an insulating layer 365 is depicted) that partially surrounds the electrode material 661. Figure 6B It is also explained that the electrode sheets (eg, electrode sheet 655 - b1, electrode sheet 655 - b2) may have been formed in advance in the first layer (eg, D1 layer) of the stack 605. In addition, Figure 6B A via hole filled with a dielectric material, which may be referred to as a dielectric plug (eg, dielectric plug 644 - a1 , dielectric plug 644 - a2 ) is illustrated extending through a gate electrode (eg, gate electrode 660 - a including electrode material 661 - a ).

[0178] Figure 6C A cross-sectional side view of stack 605 is illustrated after performing at least one etching process step using a third via group (e.g., vias indicated by arrows). In some cases, the etching process step may include an anisotropic etching process that may form via holes corresponding to the third via group (e.g., vias 641-c1 through 641-c5) as described herein, e.g., vertically removing various materials through stack 605 and stopping on a bottom layer of stack 605.

[0179] Fig.6D A cross-sectional side view of the stack 605 is shown after performing at least one etching process step using the third via group to form a via cavity 642. The via cavity 642 can be concentric with the via hole already formed in the stack 605, as shown in FIG. Figure 6C Described. In some cases, the etching scheme may include an isotropic etching process that selectively removes the first dielectric material of the first layer (e.g., D1 layer) and the second dielectric material of the third layer (e.g., D2 layer). The isotropic etching process may leave other materials exposed in the via hole, such as the placeholder material of the second layer (e.g., DM layer), the insulating layer 665, and the array electrode sheet 655. In some cases, the via cavities corresponding to two or more via holes (e.g., via hole 641-c2 to via hole 641-c4) may be merged to form a via cavity (e.g., via cavity 643). Due to the isotropic etching process, the array electrode (e.g., electrode sheet 655) is exposed to subsequent process steps. In some cases, the via cavity (e.g., via cavity 642-c1a, via cavity 642-c1b, via cavity 642-c1c) may span the first layer (e.g., D1 layer), the second layer (e.g., DM layer), and the third layer (e.g., D2 layer).

[0180] Fig. 6E A cross-sectional side view of stack 605 is shown after performing at least one deposition process step using a third group of vias (e.g., vias indicated by arrows). In some cases, the deposition process step may use ohmic material 675 (which may be reference Figures 3A to 3L375) to fill via holes (eg, via holes 641-c1 to via holes 641-c5) and associated via cavities and trenches (eg, reference Fig.6D As a result of the deposition process steps, the ohmic material 675 may be in contact with the array electrode 655.

[0181] Fig. 6F A cross-sectional side view illustrating stack 605 after performing at least one etching process step and a deposition process step using a third via group (e.g., vias indicated by arrows). In some cases, the etching process step may include an anisotropic etching process that may vertically remove ohmic material 675 in via holes (e.g., via holes corresponding to the third via group) to thereby leave ohmic material 675 (e.g., ohmic material 675-a1, ohmic material 675-a2, ohmic material 675-a3) within the via cavity. The etching process step may leave other materials exposed within the via hole, such as placeholder material of the DM layer, insulating layer 665. In some cases, the deposition process step may fill the via hole formed by the etching process step (e.g., an anisotropic etching process that has removed the ohmic material in the via hole) with an insulating material. In some cases, a CMP process or an etch-back process may be used to remove additional insulating material on top of stack 605.

[0182] Figure 6G A cross-sectional side view of the stack 605 is illustrated after performing at least one etching process step using a fourth group of vias (eg, vias indicated by arrows). Fig. 6A , the fourth channel group may include channel 640-d1 or channel 640-d2. In some cases, the fourth channel group (e.g., channel 640-d1) may include a subset of the third channel group (e.g., channels depicted as squares with ○) and a channel (e.g., channel 640-c1) that may form a third electrode of the TFT, as shown in reference Figure 6P and 6Q As described. In some cases, the etching process step may include an anisotropic etching process that can vertically remove dielectric material (or insulating material) that may be present in the via hole corresponding to the fourth via group. The anisotropic etching process can leave other materials exposed in the via hole substantially unchanged, such as the ohmic material 675, the electrode material 661 that forms the gate electrode 660, the insulating layer 665, the first dielectric material of the first layer (e.g., the D1 layer), the placeholder material of the second layer (e.g., the DM layer), and the second dielectric material of the third layer (e.g., the D2 layer). Due to the anisotropic etching process, the ohmic material 675 (e.g., the placeholder material of the reference layer 660) is removed. Fig.6D The depicted ohmic material 675 - b ) of the channel 643 may be exposed to subsequent processing steps.

[0183] Figure 6H A cross-sectional side view of stack 605 is shown after performing at least one etching process step using a fourth via group (e.g., vias indicated by arrows). In some cases, the etching process step may include an isotropic etching process that may selectively remove filled trenches (e.g., referring to Fig.6D The isotropic etching process may leave other materials exposed in the via hole and the channel substantially unchanged, such as the electrode material 661 forming the gate electrode 660, the insulating layer 665, the first dielectric material at the first layer (e.g., D1 layer), the placeholder material at the second layer (e.g., DM layer), and the second dielectric material at the third layer (e.g., D2 layer). Due to the isotropic etching process, the first dielectric material at the first layer (e.g., D1 layer) and the placeholder material at the second layer (e.g., DM layer) may be exposed to subsequent process steps.

[0184] Fig.6I A cross-sectional side view of stack 605 after performing at least one etching process step using a fourth via group (e.g., vias indicated by arrows) is illustrated. In some cases, the etching process step may include an isotropic etching process that may selectively remove a first dielectric material at a first layer (e.g., D1 layer) and a placeholder material at a second layer (e.g., DM layer). The isotropic etching process may leave other materials exposed in the via hole and the channel substantially unchanged, such as electrode material 661 that forms gate electrode 660, insulating layer 665, a second dielectric material at a third layer (e.g., D2 layer), ohmic material 675. Due to the isotropic etching process, portions of insulating layer 665 may be exposed to subsequent process steps. In some cases, using the fourth via group, the isotropic etching process may form via cavities (e.g., via cavities 642-d1, via cavities 642-d2) and channels (e.g., channel 643-a that includes two or more adjacent via cavities). Such a via cavity or channel may span a first layer (eg, D1 layer), a second layer (eg, DM layer), and a third layer (eg, D2 layer).

[0185] Figure 6J A cross-sectional side view of the stack 605 after performing at least one etching process step and a deposition process step using a fourth via group (e.g., vias indicated by arrows) is illustrated. In some cases, the etching process step may include an isotropic etching process that may selectively remove exposed portions of the insulating layer 665. The isotropic etching process may leave other materials exposed in the via hole and the trench substantially unchanged, such as the electrode material 661 that forms the gate electrode 660, the second dielectric material at the third layer (e.g., the D2 layer), and the ohmic material 675. In some cases, the deposition step may form an oxide material 670 (which may be a reference to the oxide material 670) in contact with the electrode material 661 that forms the gate electrode 660. Figures 3A to 3LIn other words, due to the etching process step and the deposition process step, the exposed portion of the insulating layer 665 can be replaced by the oxide material 670. In some cases, the oxide material 670 can be referred to as the gate oxide of the TFT.

[0186] Figure 6K A cross-sectional side view of stack 605 is shown after performing at least one deposition process step using a fourth via group (e.g., vias indicated by arrows). In some cases, the deposition process step may fill the reference 604 with semiconductor material 680. Fig.6I The via cavity or channel described (e.g., via cavity 642, channel 643). A CMP process or an etch-back process may be used to remove the additional semiconductor material on top of the stack 605. Since the via cavity or channel is filled with semiconductor material 680, the semiconductor material 680 may be in contact with the ohmic material 675 that is further connected to the array electrode (e.g., electrode sheet 655, the second electrode of the TFT). In addition, the semiconductor material 680 may be in contact with the oxide material 670 that is further connected to the gate electrode 660 (e.g., the gate electrode 660 including the electrode material 661).

[0187] Figure 6L A cross-sectional side view of stack 605 is shown after performing at least one etching process step and a deposition process step using a fourth via group (e.g., vias indicated by arrows). In some cases, the etching process step may remove the filled reference Figure 6K The semiconductor material 680 of the via cavity or channel described above is removed to form a via hole (e.g., a via hole corresponding to the fourth via group). In some cases, the deposition process step can fill the via hole with an insulating material (or dielectric material). In some cases, removing the semiconductor material 680 within the via hole corresponding to the fourth via group can remove the parasitic current path with a shorter channel length of the TFT, so that the main current path of the TFT can have a longer channel length, as shown in reference Figure 6Q In some cases, the deposition process step may fill the via hole with a dielectric material. In some cases, the via hole filled with a dielectric material may be referred to as a dielectric plug (e.g., dielectric plug 644-a, dielectric plug 644-b) extending through a gate electrode (e.g., gate electrode 660-a including electrode material 661-a). A CMP process or an etch-back process may be used to remove the additional insulating material on top of stack 605.

[0188] Figure 6M A cross-sectional side view of the stack 605 is illustrated after performing at least one etching process step and a deposition process step using a fifth group of vias (eg, vias indicated by arrows). Fig. 6A, the fifth via group may include via 640-c1 or via 640-c2. In some cases, the etching process step may include an anisotropic etching process, which may vertically remove the insulating material filled in the via hole (such as reference Figure 6L The anisotropic etching process of the fifth via group may expose the semiconductor material 680 in the via hole (e.g., via hole 641-c2 corresponding to via 640-c2) to subsequent process steps. In some cases, the deposition step may selectively grow the insulating material 690 in contact with the semiconductor material 680 at the first layer (e.g., D1 layer) and the second layer (e.g., DM layer).

[0189] Figure 6N A cross-sectional side view of the stack 605 after performing at least one etching process step using a fifth via group (e.g., vias indicated by arrows) is illustrated. In some cases, the etching process step using the fifth via group (e.g., via 640-c2) can laterally remove semiconductor material 680 at a third layer (e.g., D2 layer) to form a cavity (e.g., cavity 642-e) at the third layer. The insulating material 690 on the surface of the semiconductor material 680 can cause the semiconductor material 680 to remain at the first layer (e.g., D1 layer) and the second layer (e.g., DM layer). The etching process step can expose portions of the semiconductor material 680 to subsequent process steps.

[0190] Fig.6O A cross-sectional side view of stack 605 is shown after performing at least one deposition process step using a fifth via group (e.g., vias indicated by arrows). In some cases, the deposition process step may fill the via holes (e.g., reference 620 ) with ohmic material 675 - e. Figure 6M The via holes 641-c2 described above and the associated via cavities (eg, reference Figure 6N Described passage cavity 642-e).

[0191] Figure 6PA cross-sectional side view of stack 605 is illustrated after performing at least one etching process step using a fifth via group (e.g., vias indicated by arrows). In some cases, the etching process may include an anisotropic etching process that may remove ohmic material 675-e in a via hole (e.g., via hole corresponding to via 640-c2). In some cases, the anisotropic etching process may create a hole (e.g., hole 641) at a bottom layer (e.g., layer 330) of stack 605. The hole may be coupled to a conductive element (e.g., conductive element 685) that may be part of a logic circuitry layer. In some cases, conductive element 685 may be coupled to an inhibit node of an inhibit driver. In some cases, conductive element 685 may be coupled to a select node of a select driver.

[0192] Figure 6Q A cross-sectional side view of stack 605 is shown after performing at least one deposition process step using a fifth set of vias (e.g., vias indicated by arrows). In some cases, the deposition step may fill via holes (e.g., via holes corresponding to via 640-c2) and holes (e.g., reference 640-c2) at the bottom layer with electrode material 695. Figure 6P The via hole 641 is shown in FIG. 1 . A CMP process or an etch-back process may be used to remove the additional electrode material 695 on the top of the stack. The via hole filled with the electrode material 695 may be referred to as a conductive plug (e.g., conductive plug 696). The conductive plug 696 may couple the conductive element 685 with the semiconductor material of the TFT (e.g., semiconductor material 680-a) through an ohmic material (e.g., ohmic material 675-e) and may complete the construction of the TFT.

[0193] In some cases, Figure 6Q The TFT described in may include a conductive plug extending through a stack including a first layer, a second layer, and a third layer, a gate electrode at the second layer, a second electrode at the first layer, and semiconductor materials at the first and second layers, the semiconductor material being coupled to the second electrode via a first segment of the ohmic material at the first layer and coupled to the conductive plug via a second segment of the ohmic material at the third layer. In some cases, the TFT may include a dielectric plug extending through the gate electrode.

[0194] Figure 6Q The current paths (e.g., current path 645-a, current path 645-b) of a TFT (e.g., an upper TFT) are also illustrated. The current paths illustrate how a particular TFT may couple a node of a logic circuitry layer with an array electrode to access a memory cell in an active array region of the array layer when the TFT is activated. For example, conductive element 685 may be coupled to a select node of a select driver. Conductive element 685 may be coupled to a select node of a select driver. Figure 6Q696 is coupled to the common source of the TFTs (e.g., both the upper TFT and the lower TFT) depicted in FIG. The conductive plug 696 contacts the semiconductor material 680-a through the ohmic material 675-e. The semiconductor material 680-a can form an active channel that allows current to flow based on a voltage applied to the gate electrode 660 (e.g., the gate electrode 660-a including the electrode material 661-a).

[0195] In addition, the semiconductor material 680-a is connected to the electrode sheet 655-a1 through the ohmic material 675-a1. Figure 6R Array electrode 650-e) depicted in FIG. 6 can serve as the drain of a TFT (e.g., the left TFT of the upper TFT). In this way, when an active channel is formed within a semiconductor material (e.g., semiconductor material 680-a) (when a voltage applied to a gate electrode (e.g., gate electrode 660-a including electrode material 661-a) is greater than a threshold voltage of the TFT and when a voltage difference exists between the source (which is coupled to a node of the logic circuitry layer) and the drain (which is coupled to the array electrode) of the TFT), current can flow (e.g., current path 645-a) between the source and drain of the TFT.

[0196] The current flowing in the TFT flows in both the vertical direction and the horizontal direction (eg, relative to the horizontal substrate) and the TFT may be referred to as a hybrid TFT (eg, referring to Figure 3K The vertical TFT described and reference Figure 4Z A mixture of horizontal TFTs as described above). Figure 6Q As described in , the channel length of the hybrid TFT (e.g., the distance between the source and drain of the TFT) can be greater than the channel length of the vertical TFT or the horizontal TFT. This increased channel length can benefit some aspects of TFT operation, such as being less susceptible to leakage current issues related to channel length.

[0197] Figure 6R A top view of a stack 605 is illustrated in which the socket region includes four TFTs (eg, hybrid TFTs). Figure 6Q The cross-sectional side view may correspond to the area of ​​the socket where the dashed line AA extends, as shown Figure 6R As shown in . Figure 6R Aspects of structural features that have been constructed using the manufacturing techniques described herein are described. For example, Figure 6R An array electrode 650 that may serve as a second electrode (eg, a drain) of the TFT, a gate electrode 660 of the TFT, and a conductive plug 696 are depicted. Figure 6R Also depicts reference Figure 6Q A top view of depicted current paths (eg, current path 645 - c , current path 645 - d ).

[0198] Figures 7A to 7D Diagram illustrating an exemplary memory array including an active array region and a socket region supporting thin film transistors and related fabrication techniques according to an embodiment of the present disclosure. Figures 7A to 7D Describes a group of TFTs that can be constructed simultaneously in reference Figure 7C The composite stack 705 described (e.g., reference Figures 3A to 3L Various aspects of a socket area within one or more vertically integrated composite stacks 305) are described. Figures 7A to 7D A top view of a portion of a socket area (e.g., a layout of the socket area) is included to illustrate that a subset of TFT groups can be configured to couple nodes of a circuitry layer (e.g., a row decoder 120 constructed in substrate 204) to a subset of array electrodes (e.g., access lines, word lines, bit lines) of an active array area where memory cells are located. Additionally, Figures 7A to 7D Cross-sectional side views of different portions of the socket area are included to illustrate that the set of TFTs can couple the array electrodes to the nodes of the circuitry layer. In some cases, the circuitry layer can be a portion of the substrate over which the array layer is positioned.

[0199] Figures 7A to 7D A circuit representation of the TFT group is also included to illustrate that the TFT group can be combined with the circuit system layer to facilitate access operations. Figures 7A to 7D A socket region including a set of vertical TFTs is depicted as an illustrative example, but the present disclosure is not limited thereto, for example, the socket region may include other types of TFTs described herein or any combination thereof. In addition, Figures 3A to 3L Aspects of the fabrication techniques and operation of vertical TFTs are described in .

[0200] Fig. 7A A top view 700 of an array layer including an active array region and two socket regions, each of which includes a set of TFTs, is illustrated. In some cases, the active array region can include a set of memory cell layers constructed within a composite stack 705. As described herein, a set of TFTs can also be constructed in the socket region of the composite stack 705. In some cases, the set of TFTs can include reference Figures 3A to 3L Thus, each TFT of the TFT group may include a conductive plug 796 (e.g., referring to Figure 3L735-c) and a second TFT subgroup (e.g., TFT 735-b, TFT 735-d). In some cases, the first TFT subgroup (e.g., TFT 735-a) can be configured to couple a first node (e.g., a select node) of a circuitry layer (e.g., a row decoder 120 constructed in substrate 204) to one or more array electrodes 750 (which can also be referred to as electrodes, access lines, word lines, or bit lines). Additionally or alternatively, the second TFT subgroup (e.g., TFT 735-b) can be configured to couple a second node (e.g., an inhibit node) of the circuitry layer to one or more array electrodes 750.

[0201] Furthermore, in some cases, the first TFT subgroup and the second TFT subgroup may be constructed differently based on their operating characteristics. For example, the first TFT subgroup (e.g., TFTs for selection) may be constructed to provide a suitable amount of drive current, and the second TFT subgroup (e.g., TFTs for inhibition) may be constructed to provide an acceptable leakage current (e.g., limiting the leakage current to an acceptable amount). In some cases, the second TFT subgroup may be constructed using relatively simpler processing steps (e.g., associated with a fewer number of processing steps than the first TFT subgroup) or constructed to facilitate lower voltage operation (e.g., configured to support a lower supply voltage than the first TFT subgroup). In some cases, the first TFT subgroup and the second TFT subgroup may be different types of TFTs (e.g., n-type TFTs, p-type TFTs). In some cases, the base terminal (e.g., reference TFT) may be connected to the substrate. Figure 5N A fourth terminal of the base of the depicted TFT) is incorporated into the composite stack 705 so that the base terminal can facilitate controlling the threshold voltage of the TFT.

[0202] In some cases, the two socket areas shown in top view 700 may illustrate socket areas associated with word lines (which may also be referred to as first type of access lines). Array electrodes 750 may correspond to electrodes (e.g., word lines) at a first layer of the composite stack (e.g., D1 layer of stack 305). In other cases, the two socket areas shown in top view 700 may illustrate socket areas associated with bit lines (which may also be referred to as second type of access lines). Thus, array electrodes 750 may instead correspond to electrodes (e.g., bit lines) at a third layer (e.g., D2 layer of stack 305). Memory cells associated with array electrodes (e.g., word lines, first type of access lines, bit lines, second type of access lines) may be constructed at a second layer (e.g., DM layer of stack 305).

[0203] Top view 700 also depicts that one or more via cavities (e.g., via cavity 742-a) may be used to divide a first array electrode (e.g., electrode 750-a) into two or more array electrodes (e.g., electrode 750-a1, electrode 750-a2). In addition, one or more via cavities (e.g., via cavity 742-b) may be used to divide a second array electrode (e.g., electrode 750-b) into two or more array electrodes (e.g., electrode 750-b1, electrode 750-b2). In some cases, a set of vias (e.g., vias positioned between electrode 750-a and electrode 750-b) may have been used to construct the first array electrode and the second array electrode. In this way, the first array electrode (e.g., electrode 750-a1) may be coupled to a first group of two TFTs (e.g., TFT 735-a1, TFT 735-b1) and the second array electrode (e.g., electrode 750-b1) may be coupled to a second group of two TFTs (e.g., TFT 735-c1, TFT 735-d1). In some cases, the TFT (e.g., TFT 735-a1, TFT 735-b1) may be coupled to the electrode (e.g., electrode 750-a1) at a point between the two ends of the electrode (e.g., electrode 750-a1) (e.g., a midpoint, a center point in the center region). Similarly, the TFT (e.g., TFT 735-c1, TFT 735-d1) may be coupled to the electrode (e.g., electrode 750-b1) at a point between the two ends of the electrode (e.g., electrode 750-c1) (e.g., a midpoint, a center point in the center region).

[0204] In some cases, a first electrode segment (e.g., electrode 750-b2) may be located at a layer of a plane (e.g., D1 layer) and shorter than an electrode (e.g., electrode 750-a1), wherein the electrode may be an access line of a first type (e.g., a word line) and extend in a first direction at a layer of the plane, and wherein a conductive plug (e.g., conductive plug 796-b) may be located between the electrode and the first electrode segment. In some cases, a second access line of a first type (e.g., electrode 750-b1) may extend in a first direction at a layer of the plane, wherein the second access line (e.g., electrode 750-b1) may be coaxial with the first electrode segment (e.g., electrode 750-b2). In some cases, a second electrode segment (e.g., electrode 750-a2) may be located at a layer of the plane and shorter than an electrode (e.g., electrode 750-a1), wherein the second electrode segment may be coaxial with the electrode.

[0205] Thus, the group of TFTs can facilitate access operations (e.g., read operations, write operations) to memory cells associated with array electrodes in the active array area. For example, when TFT 735-a1 is activated, a select node of a circuitry layer (e.g., a row decoder 120 constructed in substrate 204) can be coupled to electrode 750-a1 (and therefore a memory cell associated with electrode 750-a1) to perform an access operation. Additionally or alternatively, other TFTs (e.g., TFT 735-d) can be activated to couple an inhibit node to a subset of array electrodes (e.g., electrodes including electrode 750-b1 that are not selected during an access operation) to maintain leakage current levels associated with unselected memory cells below an acceptable threshold during an access operation.

[0206] Fig. 7A Top views 700-a and 700-b illustrate a socket area that each includes a set of TFTs. Top view 700-a may be a portion of a wordline socket area that includes array electrodes (e.g., electrode 750-c in D1 layer of composite stack 705) that may correspond to wordlines extending along a first direction. Additionally, top view 700-a depicts a set of TFTs (e.g., TFT 735-aa, TFT 735-bb) that include conductive plugs (e.g., conductive plug 796-c). As described herein, TFT 735-aa may be coupled to a select node of a circuitry layer and TFT 735-bb may be coupled to an inhibit node of a circuitry layer.

[0207] Similarly, top view 700-b may be a portion of a bit line socket region that includes an array electrode (e.g., electrode 751 in D2 layer of composite stack 705) that may correspond to a bit line extending along a second direction (e.g., a second direction substantially orthogonal to the first direction). In addition, top view 700-b depicts a group of TFTs (e.g., TFT 735-ee, TFT 735-ff) that include a conductive plug (e.g., conductive plug 796-e). As described herein, TFT 735-ee may be coupled to a select node of a circuit system layer and TFT 735-ff may be coupled to an inhibit node of a circuit system layer.

[0208] In some cases, the socket region of the array layer may include a first socket region (e.g., a socket region associated with a word line) including a conductive plug (e.g., conductive plug 796-c), wherein an electrode (e.g., electrode 750-c) may include an access line of a first type (e.g., a word line) extending into the first socket region. In some cases, the socket region of the array layer may include a second socket region (e.g., a socket region associated with a bit line) including a second conductive plug (e.g., conductive plug 796-e), wherein a second electrode (e.g., electrode 751-a) may include an access line of a second type (e.g., a bit line) extending into the second socket region.

[0209] Figure 7B A top view 701 illustrating a socket region and another top view 702 of a vertical TFT that may be included in the socket region. Top view 701 depicts a set of array electrodes 750, a set of gate electrodes 760 (which may be reference Figures 3A to 3L 700 ), a set of via cavities 742, and a set of TFTs 735, each of which is in contact with a respective conductive plug 796. In some cases, top view 701 may be a variation of the socket region depicted in top view 700 .

[0210] For example, a subset of TFTs (e.g., a group of two TFTs) may be offset from the remaining TFTs, e.g., TFT 735-e1 and TFT 735-e2 are offset relative to TFT 735-e3 and TFT 735-e4. Due to the offsetting of the subset of TFTs in a zigzag pattern, the distance between the conductive plugs in the socket depicted in top view 701 (e.g., the distance between conductive plug 796-e2 and conductive plug 796-e3) may be greater than the corresponding distance in the socket depicted in top view 700. This increase in distance may contribute to improved results during the photolithography step. In some cases, each TFT (e.g., instead of a group of two TFTs) may be offset from the adjacent TFTs so that the minimum distance between the conductive plugs may be the diagonal distance between the two conductive plugs. For example, while top view 701 illustrates an example in which the TFTs are offset in pairs (zigzag) (TFT pairs are offset from each other), it should be understood that any number of other offset patterns are possible, including configurations in which each TFT in a socket area is offset from each adjacent (immediately adjacent) TFT in the socket area.

[0211] In some cases, the socket area may include a first gate electrode (e.g., gate electrode 760-b) that may surround a conductive plug (e.g., conductive layer plug 796-e3, conductive plug 796-e4) and a second gate electrode (e.g., gate electrode 760-a) that may surround a first additional conductive plug (e.g., conductive plug 796-e5) extending through the layer group and a second additional conductive plug (e.g., conductive plug 796-e2) extending through the layer group, wherein an electrode (e.g., electrode 750-e, electrode 750-f) may extend between the first additional conductive plug and the second additional conductive plug.

[0212] The top view 702 of the vertical TFT may depict a variation of the vertical TFT depicted in the top view 700. For example, the gate electrode 760-c may be configured to surround more than one conductive plug (e.g., four conductive plugs 796-f1 to 796-f4). Thus, the vertical TFT may generate a drive current that may be nearly four (4) times greater than the drive current that an individual TFT (e.g., TFT 735-a1, TFT 735-c1 shown in the top view 700) may generate. Other features of the vertical TFT in the top view 702 have been omitted for clarity.

[0213] Figure 7C An example schematic cross-sectional side view 703 of an array layer including eight (8) memory cell levels is illustrated. In some cases, the eight (8) memory cell levels may include five (5) groups of word lines that may each extend along a first direction (e.g., the x-direction) and four (4) groups of bit lines that may each extend along a second direction (e.g., the z-direction). The memory cell levels (depicted as cross-hatched rectangles in the cross-sectional side view 703) may be positioned between a subset of word lines (e.g., WL1) and a subset of bit lines (e.g., BL1). Some access lines (e.g., word lines, bit lines) may be shared by more than one memory cell level. For example, WL2 may be shared by two memory cell levels (i.e., a first memory cell level positioned between WL2 and BL1 and a second memory cell level positioned between WL2 and BL2). Similarly, BL4 may be shared by two memory cell levels (i.e., a third memory cell level positioned between BL4 and WL4 and a fourth memory cell level positioned between BL4 and WL5).

[0214] The cross-sectional side view 703 illustrates the various layers of the composite stack 705. For example, the cross-sectional side view 703 depicts five (5) first layers 715 (eg, reference 714) that may each include a word line subset (eg, WL1). Figure 3A The D1 layer, layer 315 described above), each of which may include eight (8) second layers 720 (e.g., reference Figure 3A The DM layer, layer 320) and four (4) third layers 725 (such as reference Figure 3A Described D2 layer, layer 325).

[0215] Figure 7C Also illustrated is a cross-sectional side view 704 of a socket region of an array layer. Cross-sectional side view 704-a may correspond to a cross-sectional side view of a word line socket region across dashed line AA, as shown in reference to FIG. Fig. 7A The cross-sectional side view 704-a may correspond to the composite stack 705 and illustrate five (5) array electrodes 750 (eg, array electrodes 750-f1 through 750-f5 at the D1 layer, which may be referred to as word lines or first type access lines).

[0216] The cross-sectional side view 704-a also depicts conductive plugs (e.g., conductive plug 796-c, conductive plug 796-d) that can each be coupled to a conductive element (e.g., conductive element 785-a1, conductive element 785-b1). Each conductive element can be coupled to a node (e.g., a selection node, an inhibition node) of a circuit system layer (e.g., a word line select driver, a word line inhibit driver). The cross-sectional side view 704-a also depicts eight (8) pairs of gate electrodes (e.g., a pair of gate electrodes at each layer 720), wherein each gate electrode surrounds a conductive electrode (e.g., conductive plug 796-c, conductive plug 796-d). Thus, the cross-sectional side view 704-a depicts a total of sixteen (16) TFTs. In addition, the cross-sectional side view 704-a illustrates a current path 745-a, which a group of TFTs in the word line socket area can activate so that a drive current can flow between the conductive element 785 and the word line 750 during an access operation.

[0217] Similarly, the cross-sectional side view 704-b may correspond to a cross-sectional side view of the bit line socket region across the dashed line BB, as shown in reference Fig. 7A 4. The top view 700-b of the embodiment of the present invention is shown in the described top view 700-b. The cross-sectional side view 704-b may also correspond to the composite stack 705 and illustrate four (4) array electrodes 751 (e.g., array electrodes 751-c1 to 751-c4 at the D2 layer, which may be referred to as bit lines or second type of access lines). The cross-sectional side view 704-b also depicts conductive plugs (e.g., conductive plugs 796-e, conductive plugs 796-f) that may each be coupled to a conductive element (e.g., conductive element 785-a2, conductive element 785-b2). Each conductive element may be coupled to a node (e.g., a selection node, an inhibition node) of a circuit system layer (e.g., a bit line selection driver, a bit line inhibition driver). The cross-sectional side view 704-b also depicts eight (8) pairs of gate electrodes (e.g., a pair of gate electrodes at each layer 720), wherein each gate electrode surrounds a conductive electrode (e.g., conductive plugs 796-e, conductive plugs 796-f). Thus, cross-sectional side view 704-b also depicts a total of sixteen (16) vertical TFTs. In addition, cross-sectional side view 704-b illustrates current path 745-b, which the group of TFTs in the bit line socket area can activate so that a drive current can flow between conductive element 785 and bit line 751 during an access operation.

[0218] In some cases, the socket area of ​​the memory device (e.g., reference Figure 7CThe word line socket region described above may include a conductive plug (e.g., conductive plug 796-c) extending through a set of memory cell levels and a set of transistors (e.g., eight (8) vertical TFTs in the word line socket region) each at least partially surrounding the conductive plug. In some cases, the memory device may include a driver (e.g., a word line select driver) coupled to the conductive plug and configured to selectively couple with an electrode (e.g., word line 750-f1) included in a level of the level group through the transistors of the transistor group. In some cases, a second socket region of the memory device (e.g., reference 796-c) may include a conductive plug (e.g., conductive plug 796-c) extending through a set of memory cell levels and a set of transistors (e.g., eight (8) vertical TFTs in the word line socket region) each at least partially surrounding the conductive plug. Figure 7C The described bit line socket area) may include a second conductive plug (e.g., conductive plug 796-e) extending through the layer group, a second group of transistors (e.g., eight (8) vertical TFTs in the bit line socket area), each of which at least partially surrounds the second conductive plug, and a second driver (e.g., a bit line selection driver) coupled to the second conductive plug and configured to selectively couple with a second electrode (e.g., bit line 751-c1) included in the layer through the second group of transistors.

[0219] In some cases, the electrode (e.g., word line 750-f1) can be located at a first layer (e.g., layer 715 of composite stack 705) and the socket region can further include a gate electrode (e.g., gate electrode 760-a) for a transistor at a second layer (e.g., layer 720 of composite stack 705), wherein the gate electrode at least partially surrounds the conductive plug. In some cases, the vertical TFT of the socket region can be configured to include a gate electrode (e.g., reference Figure 7B The gate electrode 760-c described above surrounds a set of conductive plugs (eg, reference 760-c) extending through the set of planes and each coupled to a driver (eg, a word line select driver). Figure 7B The conductive plugs 796 - f1 and 796 - f4 are described, wherein the conductive plug group may include a conductive plug (eg, conductive plug 796 - c ).

[0220] In some cases, the socket region (e.g., the wordline socket region) may include a third conductive plug (e.g., conductive plug 796-d) extending through the layer group and a third group of transistors (e.g., eight (8) TFTs in the wordline socket region) each at least partially surrounding the third conductive plug. In some cases, the memory device may include a third driver coupled to the third conductive plug and configured to selectively couple with a first type of access line included in the layer group of the group through a subset of transistors of the third group. In some cases, the socket region (e.g., the bitline socket region) may include a fourth conductive plug (e.g., conductive plug 796-f) extending through the layer group and a fourth group of transistors (e.g., eight (8) TFTs in the bitline socket region) each at least partially surrounding the fourth conductive plug. In some cases, the memory device may include a fourth driver coupled to the fourth conductive plug and configured to selectively couple with a second type of access line included in the layer group of the group through a subset of transistors of the fourth group.

[0221] Fig.7D Description Reference Figure 7C Circuit diagram 738 and schematic cross-sectional side view 703 of the array layer described. Circuit diagram 738-a may correspond to a wordline socket region including the sixteen (16) TFTs described with reference to cross-sectional side view 704-a. Similarly, circuit diagram 738-b may correspond to a bitline socket region including the sixteen (16) TFTs described with reference to cross-sectional side view 704-b. Both circuit diagrams 738 depict n-type TFTs for illustration, but the present disclosure is not limited thereto, for example, circuit diagram 738 may include n-type TFTs, p-type TFTs, or any combination thereof. In addition, the gate of the TFT in circuit diagram 738 may indicate an activated or deactivated TFT, for example, a gate of a TFT depicted as a gray rectangle indicates that a first gate voltage (e.g., Von) applied to the gate to activate the TFT is greater than a threshold voltage of the TFT, and a gate of a TFT depicted as a white rectangle indicates that a second gate voltage (e.g., Voff) applied to the gate to deactivate the TFT is less than a threshold voltage of the TFT.

[0222] The circuit diagram 738-a also depicts the respective corresponding reference Figure 7CThe common node 797 (e.g., nodes 797-c to 797-f) of the TFT of the conductive plug 796 described. In some cases, the common node may correspond to the source (or drain) of the TFT. For example, the common node 797-c corresponds to the conductive plug 796-c coupled to the conductive element 785-a1. The conductive element 785-a1 may be coupled to a node of a driver (e.g., a selection node of the word line selection driver 736-a). Similarly, the common node 797-d corresponds to the conductive plug 796-d coupled to the conductive element 785-b1. The conductive element 785-b1 may be coupled to a node of a driver (e.g., an inhibition node of the word line inhibition driver 737-a). In addition, the common node 797-e corresponds to the conductive plug 796-e coupled to the conductive element 785-a2. The conductive element 785-a2 may be coupled to a node of a driver (e.g., a selection node of the bit line selection driver 736-b). Similarly, the common node 797-f corresponds to the conductive plug 796-f coupled to the conductive element 785-b2. The conductive element 785-b2 can be coupled to a node of a driver (e.g., an inhibition node of a bit line inhibition driver 737-b). It should be understood by those skilled in the art that the selection driver (e.g., word line selection driver 736-a, bit line selection driver 736-b) and the inhibition driver (e.g., word line inhibition driver 737-a, bit line inhibition driver 737-b) can perform different functions (e.g., word line selection driver 736-a performs inhibition function, word line inhibition driver 737-a performs selection function) based on the access operation of the memory cell or memory technology (e.g., self-select memory, FeRAM, CBRAM).

[0223] Fig.7D TFTs in the word line socket region (e.g., circuit diagram 738-a) and TFTs in the bit line socket region (e.g., circuit diagram 738-b) are illustrated to facilitate access operations (e.g., read operations, write operations) to the memory cell level. For example, an access command may access a memory cell at a sixth memory cell level located between BL3 and WL4 (e.g., a memory cell located at the second layer 720-f), as indicated in the cross-sectional side view 703. The corresponding BL3 and WL4 in the circuit diagram 738 are highlighted (e.g., depicted as bold lines) to indicate which TFTs may be activated.

[0224] In some cases, WL4 in circuit diagram 738-a may be coupled to a select node of word line select driver 736-a by activating a TFT above WL4 (e.g., applying Von to gate electrode 760-c6) or activating a TFT below WL4 (e.g., applying Von to gate electrode 760-c7), or both. Similarly, BL3 in circuit diagram 738-b may be coupled to a select node of bit line select driver 736-b by activating a TFT above BL3 (e.g., applying Von to gate electrode 760-d5) or activating a TFT below BL3 (e.g., applying Von to gate electrode 760-d6), or both. In some cases, a driver (e.g., word line select driver 736-a, bit line select driver 736-b) may be configured to selectively couple to an electrode (e.g., word line, bit line) through a group of at least two transistors (e.g., two TFTs in a word line socket region, two TFTs in a bit line socket region).

[0225] Additionally or alternatively, TFTs coupled to the inhibition node of the word line inhibit driver 737-a (e.g., TFTs coupled to the common node 797-d) may be activated or deactivated (e.g., six TFTs are activated and two TFTs are deactivated, as depicted in the circuit diagram 738-a) such that the activated TFTs may couple unselected word lines (e.g., WL1, WL2, WL3, WL5) to the inhibition node of the word line inhibit driver 737-a. Similarly, TFTs coupled to the inhibition node of the bit line inhibit driver 737-b (e.g., TFTs coupled to the common node 797-f) may be activated or deactivated (e.g., six TFTs are activated and two TFTs are deactivated, as depicted in the circuit diagram 738-b) such that the activated TFTs may couple unselected word lines (e.g., BL1, BL2, BL4) to the inhibition node of the bit line inhibit driver 737-b. In this way, disturbances due to unselected word lines or bit lines may be mitigated during access operations.

[0226] In some cases, a pair of gates of a TFT may be configured to be electrically connected (e.g., shorted) during decoding of an access command so that two TFTs (rather than one TFT) can provide greater current drive capability to a selected memory cell layer. For example, a first subset of access lines (e.g., WL2, WL3, WL4) may be driven by a pair of TFTs rather than a single TFT. Such TFT pairs may be positioned above and below access lines (e.g., word lines, bit lines) and Fig.7DSeveral examples of TFT pairs are illustrated using double arrows with gray lines. In some cases, some gates of the TFTs (e.g., gate electrode 760-c1, gate electrode 760-c8) may lack adjacent gates to provide greater current drive capability. In such cases, a second subset of access lines (e.g., WL1, WL5) may be driven by a single TFT instead of a pair of TFTs. This configuration (e.g., selectively connecting two TFTs above and below an access line) may be implemented in a crossover region, as described in reference to FIG. Fig. 10A and 10B described.

[0227] Figures 8A to 8C Diagram illustrating an exemplary socket area and decoding scheme to support thin film transistor and related manufacturing techniques according to an embodiment of the present disclosure. Figures 8A to 8C Describes a group of TFTs that can be simultaneously constructed in a composite stack 805 (e.g., reference Figures 3A to 3L Various aspects of the socket area within the one or more vertically integrated composite stacks 305) are described as described herein. Figures 8A to 8C A top view of a portion of a socket area (eg, a layout of the socket area) is included to illustrate that a subset of TFT groups may be configured to couple with a subset of array electrodes (eg, access lines, word lines, bit lines) of an active array area where memory cells are located.

[0228] in addition, Figures 8A to 8C The cross-sectional side views of different portions of the socket area are included to illustrate that the TFT group can couple the array electrode to a circuit system layer (e.g., row decoder 120 constructed in substrate 204). In some cases, the circuit system layer can be a portion of the substrate over which the array layer is positioned. In addition, Figures 8A to 8C The TFT group described in the above can be used during access operation according to the reference Figures 7A to 7D The circuit representation of the described TFT group operates. Figures 8A to 8C A socket area including a set of wraparound TFTs is depicted as an illustrative example, but the present disclosure is not limited thereto, for example, the socket area may include other types of TFTs described herein or any combination thereof. Figures 5A to 5N Aspects of the fabrication techniques and operation of wraparound TFTs are described in .

[0229] Fig. 8AA top view 801 is illustrated of a socket area including two sets of wraparound TFTs. The top view 801 may be a portion of a wordline socket area including array electrodes that may correspond to wordlines (e.g., electrode 850-a in the D1 layer of the composite stack 805). Additionally, the top view 801 depicts a first conductive plug 896-a and a second conductive plug 896-b. In some cases, the first conductive plug may be coupled to a first node of a first driver (e.g., a select node of a wordline select driver) and the second conductive plug may be coupled to a second node of a second driver (e.g., an inhibit node of the wordline select driver). The top view 801 also depicts a gate electrode 860 at a second layer of the composite stack 805 (e.g., gate electrode 860-a including electrode material 861-a, gate electrode 860-b including electrode material 861-b).

[0230] In some cases, an electrode (e.g., electrode 850-a) may include a first portion (e.g., electrode sheet 855-a) extending along a first direction between a conductive plug (e.g., conductive plug 896-a) and a second conductive plug (e.g., conductive plug 896-b), a second portion (e.g., electrode 850-a1) extending along a second direction coupled to an end of the first portion, and a third portion (e.g., electrode 850-a2) extending along the second direction coupled to a second end of the first portion. In some cases, the first portion (e.g., electrode sheet 855-a) may be wider than the second portion (e.g., electrode 850-a1) and the third portion (e.g., electrode 850-a2).

[0231] Fig. 8A A cross-sectional side view 802 of a socket region of the array layer is also illustrated. The cross-sectional side view 802-a may correspond to a cross-sectional side view of a word line socket region across dashed line AA, as shown in the top view 801. For clarity, the cross-sectional side view 802-a omits dielectric plugs, such as a dielectric plug between conductive plug 896-a and conductive plug 896-b, a dielectric plug surrounded by a gate electrode. The cross-sectional side view 802-a illustrates a composite stack 805 including five (5) array electrodes, such as word lines, array electrodes including electrode pads 855 at layer 815.

[0232] The cross-sectional side view 802-a also depicts conductive plugs (e.g., conductive plug 896-a) that can each be coupled to a conductive element (e.g., conductive element 855-a1). The conductive plug can serve as a common node (e.g., source or drain) for a group of TFTs. Each conductive element can be coupled to a node (e.g., selection node, inhibition node) of a circuit system layer (e.g., word line select driver, word line inhibit driver). The cross-sectional side view 802-a also depicts eight (8) pairs of gate electrodes (e.g., a pair of gate electrodes at each layer 820). Thus, the cross-sectional side view 802-a depicts a total of sixteen (16) wraparound TFTs. In addition, the cross-sectional side view 802-a illustrates a current path 845-a, which can be activated by a group of TFTs in the word line socket area so that a drive current can flow between the conductive element 885 and the word line 850 during an access operation.

[0233] Similarly, cross-sectional side view 802-b may correspond to a cross-sectional side view of a bitline socket region. The top view of the bitline socket region may be the same as top view 801 depicting a wordline socket region, except that the top view of the bitline socket region may be rotated approximately 90° relative to top view 801 depicting a wordline socket region (because the bitlines may extend in a direction that may be substantially orthogonal to the wordlines). Cross-sectional side view 802-b may also correspond to composite stack 805 and illustrate four (4) array electrodes (e.g., bitlines, array electrodes including electrode pads 856 at layer 825).

[0234] The cross-sectional side view 802-b also depicts conductive plugs (e.g., conductive plug 896-c) that can each be coupled to a conductive element (e.g., conductive element 855-a2). Each conductive element can be coupled to a node (e.g., a select node, an inhibit node) of a circuit system layer (e.g., a bit line select driver, a bit line inhibit driver). The cross-sectional side view 802-b also depicts eight (8) pairs of gate electrodes (e.g., a pair of gate electrodes at each layer 820). Thus, the cross-sectional side view 802-b also depicts a total of sixteen (16) wraparound TFTs. In addition, the cross-sectional side view 802-b illustrates a current path 845-b that can be activated by a group of TFTs in the bit line socket area so that a drive current can flow between the conductive element 885 and a line 851 (e.g., a bit line including electrode 856 at layer 825) during an access operation.

[0235] In some cases, the socket area of ​​the memory device (e.g., reference Fig. 8AThe line socket area described above may include a conductive plug (e.g., conductive plug 896-a) extending through a group of memory cell levels and a group of transistors (e.g., wraparound TFTs that may be coupled to a select node) each having a source or drain in contact with the conductive plug. In some cases, the memory device may include a driver (e.g., a word line select driver) coupled to the conductive plug and configured to selectively couple with an electrode (e.g., word line 850) included in a level of the level group through the transistors of the transistor group.

[0236] In some cases, the socket region may include a second conductive plug (e.g., conductive plug 896-b) extending through the layer group and a second set of transistors (e.g., wraparound TFTs that may be coupled to an inhibiting node) each having a source or drain in contact with the conductive plug. In some cases, the memory device may include a second driver (e.g., a word line inhibiting driver) coupled to the second conductive plug and configured to selectively couple with the first type of access line included in a layer subset of the layer group through a second set of transistor subsets.

[0237] In some cases, the socket area may include a first set of gate electrodes (e.g., gate electrode 860-a) of a transistor group (e.g., a wraparound TFT that may be coupled to a selection node) and a second set of gate electrodes (e.g., gate electrode 860-b) of a second set of transistors (e.g., a wraparound TFT that may be coupled to an inhibition node), wherein a conductive plug (e.g., conductive plug 896-a) and a second conductive plug (e.g., conductive plug 896-b) may be located between the first set of gate electrodes (e.g., gate electrode 860-a) and the second set of gate electrodes (e.g., gate electrode 860-b).

[0238] Figure 8B FIG. 803 - a illustrates an array layer including an active array region and two socket regions (e.g., wordline socket regions) each including a set of TFTs. FIG. 803 - a depicts some aspects of a top view of the array layer (e.g., access lines and structural features of the TFT groups), and omits other aspects for visual clarity. In some cases, the active array region may include a set of memory cell layers constructed within a composite stack 805. As described herein, the TFT groups may also be constructed in the socket regions of the composite stack 805. In some cases, the TFT groups may include reference Figures 5A to 5N The lines (eg, electrodes of word lines) depicted in the mosaic diagram 803-a (eg, each word line is associated with a wider portion that is shorter than a narrower portion extending into the active array area, as shown in reference Figure 5A and 8AThe TFTs may be positioned approximately at the center of a word line (e.g., a center tap array electrode).

[0239] Schematic 803-a includes sixteen (16) word lines as an example and therefore includes sixteen (16) groups of wraparound TFTs, i.e., eight (8) are located on one side of the active array area and the other eight (8) are located on the opposite side. In addition, diagram 803-a depicts an inhibit driver 837 (which may be an example of a word line inhibit driver 737) which may be a word line inhibit driver. In some cases, the inhibit driver 837 may be shared by the eight (8) groups of wraparound TFTs. In other cases, each group of wraparound TFTs may be coupled to a separate inhibit driver. Diagram 803-a also depicts a group of eight (8) select drivers 836 (which may be an example of a word line select driver 736). Each select driver may be a word line select driver coupled to one of the eight (8) groups of wraparound TFTs. In some cases, the inhibit driver 837 and the group of eight (8) select drivers 836 may be positioned below (or above) the memory cell level group. In some cases, an inhibit driver (e.g., inhibit driver 837) and a select driver (e.g., select driver 736) may perform different functions (e.g., inhibit driver 837 performs a select function and select driver 736 performs an inhibit function) based on an access operation of a memory cell or memory technology (e.g., self-select memory, FeRAM, CBRAM).

[0240] Diagram 803-a also includes a common layer selection line 846 and a common layer inhibition line 847 that can control the gate electrodes of the surrounding TFTs (e.g., gate electrode 860 at layer 820 within composite stack 805). The common layer selection line 846 can be configured to couple (e.g., short) all gate electrodes of the surrounding TFTs (e.g., the surrounding TFTs configured to be coupled to the selection node of the word line selection driver) associated with the layer's selection signal. In addition, the common layer selection line 846 can be coupled with a first common gate driver positioned below (or above) the memory cell layer group. Similarly, the common layer inhibition line 847 can be configured to couple (e.g., short) all gate electrodes of the surrounding TFTs (e.g., the surrounding TFTs configured to be coupled to the inhibition node of the word line inhibition driver) associated with the layer's inhibition signal. In addition, the common layer inhibition line 847 can be coupled with a second common gate driver positioned below (or above) the memory cell layer group. In some cases, the common gate driver (which can be referred to as a layer selection driver) can be positioned in a location different from the socket area. In some cases, a common gate driver may be shared between a set of socket regions, where a portion of a memory array includes the set of socket regions and one or more active array regions. In some cases, the socket region may include a set of gate electrodes (e.g., gate electrodes 860) included in a layer and coupled to each other (e.g., common layer select lines 846, common layer inhibit lines 847) and to a common gate driver below (or above) the set of memory cell layers. In some cases, the set of gate electrodes includes gate electrodes of transistors (e.g., wraparound TFTs in the socket region).

[0241] Figure 8CFIG. 803-b illustrates an array layer including an active array region and two socket regions (e.g., wordline socket regions) each including a set of TFTs. FIG. 803-b depicts some aspects of a top view of the array layer, such as access lines and structural features of a set of TFTs (e.g., wraparound TFTs). FIG. 803-b includes a wordline select driver 836-a (which may be an example of wordline select driver 736-a) and a wordline inhibit driver 837-a (which may be an example of wordline inhibit driver 737-a). Additionally, FIG. 803-b depicts a decoder circuitry 876. In some cases, the wordline select driver 836-a, the wordline inhibit driver 837-a, and the decoder circuitry 876 may be positioned below (or above) the set of memory cell layers. Compared to FIG. 803-a, FIG. 803-b may depict an alternative configuration for controlling a gate electrode (e.g., gate electrode 860 at layer 820 within composite stack 805) of a wraparound TFT. For example, instead of coupling all gate electrodes of the wraparound TFTs (e.g., using common level select lines 846 and common level inhibit lines 847 as described with reference to FIG. 803-a), decoder circuitry 876 may be configured to decode control signals for each gate electrode. In the example depicted in FIG. 803-b, each of the sixty-four (64) TFTs in the two socket regions may be coupled with a driver for the gate electrode. In some cases, a memory device including a socket region may include decoder circuitry located below a level group and configured to activate a transistor based on selecting the gate electrode of the transistor from a set of gate electrodes included in the level.

[0242] Fig. 9 FIG900 illustrates an exemplary decoding scheme supporting thin film transistors and related manufacturing techniques according to an embodiment of the present disclosure. The TFT-based decoder circuitry depicted in FIG900 may be constructed within a composite stack (e.g., composite stack 305, composite stack 705, composite stack 805). Such a decoder circuitry constructed within a composite stack may perform at least a portion of a decoding function that may otherwise be performed by a logic circuitry layer. For example, the decoder circuitry may perform additional functions in addition to selecting a level from a set of memory cell levels. In some cases, the logic circuitry layer may be located within a substrate over which the set of memory cell levels may be constructed. In this way, the logic circuitry within the substrate may be simplified to reduce the area corresponding to the logic circuitry or may support additional memory array levels.

[0243] Diagram 900 depicts decoder circuitry that may include planar TFTs for illustration, but the disclosure is not so limited, for example, decoder circuitry within a composite stack may include other types of TFTs described herein or any combination thereof. Figures 4A to 4AAAspects of the fabrication techniques and operation of planar TFTs are described. In addition, diagram 900 depicts a single-ended driver scheme, e.g., a TFT provides a drive current to an access line (e.g., a word line) located at the end of the access line. Those skilled in the art will appreciate that a different driver scheme (e.g., a TFT provides a drive current located between the two ends of the access line) or a more complex driver circuit system may be used without any loss of functionality.

[0244] Diagram 900 depicts a cluster of levels stacked one above the other, such as cluster 967 including eight (8) levels (i.e., level 966-a through level 966-h), where each level may include one or more tiles. Diagram 900 depicts a set of TFTs to perform decoding functions within a tile, such as activating access lines (e.g., word lines) from a set of access lines (e.g., eight (8) word lines) within a tile. In the context of the decoder circuitry described herein, a cluster may refer to a group of tiles, and a tile may refer to an array decoding unit. In addition, diagram 900 depicts a select driver 936 (which may be an example of word line select driver 736-a) and an inhibit driver 937 (which may be an example of word line inhibit driver 737-a). In some cases, select driver 936 and inhibit driver 937 may be located within the logic circuitry layer.

[0245] In some cases, an electrode layer (e.g., a layer including access lines (e.g., word lines and bit lines)) within a layer (e.g., layers 966-a through 966-h) may include providing a second set of TFTs (e.g., a pair of TFTs coupled to the word lines, such as Fig. 9 A first group of TFTs having a control signal of a gate thereof (shown in FIG. 1 ), wherein a source or a drain of the first group of TFTs may be coupled to a third group of TFTs at an electrode layer that may be constructed within the plane.

[0246] For example, diagram 900 depicts that the decoder circuitry can perform one of eight (8) decodes within a tile within a level 966 (e.g., level 966-a through level 966-h), e.g., one of eight pairs of TFTs (e.g., two TFTs in a series configuration) can be activated to activate one of eight access lines (e.g., word lines) within the tile. Furthermore, diagram 900 depicts that the decoder circuitry can perform one of sixty-four (64) decodes in conjunction with a level-level decoder that can perform level-level decoding, e.g., a level-level decoder can select (or activate) one of eight levels within cluster 967 (e.g., one of levels 966-a through level 966-h).

[0247] Fig. 10A and 10B Diagram illustrating exemplary crossover regions supporting thin film transistors and related manufacturing techniques according to embodiments of the present disclosure.

[0248] Fig. 10A Illustration depicts a top view of an array layer including active array regions (e.g., active arrays 1055-a through 1055-d) and socket regions (e.g., socket regions 1065, 1066) where TFT groups may be constructed, as described herein. Figure 1 Some aspects of an example of a memory device 100 are described. In some cases, diagram 1000 may be a portion of a 3D memory device that includes a composite stack 1005 (which may be referenced to Figure 7C Two or more memory cell levels within the composite stack 705 example described herein, such as Fig. 10B In some examples, diagram 1000 may be an example of a packing architecture described herein. The TFT group may be constructed within a composite stack 1005 and may include reference Figures 3A to 3L The vertical TFT constructed as described, reference Figures 4A to 4AA The described planar TFT, ref. Figures 5A to 5N The wraparound TFT described or reference Figures 6A to 6R The hybrid TFT described or any combination thereof.

[0249] In addition, diagram 1000 depicts that active array 1055 may include a first set of access lines of a first type (e.g., word lines) extending along a first direction and a second set of access lines of a second type (e.g., bit lines) extending along a second direction that may be substantially orthogonal to the first direction. The first set of access lines may be positioned at a first layer (e.g., D1 layer, reference layer 1054) of composite stack 1005. Fig. 10B Similarly, the second set of access lines may be located at a third layer (e.g., D2 layer, reference layer 1015) of the composite stack 1005. Fig. 10B 1025). Diagram 1000 depicts that a first set of access lines (e.g., word lines) may cross the boundaries of the active arrays (e.g., the boundaries of active arrays 1055-a and 1055-b). Similarly, a second set of access lines (e.g., bit lines) may cross the boundaries of the active arrays (e.g., the boundaries of active arrays 1055-a and 1055-c).

[0250] In addition, the TFTs in the socket region 1065 can be configured to couple with a first set of access lines (e.g., word lines), and the TFTs in the socket region 1066 can be configured to couple with a second set of access lines (e.g., bit lines). In this way, the TFTs in the socket region 1065 (e.g., word line sockets) can couple nodes of the circuitry layer (e.g., select nodes, inhibit nodes) with one or more word lines of the active array 1055. Similarly, the TFTs in the socket region 1066 (e.g., bit line sockets) can couple nodes of the circuitry layer (e.g., select nodes, inhibit nodes) with one or more bit lines of the active array 1055.

[0251] In addition, the layer selection line 1070 can be defined in the socket area (e.g., socket area 1065, socket area 1066) at the second layer (e.g., DM layer, layer 1020 described with reference to 10B) of the composite stack 1005. In some cases, the layer selection line 1070 can be coupled with the gate electrode of the TFT also constructed at the second layer (e.g., DM layer, layer 1020), as described herein for various TFTs. Thus, the layer selection line 1070 can be coupled with the gate electrode of the TFT and can be referred to as a control line for the gate of the TFT within the socket area.

[0252] The level selection lines 1070 of two sets of access lines (e.g., word lines and bit lines) may be constructed at a second layer (e.g., DM layer, layer 1020 of composite stack 1005), and crossover regions 1075 may be defined to avoid shorting of level selection lines 1070, where two level selection lines may cross (e.g., crossover region 1075-a where level selection line 1070-a crosses level selection line 1070-d, crossover region 1075-b where level selection line 1070-b crosses level selection line 1070-d). Such crossover regions may be located at various locations based on the configuration of the active array arrangement (e.g., a stuffing architecture). As an example, diagram 1000 depicts a crossover region at a corner of active array 1055.

[0253] Fig. 10BA diagram 1001 depicting an enlarged top view of a crossover region and a diagram 1002 depicting a crossover region at various locations across the crossover region are illustrated. Diagram 1001 includes a crossover region 1075-d where a first set of level selection lines, such as level selection lines including level selection line 1070-f1, may cross with a second set of level selection lines, such as level selection lines including level selection line 1070-g1. The first set of level selection lines may be associated with word line sockets, such as socket region 1065, and may be control lines for gates of TFTs within the word line sockets, such as TFTs configured to be coupled with word lines. Similarly, the second set of level selection lines may be associated with bit line sockets, such as socket region 1066, and may be control lines for gates of TFTs within the bit line sockets, such as TFTs configured to be coupled with bit lines.

[0254] Fig. 10B Also illustrated is a diagram 1002 depicting a cross-sectional side view of a level select line (e.g., level select line 1070-f1) that traverses the dashed lines shown in diagram 1001 (e.g., dashed line AA to dashed line EE that transitions level select line 1070-f1 across region 1075-d). Diagram 1002 depicts a composite stack 1005 including a first layer (e.g., D1 layer, layer 1015), a second layer (e.g., DM layer, layer 1020), and a third layer (e.g., D2 layer, layer 1025).

[0255] The cross-sectional view 1002-a across the dashed line AA depicts an array electrode 1050 constructed at the D1 layer (e.g., layer 1015). The dashed line AA corresponds to a word line and the array electrode 1050 depicted in the cross-sectional view 1002-a can be coupled to the word line. The cross-sectional view 1002-a also depicts a gate electrode (e.g., a gate electrode including electrode material 1061) constructed at the DM layer (e.g., layer 1020). The gate electrode depicted in the cross-sectional view 1002-a can be part of a layer selection line 1070-f1 (e.g., a control line for the gate of the TFT within the word line socket area 1065).

[0256] Cross-sectional view 1002-b crossing dashed line BB depicts a similar structure to cross-sectional view 1002-a, except that array electrode 1050 is not present because the first portion of the cross-over region including dashed line BB is away from the line depicted in cross-sectional view 1002-a.

[0257] Cross-sectional view 1002-c across dashed line CC depicts that a gate electrode (e.g., a gate electrode including electrode material 1061) can be constructed across both the D1 layer (e.g., layer 1015) and the DM layer (e.g., layer 1020) in a second portion of the crossover region including dashed line CC, e.g., electrode material 1061 spans the D1 layer and the DM layer. In this way, a pair of inner gate electrodes (e.g., an electrode corresponding to electrode material 1061-b and an electrode corresponding to electrode material 1061-c) can be connected (e.g., electrically shorted), as indicated by the gray arrows.

[0258] Cross-sectional view 1002-d across dashed line DD depicts that a gate electrode (e.g., a gate electrode including electrode material 1061) may be constructed at a D1 layer (e.g., layer 1015) in a third portion of the crossover region including dashed line DD. In this manner, a gate electrode (e.g., a control line for a gate of a TFT within wordline socket region 1065) may be converted from a gate electrode at eight (8) DM layers (e.g., layer 1020) to a gate electrode at five (5) D1 layers (e.g., layer 1015) while transitioning from a first portion of the crossover region to a third portion of the crossover region. As described herein, the inner electrode pair may be electrically connected during the transition. The inner gate electrode pair may correspond to reference Fig.7D The gate pair of the TFT described in circuit diagram 738-a (e.g., the gate pair represented by the gray arrows).

[0259] Similarly, the layer select line 1070-g1 (e.g., the control line for the gate of the TFT within the bitline socket area 1066) can be constructed to have different structural configurations that pass through different portions of the crossover region 1075-d. In this way, the gate electrode (e.g., the control line for the gate of the TFT within the bitline socket area 1066) can be converted from a gate electrode at eight (8) DM layers (e.g., layer 1020) to a gate electrode at four (4) D2 layers (e.g., layer 1025) within the crossover region 1075-d, such that the layer select line 1070-g1 transitions into the crossover region 1075-d along an orthogonal direction relative to the dashed line AA to EE. During the transition, the inner gate electrode pair may be electrically connected because the electrode material 1062 of the gate electrode may be constructed across the DM layer (e.g., layer 1020) and the D2 layer (e.g., layer 1025), for example, the electrode material 1062 crosses the DM layer and the D2 layer at a portion of the crossover region 1075-d corresponding to the second portion of the crossover region of the dashed line CC including the layer selection line 1070-f1. The inner gate electrode pair may correspond to the reference Fig.7D The gate pair of the TFT described in circuit diagram 738-b (e.g., the gate pair represented by the gray arrows).

[0260] In this manner, cross-sectional view 1002-e across dashed line EE depicts that the gate electrode of level select line 1070-f1 (e.g., a gate electrode including electrode material 1061-a, electrode material 1061-i, electrode material 1061-j, electrode material 1061-k, electrode material 1061-h) may be constructed at layer 1015 and the gate electrode of level select line 1070-g1 (e.g., a gate electrode including electrode material 1062-a, electrode material 1062-b, electrode material 1062-c, electrode material 1062-d) may be constructed at layer 1025. Thus, level select line 1070-f1 and level select line 1070-g1 may cross over without electrically shorting each other.

[0261] The cross-sectional views of the diagram 1002 may also represent a cross-sectional side view of the level selection line 1070-f1 transitioning from the crossover region 1075-d. In other words, the cross-sectional view 1002-d across the dashed line DD may be the same as the cross-sectional view across the dashed line D'D'. Similarly, the cross-sectional view 1002-c across the dashed line CC may be the same as the cross-sectional view across the dashed line C'C'. Furthermore, the cross-sectional view across the dashed line A'A' is the same as the cross-sectional view 1002-a across the dashed line AA.

[0262] In some cases, a memory device (e.g., a reference Figure 1 The described memory device, 3D memory device) may include a set of memory cell layers, each of which includes a first layer (e.g., D1 layer), a second layer (e.g., DM layer), a third layer (e.g., D2 layer), and a set of memory arrays, a set of first electrodes extending along a first direction, and a set of second electrodes extending along a second direction intersecting the first direction. In some cases, within a region (e.g., crossover region 1075) between memory arrays of the memory array group, each first electrode in the first electrode group includes a first portion at the second layer, a second portion at the first layer, and a third portion at the second layer, and each second electrode in the second electrode group includes a first portion at the second layer, a second portion at the third layer, and a third portion at the second layer.

[0263] In some cases, each first electrode in the first electrode group further includes a fourth portion that spans at least the second layer and the first layer in the region, and each second electrode in the second electrode group further includes a fourth portion that spans at least the second layer and the third layer in the region. In some cases, the fourth portion of at least two first electrodes of the first electrode group may be shared by the at least two first electrodes, and the fourth portion of at least two second electrodes of the second electrode group may be shared by the at least two second electrodes.

[0264] In some cases, each first electrode in the first electrode set further includes a fifth portion within the region spanning at least the first layer and the second layer, and each second electrode in the second electrode set further includes a fifth portion within the region spanning at least both of the third layer and the second layer. In some cases, at least a subset of the first electrodes of the first electrode set may be coupled together within the region, and at least a subset of the second electrodes of the second electrode set may be coupled together within the region.

[0265] In some cases, a memory device may include a first set of transistors located within a memory array of a group and configured to select a first type of access line, wherein a first electrode of the group may be coupled to a gate of the first set of transistors. In some cases, a memory device may include a second set of transistors located within a memory array of a group and configured to select a second type of access line, wherein a second electrode of the group may be coupled to a gate of the second set of transistors. In some cases, the first set of transistors and the second set of transistors may be located within a layer of the group.

[0266] Fig.11 FIG. 1100 illustrates an exemplary memory device supporting thin film transistors and related manufacturing techniques according to embodiments of the present disclosure. In some cases, the memory device may include reference Figure 1 and 2 Two or more memory cell layers are described. FIG. 1100 includes a substrate 1156, one or more array layers 1157 (each of which includes an active array region and a socket region), and a layer of TFT circuitry 1158. The substrate 1156 may be a reference Figure 2 7, 8, and 10. Array layer 1157 may include a composite stack (e.g., Figure 7C The composite stack 705 described in reference Fig. 8A The composite stack 805 described in reference Fig. 10B The composite stack 1005 described herein. In addition, the array layer 1157 may include a set of memory cell layers in the active array area and a socket area in which a set of TFTs are positioned. In some cases, each array layer (e.g., array layer 1157-a, array layer 1157-b) may include a certain number of memory cell layers (e.g., eight (8) layers, sixteen (16) layers, thirty-two (32) layers, sixty-four (64) layers). The TFT group may include vertical TFTs, planar TFTs, wraparound TFTs, or hybrid TFTs, or any combination thereof. A layer of TFT circuitry 1158 may be referenced Fig. 9 An example of a TFT-based decoder circuitry is described.

[0267] In some cases, a memory device may include a memory array including a first layer (eg, reference Figure 7C A set of electrodes at the first layer 715) and a second layer (eg, reference Figure 7C The memory device may also include a group of memory cells at the second layer 720 described above. The memory device may also include a group of transistors configured to select electrodes from the electrode group, the transistor groups each including a gate electrode at the second layer, a semiconductor material at the first layer. In some cases, the memory array may be located at a first level of the memory device (e.g., a first memory cell level of array layer 1157-a). In some cases, the memory device may also include a second level (e.g., a second memory cell level of array layer 1157-b), wherein the second level may include: a second memory array including a second group of electrodes at the first layer of the second level and a second group of memory cells at the second layer of the second level; and a second group of transistors configured to select electrodes from the second group of electrodes, the second group of transistors each including a gate electrode at the second layer of the second level and a semiconductor material at the first layer of the second level.

[0268] In some cases, a first level of the memory device may be included in a first set of levels (e.g., a first memory cell level of array layers 1157-a that may include a number of memory cell levels) and a second level of the memory device may be included in a second set of levels (e.g., a second memory cell level of array layers 1157-b that may include a number of memory cell levels). In some cases, the memory device may further include a decoder circuitry (e.g., a layer of TFT circuitry 1158) between the first set of levels (e.g., array layers 1157-a) and the second set of levels (e.g., array layers 1157-b), wherein the decoder circuitry may be configured to select one or more levels from the first set of levels (e.g., array layers 1157-a) and the second set of levels (e.g., array layers 1157-b).

[0269] In some cases, the memory array may be located at a level included in a set of levels of a memory device (e.g., a memory cell level of array layer 1157-a that may include a number of memory cell levels), and the memory device may further include decoder circuitry (e.g., reference 1154 to FIG. 1 ). Fig. 9 Decoder circuitry described herein is included in a layer and is configured to activate transistors of a transistor group based on selecting gate electrodes of the transistors from a set of corresponding gate electrodes included in the layer.

[0270] Fig.12 A method 1200 for supporting thin film transistors and related manufacturing techniques according to an embodiment of the present disclosure is described. The operations of the method 1200 may be performed by, for example, reference 1200 herein. Figures 3A to 3L The described method is implemented.

[0271] In block 1205, a first set of vias and a second set of vias may be formed through a top layer of a stack including a first layer, a second layer, and a third layer. The operations of block 1205 may be performed according to methods described herein. In a specific example, aspects of the operations of block 1205 may be performed as described in reference to FIG. Figures 3A to 3L A portion of one or more processes being described.

[0272] In block 1210, a gate electrode of a transistor may be formed using the first set of vias, the gate electrode being located at the second layer. The operations of block 1210 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1210 may be performed as described in reference to Figures 3A to 3L A portion of one or more processes being described.

[0273] In block 1215, a second set of vias may be used to form a second electrode of the transistor, the second electrode being located at the first layer. The operations of block 1215 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1215 may be performed as described in reference to Figures 3A to 3L A portion of one or more processes being described.

[0274] In block 1220, a via common to the first set of vias and the second set of vias may be used to form a third electrode of the transistor, the third electrode extending through at least the third layer. The operations of block 1220 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1220 may be performed as described in reference to Figures 3A to 3L A portion of one or more processes being described.

[0275] In some examples, an apparatus described herein may perform one or more methods, such as method 1200. The apparatus may include features, circuitry, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: forming a first plurality of vias and a second plurality of vias through a top layer of a stack including a first layer, a second layer, and a third layer; using the first plurality of vias to form a gate electrode of a transistor, the gate electrode being located at the second layer; using the second plurality of vias to form a second electrode of the transistor, the second electrode being located at the first layer; and using a via common to the first plurality of vias and the second plurality of vias to form a third electrode of the transistor, the third electrode extending through at least the third layer.

[0276] In some examples of the methods 1200 and apparatus described herein, forming a gate electrode of a transistor may include operations, features, circuit systems, means, or instructions for: forming a channel aligned with the first set of vias at the second layer; forming an insulating material conformal to the channel; and filling the channel with an electrode material based on forming the insulating material. Some examples of the methods 1200 and apparatus described herein may further include operations, features, circuit systems, means, or instructions for: using the via to remove a portion of the gate electrode to form a cavity at the second layer and using the via to form an oxide material located in the cavity at the second layer and in contact with the gate electrode. Some examples of the methods 1200 and apparatus described herein may further include operations, features, circuit systems, means, or instructions for: using the via to remove a portion of the second electrode to form a cavity at the first layer and using the via to form an ohmic material located in the cavity at the first layer and in contact with the second electrode. Some examples of the method 1200 and apparatus described herein may further include operations, features, circuitry, means, or instructions for forming a cavity spanning the first layer and the second layer using the via and forming semiconductor material in the cavity spanning the first layer and the second layer using the via.

[0277] Some examples of the methods 1200 and apparatus described herein may further include operations, features, circuit systems, components, or instructions for using the via to form an insulating material in contact with the semiconductor material. Some examples of the methods 1200 and apparatus described herein may further include operations, features, circuit systems, components, or instructions for: using the via to form a cavity at the third layer and using the via to form an ohmic material located in the cavity at the third layer and in contact with the third electrode. In some examples of the methods 1200 and apparatus described herein, forming the third electrode of the transistor may include operations, features, circuit systems, components, or instructions for: using the via to form a hole through the stack to the logic circuit system layer and filling the hole with an electrode material. In some examples of the method 1200 and apparatus described herein, forming a second electrode of the transistor may include operations, features, circuit systems, components, or instructions for: forming a channel aligned with a second set of vias at a first layer, wherein the second set of vias forms a second row of vias that intersects a first row of vias formed by the first set of vias; filling the channel at the first layer with an electrode material; and forming a set of dielectric plugs corresponding to the second set of vias, wherein the dielectric plugs extend through the electrode material in the channel at the first layer.

[0278] Fig.13 A method 1300 for supporting thin film transistors and related manufacturing techniques according to an embodiment of the present disclosure is described. The operations of the method 1300 may be performed by, for example, reference 1300 herein. Figures 4A to 4AA The described method is implemented.

[0279] In block 1305, a first via, a second via, and a third via may be formed through a top layer of a stack including a first layer and a second layer. The operations of block 1305 may be performed according to methods described herein. In a specific example, aspects of the operations of block 1305 may be performed as described in reference to Figures 4A to 4AA A portion of one or more processes being described.

[0280] In block 1310, a first via may be used to form a gate electrode of a transistor. The operations of block 1310 may be performed according to methods described herein. In a specific example, aspects of the operations of block 1310 may be performed as described in reference to Figures 4A to 4AA A portion of one or more processes being described.

[0281] In block 1315, a second via may be used to form a second electrode of the transistor, the second electrode extending through the first layer and the second layer. The operations of block 1315 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1315 may be performed as described in reference to Figures 4A to 4AA A portion of one or more processes being described.

[0282] In block 1320, a third electrode of the transistor may be formed using at least the first via and the third via. The operations of block 1320 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1320 may be performed as described in reference to FIG. Figures 4A to 4AA A portion of one or more processes being described.

[0283] In some examples, an apparatus described herein may perform one or more methods, such as method 1300. The apparatus may include features, circuitry, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: forming a first via, a second via, and a third via through a top layer of a stack including a first layer and a second layer; forming a gate electrode of a transistor using the first via; forming a second electrode of the transistor using the second via, the second electrode extending through the first layer and the second layer; and forming a third electrode of the transistor using at least the first via and the third via.

[0284] In some examples of the methods 1300 and apparatus described herein, forming a gate electrode of a transistor may include features, circuitry, means, or instructions for: forming a channel at a second layer using a set of vias including a first via; forming an insulating material conformal to the channel at the second layer; and filling the channel with an electrode material contacting the insulating material. In some cases, the method 1300 may further include features, circuitry, means, or instructions for: forming a cavity at the first layer using the first via to expose at least a portion of the gate electrode; forming an oxide material contacting the gate electrode using the first via based on forming the cavity; and forming a semiconductor material located in the cavity at the first layer and contacting the oxide material using the first via.

[0285] In some cases, the methods 1300 and apparatus described herein may further include features, circuitry, means, or instructions for: forming a second cavity at the first layer using at least the second via to expose at least a portion of the third electrode and the semiconductor material; forming a third cavity at the first layer using the third via to expose the semiconductor material; and filling the second cavity and the third cavity at the first layer with an ohmic material. In some examples of the methods 1300 and apparatus described herein, forming a third electrode of a transistor may include features, circuitry, means, or instructions for: forming a first channel at the first layer using at least the first via and the third via; filling the first channel at the first layer with an electrode material; forming a second channel narrower than the first channel in the electrode material within the first channel at the first layer; and filling the second channel with a dielectric material. In some examples of the methods 1300 and apparatus described herein, forming a second electrode of a transistor may include features, circuitry, means, or instructions for: forming a hole through the stack to the logic circuitry layer using the second via and filling the hole with the electrode material.

[0286] Fig.14 A method 1400 for supporting thin film transistors and related manufacturing techniques according to an embodiment of the present disclosure is described. The operations of the method 1400 may be performed by, for example, reference 1400 herein. Figures 5A to 5N or Figures 6A to 6R The described method is implemented.

[0287] In block 1405, a first set of vias, a second set of vias, and a third via may be formed through a top layer of a stack including a first layer, a second layer, and a third layer. The operations of block 1405 may be performed according to methods described herein. In a specific example, aspects of the operations of block 1405 may be performed as described in reference to Figures 5A to 5N or Figures 6A to 6R A portion of one or more processes being described.

[0288] In block 1410, a gate electrode of a transistor may be formed using the first set of vias, the gate electrode being located at the second layer. The operations of block 1410 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1410 may be performed as described in reference to Figures 5A to 5N or Figures 6A to 6R A portion of one or more processes being described.

[0289] In block 1415, a second set of vias may be used to form a second electrode of the transistor, the second electrode being located at the first layer. The operations of block 1415 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1415 may be performed as described in reference to Figures 5A to 5N or Figures 6A to 6R A portion of one or more processes being described.

[0290] In block 1420, a third via may be used to form a third electrode of the transistor, the third electrode extending through at least the third layer. The operations of block 1420 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1420 may be performed as described in reference to Figures 5A to 5N or Figures 6A to 6R A portion of one or more processes being described.

[0291] In some examples, an apparatus described herein may perform one or more methods, such as method 1400. The apparatus may include features, circuitry, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: forming a first plurality of vias, a second plurality of vias, and a third via through a top layer of a stack including a first layer, a second layer, and a third layer; using the first plurality of vias to form a gate electrode of a transistor, the gate electrode being located at the second layer; using the second plurality of vias to form a second electrode of the transistor, the second electrode being located at the first layer; using the third via to form a third electrode of the transistor, the third electrode extending at least through the third layer.

[0292] In some examples of the methods 1400 and apparatus described herein, forming a gate electrode of a transistor may include features, circuitry, means, or instructions for: forming a channel at the second layer using a first set of vias; forming an insulating material in contact with the channel at the second layer; filling the channel at the second layer using an electrode material; and forming a set of corresponding holes extending through the electrode material using the first set of vias. In some cases, the methods 1400 and apparatus described herein may also include features, circuitry, means, or instructions for: forming a third set of vias through the top layer of the stack and forming a cavity spanning the first layer, the second layer, and the third layer using the third set of vias, wherein the cavity spanning the first layer, the second layer, and the third layer exposes the insulating material conformal to the gate electrode.

[0293] In some cases, the methods 1400 and apparatus described herein may also include features, circuitry, means, or instructions for: using a third set of vias to remove a portion of the insulating material in contact with the gate electrode; after removing the portion of the insulating material, using the third set of vias to form an oxide material in contact with the gate electrode; and filling the cavity spanning the first layer, the second layer, and the third layer with a semiconductor material in contact with the oxide material. In some cases, the methods 1400 and apparatus described herein may also include features, circuitry, means, or instructions for: forming a hole through the semiconductor material to the logic circuitry layer and filling the hole with an electrode material to form a fourth electrode of the transistor.

[0294] In some cases, the method 1400 and apparatus described herein may further include features, circuit systems, components, or instructions for: using a third via to form a cavity at the first layer to expose the semiconductor material and the second electrode; using the third via to fill the cavity at the first layer with an ohmic material, the ohmic material being in contact with the semiconductor material and the second electrode; using the third via to remove a portion of the ohmic material; using the third via to form an insulating material in contact with the ohmic material; and using the third via to form an ohmic material located at the third layer and in contact with the semiconductor material.

[0295] In some cases, the methods 1400 and apparatus described herein may further include features, circuitry, means, or instructions for: filling a cavity across the first, second, and third layers with an ohmic material; forming a second cavity across the first, second, and third layers with a subset of the third set of vias and the third via; and filling the second cavity across the first, second, and third layers with a semiconductor material. In some cases, the methods 1400 and apparatus described herein may further include features, circuitry, means, or instructions for: forming a hole through the first, second, and third layers with a third via; forming an insulating material in contact with the semiconductor material at the first and second layers with a third via; forming a cavity at the third layer with a third via; and filling the cavity at the third layer with an ohmic material. In some examples of the methods 1400 and apparatus described herein, forming a third electrode of a transistor may include features, circuitry, means, or instructions for: forming a hole through the stack to the logic circuitry layer with a third via and filling the hole with an electrode material.

[0296] Fig.15 A method 1500 for supporting thin film transistors and related manufacturing techniques according to an embodiment of the present disclosure is described. The operations of the method 1500 may be implemented by a controller or components thereof as described herein. For example, the operations of the method 1500 may be implemented by a controller (e.g., reference Figure 1 The memory controller 140 described herein may be executed by the controller. In some examples, the controller may execute a set of instructions to control the functional elements of the memory array to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform aspects of the functions described herein.

[0297] In block 1505, the controller may receive an indication of an access operation of a memory unit. The operations of block 1505 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1505 may be performed as described in reference to Figure 7C , 7D , 8A to 8C and part of one or more processes described in 9.

[0298] In block 1510, the controller may identify a memory cell layer including memory cells, the layer being included in a set of layers. The operations of block 1510 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1510 may be performed as referenced. Figure 7C , 7D , 8A to 8C and part of one or more processes described in 9.

[0299] In block 1515, the controller may couple an electrode included in the layer with a conductive plug extending through the layer set based on identifying and using a first transistor included in the layer. The operations of block 1515 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1515 may be performed as described in reference to Figure 7C , 7D , 8A to 8C and part of one or more processes described in 9.

[0300] In block 1520, the controller may drive the electrode to a voltage associated with an access operation based on coupling the electrode with the conductive plug. The operations of block 1520 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1520 may be performed as described in reference to Figure 7C , 7D , 8A to 8C and part of one or more processes described in 9.

[0301] An apparatus for performing one or more methods, such as method 1500, is described. The apparatus may include means for receiving an indication of an access operation of a memory cell, means for identifying a memory cell level including the memory cell, the level included in a set of levels, means for coupling an electrode included in the level with a conductive plug extending through the set of levels based on identifying and using a first transistor included in the level, and means for driving the electrode to a voltage associated with the access operation based on coupling the electrode with the conductive plug.

[0302] Another apparatus for performing one or more methods, such as method 1500, is described. The apparatus may include a memory array and a memory controller in electronic communication with the memory array, wherein the memory controller is operable to: receive an indication of an access operation of a memory cell; identify a memory cell layer including the memory cell, the layer included in a set of layers; couple an electrode included in the layer with a conductive plug extending through the set of layers based on identifying and using a first transistor included in the layer; and drive the electrode to a voltage associated with the access operation based on coupling the electrode with the conductive plug.

[0303] Some examples of the method 1500 and apparatus described herein may further include a process, feature, component, or instruction for coupling a second electrode included in a layer with a second conductive plug extending through the layer group based on identifying and using a second transistor included in the layer. Some examples of the method 1500 and apparatus described herein may further include a process, feature, component, or instruction for driving a second electrode to a second voltage associated with an access operation based on coupling the second electrode with a second conductive plug. Some examples of the method 1500 and apparatus described herein may further include a process, feature, component, or instruction for coupling an electrode included in a layer with a conductive plug based on identifying and using a third transistor included in a second layer of the layer group. Some examples of the method 1500 and apparatus described herein may further include a process, feature, component, or instruction for coupling a second electrode included in a layer with a second conductive plug based on identifying and using a fourth transistor included in a third layer of the layer group, wherein the layer may be located between the second layer and the third layer.

[0304] In some examples of the methods 1500 and apparatus described herein, the electrode may include an access line of the first type. Some examples of the methods 1500 and apparatus described herein may further include processes, features, means, or instructions for coupling an access line of the first type included in each level of the level group of the level group based on identifying and using transistors included in a subset of levels of the level group, wherein the subset does not include levels. Some examples of the methods 1500 and apparatus described herein may further include processes, features, means, or instructions for driving an access line of the first type included in each level of the level group of the level group to a third voltage associated with an access operation based on coupling the access line of the first type included in each level of the level group of the level group with the third conductive plug.

[0305] Fig.16 A method 1600 for supporting thin film transistors and related manufacturing techniques according to an embodiment of the present disclosure is described. The operations of the method 1600 may be implemented by a controller or components thereof as described herein. For example, the operations of the method 1600 may be implemented by a controller (e.g., reference Figure 1 The memory controller 140 described herein may be executed by the controller. In some examples, the controller may execute a set of instructions to control the functional elements of the memory array to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform aspects of the functions described herein.

[0306] In block 1605, the controller may receive an indication of an access operation of a memory unit. The operations of block 1605 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1605 may be performed as described in reference to Figure 7C , 7D , 8A to 8C and part of one or more processes described in 9.

[0307] In block 1610, the controller may identify a memory cell layer including memory cells, the layer being included in a set of layers. The operations of block 1610 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1610 may be performed as referenced. Figure 7C , 7D , 8A to 8C and part of one or more processes described in 9.

[0308] In block 1615, the controller may couple an electrode included in the layer with a conductive plug extending through the layer set based on identifying and using a first transistor included in the layer. The operations of block 1615 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1615 may be performed as described in reference to Figure 7C , 7D , 8A to 8C and part of one or more processes described in 9.

[0309] In block 1620, the controller may drive the electrode to a voltage associated with an access operation based on coupling the electrode with the conductive plug. The operations of block 1620 may be performed according to the methods described herein. In a specific example, aspects of the operations of block 1620 may be performed as described in reference to Figure 7C , 7D , 8A to 8C and part of one or more processes described in 9.

[0310] An apparatus for performing one or more methods, such as method 1600, is described. The apparatus may include means for receiving an indication of an access operation of a memory cell, means for identifying a memory cell level including the memory cell, the level included in a set of levels, means for coupling an electrode included in the level with a conductive plug extending through the level set based on identifying and using a first transistor included in the level, means for driving the electrode to a voltage associated with the access operation based on coupling the electrode with the conductive plug, means for coupling a second electrode included in the level with a second conductive plug extending through the level set based on identifying and using a second transistor included in the level, and means for driving the second electrode to a second voltage associated with the access operation based on coupling the second electrode with the second conductive plug.

[0311] Another apparatus for performing one or more methods, such as method 1600, is described. The apparatus may include a memory array and a memory controller in electronic communication with the memory array, wherein the memory controller is operable to: receive an indication of an access operation of a memory cell; identify a memory cell layer including the memory cell, the layer included in a set of layers; based on identifying and using a first transistor included in the layer, coupling an electrode included in the layer with a conductive plug extending through the set of layers; based on coupling the electrode with the conductive plug, driving the electrode to a voltage associated with the access operation; based on identifying and using a second transistor included in the layer, coupling a second electrode included in the layer with a second conductive plug extending through the set of layers; and based on coupling the second electrode with the second conductive plug, driving the second electrode to a second voltage associated with the access operation.

[0312] It should be noted that the methods described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more methods may be combined.

[0313] Any of a variety of different technologies may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to in the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate several signals as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a bus of signals, where the bus may have various bit widths.

[0314] The terms "electronic communication" and "coupling" refer to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components or may include intermediate components. Components that are electronically in communication or coupled with each other may actively exchange electrons or signals (e.g., in a powered-on circuit system) or may not actively exchange electrons or signals (e.g., in a powered-off circuit system) but may be configured and operated to exchange electrons or signals after the circuit is powered on. For example, two components that are physically connected via a switch (e.g., a transistor) are in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

[0315] As used herein, the term "substantially" means that the modified property (such as a verb or adjective modified by the term "substantially") need not be absolute, but rather comes close enough to achieving the advantage of the property.

[0316] As used herein, the term "electrode" may refer to an electrical conductor and, in some cases, may serve as an electrical contact for a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, or the like that provides a conductive pathway between elements or components of memory device 100.

[0317] The chalcogenide material may be a material or alloy including at least one of the elements S, Se and Te. The chalcogenide material may include an alloy of S, Se, Te, Ge, As, Al, Si, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge- As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te- Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. As used herein, chemical composition symbols connected by hyphens indicate the elements contained in a particular compound or alloy and are intended to represent all stoichiometric amounts involving the indicated elements. For example, Ge-Te may contain Ge x Te y, where x and y may be any positive integer. Other examples of variable resistance materials may include binary metal oxide materials or mixed valence oxides that include two or more metals, such as transition metals, alkaline earth metals, and / or rare earth metals. Embodiments are not limited to one or more specific variable resistance materials associated with the memory component of the memory cell. For example, other examples of variable resistance materials may be used to form the memory component and may include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, among others.

[0318] The term "isolation" refers to a relationship between components in which electrons cannot currently flow between the components; if there is an open circuit between the components, they are isolated from each other. For example, two components physically connected by a switch may be isolated from each other when the switch is open.

[0319] The devices discussed herein, including memory device 100, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP) or an epitaxial layer of a semiconductor material on another substrate. The conductivity of a substrate or a sub-region of a substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation or any other doping method during the initial formation or growth of the substrate.

[0320] One or more transistors discussed herein may represent a field effect transistor (FET) and include a four-terminal device including a source, a drain, a gate, and a base (or substrate). The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel (which may be part of the base). If the channel is n-type (i.e., most carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated." A transistor may be turned “off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0321] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "better than" or "superior to" other examples. The embodiments include specific details for understanding the present disclosure. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid making the concepts of the described examples unclear.

[0322] In the accompanying drawings, similar components or features may have the same reference element number. In addition, various components of the same type may be distinguished by following the reference element number with a dash and a second element number that distinguishes the similar components. If only the first reference element number is used in the specification, the description applies to any of the similar components having the same first reference element number, regardless of the second reference element number.

[0323] Any of a variety of different technologies may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to in the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0324] The various illustrative blocks and modules described in conjunction with the present disclosure may be implemented or executed using a general purpose processor designed to perform the functions described herein, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0325] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted by a computer-readable medium as one or more instructions or program codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of the software, the functions described herein may be implemented using software, hardware, firmware, hard wiring, or a combination of any of these executed by a processor. The features of the implementation functions may also be physically located at various locations, including being distributed so that some functions are implemented at different physical locations. In addition, as used herein (included in the claims), the "or" used in a list of items (e.g., in conjunction with a list of items such as "at least one of..." or "one or more of..." phrases) indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on..." should not be interpreted as referring to a set of closed conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on..." should be interpreted in the same manner as the phrase "based at least in part on..."

[0326] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media that can be accessed by a general or special-purpose computer. For example, but not limited to, non-transitory computer-readable media may include RAM, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage device or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special-purpose computer or a general or special-purpose processor. Any other non-transitory media. In addition, any connection is appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0327] This description is provided to enable those skilled in the art to make or use the present disclosure. Those skilled in the art will readily appreciate various modifications of the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: forming a first plurality of vias and a second plurality of vias through a top layer of a stack comprising a first layer, a second layer, and a third layer; forming a gate electrode of a transistor using the first plurality of vias, the gate electrode being located at the second layer; forming a second electrode of the transistor using the second plurality of vias, the second electrode being located at the first layer; forming a third electrode of the transistor using a via common to the first plurality of vias and the second plurality of vias, the third electrode extending through at least the third layer; removing a portion of the gate electrode using the via to form a cavity at the second layer; and An oxide material is formed using the via in the cavity at the second layer and in contact with the gate electrode.

2. The method of claim 1 , wherein forming the gate electrode of the transistor comprises: forming trenches at the second layer aligned with the first plurality of vias; forming an insulating material conformal to the channel; and The trench is filled with an electrode material based at least in part on forming the insulating material.

3. The method according to claim 1, further comprising: removing a portion of the second electrode using the via to form a cavity at the first layer; and An ohmic material is formed using the via in the cavity at the first layer and in contact with the second electrode.

4. The method according to claim 1, wherein forming the third electrode of the transistor comprises: using the via to form a hole through the stack to a logic circuitry layer; and The pores are filled with electrode material.

5. A method comprising: forming a first plurality of vias and a second plurality of vias through a top layer of a stack comprising a first layer, a second layer, and a third layer; forming a gate electrode of a transistor using the first plurality of vias, the gate electrode being located at the second layer; forming a second electrode of the transistor using the second plurality of vias, the second electrode being located at the first layer; forming a third electrode of the transistor using a via common to the first plurality of vias and the second plurality of vias, the third electrode extending through at least the third layer; using the via to form a cavity spanning the first layer and the second layer; and The via is used to form semiconductor material in the cavity spanning the first layer and the second layer.

6. The method according to claim 5, further comprising: The via is used to form an insulating material in contact with the semiconductor material.

7. A method comprising: forming a first plurality of vias and a second plurality of vias through a top layer of a stack comprising a first layer, a second layer, and a third layer; forming a gate electrode of a transistor using the first plurality of vias, the gate electrode being located at the second layer; forming a second electrode of the transistor using the second plurality of vias, the second electrode being located at the first layer; forming a third electrode of the transistor using a via common to the first plurality of vias and the second plurality of vias, the third electrode extending through at least the third layer; using the via to form a cavity at the third layer; and An ohmic material is formed using the via in the cavity at the third layer and in contact with the third electrode.

8. A method comprising: forming a first plurality of vias and a second plurality of vias through a top layer of a stack comprising a first layer, a second layer, and a third layer; forming a gate electrode of a transistor using the first plurality of vias, the gate electrode being located at the second layer; forming a second electrode of the transistor using the second plurality of vias, the second electrode being located at the first layer, wherein forming the second electrode of the transistor comprises: forming trenches at the first layer aligned with the second plurality of vias, wherein the second plurality of vias form a second row of vias intersecting a first row of vias formed by the first plurality of vias; filling the trench at the first layer with an electrode material; and forming a plurality of dielectric plugs corresponding to the second plurality of vias, wherein the dielectric plugs extend through the electrode material in the trench at the first layer; and A third electrode of the transistor is formed using a via common to the first and second pluralities of vias, the third electrode extending through at least the third layer.

9. A device comprising: a conductive plug extending through the stack including the first layer, the second layer, and the third layer; A semiconductor material located at the first layer and the second layer, wherein the semiconductor material surrounds the conductive plug; an oxide material located at the second layer and in contact with the semiconductor material; a gate electrode located at the second layer and in contact with the oxide material; and An ohmic material is located at the third layer, the ohmic material is in contact with the semiconductor material and surrounds the conductive plug.

10. The apparatus of claim 9, further comprising: An insulating material is inserted between the conductive plug and the semiconductor material.

11. The apparatus of claim 9, further comprising: An ohmic material is located at the first layer, and the ohmic material surrounds the semiconductor material and contacts the semiconductor material.

12. A method comprising: forming a first via, a second via, and a third via through a top layer of a stack including the first layer and the second layer; forming a gate electrode of a transistor using the first via; forming a second electrode of the transistor using the second via, the second electrode extending through the first layer and the second layer; and forming a third electrode of the transistor using at least the first via and the third via, wherein forming the second electrode of the transistor comprises: using the second via to form a hole through the stack to a logic circuitry layer; and The pores are filled with electrode material.

13. The method of claim 12, wherein forming the gate electrode of the transistor comprises: forming a channel at the second layer using a plurality of vias including the first via; forming an insulating material conformal to the channel at the second layer; and The trench is filled with an electrode material contacting the insulating material.

14. The method according to claim 12, further comprising: forming a cavity at the first layer using the first via to expose at least a portion of the gate electrode; forming an oxide material in contact with the gate electrode using the first via based at least in part on forming the cavity; and A semiconductor material is formed in the cavity at the first layer and in contact with the oxide material using the first via.

15. The method according to claim 12, further comprising: forming a second cavity at the first layer using at least the second via to expose at least a portion of the third electrode and semiconductor material; forming a third cavity at the first layer using the third via to expose the semiconductor material; and The second cavity and the third cavity at the first layer are filled with an ohmic material.

16. The method of claim 12, wherein forming the third electrode of the transistor comprises: forming a first channel at the first layer using at least the first via and the third via; filling the first trench at the first layer with an electrode material; forming a second channel narrower than the first channel in the electrode material within the first channel at the first layer; and The second trench is filled with a dielectric material.

17. An apparatus comprising: a dielectric plug extending through the stack including the first layer and the second layer; a semiconductor material located at the first layer, the semiconductor material surrounding the dielectric plug; a gate electrode located at the second layer, the gate electrode contacting the dielectric plug and surrounding the dielectric plug; and An oxide material contacts the dielectric plug and is located between the semiconductor material and the gate electrode.

18. The apparatus of claim 17, further comprising: a conductive plug extending through the stack; and An ohmic material is located at the first layer, and the ohmic material surrounds the conductive plug.

19. The apparatus of claim 18, wherein the ohmic material surrounding the conductive plug contacts the semiconductor material surrounding the dielectric plug.

20. The apparatus of claim 18, further comprising: a second dielectric plug extending through the stack, wherein: The semiconductor material at the first layer surrounding the dielectric plug includes a first segment of the semiconductor material; and The ohmic material surrounding the conductive plug is in contact with a second segment of the semiconductor material surrounding the second dielectric plug.

21. A method comprising: forming a first plurality of vias, a second plurality of vias, and a third via through a top layer of a stack comprising the first layer, the second layer, and the third layer; forming a gate electrode of a transistor using the first plurality of vias, the gate electrode being located at the second layer; forming a second electrode of the transistor using the second plurality of vias, the second electrode being located at the first layer; forming a third electrode of the transistor using the third via, the third electrode extending at least through the third layer; forming a third plurality of vias through the top layer of the stack; as well as A cavity is formed using the third plurality of vias spanning the first layer, the second layer, and the third layer, wherein the cavity spanning the first layer, the second layer, and the third layer exposes an insulating material conformal to the gate electrode.

22. The method of claim 21 , wherein forming the gate electrode of the transistor comprises: forming a channel at the second layer using the first plurality of vias; forming an insulating material in contact with the channel at the second layer; filling the trench at the second layer with an electrode material; and The first plurality of vias are used to form a corresponding plurality of holes extending through the electrode material.

23. The method of claim 21, further comprising: removing a portion of the insulating material in contact with the gate electrode using the third plurality of vias; forming an oxide material in contact with the gate electrode using the third plurality of vias after removing the portion of the insulating material; and The cavity spanning the first layer, the second layer, and the third layer is filled with a semiconductor material in contact with the oxide material.

24. The method of claim 23, further comprising: forming a hole through the semiconductor material to a logic circuitry layer; and The hole is filled with an electrode material to form a fourth electrode of the transistor.

25. The method of claim 23, further comprising: forming a cavity at the first layer using the third via to expose the semiconductor material and the second electrode; and using the third via to fill the cavity at the first layer with an ohmic material, the ohmic material being in contact with the semiconductor material and the second electrode; removing a portion of the ohmic material using the third via; forming an insulating material in contact with the ohmic material using the third via; and The ohmic material is formed at the third layer and in contact with the semiconductor material using the third via.

26. The method of claim 21, further comprising: filling the cavity spanning the first layer, the second layer, and the third layer with an ohmic material; forming a second cavity spanning the first layer, the second layer, and the third layer using a subset of the third plurality of vias and the third via; and The second cavity spanning the first layer, the second layer, and the third layer is filled with a semiconductor material.

27. The method of claim 26, further comprising: using the third via to form a hole through the first layer, the second layer, and the third layer; forming an insulating material in contact with the semiconductor material at the first layer and the second layer using the third via; forming a cavity at the third layer using the third via; and The cavity at the third layer is filled with the ohmic material.

28. The method of claim 21, wherein forming the third electrode of the transistor comprises: forming a hole through the stack to a logic circuitry layer using the third via; and The pores are filled with electrode material.

29. An apparatus comprising: a conductive plug extending through the stack including the first layer, the second layer, and the third layer; a gate electrode located at the second layer; a second electrode located at the first layer; and A semiconductor material is located at the first layer and the second layer, the semiconductor material is coupled with the second electrode via a first segment of the ohmic material at the first layer and is coupled with the conductive plug via a second segment of the ohmic material at the third layer.

30. The apparatus of claim 29, wherein the semiconductor material at the first layer and the second layer extends into the third layer.

31. The apparatus of claim 29, further comprising: A dielectric plug extends through the gate electrode.

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