Microdevice with floating conductive layer

Abstract

A micro device with a floating conductive layer, such as a transformer and a capacitor, is disclosed. The floating conductive layer can be disposed in an insulator layer and can reduce the maximum electric field between a first planar conductor and a second planar conductor of the micro passive device. Reducing the maximum electric field between the first planar conductor and the second planar conductor can reduce adverse effects on electronic components.

Description

Technical Field

[0001] The present application relates to micro devices, such as transformers or capacitors. Background Art

[0002] Tiny devices such as transformers or capacitors can provide electric fields between components. Electric fields can have undesirable effects on electrical components. Summary of the invention

[0003] A micro device with a floating conductive layer, such as a transformer and a capacitor, is disclosed. The floating conductive layer can be disposed in an insulator layer and can reduce the maximum electric field between a first planar conductor and a second planar conductor of the micro passive device. Reducing the maximum electric field between the first planar conductor and the second planar conductor can reduce adverse effects on electronic components.

[0004] According to a first aspect of the present disclosure, an isolated micro passive device is provided, which is configured to be disposed on a substrate including an upper surface. The isolated micro passive device includes: a first planar conductor; a second planar conductor, which is configured to be disposed between the first planar conductor and the substrate; an insulator layer disposed between the first planar conductor and the second planar conductor; and a floating conductive layer in the insulator layer.

[0005] According to a second aspect of the present disclosure, an isolated micro passive device is provided, which is configured to be disposed on a substrate including an upper surface. The isolated micro passive device includes: a first planar conductor; a second planar conductor, configured to be disposed between the first planar conductor and the substrate; a first insulator layer disposed between the first planar conductor and the second planar conductor; a second insulator layer disposed between the first planar conductor and the second planar conductor; and a floating conductive layer disposed between the first insulator layer and the second insulator layer.

[0006] According to a third aspect of the present disclosure, an isolated micro passive device is provided, which is configured to be disposed on a substrate including an upper surface. The isolated micro passive device includes: a first planar conductor; a second planar conductor, which is configured to be disposed between the first planar conductor and the substrate; and a member for reducing a maximum electric field between the first planar conductor and the second planar conductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects and embodiments of the present application will be described with reference to the following drawings. It should be understood that the drawings are not necessarily drawn to scale. Items appearing in multiple figures are represented by the same reference numerals in all the figures in which they appear.

[0008] Figure 1 is a cross-sectional side view of a micro passive device;

[0009] Figure 2 is a cross-sectional side view of a micro passive device;

[0010] Figure 3 It is a top view of the assembly of micro passive devices;

[0011] Figure 4 It is a top view of the assembly of micro passive devices;

[0012] Figure 5 is a cross-sectional side view of a micro passive device;

[0013] Figure 6 is a cross-sectional side view of a micro passive device;

[0014] Figure 7 is a cross-sectional side view of a micro passive device;

[0015] Figure 8 is a cross-sectional side view of a micro passive device; and

[0016] Fig. 9 is a cross-sectional side view of a micro passive device. DETAILED DESCRIPTION

[0017] According to aspects of the present application, a micro device is provided. The micro device may include an isolated micro passive device, and may include a first planar conductor and a second planar conductor, with an insulator layer between the first planar conductor and the second planar conductor. The micro passive device is configured to exhibit a reduced maximum electric field. The floating conductive layer in the insulator layer may be configured to reduce the maximum electric field.

[0018] The present disclosure relates to miniature passive devices. Two types of miniature passive devices are planar coil transformers and planar capacitors. Transformers can be used to convert a first voltage level at a first portion of a circuit to a second voltage level at a second portion of the circuit. Transformers and capacitors can transmit data and / or power signals. Transformers and capacitors can be used to isolate signals between two portions of a circuit and thus can form part of an isolator or isolation device. Transformers and capacitors can typically transmit AC signals, but can also transmit DC signals.

[0019] Miniature passive devices such as transformers and capacitors may include two or more miniature planar conductors. Each of the first conductor and the second conductor may be arranged on a substrate in a substantially planar configuration. The planar conductor of the transformer may include a planar coil. The planar coil may be patterned on the substrate in a generally spiral shape around a conductor axis. The planar conductor of the capacitor may include a flat plate. The flat plate may be patterned on the substrate in a generally continuous circular pattern around the conductor axis.

[0020] The first conductor and the second conductor may be maintained at different potentials. Due to the different potentials of the first conductor and the second conductor, an electric field may be generated between the first conductor and the second conductor. The electric field may be generated in the transformer due to parasitic capacitance between transformer coils. The electric field may be generated in the capacitor due to the operation of the capacitor.

[0021] Such an electric field may include a point with a maximum electric field. The inventors have recognized that electric fields in electronic devices may have adverse effects on electrical components. The inventors have recognized that maximum electric fields in electronic devices may be aspects of particularly undesirable effects on electrical components.

[0022] The inventors have recognized that increasing the height of the insulator layer can reduce the average electric field of the electronic device. However, the inventors have further recognized that, while increasing the height of the insulator layer can reduce the average electric field of the electronic device inversely proportional to the height of the insulator, increasing the height of the insulator layer can reduce the maximum electric field of the electronic device not inversely proportional to the increase in height. For example, doubling the height of the insulator can reduce the average electric field E_av to the average electric field E_av / 2, but the same increase in the height of the insulator unexpectedly only reduces the maximum electric field E_max to the maximum electric field E_max / (sqrt(2)). The inventors have recognized that increasing the height of the insulator produces diminishing returns to reducing the maximum electric field.

[0023] The inventors have recognized that providing a floating conductive layer in an insulator layer can reduce the maximum electric field, not just the reduction in the maximum electric field due to the increase in the height of the insulator. For example, in some embodiments, increasing the height of the insulator by a factor of two, combined with including a floating conductive layer at approximately half the height of the insulator layer, can reduce the maximum electric field E_max to the maximum electric field E_max / 2. Therefore, aspects of the present disclosure provide a micro passive device having a floating conductive layer in an insulator layer.

[0024] Figure 1 A cross-sectional side view of micro passive device 100 is shown. Micro passive device 100 is disposed on substrate 102 having upper surface 104 and includes layer 106, insulator layer 108, conductor 110, conductor 112, conductor layer 114, shown including conductor 116 and voltage source 118.

[0025] The micro passive device 100 may include one of various micro passive devices. In some embodiments, the micro passive device 100 includes a transformer. In some embodiments, the micro passive device 100 includes a capacitor. In some embodiments, the micro passive device 100 includes an inductor. In some embodiments, the micro passive device 100 includes an isolator or an isolated micro passive device, for example, an isolated transformer or an isolated capacitor.

[0026] The micro passive device 100 includes a conductor 110. In some embodiments, the conductor 110 includes a planar conductor. Figure 1 In the illustrative embodiment of , conductor 110 is disposed in layer 106. In some embodiments, layer 106 may include a first layer. Layer 106 may be patterned to form conductor 110. In various embodiments, layer 106 may include an oxide layer on substrate 102. For example, layer 106 may include glass or silicon dioxide.

[0027] exist Figure 1 1 , conductor 110 is disposed above substrate 102. In embodiments where micro passive device 100 includes a transformer, conductor 110 may include a coil of the transformer. In embodiments where micro passive device 100 includes a capacitor, conductor 110 may include a plate of the capacitor. At least one terminal of conductor 110 may be coupled to a voltage source such as voltage source 118.

[0028] The micro passive device 100 includes a conductor 112. In some embodiments, the conductor 112 includes a planar conductor. The conductor 112 can be arranged in the insulator layer 108, for example, substantially on top of the insulator layer 108. In other embodiments, the conductor 112 can be arranged in a layer above the insulator layer. The conductor 112 can be arranged above and above the conductor 110. The conductor 112 can be arranged so that the conductor 110 is configured to be arranged between the conductor 112 and the substrate 102. In an embodiment where the micro passive device 100 includes a transformer, the conductor 112 can include a coil of the transformer. In an embodiment where the micro passive device 100 includes a capacitor, the conductor 112 can include a plate of the capacitor. At least one terminal of the conductor 112 can be coupled to a voltage source such as a voltage source 118.

[0029] In some embodiments, conductor 112 may include a first conductor and conductor 110 may include a second conductor. Conductor 110 and conductor 112 may be coupled. In an exemplary embodiment where conductor 110 is arranged on the primary side of micro passive device 100 and conductor 112 is arranged on the secondary side of micro passive device 100, conductor 110 may be a transmitting conductor and conductor 112 may be a receiving conductor. Conductor 110 may transmit a signal received by conductor 112. However, each conductor may include a transmitting conductor arranged on the primary side or a receiving conductor arranged on the secondary side. For example, in some embodiments, conductor 112 may be arranged on the primary side as a transmitting conductor, and conductor 110 may be arranged on the secondary side as a receiving conductor. In a transformer, the transmitting conductor may include a transmitting coil, and the receiving conductor may include a receiving coil. In a capacitor, the transmitting conductor may include a transmitting plate, and the receiving conductor may include a receiving plate.

[0030] Conductor 110 and conductor 112 may each be arranged around a respective conductor axis. In some embodiments, such a conductor axis is perpendicular to the upper surface 104 of substrate 102. In some embodiments, conductor 110 is vertically spaced apart from conductor 112 along the conductor axis. In some embodiments, conductor 110 is disposed in a plane parallel to the upper surface 104 of substrate 102, and conductor 112 is disposed in a different plane parallel to the upper surface 104 of substrate 102. Conductor 110 and conductor 112 may be patterned in their respective layers so that conductor 110 and conductor 112 are patterned perpendicular to the conductor axis, respectively. In some embodiments, the conductor axes are substantially aligned with each other, or may include the same conductor axis.

[0031] The micro passive device 100 includes a conductive layer 114. In some embodiments, for example, when the conductive layer 114 is not coupled to other conductive elements, the conductive layer may include a floating conductive layer. In some embodiments, the conductive layer 114 is arranged so that it is only in contact with an insulating element such as the insulator layer 108. In some embodiments, the conductive layer 114 may not be maintained at any potential or grounded. In some embodiments, the conductive layer 114 may be embedded in the insulator layer 108. In some embodiments, the conductive layer 114 may be encapsulated by the insulator layer 108.

[0032] Conductive layer 114 is disposed between conductor 110 and conductor 112 along the direction of the conductor axis. Conductive layer 114 may further be disposed at least partially between conductor 110 and conductor 112 along a direction approximately perpendicular to the conductor axis.

[0033] In some embodiments, the conductive layer 114 may include a conductor 116, which may be a planar conductor. The conductor 116 may include a third conductor. The conductor 116 may include an intermediate conductor. For example, the conductor 116 may be patterned in a plane different from the conductors 110 and 112. The plane of the conductor 116 may be parallel to the upper surface 104 of the substrate 102, so that the conductor 116 is patterned perpendicular to the conductor axis. In some embodiments, the conductor 116 includes a first surface and a second surface. The first surface may be substantially planar. The second surface may be substantially planar. The first planar surface may face the conductor 110, and the second planar surface may face the conductor 112. In some embodiments, each of the first planar surface and the second planar surface is completely covered by the insulator layer 108. In various embodiments, the distance that the conductor 116 may extend in a direction perpendicular to the conductor axis is greater than the distance along one or more conductors 110 or conductors 112 extending in a direction perpendicular to the conductor axis. In various embodiments, the thickness of conductor 116 along the conductor axis may be greater than about 0.4 microns, greater than about 2 microns, less than about 6 microns, less than about 8 microns, between about 0.4 microns and about 8 microns, between about 2 microns and about 6 microns, or about 4 microns.

[0034] exist Figure 1 , the conductive layer 114 is arranged in the insulator layer 108. The insulator layer 108 is arranged between the conductor 110 and the conductor 112. In some embodiments, a first portion of the insulator layer 108 is arranged between the conductive layer 114 and the conductor 110. In some embodiments, a second portion of the insulator layer 108 is disposed between the conductive layer 114 and the conductor 112. In some embodiments, the insulator layer 108 can be formed as a first insulator layer between one or more of the substrate 102 or layer 106 and the conductive layer 114, and a second insulator layer between the conductive layer 114 and the conductor 112. The insulator layer 108 may include an isolation layer, which may be formed of an insulating or dielectric material. In some embodiments, the insulator layer 108 may include a polymer, such as polyimide.

[0035] An electric field may be generated between conductor 110 and conductor 112. In both embodiments where micro passive device 100 includes a transformer and both embodiments where micro passive device 100 includes a capacitor, an electric field may be generated between conductor 110 and conductor 112 when a voltage is applied between conductor 110 and conductor 112 by voltage source 118. In various embodiments, the voltage source may apply one or more of an AC signal, a DC signal, or a combination thereof to conductor 110 and conductor 112.

[0036] The electric field may be the result of a voltage difference between conductor 110 and conductor 112. In some embodiments, when micro passive device 100 includes a capacitor due to the operation of the capacitor, an electric field may occur. In some embodiments, when micro passive device 100 includes a transformer, an electric field may be generated due to parasitic capacitance between coils (e.g., planar coils) of the transformer. Within the electric field, there may be a point with a maximum electric field. Conductive layer 114 may be configured to reduce the maximum electric field of micro passive device 100. Conductors, such as, Figure 1 Conductor 116 in the micro passive device 100 can be configured to reduce the maximum electric field of the micro passive device 100. For example, the conductive layer 114 can float at an intermediate voltage potential, such as about halfway between the voltage potential of the conductor 110 and the voltage potential of the conductor 112. By floating at the intermediate voltage potential, the conductive layer can reduce the maximum electric field at any given point. The conductive layer 114 can float at the intermediate voltage potential by not being held at a voltage potential or grounded by other electronic components.

[0037] Conductors such as coils or plates, conductive layers such as planar conductors or conductive particles, and other elements may include various materials. In some embodiments, the conductors or conductive layers include conductive materials, such as metals, such as copper, gold, or aluminum, or may include semiconductor materials, such as doped semiconductor materials. In some embodiments, each conductor and conductive layer is arranged in a metallization layer, or in more than one metallization layer.

[0038] The substrate 102 has an upper surface 104. The upper surface 104 may be substantially flat. The upper surface of the substrate 104 is disposed between the substrate 102 and the layer 106.

[0039] According to aspects of the present application, a substrate such as substrate 102 may include various materials. In some embodiments, the substrate may include a semiconductor material. For example, the substrate may include a bulk or single crystal semiconductor substrate, such as a bulk or single crystal silicon substrate. In some embodiments, the substrate may include a deposited semiconductor substrate, such as polycrystalline silicon. In some embodiments, the substrate may include a silicon-on-insulator substrate or may include a buried oxide layer. Other semiconductor materials may be used as substrates. In some embodiments, a substrate such as substrate 102 may include a glass substrate or a printed circuit board (PCB).

[0040] Figure 2 1 shows a cross-sectional side view of a micro passive device 100, which shows distance A, distance B, distance C, distance D, distance E, distance F, distance G, and distance H. In some embodiments, it can be taken Figure 2 1, such that the illustrated cross-sections of insulator layer 108, conductor 110, conductor 112, and conductor 116 show the maximum dimension of each of these components along a direction perpendicular to the conductor axis.

[0041] In some embodiments, distance A comprises a measurement between conductor 112 and conductor 116 along a direction parallel to the conductor axis. In some embodiments, distance B comprises a measurement between layer 106 and conductor 116 along a direction parallel to the conductor axis. In some embodiments, distance C comprises a dimension between the outermost edge of conductor 112 and the outermost edge of conductor 116 along a direction perpendicular to the conductor axis, the outermost edges being arranged for illustration purposes only. Figure 2 In some embodiments, distance D includes a dimension between the outermost edge of conductor 112 and the outermost edge of conductor 116 in a direction perpendicular to the conductor axis, the outermost edges being arranged at left for illustration purposes only. Figure 2 In some embodiments, distance E includes a dimension along a direction perpendicular to the conductor axis between the outermost edge of insulator layer 108 and the outermost edge of conductor 112, which is arranged at right angles to the conductor axis for illustration purposes only. Figure 2In some embodiments, distance F includes a dimension between the outermost edge of insulator layer 108 and the outermost edge of conductor 112 in a direction perpendicular to the conductor axis, the outermost edge being arranged at 104 for illustration purposes only. Figure 2 In some embodiments, distance G includes a dimension along a direction perpendicular to the conductor axis between the outermost edge of insulator layer 108 and the outermost edge of conductor 116, which is arranged at right angles for illustration purposes only. Figure 2 In some embodiments, distance H includes a dimension along a direction perpendicular to the conductor axis between the outermost edge of insulator layer 108 and the outermost edge of conductor 116, which is disposed at left for illustration purposes only. Figure 2 Right side.

[0042] In various embodiments, distance A can be approximately equal to distance B, such that conductive layer 114 and conductor 116 are disposed approximately halfway between conductor 110 and conductor 112 along the conductor axis. Distance C can be approximately equal to distance D. Distance E can be approximately equal to distance F. Distance G can be approximately equal to distance H. In some embodiments, distance C can be approximately twice distance A. In some embodiments, distance E can be approximately twice distance G. In some embodiments, distance C can be approximately equal to distance G. In some embodiments, distance A can be approximately 20 microns. In some embodiments, distance C can be approximately 10 microns.

[0043] Figure 3 1 shows a top view of a conductor 316, which is a component of a micro passive device such as micro passive device 100. Conductor 316 may include a planar conductor. In some embodiments, Figure 1 The illustrated conductive layer 114 may include conductors 316 .

[0044] When the micro passive device 100 includes a transformer, when the conductors 110 and 112 of the micro passive device 100 include a first coil and a second coil, the conductor 316 may be included in the micro passive device 100 .

[0045] As in Figure 3 In the exemplary embodiment shown in FIG. 3 , conductor 316 may include a substantially circular shape having a substantially circular perimeter in a plane perpendicular to the conductor axis. However, aspects of the present disclosure are not limited by the shape of conductor 316. For example, conductor 316 may alternatively have any shape and perimeter that substantially corresponds to one or more of the first coil or the second coil of the micro passive device that includes conductor 316.

[0046] The inventors have recognized that for miniature passive devices including transformers, it may be beneficial to allow the magnetic field to substantially pass through the conductor. In some embodiments, the conductor, such as Figure 4 The conductor 316 in the embodiment may be configured to reduce or substantially eliminate the amount of magnetic field that is blocked by the conductor so that the magnetic field passes substantially completely through the conductor.

[0047] The conductor 316 may include a slotted conductor. For example, the conductor 316 may include at least one slot 302. The at least one slot 302 is configured to reduce eddy currents in the conductor 316. The at least one slot 302 may form at least one high aspect ratio segment 304 in the conductor 316. The at least one high aspect ratio segment 304 is configured to reduce eddy currents in the conductor 316. The plurality of high aspect ratio segments may be patterned to form an overall circular or other shape of the conductor 316.

[0048] Eddy currents may be generated in the electrical components of the transformer. Eddy currents are closed loops of electrical current that may be induced in a conductor 316 or another electronic component that is perpendicular to a changing magnetic field passing through the electronic component. The physical space that the changing magnetic field passes through, such as a two-dimensional area in a plane perpendicular to the magnetic field, may determine the size of the eddy current loop. The magnitude of the current is proportional to the size of the loop. Larger currents correspond to larger energy losses from the magnetic field, thereby reducing the efficiency of the transformer. Therefore, reducing the size of the loop, such as by using slots 302 and high aspect ratio segments 304, will allow more of the magnetic field to pass through the conductor 316 and will reduce or substantially eliminate the effects of eddy currents that reduce efficiency.

[0049] Figure 4 4 shows a top view of a conductor 416, which is a component of a micro passive device such as micro passive device 100. Conductor 416 may include a planar conductor. In some embodiments, Figure 1 The illustrated conductive layer 114 may include conductors 416 .

[0050] When the micro passive device 100 includes a capacitor, when the conductor 110 and the conductor 112 of the micro passive device 100 include a first plate and a second plate, the conductor 416 may be included in the micro passive device 100 .

[0051] As in Figure 4 As shown in the exemplary embodiment of , conductor 416 can include a substantially circular shape having a substantially circular perimeter in a plane perpendicular to the conductor axis described above. However, aspects of the present disclosure are not limited by the shape of conductor 416. For example, conductor 416 can alternatively have any shape and perimeter that substantially corresponds to one or more of the first plate or the second plate of the micro passive device including conductor 416.

[0052] Conductor 416 may include a continuous conductor. For example, in some embodiments, conductor 416 may not include at least one slot and may not include at least one high aspect ratio segment. In some embodiments, conductor 416 does not include at least one slot and does not include at least one high aspect ratio segment because conductor 416 is not configured to experience a significantly changing magnetic field and is therefore not configured to generate significant eddy currents.

[0053] Figure 5 A cross-sectional side view of micro passive device 500 is shown. Micro passive device 500 includes an alternative arrangement of conductive layer 114. Micro passive device 500 is arranged on substrate 102 having upper surface 104 and includes layer 106, insulator layer 108, conductor 110, conductor 112, conductive layer 114, conductive layer 114 shown includes conductor 516a, conductor 516b, and conductor 516c. Although in Figure 5 Not shown, but micro passive device 500 may include a voltage source, such as voltage source 118 .

[0054] In some embodiments, conductive layer 114 may include a plurality of conductors. Figure 5 , conductive layer 114 includes conductor 516a, conductor 516b, and conductor 516c. Each of conductor 516a, conductor 516b, and conductor 516c may include a planar conductor. In some embodiments, each of conductor 516a, conductor 516b, and conductor 516c includes a portion of a floating conductive layer, and may include a floating conductor in insulator layer 108, for example. A plurality of conductors may be configured, for example, Figure 5 The conductor 516a, the conductor 516b and the conductor 516c in the micro passive device 100 are used to reduce the maximum electric field of the micro passive device 100. The micro passive device 500 having a conductive layer includes a plurality of conductors, such as Figure 5 The conductors 516a, 516b and 516c in the micro passive device can provide a further reduction in the maximum electric field compared to a micro passive device having a conductive layer containing only a single conductor. In some embodiments, the micro passive device 500 can have a greater insulator height than the micro passive device 100.

[0055] Conductor 516a, conductor 516b, and conductor 516c are spaced apart along the conductor axis such that each of conductor 516a, conductor 516b, and conductor 516c is arranged in a different plane perpendicular to the conductor axis. In some embodiments, a portion of insulator layer 108 is disposed between each adjacent conductor. In some embodiments, an insulator layer is formed between each adjacent conductor.

[0056] In various embodiments, each of conductors 516a, 516b, and 516c may extend a distance in a direction perpendicular to the conductor axis that is greater than a distance in a direction perpendicular to the conductor axis (where one or more of conductors 110 or 112 extend).

[0057] In various embodiments, each subsequently centrally located conductor may extend a distance along a direction perpendicular to the conductor axis that is greater than the distance along a direction perpendicular to the conductor axis that each subsequently centrally located slightly smaller conductor extends. Figure 5 In the embodiment, the distance along the direction perpendicular to the conductor axis that the conductor 516b located more centrally extends is greater than the distance along the direction perpendicular to the conductor axis that each of the conductors 516a and 516c extends.

[0058] although Figure 5 A conductive layer including three conductors is shown, but this arrangement of conductors, including the arrangement of conductor extension distances, can be applied to any number of conductors, such as two, four, five, six, or more than six conductors. In embodiments including an even number of conductors, the two innermost conductors can extend approximately the same distance.

[0059] Figure 6 A cross-sectional side view of a micro passive device 600 is shown. The micro passive device 600 includes an alternative arrangement of a conductive layer 114. The micro passive device 600 is arranged on a substrate 102 having an upper surface 104 and includes a layer 106, an insulator layer 108, a conductor 110, a conductor 112, and a conductive layer 114, wherein the conductive layer 114 is shown to include a plurality of conductors 616. Although in Figure 6 Although not shown, the micro passive device 600 may include a voltage source such as the voltage source 118. A plurality of conductive particles, e.g. Figure 6 The conductive particles 616 in the micro passive device 100 can be configured to reduce the maximum electric field of the micro passive device 100.

[0060] In some embodiments, the conductive layer 114 may include a plurality of conductive particles. Figure 6, conductive layer 114 includes a plurality of conductive particles 616, of which only four are labeled for illustrative purposes. In some embodiments, each conductive particle 616 comprises a portion of a floating conductive layer, and may, for example, comprise a floating conductor in insulator layer 108. In some embodiments, conductive particles 616 may be distributed throughout insulator layer 108. In some embodiments, conductive particles 616 may be substantially uniformly distributed within insulator layer 108. In some embodiments, conductive particles 616 may be substantially distributed from a lower surface to an upper surface of insulator layer 108. In some embodiments, some of conductive particles 616 may be distributed in insulator layer 108 in the same plane as conductor 112, such that the conductive particles are arranged adjacent to conductor 112 along a direction perpendicular to the conductor axis.

[0061] In various embodiments, the conductive particles may have a thickness along the conductor axis, a width along a direction perpendicular to the conductor axis, or a maximum lateral width in any direction greater than about 0.4 microns, greater than about 2 microns, less than about 6 microns, less than about 8 microns, about 0.4 microns to about 8 microns, about 2 microns to about 6 microns, or about 4 microns.

[0062] Figure 7 1 shows a cross-sectional side view of micro passive device 100, which shows points 702a and 702b on conductor 110, points 702c and 702d on conductor 116, and points 702e and 702f on conductor 112. In some embodiments, one or more of point 702e or point 702f may be the point with the maximum electric field of micro passive device 100. For illustrative purposes, Figure 7 The voltage source 118 is not shown.

[0063] In some embodiments, when conductor 116 comprises a thin conductor, such as a conductor having a thickness of about 0.4 microns, one or more of point 702c or point 702d may be the point of the micro passive device 100 having the maximum electric field. Figure 7 In the embodiment of the present invention, point 702c and point 702d are arranged at the outer edge of the lower surface of conductor 116. However, in some embodiments, alternatively or additionally, when conductor 116 includes a thin conductor, one or more points arranged at the outer edge of the top surface of conductor 116 may be points having the maximum electric field of micro passive device 100.

[0064] In some embodiments, when conductor 116 includes a thin conductor, such as a conductor having a thickness of about 0.4 microns, one or more of point 702a or point 702b can have an increased electric field compared to an arrangement when conductor 116 does not include a thin conductor. In some embodiments, one or more of point 702e or point 702f has a high electric field. For example, in some embodiments, points 702e and 702f can age at an accelerated rate during high voltage withstand (HVE), such as when conductive layer 114 is more tightly coupled to conductor 110 than to conductor 112, as discussed in more detail below.

[0065] Figure 8 A cross-sectional side view of micro passive device 100 is shown, showing capacitor 802a, capacitor 802b, capacitor 802c, and capacitor 802d. For illustration purposes, Figure 8 The voltage source 118 is not shown.

[0066] Capacitance 802a may represent capacitance between conductor 116 and substrate 102. Capacitance 802b may represent capacitance between conductor 116 and conductor 110. Capacitance 802c may represent capacitance between conductor 116 and substrate 102. Capacitance 802d may represent capacitance between conductor 116 and conductor 112. In some embodiments, capacitance 802b may be substantially balanced by capacitance 802d.

[0067] In some embodiments, the first capacitance may include the capacitance between conductor 116 and the combination of substrate 102 and conductor 110. In some embodiments, the first capacitance may include a lower capacitance or a bottom capacitance. In some embodiments, the first capacitance may include the total capacitance of capacitor 802a, capacitor 802b, and capacitor 802c.

[0068] In some embodiments, the second capacitance may include capacitance between conductor 116 and conductor 112. In some embodiments, the second capacitance may include an upper capacitance or a top capacitance. In some embodiments, the second capacitance may include capacitance 802d.

[0069] In some embodiments, the first capacitance can be greater than the second capacitance. In some embodiments, a larger first capacitance can cause conductor 116 to have a voltage potential that is closer to the voltage potential of conductor 110 than the voltage potential of conductor 112. Conductor 116 having a voltage that is closer to the voltage potential of conductor 110 than the voltage potential of conductor 110 may cause the average electric field between conductor 116 and conductor 112 to be higher than the average electric field if the first capacitance is approximately balanced with the second capacitance. If the second capacitance is approximately balanced with the first capacitance, conductor 116 having a voltage potential that is closer to the potential of conductor 110 than the potential of conductor 110 may cause one or more of point 702e or point 702f to have a higher electric field, such as a higher maximum electric field.

[0070] In some embodiments, conductor 116 is forced to have a voltage potential that is intermediate between the voltage potential of conductor 110 and the voltage potential of conductor 112. In such embodiments, increases in average and maximum electric fields due to capacitive imbalance may be reduced or substantially eliminated.

[0071] The inventors have recognized that at high voltages, such as at voltages just below the breakdown voltage, conductor 116 may reach a potential close to halfway between the potential of conductor 110 and the potential of conductor 112 due to leakage occurring at voltages just below the breakdown voltage. In some embodiments, leakage occurs before breakdown and may shift the potential of conductor 116 away from the potential of substrate 102 or conductor 110 and closer to the potential of conductor 112. In some embodiments, the shift in the potential of conductor 116 due to leakage may reduce the electric field of conductor 112 and, in some embodiments, offset the larger first capacitance, thereby reducing the electric field at one or more of point 702e or point 702f.

[0072] Fig. 9 9 shows a cross-sectional side view of a micro passive device 900. Micro passive device 900 is disposed on substrate 102 having upper surface 104 and includes layer 106, insulator layer 108, conductor 910, conductor 912, and conductive layer 114, conductive layer 114 shown to include conductor 916. Fig. 9 Not shown, but micro passive device 900 may include a voltage source, such as voltage source 118 .

[0073] In some embodiments, micro passive device 900 may include micro passive device 100. Conductor 910 may include conductor 110. Fig. 9 In the illustrative embodiment of , conductor 910 comprises a planar coil. Conductor 912 may comprise conductor 112. Fig. 9 In the illustrative embodiment of FIG. , conductor 912 comprises a planar coil. Although Fig. 91 and 2, the conductive layer 114 is illustrated as conductor 916, but other arrangements are possible. For example, Fig. 9 The conductive layer 114 may include a plurality of conductors or a plurality of conductive particles.

[0074] In some embodiments, conductor 910 may include a coil hole. Distance X may include the coil hole diameter of conductor 910. In some embodiments, distance Y may include the radius of conductor 116. In some embodiments, conductor 912 may not include a coil hole. In some embodiments, distance Z may include the coil outer radius of conductor 912.

[0075] Fig. 9 Capacitor 902a, capacitor 902b, capacitor 902c, capacitor 902d, capacitor 902e, capacitor 902f, capacitor 902g, capacitor 902h, capacitor 902i, capacitor 902j, and capacitor 902k are shown. Fig. 9 Shown are distance X, distance Y, and distance Z. In some embodiments, the difference between distance Y and distance Z may be approximately 40 microns.

[0076] Capacitance 902a may represent capacitance between conductor 916 and substrate 102. Capacitance 902b may represent capacitance between the surface of layer 106 that contacts insulator layer 108 and the exterior of conductor 910. Capacitance 902c may represent capacitance between conductor 916 and the surface of layer 106. Capacitance 902d may represent capacitance between the surface of layer 106 and substrate 102. Capacitance 902e may represent capacitance between conductor 916 and the surface of layer 106. Capacitance 902f may represent capacitance between the surface of layer 106 and the exterior of conductor 910. Capacitance 902g may represent capacitance between conductor 916 and the surface of layer 106. Capacitance 902h may represent capacitance between conductor 916 and substrate 102.

[0077] Capacitance 902i may represent the capacitance between conductor 916 and the exterior of conductor 912. Capacitance 902j may represent the capacitance between conductor 916 and the interior of conductor 912. Capacitance 902k may represent the capacitance between conductor 916 and the exterior of conductor 912.

[0078] In some embodiments, capacitor 902c can be approximately balanced with capacitor 902i. In some embodiments, capacitor 902e can be approximately balanced with capacitor 902j. In some embodiments, capacitor 902g can be approximately balanced with capacitor 902k.

[0079] The total capacitance of capacitors 902a, 902b, 902c, 902d, 902e, 902f, 902g and 902h can provide a first capacitance for micro passive device 900. The total capacitance of capacitors 902i, 902j and 902k can provide a second capacitance for micro passive device 900.

[0080] In some embodiments, capacitor 902a can increase the first capacitance. In some embodiments, capacitor 902h can increase the first capacitance. In some embodiments, capacitor 902b can reduce the first capacitance. In some embodiments, capacitor 902d can reduce the first capacitance. In some embodiments, capacitor 902f can reduce the first capacitance. These increases and decreases may cause an imbalance between the first capacitance and the second capacitance. For example, the first capacitance may be greater than the second capacitance.

[0081] The inventors have recognized various conditions that affect the balance of the first capacitance and the second capacitance. The inventors have recognized that the presence of substrate 102 can increase the first capacitance. The inventors have recognized that the difference between distance Y, the radius of conductor 916, and distance Z, the radius of conductor 912 can increase the first capacitance. The inventors have recognized that the presence of coil holes in conductor 910 and the absence of coil holes in conductor 912 can reduce the first capacitance. The inventors have recognized that the thickness of layer 106 can reduce the first capacitance.

[0082] The inventors have recognized that, under at least some operating conditions, balanced capacitance can provide a more robust micro passive device. The inventors have recognized that increasing the distance X, i.e., the diameter of the coil hole, can reduce the first capacitance. The inventors have recognized that increasing the thickness of layer 106, which can, for example, reach a thickness of about 50 microns, can reduce the first capacitance or substantially balance the first capacitance with the second capacitance. The inventors have recognized that reducing the difference between the distance Y (the radius of conductor 916) and the distance Z (the radius of conductor 912) to, for example, about 10 microns can reduce the first capacitance or substantially balance the first capacitance with the second capacitance.

[0083] The inventors have realized that Figure 2The distances A and B can be formed to have a height that makes the first capacitance roughly balanced with the first capacitance. For example, the distance A can be configured to be smaller than the distance B. In some embodiments, the total thickness of the insulator layer 108 can be about 40 microns. In such an embodiment, in order to balance the first capacitance with the first capacitance, the distance A can be configured to be between about 1 micron and about 2 microns smaller than the distance B. In various embodiments, the distance A can be configured to be about 2.5% to about 12.5%, or about 5% to about 10%, or about 5% to about 10%, or about 6.25% to about 8.75% or about 7.5% smaller than the distance B. Providing an insulator layer 108 with these conditions can make the first capacitance substantially balanced with the second capacitance.

[0084] Compared to back-to-back designed micro passive devices, micro passive devices according to aspects of the present disclosure, such as micro passive devices including stacks of double insulator heights and conductive layers in the insulator layers, can have various advantages. Back-to-back designed micro passive devices can include two series-connected, adjacent stacks of single insulator heights without conductive layers in the insulator layers.

[0085] In some embodiments, the micro passive device of the present disclosure may have a higher coupling factor than a micro passive device designed back to back. For example, where the coupling factor of a stack of a single insulator height is K, the micro passive device of the present disclosure may have a coupling factor of approximately K / 1.3, while the coupling factor of a micro passive device designed back to back may be a function of K^2 of approximately K / 2. In some embodiments, the micro passive device of the present disclosure may have a coupling factor of approximately 54% higher than a micro passive device designed back to back.

[0086] In some embodiments, the micro passive devices of the present disclosure can occupy less area on the surface of the substrate than micro passive devices of back-to-back design. For example, the micro passive devices of the present disclosure can occupy about 40% less area on the surface of the substrate than micro passive devices of back-to-back design.

[0087] In some embodiments, the micro passive devices of the present disclosure can exhibit less IR loss than micro passive devices of back-to-back design. For example, the micro passive devices of the present disclosure can exhibit about 40% less IR loss than micro passive devices of back-to-back design. In some embodiments, the micro passive devices of the present disclosure can exhibit less IR loss than micro passive devices of back-to-back design because fewer transmit and receive conductors are required, and therefore the required conductor size is smaller.

[0088] In some embodiments, the micro passive device of the present disclosure may not require an isolation substrate that may be required for a back-to-back designed micro passive device because the conductors of the isolation substrate are maintained at a higher voltage potential. Therefore, in some embodiments, the micro passive device of the present disclosure may have a smaller, less complex, or less costly substrate than a back-to-back designed micro passive device.

[0089] A method for manufacturing a micro passive device may include the following steps: forming Figure 1 , 2 , each layer described in any one of 5, 6, 7, 8 and 9, and patterning each conductor and conductive layer, including Figure 3 and 4 For example, a substrate may be provided. A layer including a conductor may be formed on the substrate. The conductor may be patterned in the layer in the above arrangement. At least one insulator layer including at least one conductive layer may be formed on the layer. In the above arrangement, at least one conductive layer may be patterned in at least one insulator layer. In the above arrangement, the conductor may be patterned in or on the insulator layer.

[0090] A method of operating a micro passive device may include the steps of applying a set of signals to a terminal of a first conductor and a terminal of a second conductor of the micro passive device to provide an electric field between the first conductor and the second conductor. The method may include reducing a maximum electric field between the first conductor and the second conductor. The method may include using at least one floating conductive layer in an insulator layer to reduce the maximum electric field between the first conductor and the second conductor.

[0091] Although the floating conductive layer in this application may generally be described with respect to micro passive devices such as transformers and capacitors, aspects of the present application may be applied to other electronic devices. For example, in some embodiments, the floating conductive layer described in this application may be applied to other transformers, capacitors, other micro devices, or other electronic devices that exhibit undesirable electric fields or maximum electric fields.

[0092] Moreover, as described, some aspects may be embodied as one or more methods. The actions performed as part of the method may be ordered in any suitable manner. Thus, embodiments may be constructed in which actions are performed in an order different from that shown, and even if shown as sequential actions in an illustrative embodiment, the actions may include performing some actions simultaneously.

[0093] The terms "approximately," "substantially," and "roughly" may be used in some embodiments to indicate within ±20% of a target value, in some embodiments to indicate within ±10% of a target value, in some embodiments to indicate within ±5% of a target value, and in some embodiments to indicate within ±2% of a target value. The terms "approximately" and "roughly" may include the target value.

Claims

1. An isolated micro passive device, configured to be disposed on a substrate including an upper surface, the isolated micro passive device comprising: a first planar conductor; a second planar conductor configured to be disposed between the first planar conductor and the substrate; an insulator layer disposed between the first planar conductor and the second planar conductor; and a floating conductive layer in said insulator layer, in: The first planar conductor has a first spacing relative to the floating conductive layer; The second planar conductor has a second spacing relative to the floating conductive layer; The first pitch is smaller than the second pitch, such that the first pitch and the second pitch are configured to substantially balance a first capacitance of the isolated micro passive device and a second capacitance of the isolated micro passive device; The first capacitor comprises: capacitance between the floating conductive layer and the second planar conductor; and Capacitance between the floating conductive layer and the substrate; and The second capacitance includes capacitance between the floating conductive layer and the first planar conductor.

2. The isolated micro passive device of claim 1, wherein: The second planar conductor extends a first distance along an axis parallel to the upper surface of the substrate; The floating conductive layer includes at least one conductor extending a second distance along the axis; and The second distance is greater than the first distance.

3. The isolated micro passive device of claim 1, wherein the floating conductive layer is embedded within the insulator layer.

4. The isolated micro passive device of claim 1, wherein the floating conductive layer comprises a third planar conductor.

5. The isolated micro passive device of claim 4, wherein: The third planar conductor includes a first planar surface and a second planar surface; and Each of the first planar surface and the second planar surface is completely covered by the insulator layer.

6. The isolated micro passive device of claim 1, wherein: A first portion of the insulator layer is disposed between the floating conductive layer and the first planar conductor; and A second portion of the insulator layer is disposed between the floating conductive layer and the second planar conductor.

7. The isolated micro passive device of claim 1, wherein the floating conductive layer comprises a plurality of third planar conductors.

8. An isolated micro passive device, configured to be disposed on a substrate including an upper surface, the isolated micro passive device comprising: a first planar conductor; a second planar conductor configured to be disposed between the first planar conductor and the substrate; a first insulator layer disposed between the first planar conductor and the second planar conductor; a second insulator layer disposed between the first planar conductor and the second planar conductor; and a floating conductive layer disposed between the first insulator layer and the second insulator layer, in: The first planar conductor has a first spacing relative to the floating conductive layer; The second planar conductor has a second spacing relative to the floating conductive layer; The first pitch is smaller than the second pitch, such that the first pitch and the second pitch are configured to substantially balance a first capacitance of the isolated micro passive device and a second capacitance of the isolated micro passive device; The first capacitor comprises: capacitance between the floating conductive layer and the second planar conductor; and Capacitance between the floating conductive layer and the substrate; and The second capacitance includes capacitance between the floating conductive layer and the first planar conductor.

9. The isolated micro passive device of claim 8, wherein the first planar conductor is spaced apart from the second planar conductor along an axis perpendicular to the upper surface of the substrate.

10. The isolated micro passive device of claim 9, wherein: The first planar conductor is disposed in a first plane parallel to an upper surface of the substrate; and The second planar conductor is disposed in a second plane parallel to the upper surface of the substrate.

11. The isolated micro passive device of claim 9, wherein: The floating conductive layer includes a plurality of third planar conductors; and The plurality of third planar conductors are spaced apart along the axis.

12. The isolated micro passive device of claim 9, wherein the floating conductive layer is disposed halfway along the axis between the first planar conductor and the second planar conductor.

13. The isolated micro passive device of claim 9, wherein along the axis, a distance between the floating conductive layer and the first planar conductor is 2.5% to 12.5% ​​smaller than a distance between the floating conductive layer and the second planar conductor.

14. An isolated micro passive device configured to be disposed on a substrate including an upper surface, the isolated micro passive device comprising: a first planar conductor; a second planar conductor configured to be disposed between the first planar conductor and the substrate; means for reducing a maximum electric field between the first planar conductor and the second planar conductor; as well as means for substantially balancing a first capacitance of the isolated micro passive device with a second capacitance of the isolated micro passive device, wherein: The first capacitor comprises: a capacitance between the floating conductive layer and the second planar conductor; and a capacitance between the floating conductive layer and the substrate; and The second capacitance includes capacitance between a floating conductive layer and the first planar conductor.

15. The isolated micro passive device of claim 14, wherein the isolated micro passive device comprises a transformer; The first planar conductor comprises a first planar coil of the transformer; and The second planar conductor comprises a second planar coil of the transformer.

16. The isolated micro passive device of claim 15, wherein: The means for reducing a maximum electric field between the first planar conductor and the second planar conductor comprises a floating conductive layer in an insulator layer; and The floating conductive layer includes a slotted planar conductor.

17. The isolated micro passive device of claim 14, wherein the isolated micro passive device comprises a capacitor; The first planar conductor comprises a first plate of the capacitor; and The second planar conductor comprises a second plate of the capacitor.

18. The isolated micro passive device of claim 17, wherein: The means for reducing a maximum electric field between the first planar conductor and the second planar conductor comprises a floating conductive layer in an insulator layer; and The floating conductive layer includes a continuous planar conductor.

19. The isolated micro passive device of claim 14, wherein the means for reducing the maximum electric field between the first planar conductor and the second planar conductor comprises a floating conductive layer encapsulated by an insulator layer.

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