Semiconductor device and method of manufacturing

Abstract

The present disclosure relates to semiconductor devices and manufacturing methods. A semiconductor device and a manufacturing method thereof are presented, in which a spacer is manufactured on a sidewall of a gate of the semiconductor device. In embodiments, the spacer comprises a first seal, a second seal, and a contact etch stop layer, wherein the first seal comprises a first shell and a first bulk material, the second seal comprises a second shell and a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods of manufacture. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material onto a semiconductor substrate and patterning the individual layers of material using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to move toward smaller feature sizes of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. SUMMARY

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a first spacer layer comprising an inner layer disposed between two outer layers, wherein the inner layer and the two outer layers each comprise a first material, wherein a carbon content of the two outer layers is greater than a carbon content of the inner layer, and an oxygen content of the two outer layers is less than an oxygen content of the inner layer; and a second spacer layer comprising a first layer and a second layer, the first layer being the first material and in direct contact with one of the two outer layers.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a first seal adjacent to a gate stack, the first seal comprising: a first shell of a first material having a first composition; and a first bulk material of the first material having a second composition different from the first composition; a second seal in physical contact with the first seal, the second seal comprising: a second shell of the first material having a third composition; and a second bulk material of the first material having a fourth composition different from the third composition; and a contact etch stop layer in physical contact with the second seal, the contact etch stop layer comprising: a third bulk material of the first material having a fifth composition; and a third shell of a second material different from the first material.

[0006] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: patterning a dummy gate electrode over a semiconductor fin; sequentially introducing a first group of precursors into the dummy gate electrode using a first set of exposure times to form a first shell layer; sequentially introducing the first group of precursors into the dummy gate electrode using a second set of exposure times different from the first set of exposure times to form a first bulk dielectric material; sequentially introducing the first group of precursors into the dummy gate electrode using a third set of exposure times to form a second bulk dielectric material; sequentially introducing the first group of precursors into the dummy gate electrode using a fourth set of exposure times different from the first set of exposure times to form a second shell layer; sequentially introducing the first group of precursors into the dummy gate electrode using a fifth set of exposure times to form a third bulk dielectric material; and depositing a dielectric material after sequentially introducing the first group of precursors into the dummy gate electrode using the fifth set of exposure times. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a FinFET in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 11D 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 18A 、 Figure 18B 、 Figure 19A ,as well as Figure 19B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature relative to another element(s) or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0012] Embodiments will now be discussed with reference to specific embodiments described below, in which sealed spacers are utilized to assist in reducing damage while also maintaining an appropriate dielectric constant. However, the described embodiments are not intended to limit the specific embodiments of the concepts presented herein. Rather, these concepts can be utilized in a variety of embodiments, and all such embodiments are fully intended to be included within the scope of this specification.

[0013] Figure 1An example of a FinFET in a three-dimensional view according to some embodiments is shown. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are provided in the substrate 50, and the fins 52 are above and protrude from adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer to only the semiconductor substrate or the semiconductor substrate including the isolation regions. In addition, although the fin 52 is shown as a single continuous material like the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to the portion that extends between adjacent isolation regions 56.

[0014] Gate dielectric layer 92 is along the sidewalls of fin 52 and over the top surface of fin 52, and gate electrode 94 is over gate dielectric layer 92. Epitaxial source / drain regions 82 are disposed on opposite sides of fin 52 from gate dielectric layer 92 and gate electrode 94. Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA is along the longitudinal axis of gate electrode 94 and is oriented perpendicularly to the direction of current flow, for example, between the epitaxial source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and is along the longitudinal axis of fin 52 and is oriented perpendicularly to the direction of current flow, for example, between the epitaxial source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0015] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs), nanostructured (e.g., nanosheets, nanowires, gate-all-around, etc.) field-effect transistors (NSFETs), and the like.

[0016] Figures 2 to 19B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figures 2 to 7 Shown Figure 1 Reference cross section AA is shown, with the difference being multiple fins / FinFETs. Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A and Figure 19A Along Figure 1 The reference cross section AA shown is shown, and Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B and Figure 19B Along Figure 1 A similar cross section BB is shown, but with multiple fins / FinFETs. Figure 8C 、 Figure 8D 、 Figure 9C 、 Figure 9D 、 Figure 10C 、 Figure 10D 、 Figure 11C 、 Figure 11D 、 Figure 12C 、 Figure 12D 、 Figure 13C and Figure 13D Along Figure 1 The reference cross section CC shown shows that the difference lies in the multiple fins / FinFETs in different areas.

[0017] exist Figure 2 In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. For example, the insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0018] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type FinFET). The p-type region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type FinFET). The n-type region 50N can be physically separated from the p-type region 50P (as indicated by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P.

[0019] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. The etching process can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching process can be anisotropic.

[0020] The fins may be patterned by any suitable method. For example, the fins 52 may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-aligned process, allowing the creation of patterns having, for example, a smaller spacing than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, a mask (or other layer) may remain on the fins 52.

[0021] exist Figure 4, an insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it into another material (e.g., oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the embodiment shown, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filler material such as the filler material described above may be formed over the liner.

[0022] exist Figure 5 In the embodiment of the present invention, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes the fin 52 such that after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 are flush. In embodiments where a mask remains on the fin 52, the planarization process may expose the mask or remove the mask such that after the planarization process is completed, the top surfaces of the mask or the fin 52 and the insulating material 54, respectively, are flush.

[0023] exist Figure 6 Insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. Insulating material 54 is recessed so that the upper portions of fins 52 in n-type region 50N and p-type region 50P protrude from between adjacent STI regions 56. In addition, the top surface of STI region 56 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dished), or a combination thereof. The top surface of STI region 56 can be formed to be flat, convex, and / or concave by appropriate etching. STI region 56 can be recessed using an acceptable etching process, such as an etching process that is selective to the material of insulating material 54 (e.g., etches the material of insulating material 54 at a faster rate than the material of fin 52). For example, oxide removal using, for example, dilute hydrofluoric (dHF) acid can be used.

[0024] refer to Figures 2 to 6The process described is only one example of how the fin 52 may be formed. In some other embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for the fin 52. For example, Figure 5 The fin 52 in the substrate 50 may be recessed, and a material different from the fin 52 may be epitaxially grown over the recessed fin 52. In such an embodiment, the fin 52 includes the recessed material, and the epitaxially grown material disposed over the recessed material. In another embodiment, a dielectric layer may be formed over the top surface of the substrate 50, and trenches may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments in which a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid prior and subsequent implantations, but in situ doping and implantation doping may be used together.

[0025] Furthermore, in some embodiments where a heteroepitaxial structure is desired, a second semiconductor material 59 may be epitaxially grown as part of the fin 52 in the p-type region 50P, different from the material in the n-type region 50N. For example, the upper portion of the fin 52 in the p-type region 50P may be made of silicon germanium (SiGe). x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc. However, any suitable material and any suitable process may be used.

[0026] Further references Figure 6 Appropriate wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N, and an N-well may be formed in the p-type region 50P. In some embodiments, either a P-well or an N-well may be formed in both the n-type region 50N and the p-type region 50P.

[0027] In embodiments with different well types, photoresist and / or other masks (not shown) may be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist may be formed over the fin 52 and the STI region 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 With about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0028] After the implantation of the p-type region 50P, a photoresist is formed over the fin 52 and the STI region 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed by using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted into the region at a concentration equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0029] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0030] exist Figure 7, a dummy dielectric layer 60 is formed on the fin 52. For example, the dummy dielectric layer 60 can be silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to an acceptable technique. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive material or a non-conductive material, and can be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. Dummy gate layer 62 can be made of other materials with high etch selectivity relative to etching of isolation regions (e.g., STI regions 56 and / or dummy dielectric layer 60). For example, mask layer 64 can include one or more layers of silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across n-type region 50N and p-type region 50P. Note that dummy dielectric layer 60 is shown as covering only fin 52 for illustrative purposes only. In some embodiments, dummy dielectric layer 60 can be deposited such that dummy dielectric layer 60 covers STI region 56, extends above the STI region, and extends between dummy gate layer 62 and STI region 56.

[0031] Figures 8A to 19B Various additional steps for fabricating an embodiment device are shown, wherein for convenience only a single fin 52 in the n-type region 50N and a single fin 52 in the p-type region 50P are shown. Figure 8A and Figure 8B In the embodiment, the mask layer 64 can be patterned using acceptable photolithography and etching techniques (see Figure 7 ) to form a mask 74. The pattern of mask 74 can then be transferred to dummy gate layer 62 to form dummy gates 72. In some embodiments (not shown), the pattern of mask 74 can also be transferred to dummy dielectric layer 60. Dummy gates 72 cover corresponding channel regions 58 of fins 52. The pattern of mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. Dummy gates 72 can also have a length direction that is substantially perpendicular to the length direction of the corresponding epitaxial fin 52.

[0032] Figure 8C and Figure 8D The fin 52 is shown along line CC (see Figure 1 ), wherein Figure 8C shows a view within the n-type region 50N, and Figure 8D 50P. From this point in the manufacturing process, it can be seen that the top of the semiconductor material of the fin 52 in the p-type region 50P has been replaced by the second semiconductor material 59. In addition, even in the dummy gate 72 (see Figures 8A-8B ), a portion of mask 74 may still be located along the sidewalls of fin 52.

[0033] Figures 9A-9D 1 shows that once the dummy gate 72 has been patterned, a first sealant 73 (or first spacer) may be deposited over the dummy gate 72. In an embodiment, the first sealant 73 may be a dielectric material such as SiCON, which is fabricated to have not only a first shell 81 adjacent to the dummy gate 72 to help the first sealant 73 reduce etching losses, but also a first bulk dielectric material 83 adjacent to the first shell 81 to reduce the effective capacitance (C) of the device. eff ) in order to improve the overall performance of the device. However, any suitable number of layers in any configuration may be utilized.

[0034] In an embodiment, the first shell 81 of the first seal 73 is deposited using a deposition process such as atomic layer deposition, but any suitable deposition process may be utilized, such as chemical vapor deposition, physical vapor deposition, etc. In such an embodiment using atomic layer deposition, a plurality of precursors are sequentially introduced to the structure (with appropriate purges between the various precursors), and these precursors will each react in a self-limiting reaction, thereby cyclically forming various layers of the desired material (e.g., SiCON) in a monolayer-by-monolayer manner.

[0035] In a specific embodiment in which the first shell 81 is formed of SiCON using atomic layer deposition, the first precursor can be a silicon-containing precursor, such as hexachlorodisilane. In this embodiment, the hexachlorodisilane can be introduced into the structure, where it reacts with exposed sites on the surface of the structure in a self-limiting reaction. In such an embodiment, the hexachlorodisilane can be introduced into the structure at a flow rate between about 0.2 slm and about 1.0 slm over a period of about 20 seconds (+ / - 15 seconds). Furthermore, the temperature during the reaction can be maintained between about 500° C. and about 680° C. However, any suitable process parameters can be utilized.

[0036] The second precursor can be a carbon-containing precursor such as propane, and the second precursor can be introduced into the structure after the first precursor is introduced. Upon introduction, the second precursor (e.g., propane) will react with the product of the hexachlorodisilane reaction in another self-limiting reaction. In such an embodiment, the propane can be introduced at a flow rate between about 0.5 slm and about 5.0 slm over a period of about 90 seconds (+ / - 30 seconds). In addition, the temperature during the reaction can be maintained at a temperature between about 500° C. and about 680° C. However, any suitable process parameters can be utilized.

[0037] The third precursor can be an oxygen-containing precursor such as oxygen (O2), and the third precursor can be introduced into the structure after the second precursor is introduced. When introduced into the structure, the third precursor (e.g., oxygen) will react with the product of the previous reaction in another self-limiting reaction. In such an embodiment, oxygen can be introduced at a flow rate between about 1 slm and about 5 slm over a period of about 15 seconds (+ / - 10 seconds). In addition, the temperature during the reaction can be maintained at a temperature between about 500°C and about 680°C. However, any suitable process parameters can be utilized.

[0038] The fourth precursor can be a nitrogen-containing precursor such as ammonia, and the fourth precursor can be introduced into the structure after the third precursor is introduced. When introduced into the structure, the fourth precursor (e.g., ammonia) will react with the product of the previous reaction in another self-limiting reaction. In such an embodiment, ammonia can be introduced at a flow rate between about 0.5 slm and about 5.0 slm over a period of about 30 seconds (+ / - 15 seconds). In addition, the temperature during the reaction can be maintained at a temperature between about 500° C. and about 680° C. However, any suitable process parameters can be utilized.

[0039] Once the fourth precursor is introduced for the first time, the first cycle of the atomic layer deposition process is complete and a second cycle can be started to form a second monolayer of the desired material. The cycle can be repeated as many times as necessary to form the first shell 81 to a desired thickness, for example, between about 0.2 nm and about 1 nm. However, any suitable thickness can be used.

[0040] By forming the first shell 81 of the first seal 73 as described above, the first shell can be formed to be more resistant to damage from a subsequent etching process (described further below). For example, in the final product, the first shell 81 can be formed to have a thickness of about 2.5 g / cm 3 and about 2.7g / cm 3, and a dielectric constant between about 5.1 and about 5.5. Furthermore, utilizing the process conditions described above, the first shell 81 of the first seal 73 can be formed to be carbon-rich and nitrogen-rich, wherein the carbon concentration is between about 5% atomic and about 20% atomic (e.g., 12% atomic) and the nitrogen concentration is between about 24% atomic and about 45% atomic (e.g., 25% atomic). Furthermore, the first shell 81 can have an oxygen concentration between about 24% atomic and about 40% atomic (e.g., 32% atomic), and a silicon concentration between about 27% atomic and about 37% atomic (e.g., 32% atomic). However, any suitable characteristics can be utilized.

[0041] Once the first housing 81 of the first seal 73 is formed, a first bulk dielectric material 83 can be deposited in situ with the first housing 81. In embodiments, the first bulk dielectric material 83 can be a similar material as the first housing 81, e.g., by being the same material but having a different composition. For example, in embodiments where the first housing 81 of the first seal 73 is SiCON, the first bulk dielectric material 83 can also be SiCON, but with a different composition to help lower the dielectric constant of the first seal 73.

[0042] In an embodiment, the first bulk dielectric material 83 can be deposited using a similar process as the first shell 81, for example, atomic layer deposition using similar precursors, such as a first precursor (e.g., hexachlorodisilane), a second precursor (e.g., propane), a third precursor (e.g., oxygen), and a fourth precursor (e.g., ammonia). However, in order to have a different composition, the amount of time each precursor is allowed to contact the structure is modified so that the first set of exposure times is different from the new set of exposure times. Furthermore, in other embodiments, the order of the precursors can also be changed.

[0043] In one particular example, to form the first bulk dielectric material 83, the first precursor can be introduced at a flow rate between about 0.2 slm and about 1.0 slm over a period of about 20 seconds (+ / - 8 seconds), while the second precursor can be introduced at a flow rate between about 0.5 slm and about 5.0 slm over a period of about 90 seconds (+ / - 30 seconds). Furthermore, before introducing the third precursor (e.g., oxygen), the fourth precursor (e.g., nitrogen) can be introduced at a flow rate between about 0.5 slm and about 5.0 slm over a period of about 9 seconds (+ / - 5 seconds). Finally, after the fourth precursor (e.g., nitrogen), the third precursor (e.g., oxygen) can be introduced at a flow rate between about 0.5 slm and about 5.0 slm over a period of about 18 seconds (+ / - 10 seconds). However, any suitable flow rates and times can be utilized.

[0044] Once the fourth precursor is introduced for the first time, the first cycle of the atomic layer deposition process is complete and a second cycle can be started to form a second monolayer of the desired material. The cycle can be repeated as many times as necessary to form the first bulk dielectric material 83 to a desired thickness, for example, between about 3 nm and about 5 nm. However, any suitable thickness can be utilized.

[0045] By utilizing these parameters, the first bulk dielectric material 83 can be formed to have properties that are more suitable for reducing the dielectric constant while not being as resistant to etching processes as the first shell 81. For example, in the final product, the first bulk dielectric material 83 can be formed to have a dielectric constant of less than about 5.0. In addition, the first bulk dielectric material 83 can be formed to have a dielectric constant of about 2.0 g / cm 3 and about 2.4g / cm 3 % atomic density, and can be an oxygen-rich film with an oxygen concentration between about 40% atomic and about 65% atomic (e.g., 53% atomic, which is greater than the oxygen content of the first shell 81). Finally, the first bulk dielectric material 83 can have a carbon concentration of less than 2% atomic (e.g., 1% atomic, which is less than the carbon content of the first shell 81), a nitrogen concentration between about 5% atomic and about 14% atomic (e.g., 12% atomic), and a silicon concentration between about 24% atomic and about 40% atomic (e.g., 32% atomic). However, any suitable characteristics can be utilized.

[0046] By depositing the first shell 81 and the first bulk dielectric material 83, the first seal 73 can be deposited with materials that allow the first seal 73 to have both an etch-resistant portion (e.g., the first shell 81) and a dielectric-reducing portion (e.g., the first bulk dielectric material 83). Furthermore, the first seal 73 can have a gradient region where the two layers partially diffuse into each other by between about 0.5 nm and about 1 nm. This arrangement allows the entire first seal 73 to have the desired resistance to etch damage without completely sacrificing a lower dielectric constant, resulting in fewer defects during the manufacturing process.

[0047] After forming the first seal 73, an implant for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. In embodiments with different device types, similar to the above Figure 6As discussed above, a mask (e.g., photoresist) may be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) may be implanted into the exposed fins 52 in the p-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) may be implanted into the exposed fins 52 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source / drain regions may have a density ranging from about 10 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0048] After the LDD region has been formed, a second sealant 75 is formed over the first sealant 73. In an embodiment, the second sealant 75 may be formed of similar materials and using similar processes as the first sealant 73. For example, the second sealant 75 may be formed of SiCON and may further include a second bulk dielectric material 85 and a second outer shell 87. However, any suitable material may be utilized.

[0049] In an embodiment, the second bulk dielectric material 85 can be deposited in situ as described above with reference to the first bulk dielectric material 83 to obtain similar physical properties. However, the second bulk dielectric material 85 is deposited before depositing the second shell 87 so that the second bulk dielectric material 85 is in physical contact with the first bulk dielectric material 83.

[0050] For example, in some embodiments, the second bulk dielectric material 85 can be formed to a thickness between about 3 nm and about 5 nm in the final product. Additionally, the second bulk dielectric material 85 can be formed to a thickness of about 2.0 g / cm 3 and about 2.4g / cm 3 , and can be an oxygen-rich film with an oxygen concentration between about 40% and about 65%. Finally, the second bulk dielectric material 85 can have a carbon concentration of less than 2%, and a nitrogen concentration between about 5% and about 12%. However, any suitable composition can be utilized.

[0051] Once the second bulk dielectric material 85 has been formed in physical contact with the first bulk dielectric material 83, a second shell 87 can be deposited to protect the second bulk dielectric material 85 from damage during subsequent etching processes. In an embodiment, the second bulk dielectric material 85 can be deposited as described above with reference to the deposition of the first shell 81.

[0052] For example, in embodiments, the second sheath 87 can be formed to resist etch damage. In one particular embodiment, in the final product, the second sheath 87 can be formed to a thickness of between about 0.2 nm and about 1 nm, and can be formed to have a density of between about 2.5 g / cm3and about 2.7 g / cm3. 3 3 Further, with the process conditions as described above, the second sheath 87 can be formed to be carbon rich and nitrogen rich, with a carbon concentration of between about 5% atomic and about 20% atomic (e.g., 12% atomic), and a nitrogen concentration of between about 24% atomic and about 45% atomic (e.g., 25% atomic). Further, the gradient region between the second sheath 87 and the second bulk dielectric material 85, the second seal 75 can have a gradient region where the two layers partially diffuse into each other between about 0.5 nm and about 1 nm. However, any suitable concentration can be utilized.

[0053] By depositing the second sheath 87 and the second bulk dielectric material 85, the second seal 75 can be deposited with materials that allow the second seal 75 to have both an etch resistant portion (e.g., the second sheath 87) and a dielectric reducing portion (e.g., the second bulk dielectric material 85). Such a profile of properties allows for an increased overall ability to resist subsequent etching, while also maintaining a lower dielectric constant.

[0054] Further, although the above describes a particular embodiment in which the first seal 73 is formed, the LDD region is formed, and then the second seal 75 is formed after the LDD region is formed, this is intended to be exemplary, and is not intended to be limiting. For example, in other embodiments, the first seal 73 and the second seal 75 are formed in situ and back to back, and the LDD region is formed only after the second seal 75 is formed. Any appropriate combination of steps can be utilized, and all such embodiments are fully intended to be included within the scope of the embodiments.

[0055] Figures 9A-9D It is also shown that once the second seal 75 has been deposited, a mask layer 77 is deposited over the structure. In embodiments, the mask layer 77 can be a dielectric layer, such as silicon nitride, aluminum oxide, deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, a combination of these, and the like. However, any suitable material and method of fabrication can be utilized.

[0056] In Figures 10A-10D ​In the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fin 52 of the p-type FinFET. The epitaxial source / drain regions 82 are formed in the fin 52 such that each dummy gate 72 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fin 52 and may also pass through the fin 52. In some embodiments, a first seal 73 and a second seal 75 are used to separate the epitaxial source / drain regions 82 from the dummy gate 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit a subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain regions 82 may be selected to impose strain in the corresponding channel region 58 to improve performance.

[0057] The epitaxial source / drain regions 82 in the p-type region 50P can be formed by masking the dummy gate 72 and the n-type region 50N within the p-type region 50P and etching to expose the underlying fin 52 (e.g., the second semiconductor material 59). The epitaxial source / drain regions 82 in the p-type region 50P are then epitaxially grown on the fin 52. The epitaxial source / drain regions 82 can include any acceptable material, such as a material suitable for a p-type FinFET. For example, if the fin 52 is silicon germanium, the epitaxial source / drain regions 82 in the p-type region 50P can include a material that applies strain in the channel region 58, such as silicon, boron-doped silicon germanium, silicon germanium, germanium tin, etc. The epitaxial source / drain regions 82 in the p-type region 50P can have surfaces that are raised from the corresponding surfaces of the fin 52 and can have facets.

[0058] Once the epitaxial source / drain regions 82 are formed, any remaining portions of the mask layer 77 may be removed (e.g., using an etchant such as H3PO4). In an embodiment, the remaining portions of the mask layer 77 may be removed using, for example, one or more etching processes (e.g., a wet etching process). However, any suitable method may be used. In some embodiments, multiple etching processes (e.g., an etch to remove the fins 52 and / or an etch to remove the mask layer 77) may further remove portions of the first seal 73 and the second seal 75 to a position below the mask 74.

[0059] Figures 11A-11D It is shown that once epitaxial source / drain regions 82 have been formed in p-type region 50P, a second mask layer 79 is formed to begin forming epitaxial source / drain regions 84 in n-type region 50N. In an embodiment, second mask layer 79 can be formed using similar processes and similar materials as mask layer 77. However, any suitable methods and materials may be utilized.

[0060] 12A to 12DIt is shown that once the second mask layer 79 is formed, the fin 52 in the n-type region 50N is exposed, and epitaxial source / drain regions 84 in the n-type region 50N are epitaxially grown on the fin 52. The epitaxial source / drain regions 84 can include any acceptable material, such as a material suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain regions 84 in the n-type region 50N can include a material that imposes tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, etc. The epitaxial source / drain regions 84 in the n-type region 50N can have surfaces that are raised from the corresponding surfaces of the fin 52 and can have small facets.

[0061] Once the epitaxial source / drain regions 84 are formed, any remaining portions of the second mask layer 79 can be removed. In an embodiment, the remaining portions of the second mask layer 79 can be removed using, for example, one or more etching processes (e.g., a wet etching process). However, any suitable method can be utilized. In some embodiments, multiple etching processes (e.g., an etch to remove the fins 52, an etch to remove the mask layer 77) can further remove portions of the first seal 73 and the second seal 75 to a position below the mask 74.

[0062] Furthermore, although a specific embodiment is described above in which epitaxial source / drain regions 84 and epitaxial source / drain regions 82 are formed on fins 52, this is intended to be exemplary and not limiting. Rather, any suitable process may be utilized, for example, exposing fins 52, recessing fins 52, and then regrowing epitaxial source / drain regions 84 and epitaxial source / drain regions 82 in the recesses. All such processes are fully encompassed within the embodiments.

[0063] The epitaxial source / drain regions 84 and / or fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a thickness of approximately 10 19 cm -3 and about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 84 may be in-situ doped during growth.

[0064] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in p-type region 50P and epitaxial source / drain regions 84 in n-type region 50N, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets can allow adjacent source / drain regions of the same FinFET to merge. In other embodiments, adjacent source / drain regions remain separated after the epitaxial process is completed.

[0065] The housings of the first and second seals 73 and 75 serve to protect the interior portions of the first and second seals 73 and 75 (at least those portions that will remain in the final product) during all etching processes used to expose and / or recess the fins 52 to form the LDD regions and the epitaxial source / drain regions 82 and 84. For example, while etchants such as sulfuric acid (H2SO4), peroxide (H2O2), dilute hydrofluoric acid (dHF), and oxygen plasma may be used to etch, ash, or otherwise remove portions of the structure, the first and second housings 81 and 87 serve to sandwich and protect the first and second bulk dielectric materials 83 and 85 from those etchants. Furthermore, while the second housing 87 serves to protect the interior materials during the etching process, portions of the second housing 87 itself may be etched and / or damaged during the etching process.

[0066] so, Figures 13A-13D A process is shown in which a contact etch stop layer (CESL) 97 may be used to supplement the outer layer of the second seal 75. In this embodiment, once the epitaxial source / drain regions 82 and the epitaxial source / drain regions 84 have been formed and an optional pre-clean using dilute hydrofluoric acid has been performed (e.g., at 1:100 for 60 seconds), the contact etch stop layer (CESL) 97 is deposited over the structure and in physical contact with the second shell 87 of the second seal 75. In embodiments, the CESL 97 may be deposited similarly to the first and second seals 73 and 75, for example, by depositing a third bulk dielectric material 91 adjacent to the second seal 75, with the third shell 93 adjacent to the third bulk dielectric material 91.

[0067] In an embodiment, the third bulk dielectric material 91 may be formed as described above with reference to the first bulk dielectric material 83 and the second bulk dielectric material 85 to obtain similar physical properties. For example, in the final product, the third bulk dielectric material 91 may be formed to a thickness between about 1.0 nm and about 3.5 nm. In addition, the third bulk dielectric material 91 may be formed to a thickness of about 2.0 g / cm 3 and about 2.4g / cm 3% and can be an oxygen-rich film, wherein the oxygen concentration is between about 40% atomic and about 65% atomic. Finally, the third bulk dielectric material 91 can have a carbon concentration of less than 2% atomic, and a nitrogen concentration between about 5% atomic and about 12% atomic. However, any suitable composition can be utilized.

[0068] Once the third bulk dielectric material 91 has been formed, a third shell 93 can be deposited over the third bulk dielectric material 91. In embodiments, the third shell 93 can be deposited as a dielectric that can be used to assist in protecting underlying layers (e.g., the third bulk dielectric material 91) from subsequent etching processes. Thus, in certain embodiments, the third shell 93 can be a dielectric material, such as silicon nitride, deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, combinations thereof, or the like. Furthermore, the third bulk dielectric material 91 can be formed to a thickness between approximately 1.5 nm and approximately 4.0 nm. However, any suitable dielectric material and thickness can be utilized.

[0069] By depositing third shell 93 and third bulk dielectric material 91, CESL 97 can be deposited with materials that allow CESL 97 to have both an etch-resistant portion (e.g., third shell 93) and a dielectric-reducing portion (e.g., third bulk dielectric material 91). Furthermore, CESL 97 can have a gradient region between approximately 0.5 nm and approximately 2.0 nm resulting from cycling during the deposition process.

[0070] By forming the first seal 73, the second seal 75, and the CESL 97, the multilayer spacer 95 (including the first seal 73, the second seal 75, and the CESL 97) can be formed to a thickness between about 4.5 nm and about 8.0 nm. In addition, the multilayer spacer 95 provides enhanced etching resistance (particularly for etchants such as plasma O2 ashing, sulfuric acid, hydrogen peroxide, dilute hydrofluoric acid, and phosphoric acid) while still maintaining a suitable dielectric constant and having a large spacer uniformity (e.g., <= 95% internal spacer uniformity in the case of an aspect ratio greater than 20). In some embodiments, the total dielectric constant of the spacer can be between about 4.2 and about 5.5. In addition, by forming the various layers in situ with each other as described above, no interlayer oxide film is formed between different films. By forming the layers as described, the total Ceff (RO%) can be increased by between about 1% and about 2%.

[0071] exist Figure 14A and Figure 14B In the first interlayer dielectric (ILD) 88 is deposited on Figure 13A and Figure 13BThe structure shown is shown above. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0072] Once the first ILD 88 has been deposited, an annealing process may be utilized to densify the material of the first ILD 88. In an embodiment, the annealing process may be a wet anneal in which the first ILD 88 is heated in a moisture-containing ambient at a temperature between about 400° C. and about 600° C. for a time between about 0.5 hours and about 3 hours, and then dried at a temperature between about 500° C. and about 700° C. for a time between about 0.5 hours and about 3 hours. However, any suitable time and temperature may be utilized.

[0073] exist Figure 15A and Figure 15B In the process, a planarization process (e.g., CMP) may be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, as well as portions of the first sealant 73, the second sealant 75, and the CESL 97 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the first sealant 73, the second sealant 75, the CESL 97, and the first ILD 88 are flush. Thus, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0074] exist Figure 16A and Figure 16BIn the embodiment of the present invention, dummy gate 72 and mask 74 (if present) are removed in one or more etching steps, thereby forming recesses 90. Portions of dummy dielectric layer 60 within recesses 90 may also be removed. In some embodiments, only dummy gate 72 is removed, and dummy dielectric layer 60 remains and is exposed by recesses 90. In some embodiments, dummy dielectric layer 60 is removed from recesses 90 in a first region of the die (e.g., the core logic region) and remains within recesses 90 in a second region of the die (e.g., the input / output region). In some embodiments, dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases (e.g., ammonia (NH3) and hydrofluoric acid (HF)) that selectively etches dummy gate 72 while leaving little or no etching on first ILD 88 or multi-layer spacers 95. Each recess 90 exposes and / or overlies the channel region 58 of a corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82 or epitaxial source / drain regions 84. During removal, dummy dielectric layer 60 may serve as an etch stop when etching dummy gate 72. Dummy dielectric layer 60 may then optionally be removed after dummy gate 72 is removed.

[0075] However, the presence of the etch-resistant first shell 81 helps reduce damage to the remainder of the multilayer spacer 95 when forming the recess 90. For example, the first shell 81 may lose less than of materials (while other materials may lose more than ), while still protecting the material of the first bulk dielectric material 83 (which may lose up to ). This protection of the multi-layer spacer 95 has the added benefit of minimizing the loss of the LDD region, which will only be or less.

[0076] exist Figure 17A and Figure 17B In the embodiment, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 17C Shown Figure 17BDetailed view of region 89 of FIG. One or more layers of a gate dielectric layer 92 are deposited in recess 90 , for example, on the top surface and sidewalls of fin 52 and on the sidewalls of multilayer spacers 95 . Gate dielectric layer 92 may also be formed on the top surface of first ILD 88 . In some embodiments, gate dielectric layer 92 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, gate dielectric layer 92 includes an interfacial layer of silicon oxide formed by thermal oxidation or chemical oxidation, and an overlying high-k dielectric material, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Gate dielectric layer 92 may include a dielectric layer having a k value greater than approximately 7.0. Methods for forming gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, or the like. In embodiments where portions of the dummy dielectric layer 60 remain in the recess 90 , the gate dielectric layer 92 includes the material of the dummy dielectric layer 60 (eg, SiO 2 ).

[0077] The gate electrode 94 is separately deposited on the gate dielectric layer 92 and fills the remaining portion of the recess 90. The gate electrode 94 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although in Figure 17B A single-layer gate electrode 94 is shown in FIG, but the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler materials 94C, such as Figure 17C As shown. After filling the recess 90, a planarization process such as CMP can be performed to remove the material of the gate electrode 94 and the excess portion of the gate dielectric layer 92 that is above the top surface of the first ILD 88. The material of the gate electrode 94 and the remaining portion of the gate dielectric layer 92 thus form the replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as a "gate stack", and the gate stack can have a gate height between about 10 nm and about 20 nm, and the gate electrode 94 can have a gate length L between about 14.5 nm and about 17 nm. g The gate and gate stack may extend along the sidewalls of the channel region 58 of the fin 52 .

[0078] The formation of gate dielectric layer 92 in n-type region 50N and p-type region 50P can occur simultaneously, such that gate dielectric layer 92 in each region is formed of the same material, and the formation of gate electrode 94 can occur simultaneously, such that gate electrode 94 in each region is formed of the same material. In some embodiments, gate dielectric layer 92 in each region can be formed using a different process, such that gate dielectric layer 92 can be a different material, and / or gate electrode 94 in each region can be formed using a different process, such that gate electrode 94 can be a different material. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0079] exist Figure 18A and Figure 18B In the embodiment of the present invention, a gate mask 96 is formed over the gate stack (including the gate dielectric layer 92 and the corresponding gate electrode 94), and the gate mask can be disposed between opposing portions of the multi-layer spacer 95. In some embodiments, forming the gate mask 96 includes recessing the gate stack to form a groove directly above the gate stack and between opposing portions of the multi-layer spacer 95. The gate mask 96 includes one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc., which are filled in the groove, and then a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD 88.

[0080] Also like Figure 18A and Figure 18B As shown, a second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. The gate contact 110 ( Figure 19A and Figure 19B ) passes through the second ILD 108 and the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0081] exist Figure 19A and Figure 19BIn some embodiments, a gate contact 110 and source / drain contacts 112 are formed through the second ILD 108 and the first ILD 88. An opening for the source / drain contact 112 is formed through the first ILD 88 and the second ILD 108, and an opening for the gate contact 110 is formed through the second ILD 108 and the gate mask 96. The opening can be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 108. The remaining liner and conductive material form the source / drain contacts 112 and the gate contact 110 in the opening. An annealing process may be performed to form silicide at the interface between epitaxial source / drain regions 82 and 84 and source / drain contact 112. Source / drain contact 112 is physically and electrically coupled to epitaxial source / drain regions 82 and 84, and gate contact 110 is physically and electrically coupled to gate electrode 94. Source / drain contact 112 and gate contact 110 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of source / drain contact 112 and gate contact 110 may be formed in different cross-sections, which may avoid shorting of the contacts.

[0082] By forming a multilayer spacer 95 as described herein, benefits can be achieved. Specifically, by using multiple layers, each of which includes both a shell portion and a body portion, etch resistance can be improved without excessively increasing the overall dielectric constant. In this way, less damage will occur, and the overall performance of the device can be improved.

[0083] In one embodiment, a semiconductor device includes: a first spacer layer including an inner layer disposed between two outer layers, wherein the inner layer and the two outer layers each include a first material, wherein the carbon content of the two outer layers is greater than the carbon content of the inner layer, and the oxygen content of the two outer layers is less than the oxygen content of the inner layer; and a second spacer layer including a first layer and a second layer, the first layer being the first material and in direct contact with one of the two outer layers. In one embodiment, the first material includes SiOCN. In one embodiment, the second layer includes silicon nitride. In one embodiment, the carbon content of the first layer of the second spacer layer is less than about 2%. In one embodiment, the density of one of the two outer layers is about 2.5 g / cm 3 and about 2.7g / cm 3In one embodiment, the nitrogen concentration of the inner layer is between about 5% and about 12%. In one embodiment, the nitrogen concentration of one of the two outer layers is between about 25% and about 45%.

[0084] In another embodiment, a semiconductor device includes a first sealant adjacent to a gate stack, the first sealant comprising a first body of a first material having a first composition; and a first bulk of the first material having a second composition different from the first composition; a second sealant in physical contact with the first sealant, the second sealant comprising a second body of the first material having a third composition; and a second bulk of the first material having a fourth composition different from the third composition; and a contact etch stop layer in physical contact with the second sealant, the contact etch stop layer comprising a third bulk of the first material having a fifth composition; and a third body of the second material different from the first material. In one embodiment, the first material comprises silicon carbon oxynitride. In one embodiment, the first composition has a lower oxygen concentration than the second composition. In one embodiment, the first composition has a higher nitrogen concentration than the second composition. In one embodiment, the first composition has a higher carbon concentration than the second composition. In one embodiment, the second material comprises silicon nitride. In one embodiment, the carbon concentration of the first composition is between approximately 5% and approximately 20%.

[0085] In yet another embodiment, a method of fabricating a semiconductor device includes patterning a dummy gate electrode over a semiconductor fin; sequentially introducing a first set of precursors to the dummy gate electrode using a first set of exposure times to form a first shell layer; sequentially introducing the first set of precursors to the dummy gate electrode using a second set of exposure times different from the first set of exposure times to form a first bulk dielectric material; sequentially introducing the first set of precursors to the dummy gate electrode using a third set of exposure times to form a second bulk dielectric material; sequentially introducing the first set of precursors to the dummy gate electrode using a fourth set of exposure times different from the first set of exposure times to form a second shell layer; sequentially introducing the first set of precursors to the dummy gate electrode using a fifth set of exposure times to form a third bulk dielectric material; and, after sequentially introducing the first set of precursors to the dummy gate electrode using the fifth set of exposure times, depositing a dielectric material. In one embodiment, the first shell layer is silicon carbon oxynitride. In one embodiment, the dielectric material is silicon nitride. In one embodiment, sequentially introducing the first set of precursors to the dummy gate electrode using the third set of exposure times occurs after forming lightly doped source / drain regions. In one embodiment, sequentially introducing the first set of precursors to the dummy gate electrode using the third set of exposure times occurs prior to forming the lightly doped source / drain regions. In one embodiment, the first shell layer has a higher nitrogen concentration than the first bulk dielectric material.

[0086] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0087] Example 1 is a semiconductor device comprising: a first spacer layer comprising an inner layer arranged between two outer layers, wherein the inner layer and the two outer layers each comprise a first material, wherein the carbon content of the two outer layers is greater than the carbon content of the inner layer, and the oxygen content of the two outer layers is less than the oxygen content of the inner layer; and a second spacer layer comprising a first layer and a second layer, the first layer being the first material and being in direct contact with one of the two outer layers.

[0088] Example 2 is the semiconductor device of Example 1, wherein the first material includes SiOCN.

[0089] Example 3 is the semiconductor device of Example 1, wherein the second layer includes silicon nitride.

[0090] Example 4 is the semiconductor device of Example 1, wherein the carbon content of the first layer of the second spacer layer is less than approximately 2%.

[0091] Example 5 is the semiconductor device of Example 1, wherein the density of one of the two outer layers is about 2.5 g / cm 3 and about 2.7g / cm 3 between.

[0092] Example 6 is the semiconductor device of Example 1, wherein a nitrogen concentration of the inner layer is between approximately 5% and approximately 12%.

[0093] Example 7 is the semiconductor device of Example 1, wherein a nitrogen concentration of one of the two outer layers is between approximately 25% and approximately 45%.

[0094] Example 8 is a semiconductor device, comprising: a first sealant, adjacent to the gate stack, the first sealant comprising: a first body of a first material having a first component; and a first bulk material of the first material having a second component, the second component being different from the first component; a second sealant, physically contacting the first sealant, the second sealant comprising: a second body of the first material having a third component; and a second bulk material of the first material having a fourth component, the fourth component being different from the third component; and a contact etch stop layer, physically contacting the second sealant, the contact etch stop layer comprising: a third bulk material of the first material having a fifth component; and a third body of a second material different from the first material.

[0095] Example 9 is the semiconductor device of Example 8, wherein the first material includes silicon carbon oxynitride.

[0096] Example 10 is the semiconductor device of Example 8, wherein the first component has a smaller oxygen concentration than the second component.

[0097] Example 11 is the semiconductor device of Example 10, wherein the first component has a greater nitrogen concentration than the second component.

[0098] Example 12 is the semiconductor device of Example 11, wherein the first component has a greater carbon concentration than the second component.

[0099] Example 13 is the semiconductor device of Example 12, wherein the second material includes silicon nitride.

[0100] Example 14 is the semiconductor device of Example 8, wherein a carbon concentration of the first component is between approximately 5% and approximately 20%.

[0101] Example 15 is a method for manufacturing a semiconductor device, the method comprising: patterning a dummy gate electrode over a semiconductor fin; sequentially introducing a first group of precursors into the dummy gate electrode using a first set of exposure times to form a first shell layer; sequentially introducing the first group of precursors into the dummy gate electrode using a second set of exposure times different from the first set of exposure times to form a first bulk dielectric material; sequentially introducing the first group of precursors into the dummy gate electrode using a third set of exposure times to form a second bulk dielectric material; sequentially introducing the first group of precursors into the dummy gate electrode using a fourth set of exposure times different from the first set of exposure times to form a second shell layer; sequentially introducing the first group of precursors into the dummy gate electrode using a fifth set of exposure times to form a third bulk dielectric material; and depositing a dielectric material after sequentially introducing the first group of precursors into the dummy gate electrode using the fifth set of exposure times.

[0102] Example 16 is the method of example 15, wherein the first shell layer is silicon oxycarbonitride.

[0103] Example 17 is the method of example 16, wherein the dielectric material is silicon nitride.

[0104] Example 18 is the method of example 15, wherein sequentially introducing the first set of precursors to the dummy gate electrode using the third set of exposure times occurs after forming a lightly doped source / drain region.

[0105] Example 19 is the method of example 15, wherein sequentially introducing the first set of precursors to the dummy gate electrode using the third set of exposure times occurs before forming a lightly doped source / drain region.

[0106] Example 20 is the method of example 15, wherein the first shell layer has a higher nitrogen concentration than the first bulk dielectric material.

Claims

1. A semiconductor device comprising: a first spacer layer comprising an inner layer disposed between two outer layers, wherein the inner layer and the two outer layers each comprise a first material, wherein the two outer layers have a carbon content greater than a carbon content of the inner layer, and wherein the two outer layers have an oxygen content less than an oxygen content of the inner layer; and A second spacer layer includes a first layer and a second layer, the first layer being the first material and in direct contact with one of the two outer layers, wherein the first material includes SiOCN and the second layer includes silicon nitride.

2. The semiconductor device according to claim 1, wherein The carbon content of the first layer of the second spacer layer is less than 2%.

3. The semiconductor device according to claim 1, wherein The density of one of the two outer layers is 2.5 g / cm 3 and 2.7 g / cm 3 between.

4. The semiconductor device according to claim 1, wherein The nitrogen concentration of the inner layer is between 5% and 12%. The semiconductor device according to claim 1 , wherein The nitrogen concentration of one of the two outer layers is between 25% and 45%.

6. A semiconductor device comprising: A first sealing member is adjacent to the gate stack, the first sealing member comprising: a first shell of a first material having a first composition; and a first bulk material of the first material having a second composition different from the first composition; A second sealing member is in physical contact with the first sealing member, and the second sealing member comprises: a second shell of said first material having a third composition; and a second body of the first material having a fourth composition different from the third composition; and a contact etch stop layer, physically contacting the second sealing member, the contact etch stop layer comprising: a third body of said first material having a fifth composition; and A third housing of a second material different from the first material, wherein the first material comprises silicon carbon oxynitride and the second material comprises silicon nitride.

7. The semiconductor device according to claim 6, wherein The first component has a smaller oxygen concentration than the second component.

8. The semiconductor device according to claim 7, wherein The first component has a greater nitrogen concentration than the second component.

9. The semiconductor device according to claim 8, wherein The first component has a greater carbon concentration than the second component.

10. The semiconductor device according to claim 6, wherein The carbon concentration of the first component is between 5% and 20%.

11. A method for manufacturing a semiconductor device, the method comprising: patterning a dummy gate electrode over the semiconductor fin; sequentially introducing a first set of precursors to the dummy gate electrode using a first set of exposure times to form a first shell layer; sequentially introducing the first set of precursors to the dummy gate electrode using a second set of exposure times different from the first set of exposure times to form a first bulk dielectric material; sequentially introducing the first set of precursors to the dummy gate electrode using a third set of exposure times to form a second bulk dielectric material; sequentially introducing the first set of precursors to the dummy gate electrode using a fourth set of exposure times different from the first set of exposure times to form a second shell layer; sequentially introducing the first set of precursors to the dummy gate electrode using a fifth set of exposure times to form a third bulk dielectric material; as well as After sequentially introducing the first set of precursors to the dummy gate electrode using the fifth set of exposure times, a dielectric material is deposited, wherein the first shell layer is silicon carbon oxynitride and the dielectric material is silicon nitride.

12. The method according to claim 11, wherein Sequentially introducing the first set of precursors to the dummy gate electrode using the third set of exposure times occurs after forming the lightly doped source / drain regions.

13. The method according to claim 11, wherein Sequentially introducing the first set of precursors to the dummy gate electrode using the third set of exposure times occurs prior to forming lightly doped source / drain regions.

14. The method according to claim 11, wherein The first shell layer has a higher nitrogen concentration than the first bulk dielectric material.

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