Semiconductor device including embedded semiconductor die and method of manufacturing the same

Abstract

A semiconductor device (10) comprises a die carrier (11); a semiconductor die (12) arranged on a main face of the die carrier (11), the semiconductor die (12) comprising one or more contact pads (12A) on a main face thereof; an encapsulant (13) at least partially covering the semiconductor die (12) and at least a portion of the main face of the die carrier (11); and an insulating layer (14) covering the encapsulant (13); and one or more electrical interconnects (15), each of the one or more electrical interconnects (15) being connected with one of the contact pads (12A) of the semiconductor die (12) and extending through the encapsulant (13).

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor devices, in particular to semiconductor power devices. The present disclosure relates in particular to a semiconductor device comprising an embedded semiconductor die arranged on a leadframe-based die carrier, and to a method for manufacturing such a semiconductor device. BACKGROUND

[0002] Chip embedding is a solution where active or passive components are positioned between at least two layers of a printed circuit board. Currently, it is commonly used for low voltage signal processing systems, first trying to apply embedding for low voltage power circuits with < 100 V, but for high voltage, special challenges related to high electric fields are expected. The motivation for doing so is manifold, e.g. increased power density, very low parasitic inductance, better EMI shielding, and also high reliability and high power cycling robustness. Moreover, chip embedding usually employs electroplated electrical interconnections, in particular galvanically plated electrical interconnections, which are superior to other types of electrical interconnections.

[0003] One solution for manufacturing chip-embedded high voltage semiconductor devices is to place the die on a leadframe, to singulate the die on the leadframe, and to embed this assembly afterwards. One risk of the embedding technology is the interaction of the device with the used carrier material, where one major mechanism is the voltage and the resulting electric field. This can lead in the worst case to a destruction of the assembly, e.g. by copper migration. Another threat is the exposed copper metallization on the die. The oxidation of the copper metallization has to be treated specially in the embedding process. After placing the components, the connection to the outer layers is done by vias. In particular the passage from the via to the die metallization is a critical point for breaking. In addition, there is a strong interaction of the embedding encapsulation material and the manufacturing process in combination with the high voltage device and the resulting electric field, leading to a chemical degradation of the encapsulation material (e.g. pentode, reversible drift), a voltage drift of the device caused by ions from the encapsulation material, a corrosion of the device. The embedding material is also humidity sensitive and cannot guarantee the density of the covered chip, which accelerates the negative effects just described. To prevent delamination of the surrounding layer, cavities in the leadframe are used, into which the die is placed afterwards. With this approach, for each die, a dedicated cavity has to be done. SUMMARY

[0004] A first aspect of the present disclosure relates to a semiconductor device comprising a die carrier; a semiconductor die arranged on the die carrier, the semiconductor die comprising one or more contact pads on a main face thereof; an encapsulant at least partially covering at least a portion of the main face of the semiconductor die and the die carrier; and an insulating layer covering the encapsulant; and one or more electrical interconnections, each of the one or more electrical interconnections being connected with one of the contact pads of the semiconductor die and extending through the encapsulant.

[0005] A second aspect of the present disclosure relates to a method for manufacturing a semiconductor device, the method comprising: providing a die carrier, disposing a semiconductor die on a main face of the die carrier, the semiconductor die comprising one or more contact pads on a main face thereof, at least partially applying an encapsulant to at least a portion of the main face of the semiconductor die and the die carrier, applying an insulating layer to the encapsulant, and manufacturing an electrical interconnect by forming an opening into the encapsulant and the insulating layer and filling the opening with an electrically conductive material.

[0006] A third aspect of the present disclosure relates to a method for manufacturing a semiconductor device, the method comprising: providing a die carrier, disposing a semiconductor die on a main face of the die carrier, the semiconductor die comprising one or more contact pads on a main face thereof, disposing a first electrical interconnect on the one or more contact pads of the semiconductor die, at least partially applying an encapsulant to at least a portion of the main face of the semiconductor die and the die carrier, applying an insulating layer to the encapsulant, and manufacturing a second electrical interconnect by forming an opening into the insulating layer and filling the opening with an electrically conductive material. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description.

[0008] Elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

[0009] Fig. 1 comprises Figures 1A-1D and shows a schematic cross-sectional side view representation of an exemplary semiconductor device according to the first aspect, wherein the die carrier comprises a planar upper surface and the semiconductor die is disposed on the planar upper surface and the encapsulant is disposed on the semiconductor die and only a portion of the planar upper surface of the die carrier (A); and several first steps (B to D) for manufacturing the semiconductor device.

[0010] Fig. 2 comprises Figures 2A-2D and shows a schematic cross-sectional side view representation of an exemplary semiconductor device according to the first aspect, wherein the die carrier comprises a planar upper surface and the semiconductor die is disposed on the planar upper surface and the encapsulant is disposed on the semiconductor die and on the complete planar upper surface and on the sides of the die carrier (A); and several first steps (B to D) for manufacturing the semiconductor module.

[0011] Fig. 3 comprises Figures 3A-3Dand a schematic cross-sectional side view representation of an exemplary semiconductor device according to the first aspect is shown, wherein the die carrier comprises a recessed area and a semiconductor die is arranged in the recessed area and an encapsulant is arranged in the recessed area on the semiconductor die and a plurality of electrical through connections (A) is formed in the encapsulant; and several first steps (B to D) for manufacturing a semiconductor module.

[0012] Fig. 4 comprises Figures 4A-4D and a schematic cross-sectional side view representation of an exemplary semiconductor device according to the first aspect is shown, wherein the die carrier comprises a recessed area and a semiconductor die is arranged in the recessed area and an encapsulant is arranged in the recessed area on the semiconductor die and a plurality of electrical through connections (A) is formed in the encapsulant; and several first steps (B to D) for manufacturing a semiconductor module.

[0013] Figure 5 a schematic cross-sectional side view representation of an exemplary semiconductor device according to the first aspect is shown, wherein two types of electrical interconnections are provided, wherein one type of electrical interconnection protrudes through the encapsulant and the other type of electrical interconnection protrudes through the insulating layer.

[0014] Figure 6 a flow chart of an exemplary method for manufacturing a semiconductor device is shown, wherein the electrical interconnections are manufactured after applying the encapsulant and the insulating layer.

[0015] Figure 7 a flow chart of an exemplary method for manufacturing a semiconductor device is shown, wherein the electrical interconnections are manufactured before applying the encapsulant and the insulating layer. DETAILED DESCRIPTION

[0016] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the disclosure can be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "leading," "trailing," etc., is used with reference to the orientation of the figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and not of limitation. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0017] It is to be understood that features of the various exemplary embodiments described herein can be combined with each other, unless specifically noted otherwise.

[0018] As employed in the present specification, the terms "engaged," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" do not mean that the elements or layers must be in direct contact; an intervening element or layer can be provided between the elements that are "engaged," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled," respectively. However, according to the present disclosure, the aforementioned terms can optionally also have the specific meaning that the elements or layers are in direct contact, i.e., no intervening element or layer is provided between the elements that are "engaged," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled," respectively.

[0019] Further, the word "over" used in reference to overlying of one or more portions, elements, or material layers, as employed in the present specification and throughout the claims, unless otherwise specifically indicated, can be used in the sense of "on," "above," or "overlying," in the sense of "directly on," "directly over," or "directly overlying," and / or in the sense of "indirectly on," "indirectly over," or "indirectly overlying." Thus, for example, a portion can be described as overlying a surface, wherein a portion, element, or layer is positioned between the overlying portion and the surface.

[0020] FIG. 1 includes Figures 1A-1D and shows a schematic cross-sectional side view representation (A) of an exemplary semiconductor device, as well as several first steps (B to D) for manufacturing the semiconductor device.

[0021] Figure 1A A semiconductor device 10 is shown, which comprises a leadframe-based die carrier 11, a semiconductor die 12 disposed on a first upper main face of the die carrier 11, the semiconductor die 12 comprising one or more contact pads 12A (not shown) on its main face, an encapsulant 13 covering a portion of the main face of the semiconductor die 12 and the die carrier 11. The semiconductor device 10 further comprises an insulating layer 14 covering the encapsulant 13 as well as a portion of the first upper main face and the second lower main face of the die carrier 11, and a plurality of electrical interconnects 15, a lower end of each of the plurality of electrical interconnects 15 being connected with one of the contact pads of the semiconductor die 12 and extending through the encapsulant 13 and the insulating layer 14. At an upper end of the electrical interconnects 15, the electrical interconnects are connected with metal traces provided on a metallization layer 16 disposed on top of the insulating layer 14. The die carrier 11 is also connected with one of the metal traces 16A by means of an electrical interconnect 15 that protrudes through a backside portion of the insulating layer 14. Alternatively, the die carrier 11 can be contacted by an electrical interconnect that protrudes through a backside portion of the insulating layer 14.

[0022] The embodiment of the semiconductor device shown in Fig. 1 is configured such that the die carrier 11 is arranged within the open portion of the PCB 17 and the insulating layer 14 covers the encapsulant 13 on the upper main face of the die carrier 11 and on the side faces of the die carrier 11 and also extends through the space between the side faces of the die carrier 11 and the side faces of the PCB 17 to the backside of the die carrier 11 and the PCB 17. The electrical interconnects 15 not only extend through the encapsulant 13 but also through a portion of the insulating layer 14 arranged on the upper surface of the encapsulant 13. As Figure 1A shown, there can also be electrical interconnects 15 extending only through the insulating layer 14, in particular the electrical interconnects connecting the die carrier with one of the metal tracks 16A.

[0023] According to the embodiment of the semiconductor device according to Fig. 1, the encapsulant 13 comprises one or more of a resin, an epoxy resin, a polyimide and a silicone resin. The encapsulant 13 can contain filler material, such as filler particles, by which the thermal conductivity is increased. If the encapsulant 13 shall be structured by laser, it is preferred to use rather small filler particles, for example, in the range from 10 pm to 50 pm diameter, such that vias with small diameter can also be structured by laser. In particular, the material type of the encapsulant 13 can be chosen depending on the properties of the semiconductor die 12, in particular depending on the voltage range of the semiconductor die 12. Thus, by choosing a suitable encapsulant material with sufficient isolation properties, semiconductor dies with a voltage higher than 100 V can be employed. The aggregation state of the applied encapsulant can be any one of a small ball, a granulate, a powder, a liquid or a wafer.

[0024] According to an embodiment of the semiconductor device according to the first aspect, the encapsulant 13 completely covers the upper main face and the side faces of the semiconductor die 12, as shown in the embodiment of Figure 1A .

[0025] According to another embodiment of the semiconductor device according to the first aspect, the encapsulant 13 only partially covers the upper main face of the semiconductor die 12. In particular, the encapsulant 13 can cover the upper surface of the semiconductor die 12 only in the edge region and possibly in the side faces but not in the central region of the upper surface for reasons of edge termination and avoidance of high electric fields. The central region can alternatively be filled by the insulating layer 14, for example, laminated by the insulating layer 14. Furthermore, in such an embodiment, the encapsulant 13 can be applied to the edge region by dispensing, potting or even bottom-filling dispensing. Furthermore, it should be noted that this embodiment can also be applied in the other embodiments shown and explained in connection with Figure 2A , Figure 3A , Figure 4A and Figure 5 .

[0026] According to an embodiment of the semiconductor device of Fig. 1, the semiconductor die 12 is connected to the die carrier by soldering, in particular by diffusion soldering or sintering, or by using glue, in particular using a conductive glue like silver glue.

[0027] According to an embodiment of the semiconductor device of Fig. 1, the semiconductor die 12 can be one or more of a vertical transistor die, a MOSFET die, an IGBT die, a SiC-MOS die, a Cool-MOS die, a S-FET die, a gate driver die, a controller, or a connection die configured to connect the semiconductor device to an external entity. The connection die can be, for example, a WiFi module or a USB interface.

[0028] According to an embodiment of the semiconductor device of Fig. 1, the semiconductor die 12 is one or more of a wide bandgap semiconductor die, a SiC die, or a GaN die.

[0029] According to an embodiment of the semiconductor device of Fig. 1, two or more semiconductor dies are arranged on the die carrier 11. For example, a first semiconductor die can be a transistor die, in particular one of the above-mentioned transistor dies, and a second semiconductor die can be another transistor die or a diode die. The transistor dies can act as switches, and the two switches can be connected in series or in parallel.

[0030] According to an embodiment of the semiconductor device of Fig. 1, the insulation layer 14 can be applied in different aggregated states, for example, as a layer of a plastic material in liquid form, as small balls, as granules, or as a laminate of any kind. Moreover, the insulation layer 14 can be made of a thermally conductive material to allow an efficient heat dissipation, in particular to the bottom. In particular, the material of the insulation layer 14 can comprise a resin like an epoxy resin, and more specifically, a material filled with thermally conductive particles, for example made of AIO, BNi, AlNi, SiN, diamond, or any other thermally conductive particles. Also, the top layer and the bottom layer of the insulation layer 14 can have different thermal conductivities. In particular, the bottom layer can have a higher thermal conductivity, since the heat dissipation to the top is already achieved by the electrical interconnect. Thus, the top layer can have a low amount or even zero amount of filler particles.

[0031] According to an embodiment of the semiconductor device 10, the electrical interconnect 15 can be manufactured by laser drilling a via hole into the encapsulant 13 and possibly also into the insulation layer 14, such that the via hole reaches down to the contact pad 12A of the semiconductor die 12, and thereafter filling the via hole with a conductive material, for example copper. In case of an IGBT die 12, the contact pad 12A on the upper surface can comprise a source or emitter pad and a gate pad. The source pad can be split into a plurality of sub-pads, and the electrical interconnect 15 can be connected with these sub-pads.

[0032] Configuration Figure 1A In the embodiment shown in Fig. 1, the die carrier 11 comprises a planar upper surface, and the semiconductor die 12 is arranged on the planar upper surface, and the encapsulant 13 covers only a portion of the main face of the die carrier 11.

[0033] According to an embodiment of the semiconductor device 10, the thickness of the die carrier 11 can be in a range from 300 pm to 3 mm, wherein the lower limit of the range can also be 400 pm or 500 pm, and the upper limit of the range can also be 2.5 mm or 2 mm.

[0034] According to an embodiment of the semiconductor device 10, the die carrier 11 can be one of a part of a leadframe, a direct copper bonding (DCB), an active metal brazing (AMB), or an isolated metal substrate (IMS).

[0035] Figures 1B-1D A first step of manufacturing the semiconductor device 10 is shown. Figure 1B A perspective view from above onto a leadframe is shown, the leadframe containing a plurality of die carriers 11 interconnected within a frame structure. Semiconductor dies 12 are to be arranged onto each of the die carriers 11 and connected to the upper main face of the die carriers 11 by, for example, diffusion welding. Figure 1C An enlarged view of the upper left part of the leadframe is shown. In the present embodiment, the semiconductor dies 12 are IGBT dies, each comprising contact pads 12A in the form of large-area source or emitter pads and small-area gate pads on their upper main face. In the present embodiment, the source pads can be split into a plurality of sub-pads, as can be seen in Fig. 1C. Figure 1C The IGBT dies 12 further comprise drain or collector pads on the back surface of the die carrier 11, through which the IGBT dies 12 are connected with the upper surface of the die carrier 11. Thereafter, the encapsulant 13 is applied individually onto each of the IGBT dies 12. Figure 1D A perspective view from above onto the leadframe is shown after the application of the individual encapsulants 13, with the IGBT dies 12 being covered by the encapsulants 13. Figure 1C The same assembly view.

[0036] The encapsulant 13 can be deposited by, for example, transfer molding or compression molding or by lamination.

[0037] Fig. 2 comprises Figures 2A-2D and shows a schematic cross-sectional side view representation (A) of an exemplary semiconductor device, as well as several first steps (B to D) for manufacturing the semiconductor module.

[0038] Figure 2AA semiconductor device 20 is shown, which comprises a leadframe-based die carrier 21, a semiconductor die 22 arranged on a first upper main face of the die carrier 21, the semiconductor die 22 comprising one or more contact pads on its main face, an encapsulant 23 covering the semiconductor die 22, the first upper main face of the die carrier 21 and the side faces. The semiconductor device 20 further comprises an insulating layer 24 covering the encapsulant 23 and a plurality of electrical interconnects 25, each of which is connected with one of the contact pads of the semiconductor die 22 and extends through the encapsulant 23.

[0039] The semiconductor device 20 differs from the semiconductor device 10 of Fig. 1 in that the encapsulant 23 is covered onto the complete upper main face and also onto the side faces of the die carrier 21 and that the electrical interconnects 25 connecting the die carrier 21 with one of the metal traces of the layer 26 extend through both the encapsulant 23 and the insulating layer 24. Thus, the insulating layer 24 covers the die carrier 21 only on its second lower main face.

[0040] Figures 2B-2D A first step of manufacturing the semiconductor device 20 is shown. Figure 2B A perspective view from above onto a leadframe is shown, which contains a plurality of die carriers 21 interconnected within a frame structure. Semiconductor dies 22 are to be arranged onto each of the die carriers 21 and connected to the upper main face of the die carrier 11 by, for example, diffusion bonding. As Figure 2B is shown, contrary to the method shown in Figures 1B-1D In the present embodiment, the encapsulant 23 is applied to the complete structure, so that the encapsulant 23 not only covers the whole upper surface of the semiconductor device, but also flows into the intermediate spaces between the semiconductor devices of the frame structure, thereby covering the side faces of the die carriers 21 as well. Figure 2C and Figure 2D The singulated semiconductor devices are shown in a perspective view from below (2C) and in a perspective view from above (2D), wherein it can be seen that the encapsulant 23 is even covered onto the small edge portions of the lower main faces of the die carriers 21.

[0041] The die carrier 21, the semiconductor die 22, the contact pads 22A, the encapsulant 23, the insulating layer 24, the electrical interconnects 25 and the metallization layer 26 of the semiconductor device 20 can have the same properties as the die carrier 11, the semiconductor die 12, the contact pads 12A, the encapsulant 13, the insulating layer 14, the electrical interconnects 15, the metallization layer 16 of the semiconductor device 10.

[0042] Fig. 3 comprises Figures 3A-3D and shows a schematic cross-sectional side view representation (A) of an exemplary semiconductor device and several first steps (B to D) for manufacturing a semiconductor module.

[0043] Figure 3A A semiconductor device 30 is shown, which comprises a leadframe-based die carrier 31 comprising a recessed area 31A in its first upper main face, a semiconductor die 32 arranged in the recessed area 31A, the semiconductor die 32 comprising one or more contact pads on its main face, an encapsulant 33 covering the semiconductor die 32 as well as the bottom face and the side faces of the recessed area 31A. The semiconductor device 30 further comprises an insulating layer 34 covering the first upper main face, the upper surface of the encapsulant 33 as well as the side faces of the die carrier 31 and the second lower main face, and a plurality of electrical interconnects 35, each of which is connected with one of the contact pads 32A of the semiconductor die 32 and extends through the encapsulant 33.

[0044] As Figure 3A embodied in the embodiments of Fig. 3, the encapsulant 33 can be filled into the recessed area 31A such that its upper surface is coplanar with the upper surface of the die carrier 31.

[0045] According to an embodiment of the semiconductor device of Fig. 3, the depth of the recessed area 31A can be in a range from 0.2 mm to 2 mm, wherein the lower limit of the range can also be 0.3 mm, 0.4 mm or 0.5 mm, the upper limit of the range can also be 1.9 mm, 1.8 mm, 1.7 mm, 1.6 mm or 1.5 mm, and the standard values can be 1.27 mm, 1 mm, 0.8 mm, 500 pm and 300 pm.

[0046] The die carrier 31, the semiconductor die 32, the contact pads 32A, the encapsulant 33, the insulating layer 34, the electrical interconnects 35 and the metallization layer 36 of the semiconductor device 30 can have the same properties as the die carrier 11, the semiconductor die 12, the encapsulant 13, the insulating layer 14, the electrical interconnects 15 and the metallization layer 16 of the semiconductor device 10.

[0047] Figures 3B-3D A first step of manufacturing the semiconductor device 30 is shown. Figure 3B A perspective view from above onto a leadframe is shown, which contains a plurality of die carriers 31 interconnected within the frame structure, each of the die carriers 31 comprising a recessed area 31A. Semiconductor dies 12 are to be inserted into each of the recessed areas 31A of the die carriers 31 and connected to the bottom face of the recessed areas 31A by, for example, diffusion bonding. Figure 3C An enlarged view of the upper left part of the leadframe is shown after filling the encapsulant 33 into the recessed areas 31A. Figure 3D A perspective view of the assembly is shown, with the encapsulant 33 partially removed.

[0048] Fig. 4 comprises Figures 4A-4Dand a schematic cross-sectional side view representation (A) of an exemplary semiconductor device is shown, as well as several first steps (B to D) for manufacturing the semiconductor module.

[0049] Figure 4A A semiconductor device 40 is shown, which comprises a leadframe-based die carrier 41 comprising a recessed area 41A in its first upper main face, a semiconductor die 42 arranged in the recessed area 41A, the semiconductor die 42 comprising one or more contact pads 42A (not shown) on its main face, an encapsulant 43 covering the semiconductor die 42 as well as the bottom face and the side faces of the recessed area 41A. The semiconductor device 40 further comprises an insulating layer 44 covering the upper surface of the encapsulant 43, the first upper main face of the die carrier 41, the side faces and the second lower main face, and first electrical interconnects 45, each of which is connected with one of the contact pads 42A of the semiconductor die 42 and extends through the encapsulant 43.

[0050] The semiconductor device 40 differs from the semiconductor device 30 of Fig. 3 in that the first electrical interconnects 45 are formed in a different way. More specifically, the first electrical interconnects 45 are applied to the contact pads 42A of the semiconductor die 42 in the form of a large continuous block of a metallic material. This can be done in different ways. One way is to pre-fabricate the metallic block, e.g. a copper block, and then to apply the block as a whole to the contact pads 42A, e.g. by adhesion using a glue like silver glue. Another way of fabricating the first electrical interconnects 45 is to employ a gas-dynamic cold-spraying or cold-spraying method, in which solid metal powder is accelerated in a supersonic jet to speeds of up to about 1200 m / s. During impact with the substrate, the particles undergo plastic deformation and adhere to the surface. To achieve a uniform thickness, the spray nozzle can be scanned along the substrate. Another way of fabricating the first electrical interconnects 45 is to apply vertical metallic wires to the contact pads prior to deposition of the encapsulant and the insulating layer. In particular, the vertical wires can extend through the upper surface of the insulating layer.

[0051] The semiconductor device 40 further differs from the semiconductor device 30 of Fig. 3 in that the first electrical interconnects 45 extend only through the encapsulant 43 and not through the insulating layer 44. In contrast, second electrical interconnects 47 are provided on top of the first electrical interconnects 45. These second electrical interconnects 47 can be fabricated, e.g., by drilling (in particular by laser) a via into the insulating layer 44 and then filling the via with a conductive material, in particular with copper. The second electrical interconnects 47 can then be connected with specific conductive traces of the metallization layer 46.

[0052] The thickness of the first electrical interconnects 45 can be in the range from 200 pm to 600 pm, wherein the lower limit can also be 250 pm or 300 pm and the upper limit can also be 550 pm or 500 pm.

[0053] After the first electrical interconnect 45 has been manufactured in the above described manner, the encapsulant 43 is filled into the recessed area 41 A. Thereafter, particularly if the upper surface of the first electrical interconnect 45 is not coplanar with the upper surface of the encapsulant 43, the upper protruding portions of the first electrical interconnect 45 can be removed. The removal process of these upper portions of the first electrical interconnect 45 can be performed by e.g. grinding or laser.

[0054] According to embodiments of the semiconductor device 30 or 40, two or more recessed areas are provided on the die carrier, wherein similar or different semiconductor dies can be arranged in the recessed areas. In case of different semiconductor dies, different encapsulants can also be employed for embedding the semiconductor dies according to different requirements with respect to e.g. the voltage range of the semiconductor dies.

[0055] Figures 4B-4D A first step of manufacturing the semiconductor device 40 is shown. Figure 4B A perspective view onto the single die carrier 41 is shown, which comprises a recessed area 41 A. A semiconductor die 42 is to be inserted into the recessed area 41 A of the die carrier 41 and is to be connected to the bottom face of the recessed area 41 A by e.g. diffusion welding. Figure 4C A perspective view after the first electrical interconnect 45 has been placed onto the contact pad 42A of the semiconductor die 42 by e.g. one of the above described methods is shown. The first electrical interconnect 45 can be applied such that its upper surface is coplanar with the upper surface of the die carrier 41. Figure 4D A perspective view after the encapsulant 43 has been filled into the recessed area 41 A is shown. The encapsulant 43 can be filled into the recessed area 41 A such that its upper surface is coplanar with the upper surface of the die carrier 41 and the upper surface of the first electrical interconnect 45 is exposed to the outside.

[0056] The die carrier 41, the semiconductor die 42, the contact pad 42A, the encapsulant 43, the insulating layer 44, the first electrical interconnect 45 and the metallization layer 46 of the semiconductor device 40 can have the same properties as the die carrier 11, the semiconductor die 12, the contact pad 12A, the encapsulant 13, the insulating layer 14, the electrical interconnect 15 and the metallization layer 16 of the semiconductor device 10.

[0057] Figure 5 A schematic cross-sectional side view representation of an exemplary semiconductor device according to the first aspect is shown.

[0058] Figure 5A semiconductor device 50 is shown, which comprises a leadframe-based die carrier 51, a semiconductor die 52 arranged on a first upper main face of the die carrier 51, the semiconductor die 52 comprising one or more contact pads on its main face, an encapsulant 53 covering at least a portion of the main faces of the semiconductor die 52 and the die carrier 51. The semiconductor device 50 further comprises an insulating layer 54 covering the encapsulant 53 as well as a portion of the first upper main face and a second lower main face of the die carrier 51, and a plurality of first electrical interconnects 55, each of the plurality of first electrical interconnects 55 being connected with one of the contact pads of the semiconductor die 52 and extending through the encapsulant 53. The semiconductor device 50 further comprises a plurality of second electrical interconnects 57, each of the plurality of second electrical interconnects 57 being connected with one of the first electrical interconnects 55 at its lower end. At its upper end, the second electrical interconnect 57 is connected with a metal trace 56. The die carrier 51 is also connected with one of the metal traces 56 via the second electrical interconnect 57. Here again, alternatively, the die carrier 51 can be contacted via electrical interconnects protruding through a backside portion of the insulating layer 54.

[0059] It should be mentioned that the first and second electrical interconnects 55 and 57 can be manufactured by forming vias into the encapsulant 53 and the insulating layer 54 by laser structuring, followed by electro deposition, or chemical plating, or sputtering or printing of metal, in particular copper, into the vias. Furthermore, the electrical interconnects 55 and 57 need not be arranged on top of each other. As Figure 5 As shown in the embodiments of Figs. 1 and 2, there can be a lateral displacement between them and the redistribution layer comprising metal lines laterally connecting the ends of the electrical interconnects 55 and 57 with each other.

[0060] The die carrier 51, the semiconductor die 52, the encapsulant 53, the insulating layer 54, the electrical interconnects 55 and the metallization layer 56 of the semiconductor device 50 can have the same properties as the die carrier 11, the semiconductor die 12, the contact pads 12A, the encapsulant 13, the insulating layer 14, the electrical interconnects 15 and the metallization layer 16 of the semiconductor device 10.

[0061] One great advantage of the present disclosure is that in all of the above embodiments, the electrical interconnects or at least a portion of the electrical interconnects can be manufactured by chemical plating, in particular by electroplating or electroplating, or sputtering or printing. Interconnects formed in this way are known to be superior to all other types of electrical contacts. Thus, semiconductor devices of high reliability and robustness can be manufactured.

[0062] Figure 6 A flow chart of an exemplary method for manufacturing a semiconductor device is shown, in which method the electrical interconnects are manufactured after the application of the encapsulant and the insulating layer.

[0063] Figure 6Method 60 includes providing a die carrier (61), disposing a semiconductor die on the main surface of the die carrier, the semiconductor die including one or more contact pads (62) on its main surface, applying an encapsulant at least partially to at least a portion of the semiconductor die and the main surface of the die carrier (63), applying an insulating layer to the encapsulant (64), and fabricating an electrical interconnect (65) by forming openings in the encapsulant and the insulating layer and filling the openings with a conductive material.

[0064] use Figure 6 Method 60, for example, can manufacture the semiconductor device shown in Figures 1 to 3. In the case of the semiconductor device 30 shown in Figure 3, a die carrier 31 including a recessed region 31A is provided.

[0065] Figure 7 A flowchart of an exemplary method for manufacturing a semiconductor device is shown, in which electrical interconnects are fabricated before an encapsulating agent and an insulating layer are applied.

[0066] Figure 7 Method 70 includes providing a die carrier (71), disposing a semiconductor die on the main surface of the die carrier, the semiconductor die including one or more contact pads (72) on its main surface, depositing a first electrical interconnect (73) on the one or more contact pads of the semiconductor die, applying an encapsulant at least partially to at least a portion of the semiconductor die and the main surface of the die carrier (74), applying an insulating layer to the encapsulant (75), and fabricating a second electrical interconnect (76) by forming an opening in the insulating layer and filling the opening with a conductive material.

[0067] use Figure 7 Method 70, for example, can be used to manufacture the semiconductor device shown in FIG4. In the case of the semiconductor device 40 shown in FIG4, a die carrier 41 including a recessed region 41A is provided. A first electrical interconnect is shown by reference numeral 45, and a second electrical interconnect is shown by reference numeral 47.

[0068] According to embodiments of methods 60 and 70, an opening is formed into both the encapsulant and the insulating layer by laser drilling (method 60) or only into the insulating layer (method 70).

[0069] According to an embodiment of method 70, the electrical interconnect is manufactured by one of the following methods: pre-fabricating a metal block or wire and then applying the block or wire to the one or more contact pads; or by cold spraying.

[0070] According to embodiments of the method 60 and 70, the functionality of the semiconductor die can be tested. In particular, the semiconductor die can be tested prior to the application of the encapsulant and the insulating layer. However, it is also possible to test the semiconductor die after the application of the encapsulant and the insulating layer, in particular in case the electrical interconnects extend through the upper surface of the insulating layer.

[0071] Further embodiments of the method 60 can be formed by adding aspects or features described above in connection with the semiconductor device according to the first aspect.

[0072] In addition, although a particular feature or aspect of an embodiment of the disclosure can have been disclosed with respect to only one of several implementations, such feature or aspect can be combined with one or more other features or aspects of the other implementations as can be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." Moreover, unless otherwise specified, all constraints cited herein are meant to be construed in a manner similar to that of a specification patent filed in the United States. Furthermore, it should be understood that the embodiments of the disclosure can be implemented in software and / or hardware. The embodiments of this disclosure can be implemented in an operating environment of distributed computing and / or networking components and / or processes that communicate over a network. Moreover, the term "exemplary" is used herein merely for the purpose of providing an example, and is not intended to convey an indication that a specific embodiment is preferred or superior over other embodiments. It should also be understood that, for simplicity and clarity, the drawings figuratively depict the described features on a relatively large scale, and that the dimensions of the various features can be exaggerated relative to other features for clarity.

[0073] While specific embodiments have been shown and described in detail to illustrate the principles of the present disclosure, it will be understood by those of ordinary skill in the art that various alternatives and / or equivalents can be used without departing from the scope of the present disclosure. The present application is intended to cover any and all alternatives, modifications, combinations, sub-combinations, and variations falling within the scope of the disclosure. Thus, the disclosure is not limited to the exact details shown and described, for purposes of illustration.

Claims

1. A semiconductor device, comprising: - A die carrier, the die carrier comprising a first upper main surface, a second lower main surface opposite to the first upper main surface, and a side surface between the first upper main surface and the second lower main surface; - A semiconductor die, the semiconductor die being disposed on the die carrier, the semiconductor die including one or more contact pads on its main surface; - An encapsulating agent that at least partially covers at least a portion of the first upper main surface of the semiconductor die and the die carrier. - An insulating layer covering the encapsulant, wherein the insulating layer covers the second lower main surface and the side surface of the die carrier, and wherein the insulating layer is made of a thermally conductive material to allow heat dissipation to the bottom, and wherein the thermal conductivity of the insulating layer covering the second lower main surface of the die carrier is higher than the thermal conductivity of the insulating layer covering the encapsulant, and wherein the encapsulant is located only in the edge region of the upper main surface of the semiconductor die and on the side surface of the semiconductor die, and not in the central region of the upper main surface of the semiconductor die, and the central region of the upper main surface of the semiconductor die is filled by the insulating layer; and - One or more electrical interconnects, each of which is connected to one of the contact pads of the semiconductor die and extends through the encapsulant.

2. The semiconductor device according to claim 1, wherein... The core carrier includes a recessed portion, wherein... The semiconductor die is disposed in the recessed portion.

3. The semiconductor device according to claim 2, wherein The encapsulant is disposed in the recessed portion such that the upper surface of the encapsulant is substantially coplanar with the first upper main surface of the core carrier.

4. The semiconductor device according to any one of the preceding claims, wherein The insulating layer comprises a laminated material.

5. The semiconductor device according to any one of claims 1-3, wherein The one or more electrical interconnects also extend through the insulating layer.

6. The semiconductor device according to any one of claims 1-3, wherein Two or more semiconductor dies are disposed on the die carrier.

7. The semiconductor device according to any one of claims 1-3, wherein The semiconductor die includes one or more of MOSFET die, IGBT die, SiC-MOS die, Cool-MOS die or S-FET die.

8. The semiconductor device according to any one of claims 1-3, wherein The die carrier is one or more of the following: part of the lead frame, direct copper bonding, active metal brazing, or isolation metal substrate.

9. A method for manufacturing a semiconductor device, the method comprising: - Provide a die carrier, wherein the die carrier includes a first upper main surface, a second lower main surface opposite to the first upper main surface, and a side surface between the first upper main surface and the second lower main surface; - A semiconductor die is disposed on the first upper main surface of the die carrier, the semiconductor die including one or more contact pads on its upper main surface; - Apply an encapsulating agent at least partially to at least a portion of the first upper main surface of the semiconductor die and the die carrier; - An insulating layer is applied to the encapsulant, wherein the insulating layer covers the second lower main surface and the side surface of the die carrier, and wherein the insulating layer is made of a thermally conductive material to allow heat dissipation to the bottom, and wherein the thermal conductivity of the insulating layer covering the second lower main surface of the die carrier is higher than the thermal conductivity of the insulating layer covering the encapsulant, and wherein the encapsulant is located only in the edge region of the upper main surface of the semiconductor die and on the side surface of the semiconductor die, and not in the central region of the upper main surface of the semiconductor die, and the central region of the upper main surface of the semiconductor die is filled by the insulating layer; and Electrical interconnects are fabricated by forming openings in the encapsulant and the insulating layer and filling the openings with conductive material.

10. A method for manufacturing a semiconductor device, the method comprising: - Provide a die carrier, wherein the die carrier includes a first upper main surface, a second lower main surface opposite to the first upper main surface, and a side surface between the first upper main surface and the second lower main surface; - A semiconductor die is disposed on the first upper main surface of the die carrier, the semiconductor die including one or more contact pads on its upper main surface; - A first electrical interconnect is provided on one or more contact pads of the semiconductor die; - Apply an encapsulating agent at least partially to at least a portion of the first upper main surface of the semiconductor die and the die carrier; - An insulating layer is applied to the encapsulant, wherein the insulating layer covers the second lower main surface and the side surface of the die carrier, and wherein the insulating layer is made of a thermally conductive material to allow heat dissipation to the bottom, and wherein the thermal conductivity of the insulating layer covering the second lower main surface of the die carrier is higher than the thermal conductivity of the insulating layer covering the encapsulant, and wherein the encapsulant is located only in the edge region of the upper main surface of the semiconductor die and on the side surface of the semiconductor die, and not in the central region of the upper main surface of the semiconductor die, and the central region of the upper main surface of the semiconductor die is filled by the insulating layer; and - A second electrical interconnect is fabricated by forming an opening in the insulating layer and filling the opening with a conductive material.

11. The method according to claim 9 or 10, wherein The opening is formed by laser drilling.

12. The method of claim 10, wherein The electrical interconnect is manufactured by one of the following methods: prefabricating a metal block or wire and then applying the metal block or wire to the one or more contact pads; or by cold spraying.

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