Semiconductor device packaging and manufacturing methods

Abstract

This disclosure provides a semiconductor device package including a carrier, an emitter, a first constructing circuit, and a first package body. The carrier has a first surface, a second surface opposite to the first surface, and side surfaces extending from the first surface to the second surface. The emitter is disposed on the first surface of the carrier. The first constructing circuit is disposed on the second surface of the carrier. The first package body encloses the side surfaces of the carrier.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package and a method of manufacturing the same, and more particularly, to a semiconductor device package including an antenna and a method of manufacturing the same. Background Technology

[0002] For example, wireless communication devices such as mobile phones typically include antennas for transmitting and receiving radio frequency (RF) signals. Similarly, wireless communication devices include antennas and communication modules, each mounted on different parts of a circuit board. Following a similar approach, the antenna and communication module are manufactured separately and then electrically connected together after being placed on the circuit board. Therefore, these two components may incur separate manufacturing costs. Furthermore, it may be difficult to reduce the size of the wireless communication device to achieve a suitable compact product design. To reduce cost and package size, the Antenna-in-Package (AiP) method is provided. Generally, organic substrates are commonly used in AiP systems. However, due to the process limitations of organic substrates, it is difficult to achieve fine pitch (less than 15 / 15 μm), and the thickness of organic substrates is relatively thick, which hinders the miniaturization of AiP systems. Summary of the Invention

[0003] According to some embodiments of this disclosure, a semiconductor device package includes a carrier, an emitter, a first constructing circuit, and a first package body. The carrier has a first surface, a second surface opposite to the first surface, and side surfaces extending from the first surface to the second surface. The emitter is disposed on the first surface of the carrier. The first constructing circuit is disposed on the second surface of the carrier. The first package body encloses the side surfaces of the carrier.

[0004] According to some embodiments of this disclosure, a semiconductor device package includes a stand-off layer, an emitter element, and a first construct circuit. The stand-off layer has a first surface, a second surface opposite to the first surface, and a side surface extending from the first surface to the second surface. The emitter element is disposed on the first surface of the stand-off layer. The first construct circuit is disposed on the second surface of the stand-off layer. The side surface of the first construct circuit and the side surface of the stand-off layer are not coplanar.

[0005] According to some embodiments of this disclosure, a method of manufacturing a semiconductor device package includes (a) providing a plurality of emitter devices spaced apart from each other; (b) forming a first package to cover the side surfaces of the emitter devices; and (c) forming a first construction circuit on the emitter devices. Attached Figure Description

[0006] Figure 1AA cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0007] Figure 1B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0008] Figure 2A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0009] Figure 2B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0010] Figure 2C A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0011] Figure 2D A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0012] Figure 3 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0013] Figure 4 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0014] Figure 5 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0015] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H and Figure 6I This invention describes a semiconductor manufacturing method according to some embodiments of the present disclosure.

[0016] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F This invention describes a semiconductor manufacturing method according to some embodiments of the present disclosure.

[0017] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F This invention describes a semiconductor manufacturing method according to some embodiments of the present disclosure.

[0018] Common reference numerals are used throughout the drawings and detailed embodiments to indicate the same or similar components. This disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0019] Figure 1A A cross-sectional view of a semiconductor device package 1A according to some embodiments of the present disclosure is shown. The semiconductor device package 1A includes a carrier 10, circuit layers 11, 13, 14, interconnect structures 12a, 12b, electronic components 15, electrical contacts 16, and package bodies 17, 18, and 19.

[0020] In some embodiments, the carrier 10 (also referred to as a support layer) may be or comprise a glass substrate. In some embodiments, the carrier 10 may be or comprise a transmitting device on which one or more transmitting components (e.g., antennas, light-emitting devices, sensors, etc.) are disposed. The carrier 10 may comprise conductive pads, traces, and interconnects (e.g., vias). In some embodiments, the carrier 10 may comprise a transparent material. In some embodiments, the carrier 10 may comprise an opaque material. Compared to organic substrates, controlling the thickness of a glass carrier is easier, which can contribute to the miniaturization of the semiconductor device package 1. The carrier 10 comprises a material having a dielectric constant (Dk) of less than about 5. The carrier 10 comprises a material having a Dk of less than about 3. The carrier 10 comprises a material having a loss tangent or dissipation factor (Df) of less than about 0.005. The carrier 10 comprises a material having a loss tangent or Df of less than about 0.003. In some embodiments, the thickness of the carrier 10 is about 400 μm. In some embodiments, the coefficient of thermal expansion (CTE) of the carrier 10 is in the range of about 0.5 to about 13. In some embodiments, the CTE of the carrier 10 is in the range of about 3.6 to about 8.5.

[0021] The carrier 10 has a surface 101, a surface 102 opposite to surface 101, and a side surface 103 extending between surface 101 and surface 102. A conductive layer 10p is disposed on surface 102 of the carrier 10. In some embodiments, the conductive layer 10p defines a patterned antenna, such as a directional antenna, an omnidirectional antenna, or an antenna array. For example, the conductive layer 10p defines a patch antenna. The conductive layer 10p is or contains a conductive material, such as a metal or metal alloy. Examples of conductive materials include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or combinations of two or more thereof. In some embodiments, the conductive layer 10p may be replaced by one or more light-emitting devices or sensors.

[0022] The circuit layer 11 (or the building block circuit) has a surface 111 facing away from the carrier 10, a surface 112 opposite to the surface 111, and a side surface 113 extending between the surfaces 111 and 112. The carrier 10 is disposed on the surface 112 of the circuit layer 11. The carrier 10 is connected to the surface 112 of the circuit layer 11. The carrier 10 is in contact with the surface 112 of the circuit layer 11. In some embodiments, the side surface 113 of the circuit layer 11 and the side surface 103 of the carrier 10 are not coplanar or discontinuous. For example, the side surface 103 of the carrier 10 is recessed from the side surface 113 of the circuit layer 11. For example, the width of the carrier 10 is smaller than the width of the circuit layer 11.

[0023] Circuit layer 11 includes one or more conductive layers (e.g., redistribution layers, RDLs) 11c and one or more dielectric layers 11d. A portion of the conductive layer 11c is covered or encapsulated by the dielectric layer 11d, while another portion of the conductive layer 11c is exposed from the dielectric layer 11d to provide electrical connectivity. In some embodiments, the surface of the conductive layer 11c facing the carrier 10 and exposed from the dielectric layer 11d contacts the surface 101 of the carrier 10. In some embodiments, the conductive layer 11c may be or include one or more antenna radiation patterns, light-emitting devices, sensors, etc.

[0024] In some embodiments, dielectric layer 11d may comprise prepreg composite fibers (e.g., a prepreg), borosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass (USG), any combination of two or more of these, etc. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating several prepreg materials / sheets. In some embodiments, depending on design specifications, any number of conductive layers 11c may be present. In some embodiments, conductive layer 11c is formed of Au, Ag, Cu, Pt, Pd, or alloys thereof, or comprises Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0025] Encapsulation 17 is disposed on surface 112 of circuit layer 11. Encapsulation 17 covers carrier 10 and conductive layer 10p. Encapsulation 17 covers surface 102 and side surface 103 of carrier 10. In some embodiments, encapsulation 17 has side surface 173 that is substantially coplanar with side surface 113 of circuit layer 11. Side surface 103 of carrier 10 is recessed from side surface 173 of encapsulation 17. For example, there is a distance between side surface 103 of carrier 10 and side surface 173 of encapsulation 17. In some embodiments, encapsulation 17 comprises epoxy resin having a filler, molding material (e.g., epoxy molding material or other molding material), polyimide, phenolic compound or material, material containing silicone dispersed therein, or combinations thereof.

[0026] One or more interconnect structures 12a (e.g., conductive pillars or conductive elements) are disposed on the surface 111 of the circuit layer 11. The interconnect structures 12a are electrically connected to the circuit layer 11 (i.e., electrically connected to the conductive layer 11c exposed from the dielectric layer 11d). In some embodiments, the interconnect structures 12a define an antenna structure. The interconnect structures 12a are or comprise a conductive material such as a metal or metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0027] Package 18 is disposed on surface 111 of circuit layer 11. Package 18 covers interconnect structure 12a. In some embodiments, package 18 has side surface 183 that is substantially coplanar with side surface 113 of circuit layer 11. In some embodiments, package 18 comprises epoxy resin having a filler, molding material (e.g., epoxy molding material or other molding material), polyimide, phenolic compound or material, material containing silicone dispersed therein, or combinations thereof.

[0028] A circuit layer 13 (or a circuitry layer) is disposed on a package 18. The circuit layer 13 has one or more dielectric layers 13d and one or more conductive layers 13c. In some embodiments, the dielectric layer 13d may contain the same material as dielectric layer 11d. Alternatively, the dielectric layer 13d and dielectric layer 11d may contain different materials. The conductive layers 13c are electrically connected to the interconnect structure 12a. In some embodiments, any number of conductive layers 13c may be present, depending on design specifications.

[0029] One or more interconnect structures 12b (e.g., conductive pillars or conductive elements) are disposed on the surface of circuit layer 13 facing away from circuit layer 11. Interconnect structures 12b are electrically connected to circuit layer 13. Interconnect structures 12b are or comprise conductive materials such as metals or metal alloys. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, or alloys thereof.

[0030] Electronic component 15 is disposed on the surface of circuit layer 13 facing away from circuit layer 11. Electronic component 15 may be an active electronic component, such as an integrated circuit (IC) chip or a die. The active surface of electronic component 15 faces circuit layer 13. Electronic component 15 is electrically connected to circuit layer 13 (e.g., electrically connected to conductive layer 13c) via electrical contacts (e.g., solder balls), and the electrical connection may be achieved, for example, using flip-chip technology.

[0031] Package 19 is disposed on the surface of circuit layer 13 opposite to circuit layer 11. Package 19 covers interconnect structure 12b and electronic component 15. In some embodiments, package 19 has sides that are substantially coplanar with the sides of circuit layer 13. In some embodiments, package 19 comprises epoxy resin with filler, molding material (e.g., epoxy molding material or other molding material), polyimide, phenolic compound or material, material containing silicone dispersed therein, or combinations thereof.

[0032] A circuit layer 14 (or a circuitry layer) is disposed on a package 19. The circuit layer 14 has one or more dielectric layers 14d and one or more conductive layers 14c. In some embodiments, the dielectric layer 14d may contain the same material as dielectric layer 11d. Alternatively, the dielectric layer 14d and dielectric layer 11d may contain different materials. The conductive layers 14c are electrically connected to the interconnect structure 12b. In some embodiments, depending on design specifications, any number of conductive layers 14c may be present.

[0033] Electrical contact 16 is disposed on conductive layer 14c exposed from dielectric layer 14d. In some embodiments, electrical contact 16 may comprise solder or other suitable material.

[0034] In some embodiments, the side 103 of the carrier 10 may be coplanar with the side 113 of the circuit layer 11. For example, the side 103 of the carrier 10 is exposed from the package 17. Such a structure can be formed by the following steps: (i) providing a glass wafer; (ii) forming circuit layers 11, 13, 14, interconnect structures 12a, 12b, and packages 17, 18, 19 and electronic components 15 on the glass wafer; and (iii) performing a single-layer split through the circuit layers 11, 13, 14, packages 17, 18, 19 and the carrier wafer. To meet the performance requirements of the antenna structure, the glass wafer should be selected from materials with a relatively low Dk (e.g., less than 5). However, a glass wafer with a relatively low Dk will also have a relatively low CTE (e.g., less than 13). Warpage problems will occur due to the CTE mismatch between the glass wafer and the package 17 (e.g., the package typically has a CTE greater than 20). As the size of the glass wafer increases, the warpage problem becomes more severe, which can cause the glass wafer to crack or be damaged.

[0035] According to such Figure 1A In the embodiment shown, the side 103 of the carrier 10 is recessed from the side 111 of the circuit layer 11. This type of structure can be formed by the following steps (the operation is described in detail below): (i) performing a single-division process on the glass wafer to divide the glass wafer into multiple glass carriers (e.g., as shown below). Figure 1A(i) a carrier 10 shown; (ii) a glass carrier attached to the release film (separating the glass carriers from each other); and (iii) circuit layers 11, 13, 14, interconnect structures 12a, 12b, and packages 17, 18, 19 and electronic components 15 formed on the glass carriers. Since the size of the segmented glass carriers is much smaller than the size of the glass wafer, warpage problems are significantly mitigated. Furthermore, since it is not necessary to select a material for the carrier 10 with a higher CTE close to that of the package 17, a material with a lower CTE (and also a lower Dk) can be selected as the carrier 10. This will enhance the performance of the antenna structure of the semiconductor device package 1A. In addition, the thickness of the carrier 10 can be reduced, which will facilitate the miniaturization of the semiconductor device package 1A.

[0036] Figure 1B This illustration shows a cross-sectional view of a semiconductor device package 1B according to some embodiments of the present disclosure. The semiconductor device package 1B is similar to... Figure 1A The semiconductor device package 1A shown in the figure is described below, and the differences therein are described.

[0037] Electronic component 15 is disposed on the surface of circuit layer 13 facing circuit layer 14. Electronic component 15 has a back surface that is bonded or attached to the surface of circuit layer 13 by an adhesive layer 15a (e.g., DAF). Electronic component 15 has an active surface facing circuit layer 14 and electrically connected to circuit layer 14 by an interconnection structure 15c (e.g., conductive pillar).

[0038] Figure 2A This illustration shows a cross-sectional view of a semiconductor device package 2A according to some embodiments of the present disclosure. The semiconductor device package 2A is similar to... Figure 1A The semiconductor device package 1A shown in the figure is described below, and the differences therein are described.

[0039] Side 113 of circuit layer 11 is recessed from side 173 of package 17 or side 183 of package 18. For example, there is a gap between side 113 of circuit layer 11 and side 183 of package 18. For example, side 113 of circuit layer 11 is covered by package 18. For example, the width of circuit layer 11 is smaller than the width of package 18. Package 18 can be directly contacted.

[0040] In some embodiments, the side surface 113 of the circuit layer 11 may be connected to, for example, Figure 2A The sides 103 of the carrier 10 shown are substantially coplanar. For example, the width of the circuit layer 11 is substantially the same as the width of the carrier 10. In some embodiments, such as Figure 2B As shown, the side surface 113 of the circuit layer 11 is not coplanar with the side surface 103 of the carrier 10 and the side surface 183 of the package 18. Figure 2BThis illustrates a cross-sectional view of semiconductor device package 2B. For example, the width of circuit layer 11 is greater than the width of carrier 10 but less than the width of package 18.

[0041] Figure 2C A cross-sectional view of a semiconductor device package 2C according to some embodiments of the present disclosure is shown. The semiconductor device package 2C is similar to... Figure 2A The semiconductor device package 2A shown in the figure is described below, and the differences therebetween are described below.

[0042] Electronic component 15 is disposed on the surface of circuit layer 13 facing circuit layer 14. Electronic component 15 has a back surface that is bonded or attached to the surface of circuit layer 13 by an adhesive layer 15a (e.g., DAF). Electronic component 15 has an active surface facing circuit layer 14 and electrically connected to circuit layer 14 by an interconnection structure 15c (e.g., conductive pillar).

[0043] Figure 2D A cross-sectional view of a semiconductor device package 2D according to some embodiments of the present disclosure is shown. The semiconductor device package 2D is similar to... Figure 2B The semiconductor device package 2B shown in the figure is described below, and the differences between them are described below.

[0044] Electronic component 15 is disposed on the surface of circuit layer 13 facing circuit layer 14. Electronic component 15 has a back surface that is bonded or attached to the surface of circuit layer 13 by an adhesive layer 15a (e.g., DAF). Electronic component 15 has an active surface facing circuit layer 14 and electrically connected to circuit layer 14 by an interconnection structure 15c (e.g., conductive pillar).

[0045] Figure 3 This illustration shows a cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure. The semiconductor device package 3 is similar to... Figure 1A The semiconductor device package 1A shown in the figure is described below, and the differences therein are described.

[0046] Semiconductor device package 3 may include two parts 3A and 3B. Part 3A includes a circuit layer 13a, a package body 19, electronic components 15, a circuit layer 14, and an interconnect structure 12b, wherein the circuit layer 13a includes one or more dielectric layers 13d1 and one or more conductive layers 13c1. Part 3B includes a circuit layer 13b, packages 17 and 18, a circuit layer 11, and a carrier 10, wherein the circuit layer 13b includes one or more dielectric layers 13d2 and one or more conductive layers 13c2. Parts 3A and 3B may be manufactured separately and then connected to each other by electrical contacts 31s (e.g., solder balls). This increases the yield of semiconductor device package 3. In some embodiments, underfill 31h may be disposed between parts 3A and 3B to cover the electrical contacts 31s. In some embodiments, the width of part 3A is the same as the width of part 3B. Alternatively, depending on design specifications, the width of part 3A may be greater than or less than the width of part 3B.

[0047] Figure 4 This illustration shows a cross-sectional view of a semiconductor device package 4 according to some embodiments of the present disclosure. The semiconductor device package 4 is similar to... Figure 3 The semiconductor device package 3 shown is described below, and the differences therebetween are described below.

[0048] Electronic component 15 is disposed on the surface of circuit layer 13a facing circuit layer 14. Electronic component 15 has a back surface that is bonded or attached to the surface of circuit layer 13a by an adhesive layer 15a (e.g., DAF). Electronic component 15 has an active surface facing circuit layer 14 and electrically connected to circuit layer 14 by an interconnection structure 15c (e.g., conductive pillar).

[0049] Figure 5 A cross-sectional view of a semiconductor device package 5 according to some embodiments of the present disclosure is shown. The semiconductor device package 5 is similar to... Figure 3 The semiconductor device package 3 shown is described below, and the differences therebetween are described below.

[0050] Electronic component 15 is disposed on the surface of circuit layer 14 facing circuit layer 13a. Electronic component 15 has a back surface that is bonded or attached to the surface of circuit layer 14 via adhesive layer 15a (e.g., DAF). Electronic component 15 has an active surface facing circuit layer 13a and electrically connected to circuit layer 13a via interconnection structure 15c (e.g., conductive pillar).

[0051] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H and Figure 6IThis invention describes a semiconductor manufacturing method according to some embodiments of the present disclosure. In some embodiments, Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H and Figure 6I The method described in the text can be used to manufacture Figure 1A Semiconductor device package 1A.

[0052] refer to Figure 6A A carrier 10' is provided. The carrier 10' can be a wafer type, a panel type, or a strip type. In some embodiments, the carrier 10' can be a glass wafer. A conductive layer 10p is formed on the carrier 10'. In some embodiments, the conductive layer 10p can be an antenna radiation pattern, a light-emitting device, or a sensor.

[0053] refer to Figure 6B A single-splitting operation is performed to divide the carrier 10' into a plurality of carriers containing the carrier 10. The carriers containing the carrier 10 are placed on the release membrane 69. The carriers are separated from each other. For example, there is a gap or distance between any two adjacent carriers. A remodeling process is then performed. In some embodiments, prior to the single-splitting operation, a thinning operation may be performed to reduce the thickness of the carrier 10' by, for example, grinding or any other suitable process.

[0054] refer to Figure 6C The package 17 is formed to release the carrier and conductive layer 10p covering the carrier 10 on the membrane 69. In some embodiments, the package 17 is formed by, for example, transfer molding, compression or any other suitable technique.

[0055] refer to Figure 6D The release film 69 is removed to expose the surface of the carrier 10 facing away from the package 17. A circuit layer 11 comprising one or more conductive layers 11c and one or more dielectric layers 11d is formed on the exposed surface of the carrier containing the carrier 10. The dielectric layer 11d is formed by, for example (but not limited to), photolithography. An interconnect structure 12a is then formed on the circuit layer 11 to be electrically connected to the circuit layer 11. In some embodiments, the interconnect structure 12a may be formed by, for example (but not limited to), plating.

[0056] refer to Figure 6EA package 18 is formed on the circuit layer 11 to cover the interconnect layer 12a. In some embodiments, the package 18 may be formed to completely cover the interconnect structure 12a. A portion of the package 18 is removed by, for example, grinding or any other suitable technique to expose the top portion of the interconnect structure 12a for electrical connection. In some embodiments, the package 18 is formed by, for example, transfer molding, compression, or any other suitable technique.

[0057] refer to Figure 6F A circuit layer 13, comprising one or more conductive layers 13c and one or more dielectric layers 13d, is formed on a package 18 and electrically connected to an interconnect structure 12a exposed from the package 18. An interconnect structure 12b is formed on the circuit layer 13 to be electrically connected to the circuit layer 13. An electronic component 15 is then disposed on the circuit layer 13 and electrically connected to the circuit layer 13. In some embodiments, the electronic component 15 may be connected to the circuit layer 13 via flip chip or any other suitable process.

[0058] refer to Figure 6G Package 19 is formed on circuit layer 13 to cover interconnect structure 12b and electronic component 15. In some embodiments, package 19 may be formed to completely cover interconnect structure 12b and electronic component 15. A portion of package 19 is removed by, for example, grinding or any other suitable technique to expose the top portion of interconnect structure 12b for electrical connection. In some embodiments, package 19 is formed by, for example, transfer molding, compression or any other suitable technique.

[0059] refer to Figure 6H A circuit layer 14, comprising one or more conductive layers 14c and one or more dielectric layers 14d, is formed on the package 19 and electrically connected to an interconnect structure 12b exposed from the package 19. An electrical contact 16 is then disposed on the conductive layer 14c exposed from the dielectric layer 14d.

[0060] refer to Figure 6I It can execute a single split to include, for example, Figure 1A The individual semiconductor package devices of the semiconductor packaging apparatus 1A shown are separated. That is, individual separation is performed through circuit layers 11, 13, 14 and packages 17, 18 and 19. This individual separation can be performed, for example, using a dicing machine, a laser or other suitable cutting technique.

[0061] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F This invention describes a semiconductor manufacturing method according to some embodiments of the present disclosure. In some embodiments, Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F The method described in the text can be used to manufacture Figure 2A The semiconductor device package 2A is available in [the context of the semiconductor device package]. Figure 6C After the operation in the middle Figure 7A The operations within. For example... Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F The operation shown is similar to that shown in the image. Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H and Figure 6I The operations shown are described below, and the differences between them are described below.

[0062] refer to Figure 7A Multiple circuit layers 11, each comprising one or more conductive layers 11c and one or more dielectric layers 11d, are formed on the exposed surface of the carrier containing the carrier 10. Each of the circuit layers 11 is formed on a corresponding carrier containing the carrier 10. The circuit layers 11 are spaced apart from each other. For example, there is a gap or distance between any two adjacent circuit layers 11. In some embodiments, the width of the circuit layer 11 is substantially the same as the width of the corresponding carrier. Alternatively, the width of the circuit layer 11 is greater than the width of the corresponding carrier.

[0063] refer to Figure 7B Package 18 is formed on circuit layer 11 and package 17 to cover interconnect layer 12a. Package 18 is in contact with the side of circuit layer 11 and package 17.

[0064] According to such Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F In the embodiment shown, circuit layers 11 are formed, which are spaced apart from each other on the corresponding carrier, and the circuit layers 11 are not located at the cleavage line. Therefore, it is possible to achieve the following: Figure 7F The single-part operation shown further alleviates the warping problem.

[0065] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F This invention describes a semiconductor manufacturing method according to some embodiments of the present disclosure. Figure 8A Operations can be performed within the system. Figure 6D This will be performed after the operations in the previous section. For example... Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F The operation shown is similar to that of... Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H and Figure 6I The operations shown are described below, and the differences between them are described below.

[0066] refer to Figure 8A After forming the circuit layer 11 and the interconnect structure 12a, a dicing operation (e.g., a half-dicing operation) is performed to form an opening 80h, dividing the circuit layer 11 into a plurality of individual circuit layers. The divided circuit layers 11 are separated from each other. For example, there is a gap or distance between any two adjacent circuit layers 11. In some embodiments, the width of the circuit layer 11 is substantially the same as the width of the corresponding carrier. Alternatively, the width of the circuit layer 11 is greater than the width of the corresponding carrier.

[0067] A portion of the package 17 is also removed during the cutting operation. For example, the opening 80h extends into the package 17 without penetrating it.

[0068] refer to Figure 8B Package 18 is formed on circuit layer 11 and within opening 80h to cover interconnect layer 12a. Package 18 contacts the side of circuit layer 11 and package 17. Package 18 contacts the bottom side and sidewall of opening 80h.

[0069] In the formation of such Figure 8F Following the single-disassembly operation of the semiconductor device package 8 described herein, package 17 may define a recess or stepped structure (which is part of opening 80h), and package 18 extends within said recess. For example, package 17 may include a first top surface substantially coplanar with the top surface of carrier 10 and a second surface in contact with package 18. For example, package 17 may include a first side surface in contact with package 18 and a second side surface exposed from package 18. In some embodiments, the second side surface of package 17 is substantially coplanar with the side surface of package 18.

[0070] As used herein, the terms “substantially,” “generally,” “approximately,” and “about” are used to indicate and explain small variations. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, the thickness of a film or layer being “substantially uniform” may refer to a standard deviation of the average thickness of the film or layer less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces located within a few micrometers along the same plane, for example, within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm. If the angle between two surfaces or components is, for example, 90° ± 10°, such as ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°, then the two surfaces or components can be considered "substantially perpendicular." When used in conjunction with an event or situation, the terms "substantially," "basically," "approximately," and "about" can refer to examples where the event or situation occurs precisely, and examples where the event or situation occurs very approximately.

[0071] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators. In the description of some embodiments, a component provided “on” or “above” another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0072] As used herein, the terms “conductivity,” “electrical conductivity,” and “conductivity” refer to the ability to conduct electric current. Conductive materials typically indicate those that exhibit very little or zero resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than about 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of a material can sometimes change with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0073] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity purposes and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0074] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between process reproductions in this disclosure and actual equipment due to variations in manufacturing processes, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor device package comprising: The first part includes: The carrier is a transparent glass carrier and has a bottom surface, a top surface opposite to the bottom surface, and a side surface extending from the bottom surface to the top surface; A transmitting element, which is disposed on the bottom surface of the carrier; A first construction circuit is disposed on the top surface of the carrier, wherein the first construction circuit includes a conductive layer, the conductive layer including at least one of an antenna radiation pattern, a light-emitting device, and a sensor; and A first package encapsulates and contacts the transmitting element, wherein the side of the carrier is recessed from the side of the first building circuit. Part Two includes: A first circuit layer is disposed on the first portion; An electronic component having an active surface facing the first circuit layer, the electronic component being disposed on the first circuit layer and the active surface being electrically connected to the first circuit layer; and A third package encapsulates and contacts the electronic components; and An electrical contact is disposed between the first portion and the second portion, wherein the second portion and the first portion are electrically connected to each other via the electrical contact.

2. The semiconductor device package of claim 1, further comprising an underfill disposed between the first portion and the second portion, wherein the side surface of the first package is substantially coplanar with the side surface of the first building circuit, and the side surface of the first package is substantially coplanar with the side surface of the underfill.

3. The semiconductor device package of claim 1, wherein the carrier directly contacts the first package, wherein the first package encapsulates and contacts the side surface and the bottom surface of the carrier.

4. The semiconductor device package according to claim 3, wherein the dielectric constant of the carrier is less than 3.

5. The semiconductor device package of claim 1, wherein the first building block further includes a dielectric layer, the top surface of the dielectric layer directly contacting the second package and the bottom surface of the dielectric layer directly contacting the carrier and the first package.

6. The semiconductor device package according to claim 2, further comprising: The first set of conductive pillars is placed on the first building circuit; and A second package covers and directly contacts the first set of conductive pillars, wherein the side of the second package is substantially coplanar with the side of the first building circuit, and the side of the second package is substantially coplanar with the side of the bottom filler.

7. The semiconductor device package of claim 6, wherein the active surface of the electronic component is electrically connected to the top surface of the carrier via the first set of conductive pillars and the electrical contacts.

8. The semiconductor device package of claim 6, further comprising: A second circuit layer is disposed on the second package; and The second set of conductive pillars is placed on the first circuit layer; The third package is disposed on the first circuit layer and covers and directly contacts the second set of conductive pillars, wherein the second portion of the semiconductor device package and the first portion of the semiconductor device package are separated from each other by the underfill.

9. The semiconductor device package of claim 8, further comprising electrical contacts and a second dielectric layer and a second conductive layer disposed on the third package, wherein the electrical contacts are disposed on the second conductive layer exposed from the second dielectric layer.

10. The semiconductor device package of claim 9, wherein The first circuit layer is spaced apart from the second circuit layer and is electrically connected through the electrical contacts; and The electrical contact is covered and encapsulated by the underfill material, wherein the underfill material contacts the first circuit layer and the second circuit layer.

11. A semiconductor device package comprising: The first part includes: The stand-off layer is a transparent glass carrier having a bottom surface, a top surface opposite the bottom surface, and a side surface extending from the bottom surface to the top surface; A transmitting element is disposed on the bottom surface of the foot layer; A first construction circuit is disposed on the top surface of the support layer, wherein the width of the support layer is smaller than the width of the first construction circuit, and the side surface of the support layer is recessed from the side surface of the first construction circuit; and A first package encapsulates and contacts the transmitting element; Part Two includes: A first circuit layer is disposed on the first portion; An electronic component having an active surface facing the first circuit layer, the electronic component being disposed on the first circuit layer and the active surface being electrically connected to the first circuit layer; and A third package encapsulates and contacts the electronic components; and An electrical contact is disposed between the first portion and the second portion, wherein the second portion and the first portion are electrically connected to each other via the electrical contact.

12. The semiconductor device package of claim 11, further comprising an underfill disposed between the first portion and the second portion, wherein the side surface of the first package is substantially coplanar with the side surface of the first building circuit, and the side surface of the first package is substantially coplanar with the side surface of the underfill.

13. The semiconductor device package of claim 11, wherein the support layer directly contacts the first package body, wherein the first package body encapsulates and contacts the side surface and the bottom surface of the support layer.

14. The semiconductor device package of claim 11, wherein the first building block further includes a dielectric layer, the top surface of the dielectric layer directly contacting the second package and the bottom surface of the dielectric layer directly contacting the carrier and the first package.

15. The semiconductor device package of claim 12, further comprising: The first set of conductive pillars is placed on the first building circuit; and A second package covers and directly contacts the first set of conductive pillars, wherein the side of the second package is substantially coplanar with the side of the first building circuit, and the side of the second package is substantially coplanar with the side of the bottom filler.

16. The semiconductor device package of claim 15, wherein the active surface of the electronic component is electrically connected to the top surface of the support layer via the first set of conductive pillars and the electrical contacts.

17. A semiconductor device package comprising: The first part includes: The carrier is a transparent glass carrier and has a bottom surface, a top surface opposite to the bottom surface, and a side surface extending from the bottom surface to the top surface; A transmitting element, which is disposed on the bottom surface of the carrier; A first construction circuit is disposed on the top surface of the carrier, wherein the width of the carrier is smaller than the width of the first construction circuit, and the side surface of the carrier is recessed from the side surface of the first construction circuit; and A first package encapsulates and contacts the side and bottom surfaces of the transmitting element; Part Two includes: A first circuit layer is disposed on the first portion; An electronic component having an active surface facing the carrier, the electronic component being disposed on the first circuit layer and the active surface being electrically connected to the first circuit layer and the carrier; and A third package encapsulates the electronic component and contacts the top surface of the electronic component; and An electrical contact is disposed between the first portion and the second portion, wherein the second portion and the first portion are electrically connected to each other via the electrical contact.

18. The semiconductor device package of claim 17, further comprising a bottom filler disposed between the first portion and the second portion, wherein the side surface of the first package is substantially coplanar with the side surface of the bottom filler.

19. The semiconductor device package of claim 17, wherein the carrier directly contacts the first package, wherein the first package encapsulates and contacts the side surface and the bottom surface of the carrier.

20. The semiconductor device package of claim 17, wherein the first building block further includes a dielectric layer, the top surface of the dielectric layer directly contacting the second package and the bottom surface of the dielectric layer directly contacting the carrier and the first package.

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