An integrated structure of antenna elements and IC chips using edge contact connection

Abstract

An antenna apparatus includes a substrate having a cavity on a first outer surface thereof. The substrate has a sidewall defining a portion of the cavity and a first edge contact formed at the sidewall. An IC chip is disposed within the cavity and has a side surface facing the sidewall and a second edge contact formed on the side surface that is electrically connected to the first edge contact. An antenna element disposed at a second outer surface of the substrate opposite the first outer surface is electrically connected to RF circuitry within the IC chip through a conductive via extending within the substrate.

Description

Technical Field

[0001] This disclosure generally relates to the connection techniques and arrangements between an IC chip and other circuit components (such as printed antenna elements) supported by a substrate. Background Technology

[0002] In wireless communication, it is often desirable to provide small-sized antenna devices that integrate antenna elements with an IC chip containing beamforming components. For example, satellite applications typically employ phased arrays with numerous microstrip patch antenna elements disposed on a substrate. The antenna elements can be electrically coupled to a distributed power amplifier supplying RF power and a phase shifter controlled by a processor to dynamically steer the resulting antenna beam. The power amplifier, phase shifter, and other front-end devices, such as receiver circuitry, can be provided within an IC chip integrated with the antenna elements. Summary of the Invention

[0003] In one aspect of the technology disclosed in this invention, an antenna device includes a substrate having a cavity on its first outer surface. The substrate has sidewalls defining a portion of the cavity, and a first edge contact is formed at the sidewalls. An IC chip is disposed within the cavity and has a side surface facing the sidewalls and a second edge contact formed on the side surface that is electrically connected to the first edge contact. An antenna element disposed on the second outer surface of the substrate opposite the first outer surface is electrically connected to RF circuitry within the IC chip via conductive vias extending within the substrate.

[0004] The electrical connection between the antenna element and the RF circuitry within the IC chip can be formed via a first edge contact and a second edge contact. Alternatively, the connection of the antenna element can be formed by electrical contacts on the bottom surface of the IC chip.

[0005] In another aspect, a method of manufacturing an antenna device involves forming a cavity in a first outer surface of a substrate and forming an antenna element on a second outer surface of the substrate opposite to the first outer surface. A first edge contact is formed at a sidewall of the cavity. An IC chip is placed in the cavity, wherein the IC chip has a second edge contact formed on its side surface and includes RF circuitry. The first and second edge contacts are electrically connected. A conductive via is formed extending from the second outer surface within the substrate, and the antenna element is electrically connected to the RF circuitry through the conductive via.

[0006] In another aspect, a method of manufacturing an antenna array that can be electronically steered includes: forming a plurality of cavities within a substrate, the plurality of cavities being spatially arranged along a first outer surface of the substrate; forming a plurality of spatially arranged antenna elements on a second outer surface of the substrate opposite to the first outer surface; providing a plurality of IC chips, each IC chip having a side surface having a corresponding second edge contact, each IC chip including a beamforming component; for each of the cavities: forming a second edge contact on a sidewall of the cavity; placing a corresponding one of the plurality of IC chips into the cavity; electrically connecting the corresponding first edge contact and second edge contact; and electrically connecting the beamforming component of the IC chip placed therein to at least one of the corresponding antenna elements. Attached Figure Description

[0007] The above and other aspects and features of the disclosed technology will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which the same reference numerals indicate the same elements or features. Various elements of the same or similar type can be distinguished by appending a dash and a second label (e.g., -1, -2) to the reference label to differentiate between identical / similar elements. However, if a given description uses only the first reference label, it applies to any of the identical / similar elements having the same first reference label, regardless of the second reference label. Elements and features may not be drawn to scale in the drawings.

[0008] Figure 1 This is an exploded perspective view of an exemplary antenna device according to the implementation scheme.

[0009] Figure 2 It is in the assembly state. Figure 1 A plan view of the antenna equipment.

[0010] Figure 3 This is a perspective view showing an exemplary first edge contact on the sidewall of the cavity.

[0011] Figure 4 This is a perspective view showing an exemplary second edge contact formed on the side surface of an IC chip.

[0012] Figure 5 It is along Figure 2 The cross-sectional view of the antenna device taken from line 5-5.

[0013] Figure 6 It is formed Figures 1-5 A flowchart of an exemplary method for an antenna device.

[0014] Figure 7A This is a top plan view of a portion of the lower substrate, which forms part of a multilayer substrate of an exemplary antenna device, wherein the view shows Figure 6The temporary configuration following step S602 of the method.

[0015] Figure 7B It was taken from section 7B-7B. Figure 7A Cross-sectional view of the lower substrate.

[0016] Figure 7C yes Figure 7A A bottom view of the lower substrate.

[0017] Figure 7D Is Figure 6 The plan view of a portion of the upper substrate of the multilayer substrate in the temporary process following step S604 shows the configuration after the notches for forming edge contacts have been cut out and metallized.

[0018] Figure 7E It was taken along line 7E-7E. Figure 7D A cross-sectional view of the upper substrate.

[0019] Figure 7F yes Figure 7D The upper substrate in Figure 6 The floor plan after step S606.

[0020] Figure 7G It was captured along the 7G-7G line. Figure 7F A cross-sectional view of the upper substrate.

[0021] Figure 7H This is an example of a multilayer substrate in Figure 6 The top view is formed after step S612 of the method.

[0022] Figure 7I It was taken along line 7I-7I. Figure 7H Cross-sectional view.

[0023] Figure 7J It corresponds to Figure 6 Step S614 onwards Figure 7I A cross-sectional view of the cross-section.

[0024] Figure 8A It is a plan view of an electronic device according to another embodiment.

[0025] Figure 8B It is along Figure 8A The cross-sectional view taken from line 8B-8B'.

[0026] Figure 9 It shows the manufacturing process. Figures 8A-8B A flowchart of an exemplary method for an electronic device.

[0027] Figure 10AIt is an exploded cross-sectional view of an electronic device with an embedded chip according to the implementation scheme.

[0028] Figure 10B It is in the assembly state. Figure 10A A cross-sectional view of an electronic device. Detailed Implementation

[0029] For illustrative purposes, the following description is provided with reference to the accompanying drawings to aid in a comprehensive understanding of certain exemplary embodiments of the technology disclosed herein. This description includes various specific details to assist those skilled in the art in understanding the technology, but these details should be considered exemplary only. Where descriptions including well-known functions and structures may obscure the understanding of the technology by those skilled in the art, such descriptions may be omitted for clarity and brevity.

[0030] Figure 1 This is an exploded perspective view of an exemplary antenna device 100 according to an embodiment. The antenna device 100 includes a substrate 130 and at least one antenna element 120 (e.g., two antenna elements 120-1, 120-2) electrically connected to RF circuitry within an IC chip 110. Each antenna element 120 is illustrated as a microstrip patch element printed on a lower surface 139 (“second outer surface”) of the substrate 130. Although depicted as a rectangular shape, the antenna element 120 can have any other suitable shape to form a desired radiation pattern. Furthermore, other types of antenna elements, such as dipole or slot antenna elements, can be substituted to achieve the target performance metrics.

[0031] The substrate 130 has a cavity 140 formed within its top surface 135 (“first outer surface”), the cavity having a depth extending to the bottom surface, which may coincide with the top surface of the ground plane 170. In the assembled state of the antenna device 100, an IC chip 110 is disposed within the cavity 140, and the top surface 115 of the IC chip 110 is substantially coplanar with the top surface 135 of the substrate 130. In the assembled state, the bottom surface 119 of the IC chip 110 faces and may be adjacent to the ground plane 170. At least one first edge contact 132 is disposed at a sidewall 144 of the cavity 140. At least one second edge contact 112 is located on a side surface 117 of the IC chip 110 and is electrically connected to the adjacent first edge contact 132. An antenna element 120 may be fed with an RF signal via a probe feed (in the transmit and / or receive direction) embodied as a through-substrate via (TSV) (hereinafter referred to as a “conductive via” or simply a “via”) 122. The via 122 can be electrically connected to a short conductive trace 168, which in turn is electrically connected to a first edge contact 132, thereby completing the electrical connection between the antenna element 120 and the RF circuitry within the IC chip 110 connected to the second edge contact 112.

[0032] In this document, the term IC chip refers to one or more electronic circuits embodied within a small, flat piece of semiconductor material. For example, IC chip 110 may be a monolithic microwave IC (MMIC) made of gallium arsenide (GaAs), indium phosphide (InP), silicon germanium (SiGe), or gallium nitride (GaN). IC chip 110 may include a power amplifier for amplifying the transmit path signal output to antenna element 120 and / or may include a low-noise amplifier (LNA) for amplifying the receive path signal received by antenna element 120.

[0033] In the illustrated example, two antenna elements 120-1 and 120-2 are connected to a single IC chip 110 via vias 122-1 and 122-2, respectively; first edge contacts 132 on opposite sidewalls 144-1 and 144-2 of the cavity 140; and second edge contacts 112 on opposite side surfaces 117-1 and 117-2 of the IC chip 110. Furthermore, the IC chip 110 includes another pair of second edge contacts 112, each connected to a conductive trace 165 via an adjacent first edge contact 132. Each conductive trace 165 may be electrically connected to a component (not shown), such as a terminal receiving a bias voltage or control signal applied to an RF component within the IC chip 110, such as an amplifier or a dynamically controlled phase shifter. In other examples, the IC chip 110 includes more or fewer edge contacts 112 to form more or fewer connections to components as needed for a particular application; and more or fewer antenna elements 120 are connected to the IC chip 110. For RF connections, microstrip or coplanar waveguide (CPW) transitions can be made. For example, conductive traces 165 and 168 in the accompanying figures are shown as single lines; in the case of microstrip, conductive trace 165 can be a microstrip line on a ground plane (e.g., 170). In the case of CPW, conductive trace 165 can each be an inner conductive trace between a pair of outer conductive ground traces (although not shown in the figures).

[0034] Antenna device 100 comprises at least one IC chip 110 and at least one antenna element 120, such as Figure 1As shown. In a typical application, antenna device 110 comprises several, dozens, or hundreds of IC chips 110, each IC chip residing within a corresponding cavity 140 spatially arranged along substrate 130. In this typical application, at least some or all of the IC chips 110 are respectively connected to one or more antenna elements 120 spatially arranged along the lower surface 139 of substrate 130, thereby forming an antenna array. The antenna array may be an electronically steered antenna, such as a phased array dynamically steered by phase shifters located collectively within IC chip 110 or elsewhere within antenna device 100. Substrate 130 may include beamforming circuitry electrically coupled to IC chip 110 to divide input RF signals during transmit operation and / or combine multiple RF signals received from antenna elements 120 and processed by IC chip 110 during receive operation (e.g., amplification, filtering, phase shifting, down-conversion, etc.).

[0035] Figure 2 It is in the assembly state. Figure 1 A plan view of antenna device 100. Figure 3 This is a perspective view showing an exemplary first edge contact 132 on the sidewall of the cavity. Figure 4 This is a perspective view showing an exemplary second edge contact 112 formed on the side surface of the IC chip 110. Figure 5 It is along Figure 2 Cross-sectional view taken from line 5-5. (For common reference) Figures 1-5 The first edge contact 132 and the adjacent second edge contact 112 can have complementary geometries. Each first edge contact 132 can have a metallic peripheral surface in a three-dimensional (3D) structure, such as a 3D structure plated to form side, base, and rear metallic peripheral surfaces. The dimensions of the complementary geometries can form a tight fit so that the IC chip 110 can be placed within the cavity 140, such that the second edge contact 112 "clicks" into the first edge contact 132. This helps to secure the IC chip 110 in the proper position within the cavity 140 before any electrical connection enhancement between the edge contacts 112, 132 is performed by welding, thermopressing, thermo-ultrasonic bonding, etc. Alternatively, without any welding, etc., a complete electrical connection can be formed simply by pressure fitting between the edge contact structures. The tight fit between adjacent first edge contacts 132 and second edge contacts 112 may result in the corresponding edge contacts being interlocked. For example, as Figure 3 As shown, the first edge contact 132 may have a slotted flared opening 149, which is a recess within the cavity sidewall 144-2. For example... Figure 4Ideally, adjacent second edge contacts 112 can be in the form of open protrusions that fit tightly within the slot opening 149 from the side surfaces 117-2. With the outer surface of the second edge contact 112 in close contact with the inner surface of the corresponding first edge contact 132, solder or other conductive bonding material 190 (see [reference]) can be applied therebetween. Figure 2 This is to complete or enhance the electrical connection. The conductive bonding material can also at least partially serve as the mechanical connection between the IC chip 110 and the substrate 130. The external dimensions of the IC chip 110 can also form a tight fit or even a pressure fit with respect to the sidewalls 144 of the cavity 140. A small gap “g” may exist between the side surface 117 of the IC chip 110 and the sidewalls 144 to allow for thermal expansion or manufacturing tolerances.

[0036] If a coplanar waveguide (CPW) transition is used for edge contacts 112 and 132 as described above, a ground-signal-ground (GSG) latching connection can be formed between the corresponding edge contacts 112 and 132. In this configuration, each electrical connection has three connection points. In other words, the second edge contact 112 can consist of three contacts: a “signal” contact between and electrically isolated from the two “ground” contacts. The corresponding first edge contact 132 also includes three connection points, which are formed by a signal contact between the two ground contacts.

[0037] In an alternative embodiment, the corresponding first edge contact 112 and second edge contact 132 each have a dielectric waveguide structure, such as an optical guide similar to an optical fiber. In this case, the conductive trace 165 is replaced by an optical guide (hereinafter referred to as optical guide 165 in this context) to allow externally supplied RF-modulated laser light to propagate through the optical guide connection of the first edge contact 112 and the second edge contact 132 to the electronics within the IC chip 110. An optical-to-RF converter within the IC chip 110 converts the optical signal into an RF signal, which is output to the antenna element 120 through the different edge contact pairs 112, 132. Thus, in this embodiment, the signal is input to the IC chip 110 as “fiber optic RF” and is then converted into RF within the IC chip 110 and radiated through the antenna element 120 in the transmission direction. In the reception direction, the RF signal received by the antenna element 120 is routed to the IC chip 110 through the pair of edge contacts 112, 132. Then, IC chip 110 converts the received path RF signal into an optical signal, which is routed to an external system for processing through the same or different optical guide tubes 165. High-bandwidth systems can be implemented in this way.

[0038] In such Figure 3In the tapered slot design of the first edge contact 132 shown, the first edge contact 132 can be constructed by first forming a notch of the desired geometry in the top surface 135 of the substrate 130 through laser drilling, photoimaging, and etching. The notch can then be metallized by electroplating to form conductive sidewalls and a conductive base, and the front portion of the notch can be cut off to form a front opening. This results in a front surface 146 that is approximately coplanar with the side surfaces 144-2, and a depth d1 (see...). Figure 5 The first edge contact 132 is formed between the recess and the rear surface 171. Alternatively, the recess is completely filled with metal, and laser drilling is performed later to form a conductive structure with the desired geometry. Later bonding... Figure 6 Further discussion is provided regarding the formation of the first edge contact 132. Various techniques can be used to form the second edge contact 112. For example, the edge contact 112 may be a quilt package nodule.

[0039] Other geometries and other types of structures are envisioned for the first edge contact 132 and the second edge contact 112. For example, the shape of the recess / protrusion can be rectangular, circular, elliptical, triangular, and / or some other shape instead of the horn shape described above. Instead of a single centralized slot 149, the edge contact 132 can have an interdigitated structure with several metallic "interdigitates" or ridges and channels. In this case, adjacent edge contacts 112 can also have interdigitated structures with complementary interlocking interdigitates or channels and ridges. In other examples, the interlocking structures on one or more sidewalls 144 of the cavity 140 and one or more side surfaces 117 of the chip 110 can be formed primarily or entirely of dielectric or semiconductor material. In this case, the edge contacts 132 and 112 can be smaller than the interlocking structure and can be located on the surface of the interlocking structure itself, on other portions of the sidewalls 144 / side surfaces 117, or they can form other complete interlocking structures. Smaller edge contacts (if any) may have flat edges adjacent to each other, or they may have small complementary geometries. In yet another example, instead of forming the second contact 132 as a recess, they may be formed as a protrusion, while the second edge contact 112 is formed as a recess. Alternatively, each of the edge contacts 112, 132 is a protrusion, such as a flat or sloping protrusion, which is adjacent to the adjacent edge contacts 132, 112, respectively. Typically, the edge contacts 112, 132 can be used to conduct energy from DC to millimeter-wave frequencies and are particularly useful for forming low-loss connections at millimeter-wave frequencies. Since the electrical connection between adjacent edge contacts 112 and 132 is formed without using wire or strip bonding, the inductance that would otherwise be added by those techniques is eliminated. This achieves extremely low-loss connections at frequencies up to at least 200 GHz. Furthermore, the overall configuration of the IC chip 110, including the cavity 140, the first edge contact 132, and the second edge contact 112, forms a compact, thin structure, wherein the top surface 115 of the chip 110 can be substantially coplanar with the top surface of the substrate 130. The electrical and mechanical connections of the IC chip 110 to the substrate 130 are simplified because the IC chip 110 can be easily snapped into the cavity 140 via the interlocking of the edge contacts 112 and 132, thus completing both mechanical and electrical connections.

[0040] Substrate 130 may be a multilayer substrate having circuitry disposed in different layers. Substrate 130 may be made of any suitable dielectric material. In some embodiments, substrate 130 is a hard substrate, such as quartz, alumina, glass, or fused silica, and is suitable for depositing thin films to form fine features. Figure 5As seen, for example, substrate 130 comprises a lower layer (interchangeably, "lower substrate") 130a and an upper layer ("upper substrate") 130b, with a ground plane 170 sandwiched between them. Substrate 130 can be formed by first providing the lower layer 130a, metallizing the top surface of the lower layer 130a to form the ground plane 170, and then forming or bonding the upper layer 130b onto the ground plane 170 using a suitable method. Some exemplary methods for such bonding include dBi bonding, glass bonding, gold bump bonding, solder bump bonding, and copper pillar bonding. Alternatively, the upper layer 130b can be provided separately and can be adhered to the ground plane 170 using a suitable adhesive. Ground plane 170 may have circular apertures 182 for receiving vias 122-1 and 122-2. The aperture 182 has a sufficiently large diameter to allow vias 122-1 and 122-2 to penetrate without contacting the ground plane 170, thereby enabling vias 122-1 and 122-2 to act as probe feeds for antenna elements 120-1 and 120-2. The ground plane 170 can be used as a microstrip ground plane to reflect RF energy transmitted / received by antenna element 120. The microstrip ground plane can also form the ground plane for a microstrip transmission line in which the conductive trace 165 is a conductor.

[0041] The IC chip 110 may have a thickness approximately equal to the depth d2 of the top surface of the ground plane 170 extending from the top surface 135 of the substrate 130 to the bottom of the cavity 140. With this size, the bottom surface 119 of the IC chip 110 may rest on the ground plane 170, and the top surface 115 of the IC chip 110 may be substantially coplanar with the top surface 135 of the substrate 130. Alternatively, the thickness of the IC chip 110 may be less than the depth d2, and a gap may exist between the ground plane 170 and the bottom surface 119. This gap may be an air gap or a gap filled with an insulating layer material. In some designs, it may be desirable for the IC chip 110 to have one or more electrical contacts on its bottom surface 119 to form an electrical connection with other components of the antenna device 100. In this case, a corresponding aperture may be formed in the ground plane 170 to facilitate the electrical connection.

[0042] Conductive vias 122-1 and 122-2 are examples of conductors and form probe feeds for antenna elements 120-1 and 120-2. As further described below, via 122 can be formed by first forming a pad on the outer surface of substrate 130, then drilling a hole through substrate 130, and filling the hole with metal by electroplating or the like. Short conductive traces 168 on the top surface 135 of substrate 130 can be extensions of such via pads (or conductive traces 168 themselves can be considered via pads), and via 122 can be interconnected to adjacent first edge contacts 132, for example, by overlapping edges 171 of first edge contacts 132. Other conductive traces 165 connecting to circuit components or terminals (not shown) other than antenna element 120 can also be formed on the surface 135 overlapping the edge 171 of the first edge contact 132 for electrical connection to connected second edge contacts 112. Any conductive trace 165 can form such an electrical connection by passing through the substrate 130 or through another via (not shown) at the side port. Any conductive trace 165 can route RF signals, DC bias voltages, or time-varying control signals to / from the IC chip 110 and other circuit components.

[0043] Figure 6 This is a flowchart of an exemplary method 600 for forming an antenna device 100. Figures 7A-7I Each is a cross-sectional or plan view showing the structure corresponding to the respective step in method 600. Note that the order of the various process steps described below with respect to method 600 may be changed as needed in other exemplary embodiments.

[0044] To form the multilayer substrate 130 of the antenna device 100, the lower substrate 130a and the upper substrate 130b can be processed separately and then bonded together. Figure 7A This is a top plan view of a portion of the substrate 130a during the process stage after the patterning metallization of its top and bottom surfaces has been performed. Figure 7B It was taken from section 7B-7B. Figure 7A A cross-sectional view of the lower substrate 130a, and Figure 7C yes Figure 7A Bottom view of the lower substrate 130a. (Reference) Figure 6 and Figures 7A-7CA lower substrate 130a (S602) is provided, and the top and bottom surfaces of the lower substrate 130a are selectively masked and metallized to form an antenna element 120 on the bottom surface and a ground plane 170 on the top surface. Prior to this metallization, the area for forming an aperture 182 in the ground plane 170 may have been masked on the top surface, and the area outside the boundary of the antenna element 120 may have been masked on the bottom surface. The aperture 182 has a first diameter to accommodate a via with a second, smaller diameter formed later. The larger diameter aperture 182 prevents the formation of a subsequent via 122 leading to the probe feed portion of the antenna element 120. Figures 1-5 (As shown in the diagram) The electrical circuit is shorted to the ground plane at 170°.

[0045] An upper substrate having a top surface and a bottom surface is provided and processed separately (S604). This process may involve cutting a left and a right notch in the top surface using laser drilling, mechanical drilling, photoimaging, etching, or other suitable techniques, each notch having a first geometry. The notches are then metallized to form a first edge contact 132 (some of the metallization is subsequently removed during another removal process). For example, Figure 7D This is a plan view of a portion of the upper substrate 130b after the notch 711 has been cut to a depth d1 (less than the thickness d2 of the upper substrate 130b) and metallized. Figure 7E It was taken along line 7E-7E. Figure 7D A cross-sectional view of the upper substrate 130b. In this example, the notch 711 is in the shape of a flared trumpet, but other structures can also be obtained, such as for forming multi-finger joints. As seen in the enlarged view A, metallization of any notch 711 by electroplating or the like can create sidewall metallized regions 717s, front wall metallized regions 717f, rear wall metallized regions 717r, and substrate metallized regions 717b within the notch 711.

[0046] A central notch (S604) for the IC chip can then be made through the top substrate. For example, Figure 7F This is a plan view of the substrate 130b after a rectangular cut 740 has been made between the left notch 711 and the right notch 711. Figure 7G This is a cross-sectional view of the upper substrate 130b taken along line 7G-7G during this stage. The notch 740 later forms the previously described cavity 140. As shown in enlarged view B, when the notch 740 is made, the front portion of the notch 711 can be cut away, thus removing the front metallization 717f of the notch 711. This opens a slot within the notch 711, thereby forming a first edge contact 132, in which a second edge contact 112 of the IC chip 110 is later inserted.

[0047] The region adjacent to the notch 711 can be metallized by pattern metallization (S608) to form adjacent upper via pads 168 or conductive traces 165 electrically connected to the metallized area in the notch. Before or after such metallization, the upper substrate 130b is attached / bonded to the lower substrate 130a using a suitable bonding method or non-conductive adhesive (S610) to form a multilayer substrate 130. Through-holes can then be drilled between each via pad 168 and the corresponding antenna element 120 (S612), and the through-holes are metallized to complete probe feeding.

[0048] For example, Figure 7H This is a top plan view of a portion of a multilayer substrate configured in an exemplary manner after step S612. Figure 7I It was taken along line 7I-7I. Figure 7H A cross-sectional view is shown. In this example, a pair of conductive traces 165 and a pair of via pads 168 have already been formed on the top surface of the upper substrate 130b. Thus, the via pads 168 / conductive traces 165 can overlap and be electrically connected to the rear wall metallized surface 717r of the adjacent first edge contact 132. Alternatively, when the notch 711 is initially formed, the adjacent shallower channels for forming the via pads 168 / conductive traces 165 can be formed simultaneously using the same laser drilling or etching process. Then, when the notch 711 is metallized, the shallower channels are metallized during the same metallization process, thereby forming via pads 168 / conductive traces 165 with their top surfaces coplanar with the top surface of the rear metallized 717r. In another alternative, the via pads 168 and conductive traces 165 are completed before the notch 711 and the first edge contact 132 are formed.

[0049] Once the via pad 168 is formed, vias that completely penetrate the multilayer structure can be drilled in step S612. Each via can be drilled through the via pad 168, the upper substrate 130b, the aperture 182, the lower substrate 130a, and through the antenna element 120 in a vertical path. The vias can then be electroplated to complete the probe feed vias leading to the corresponding antenna element 120. During this process, metallization can be built into the via region 731 of the antenna element 120, and then a planarization process such as chemical mechanical polishing (CMP) can planarize the lower surface of the antenna element 120 and the via region 731 to obtain a flat, continuous lower metal surface for the antenna element 120.

[0050] Using the multilayer substrate 130 thus formed, second edge contacts 112 can be provided for the IC chip 110 (S614), each second edge contact having a second geometry complementary to the first geometry of the adjacent first edge contact 132. The IC chip is snapped into the cavity 140, as... Figure 1 As shown, this produces the following: Figure 7J The structure shown, Figure 7J The second edge contact 112 is shown to form an electrical contact with the metallized walls 717r, 717s and 717b of the first edge contact 132.

[0051] As previously described, the second edge contact 112 can snap into the first edge contact 132, thereby forming an interlocking relationship. In some cases, the pressure fit between contacts 112 and 132 is sufficient to form an electrical connection therebetween and complete the formation of the antenna device 100. In other cases, solder or other conductive bonding material 190 is used to enhance the electrical connection between the first edge contact 112 and the second edge contact 132, as described earlier. Figure 2 As shown in the image.

[0052] Method 600 can be extended to a method of manufacturing an electronically steerable antenna array using the same operations described above but on an extended scale by: (i) forming a plurality of cavities 140 in a substrate 130, each cavity having at least one second edge contact 132, wherein the plurality of cavities 140 are spatially arranged along the top surface of the substrate 130; (ii) forming a plurality of antenna elements 120 or a plurality of groups of antenna elements 120 spatially arranged along the bottom surface of the cavity 130 (i.e., along the bottom surface of the lower substrate 130a); and (iii) snapping each of a plurality of IC chips 110 into a corresponding cavity 140, such that a beamforming component within each IC chip 110 is electrically connected to at least one antenna element 120 through at least one corresponding conductive via 122. In other words, for each of the cavities 140, the expansion method includes: forming a second edge contact 132 at a sidewall of the cavity 140; placing a corresponding one of the IC chips 110 into the cavity 140; electrically connecting the corresponding first edge contact 132 and second edge contact 112 (which may be done when the IC chip 110 is snapped into the cavity 140); and electrically connecting the beamforming component of the IC chip 110 placed therein to at least one of the corresponding antenna elements 120 (which may also be done when the IC chip 110 is snapped into the cavity 140).

[0053] Figure 8A It is a plan view of an electronic device 800 according to another embodiment. Figure 8B It is along Figure 8AA cross-sectional view taken from line 8B-8B. In one embodiment, electronic device 800 is an antenna device having at least one antenna element, such as antenna elements 820-1, 820-2, 820-3, and 820-4, electrically connected to IC chip 110'. This example will be described primarily below. In other embodiments discussed below, electronic device 800 is a non-antenna implementation omitting antenna elements 820-1 to 820-4. Hereinafter, when discussing antenna implementations, electronic device 800 will be referred to as antenna device 800.

[0054] The main difference between antenna device 800 and antenna device 100 described above is that probe feed connections to at least one component, such as an antenna element, are made via connections at the bottom surface of IC chip 110' instead of via edge contacts 112, 132. Substrate 130' is a multilayer substrate consisting of a lower substrate 130a' bonded to an upper substrate 130b', and can be substantially the same as substrate 130 except for the positions of apertures 840-1, 840-2, 840-3, 840-4 within the embedded ground plane 870. For example, first antenna elements 820-1 to fourth antenna elements 820-4 can be disposed on the bottom surface 139 of substrate 130'. IC chip 110' may include at least one bottom contact located centrally within the corresponding apertures 840-1 to 840-4 within the ground plane 870, for example, the first bottom contact to the fourth bottom contacts 830-1, 830-2, 830-3, 830-4. Bottom contacts 830-1 to 830-4 may each include connecting elements, such as solder bumps or copper pillars on their outer surfaces, for electrical connection to vias 822-1, 822-2, 822-3, and 822-4, respectively. Alternatively, connecting elements (e.g., solder bumps / copper pillars) are initially formed at the end of via 822 (in which case each illustrated contact 830 is understood to include the bottom contact of the IC chip 110' and the connecting element). Vias 822-1 to 822-4 are probe feeds, each probe feed electrically connected between a corresponding feed point of antenna elements 820-1 to 820-4 and electrical contacts 830-1 to 830-4. Electrical contacts 830 may each be connected to RF transmitter and / or receiver circuitry disposed within the IC chip 110' for handling signal transmission / reception relative to antenna element 820.

[0055] Antenna device 800 includes at least one first edge contact 132 formed at a sidewall 144 of cavity 140 for connection to a corresponding second edge contact 112 of IC chip 110'. Each conductive trace 165 is connected to an adjacent first edge contact 132 in the same manner described above to complete an electrical connection between another component / terminal of antenna device 800 and RF circuitry within IC chip 110'. In the example shown, four conductive traces 165 are provided for connection to the respective second edge contacts 112. Any conductive trace 165 can be connected to the component / terminal via a side contact on substrate 130' or via a via (neither shown).

[0056] exist Figure 8A and Figure 8B In the alternative embodiments shown, up to three bottom contacts 830 are connected to up to three antenna elements 820 via vias 822, but at least one other antenna element 820 is electrically connected to the IC chip 110' via a set of edge contacts 132, 112 and vias extending from the top surface of the substrate 130'. In either of these cases, at least one other bottom contact 830 may be connected to a conductive trace 165 (not shown) embedded in the lower substrate 130a' for connecting to another component to exchange RF signals, control signals, or DC bias, or connected to a ground plane 870 to form a ground connection.

[0057] In one non-antenna implementation, at least one bottom contact 830 is connected to an interlayer via (e.g., a shortened version of via 822-1) that connects to a conductive trace 165 extending within the lower substrate layer 130a' (neither shown). In yet another non-antenna implementation, a ground plane 870 or a portion thereof is replaced by a metal layer configured as a heat sink to cool the IC chip 110', while at least one bottom contact 830 is connected to an interlayer via similarly connected to the conductive trace 165.

[0058] Figure 9 This is a flowchart illustrating an exemplary method 900 for manufacturing an electronic device 800. Using method 900, the lower substrate 130a' and the upper substrate 130b' can be processed separately and then bonded together. An IC chip 110' is then snapped into a central cavity 140, and electrical connections are formed between the corresponding contacts of the IC chip 110' and those contacts formed within the substrate 130'.

[0059] Specifically, a lower substrate 130a' having a top surface and a bottom surface is provided (S902). Regions of the top and bottom surfaces are masked for pattern metallization to form an antenna element 120 on the bottom surface and a ground plane 870 on the top surface, the ground plane having an aperture 840 and a through-hole pad within the aperture (the upper part of the through-hole 830). Through-holes are then drilled through the through-hole pad at the feed point of the antenna element toward the bottom surface (S903). The through-holes are metallized to complete the probe feeding. The upper substrate 130b' can then be processed in steps S904, S906, S908, and S908 in the same manner as steps S604, S606, S608, and S608, except that each edge contact 132 can be connected to a conductive trace 165 instead of a through-hole 168. To form an alternative configuration in which some of the edge contacts 132 are connected to the adjacent via 168, process steps S904-S908 can be the same as S604-S608.

[0060] The upper substrate 130b' is then attached / bonded to the lower substrate 130a' using a bonding method or a non-conductive adhesive 789 (S910). As described above, suitable bonding methods for this purpose include dBi bonding, glass bonding, gold bump bonding, solder bump bonding, and copper pillar bonding.

[0061] A complementary (second) edge contact 112 can be provided for IC chip 110' (S912), and bottom contacts 830-1 to 830-4 with attached solder bumps or pillars are provided. IC chip 110' is snapped into cavity 140, and an electrical connection is formed between corresponding first edge contact 132 and second edge contact 112 in the manner described above. The electrical connection between bottom electrical contact 830 and corresponding via 822 can be formed by heating and cooling the solder bumps / pillars attached to electrical contact 830. Note that the solder bumps / pillars can alternatively be attached to the end of via 822 after formation instead of electrical contact 830, and the subsequent electrical connection from via 822 to electrical contact 830 can be formed using the same heating and cooling techniques.

[0062] Figure 10A This is an exploded cross-sectional view of an electronic device 10 with an embedded IC chip according to another embodiment. Figure 10B This is a cross-sectional view of the electronic device 10 in its assembled state. (Reference) Figure 10A and 10BThe electronic device 10 includes a multilayer substrate 30 having a dual-cavity structure formed within a top surface 35; a first IC chip 60; and a second IC chip 50. The first IC chip 60 and the second IC chip 50 are disposed within corresponding first cavity portions 80 and 70 of the dual-cavity structure. The first cavity portion 80 is located directly below the second cavity portion 70 and has a smaller perimeter than the second cavity portion 70.

[0063] The first cavity portion 80 has at least one sidewall 81 provided with one or more first edge contacts 132, wherein each first edge contact 132 can be electrically connected to an adjacent second edge contact 112 disposed on the side surface 62 of the IC chip 60. Similarly, the second cavity portion 60 has at least one first edge contact 132' electrically connected to at least one second edge contact 112' on the side surface 52 of the IC chip 50. In the illustrated example, the cavity portion 80 includes at least one first edge contact 132 at each of the opposing sidewalls 81-1, 81-2; and the second cavity portion 70 includes at least one first edge contact 132' at each of the opposing sidewalls 71-1, 71-2 for connection to the corresponding second edge contact. The edge contacts 132, 132', 112, 112' can have the same or similar structures as those previously described, and can be manufactured and electrically connected to each other in the same or similar manner as described.

[0064] Any edge contact 132 or 132' can be electrically connected to another component of the electronic device 10 via vias and / or conductive traces within the substrate 30. For example, IC chips 50 and 60 can be electrically connected to each other via one or more sets of edge contacts 112, 132, 132', and 112'. Figure 10A and 10B As shown, substrate 30 may be composed of a lower layer 30a, a middle layer 30b, and an upper layer 30c. Conductive trace 165 may be disposed between layers 30a and 30b and between layers 30b and 30c. In the example shown, circuitry within the first IC chip 60 may be electrically connected to circuitry within the second IC chip 50 via a path including a second edge contact 112, a first edge contact 132, a first conductive trace 165, a blind via 22 extending through substrate layer 30c, a via pad / second conductive trace 168, a first edge contact 132', and a second edge contact 112'.

[0065] In one exemplary embodiment, the first IC chip 60 includes an amplifier electrically coupled to one or more antenna elements (not shown) disposed on the lower surface of the substrate layer 30a. In this case, the amplifier of the first IC chip 60 can be electrically connected via the aforementioned connection path to a beamforming network circuit included within the second IC chip 50. Furthermore, several, dozens, or more IC chips 50 and 60 can be spatially arranged within the cavity of the entire substrate 30 to drive an antenna array, such as a phased array.

[0066] The first IC chip 60 may be made of a different semiconductor material than the second IC chip 50. In one example, the first IC chip 60 is made of InP, and the second IC chip 50 is made of SiGe.

[0067] When assembled within the first cavity portion 80, the first IC chip 60 may have a top surface that is substantially coplanar with the top surface of the first cavity portion 80. The second IC chip 50 may have a thickness dimension smaller than the depth of the second cavity portion 70, such that when the second IC chip 50 is assembled within the second cavity portion 70, its top surface may be substantially coplanar with the top surface 35 of the substrate 30, but its bottom surface may be spaced apart from the top surface of the second cavity portion 70 by a gap 97. In one example, the gap 97 is an air gap. In other examples, the gap 97 is an insulating underfill material formed above the first IC chip 60 after the first IC chip 60 is assembled within the first cavity portion 80. In the latter case, the second IC chip 50 may be placed above the underfill material for assembly within the second cavity portion 50. For example, the underfill material may have orifices that allow electrical connection between an upper contact formed on the first IC chip 60 and a lower contact formed on the second IC chip 50.

[0068] Material layer 87 may be disposed on the bottom surface of the first cavity portion 80. In the example, layer 87 is a portion of a ground plane similar to ground plane 170 or 870 in the above embodiments. In this case, other ground plane portions (not shown) are disposed around layer 87 between layers 30a and 30b, and all ground plane portions together serve as the ground plane for antenna elements disposed on the lower surface of substrate layer 30a. In non-antenna embodiments, the overall ground plane may simply form a ground surface for circuit paths between circuit components. Layer 87 may alternatively be configured to act as a heat sink.

[0069] In other examples, layer 87 is not a ground plane, but is patterned to form one or more conductive traces for RF, DC, or control signal connections between circuitry within the first IC 60 and other circuitry elements within the electronic device 10.

[0070] According to the techniques disclosed in this invention, electronic devices and antenna devices, such as those described above, can exhibit certain advantages over conventional devices. For example, due to the described compact configuration, the embodiments can allow for high-performance signal routing at extremely high frequencies, such as around 200 GHz. Such high performance stems at least in part from the elimination or minimization of bonding lines (which would otherwise be used) between conductive traces / vias on the chip and the substrate. The embodiments can enable next-generation such extremely high-frequency phased arrays and other components. A compact, thin configuration can be achieved, in which the outer surface of the IC chip is substantially coplanar with the surface of the outer substrate. Manufacturing is simplified by simply snapping the IC chip into the cavity of the multilayer substrate and simultaneously achieving mechanical and electrical connections through the interlocking of the first and second edge contacts.

[0071] While exemplary embodiments of the technology described herein have been specifically shown and described with reference to them, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the subject matter protected by the claims as defined by the following claims and their equivalents.

Claims

1. An antenna device, the antenna device comprising: A substrate (130) having a cavity (140) in its first outer surface (135), the substrate (130) having a sidewall (144) defining a portion of the cavity (140), wherein a first edge contact (132) is formed at the sidewall (144); an integrated circuit (IC) chip (110) disposed within the cavity (140), the IC chip having a side surface (117) facing the sidewall (144) and a second edge contact (112) formed on the side surface (117) electrically connected to the first edge contact (132); and An antenna element (120) disposed on a second outer surface (139) of the substrate (130) opposite to the first outer surface (135) is electrically connected to a radio frequency (RF) circuit within the IC chip (110) via a conductive via (122), a conductive trace (168), and a first edge contact and a second edge contact (132, 112) extending within the substrate (130).

2. The antenna device according to claim 1, wherein, The electrical connection between the antenna element (120) and the RF circuit within the IC chip (110) is formed through the first edge contact and the second edge contact.

3. The antenna device according to claim 2, further comprising a conductive trace (165) on or within the first outer surface (135) and connected to the first edge contact (132), wherein, The electrical connection between the antenna element (120) and the RF circuit is formed through the conductive via (122) leading to the conductive trace (165).

4. The antenna device according to any one of claims 1 to 3, wherein: The cavity (140) has a bottom surface facing the bottom surface of the IC chip (110); and The conductive via (122) extends to the bottom surface of the cavity (140) and connects to the connection element of the RF circuit at the bottom surface of the IC chip (110).

5. The antenna device according to claim 4, wherein, The connecting element includes solder bumps.

6. The antenna device according to claim 5, wherein, The connecting element includes a conductive post.

7. The antenna device according to any one of claims 1 to 3, further comprising a ground plane (170) within the substrate (130).

8. The antenna device according to claim 7, wherein, The cavity (140) has a bottom surface facing the bottom surface of the IC chip (110), and a portion of the ground plane (170) is formed on the bottom surface of the cavity (140).

9. The antenna device according to any one of claims 1 to 3, wherein, The antenna element (120) is a first antenna element, and the antenna device further includes at least one second antenna element disposed on the second outer surface (139), the at least one second antenna element being electrically connected to the RF circuit within the IC chip (110) via at least one other conductive via (122) extending within the substrate (130) and connected to the at least one second antenna element.

10. The antenna device according to claim 9, wherein, The first antenna element and the second antenna element are part of an antenna array, and the RF circuit within the IC chip (110) includes a beamforming component for steering the beam formed by the antenna array.

11. The antenna device according to any one of claims 1 to 3, wherein, The first edge contact and the second edge contact are welded together.

12. The antenna device according to any one of claims 1 to 3, wherein, The sidewall (144) and the side surface (117) have corresponding first interlocking features and second interlocking features with complementary shapes, the first interlocking features and the second interlocking features interlocking with each other.

13. The antenna device according to claim 12, wherein, The first interlocking feature is a recess in the sidewall (144) or a protrusion from the sidewall (144), and the second interlocking feature is a complementary protrusion from the side surface (117) or a complementary recess in the side surface (117).

14. The antenna device according to claim 12, wherein, The first edge contact and the second edge contact are disposed on the corresponding surfaces of the first interlocking feature and the second interlocking feature.

15. The antenna device according to claim 12, wherein: The sidewall (144) is a first sidewall, and the cavity (140) has a second sidewall opposite to the first sidewall, wherein a third edge contact is formed on the second sidewall; and The side surface (117) is a first side surface, and the IC chip (110) has a second side surface opposite to the first side surface and a fourth edge contact on the second side surface connected to the third edge contact.

16. The antenna device according to any one of claims 1 to 3, wherein: The cavity (140) has a dual-cavity structure, the dual-cavity structure having a first cavity portion located directly below the second cavity portion, the first cavity portion having a first circumference smaller than the second circumference of the second cavity portion; The sidewall (144) is a first sidewall defining a portion of the first cavity portion, and the substrate (130) has a second sidewall defining a portion of the second cavity portion, wherein a third edge contact is formed on the second sidewall; The IC chip (110) is a first IC chip disposed within the first cavity portion; and The antenna device further includes a second IC chip disposed within the second cavity portion and having a fourth edge contact electrically connected to the third edge contact.

17. The antenna device according to claim 16, wherein, The first IC chip and the second IC chip are electrically coupled to each other.

18. The antenna device according to claim 17, wherein, The first IC chip includes an amplifier electrically coupled to the antenna element (120), and the second IC chip includes a beamforming network circuit coupled to the amplifier.

19. The antenna device according to claim 18, wherein, The first IC chip includes a first semiconductor material, and the second IC chip includes a second semiconductor material that is different from the first semiconductor material.

20. The antenna device according to claim 18, wherein, The top surface of the first IC chip is separated from the bottom surface of the second IC chip by an air gap or an underfill material.

21. A method for manufacturing an antenna device, comprising: A cavity (140) is formed in the first outer surface (135) of the substrate (130); An antenna element (120) is formed on a second outer surface (139) of the substrate (130) opposite to the first outer surface (135); A first edge contact (132) is formed at the sidewall (144) of the cavity (140); an integrated circuit (IC) chip (110) is provided, the IC chip having a second edge contact (112) formed on its side surface (117) and including radio frequency (RF) circuitry; the IC chip (110) is placed into the cavity (140); Electrically connect the first edge contact and the second edge contact; A conductive via (122) extending from the second outer surface (139) is formed within the substrate (130); as well as The antenna element (120) is electrically connected to the RF circuit through the conductive via (122), conductive trace (168), and first and second edge contacts (132, 112).

22. The method of claim 21, further comprising: Conductive traces (165) connected to the first edge contact (132) are formed within the substrate (130) on or within the first outer surface (135) of the substrate (130). Connect the conductive via (122) to the conductive trace (165); and The antenna element (120) is electrically connected to the conductive trace (165) through the conductive via (122), thereby connecting the antenna element (120) to the RF circuit.

23. The method according to claim 22, wherein, The cavity (140) has a bottom surface, and when the IC chip (110) is placed in the cavity (140), the IC chip (110) has a bottom surface facing the bottom surface of the cavity, and the method further includes: A connecting element is formed at the bottom surface of the cavity (140); The connection element is electrically connected to the RF circuit via electrical contacts at the bottom surface of the IC chip (110); and The conductive via (122) is connected to the connection element, thereby connecting the antenna element (120) to the RF circuit.

24. The method according to claim 22, wherein, The cavity (140) is formed to have a dual-cavity structure, the dual-cavity structure having a first cavity portion located directly below the second cavity portion, the first cavity portion having a first circumference smaller than the second circumference of the second cavity portion, the IC chip being a first IC chip, and placing the IC chip including placing the first IC chip within the first cavity portion; The cavity (140) is formed with sidewalls (144), the sidewalls being first sidewalls defining a portion of the first cavity portion, and a second sidewall of the substrate (130) defining a portion of the second cavity portion, and the method further includes: A third edge contact is formed on the second sidewall; The second IC chip with a fourth edge contact on its side surface (117) is placed into the second cavity portion; and The fourth edge contact is electrically connected to the third edge contact.

25. The method of claim 22, further comprising: A first interlocking feature is formed on the sidewall (144); A second interlocking feature having a shape complementary to the first interlocking feature is formed on the side surface; as well as The step of placing the IC chip (110) into the cavity (140) includes snapping the IC chip into the cavity (140) so that the first interlocking feature and the second interlocking feature become interlocked.

26. The method according to claim 25, wherein, The first interlocking feature is formed using laser drilling.

27. The method according to claim 25, wherein, The first interlocking feature is formed using optical imaging and etching.

28. The method of claim 25, comprising plating the first interlocking feature to form the first edge contact (132) on the surface of the first interlocking feature.

29. The method according to any one of claims 21 to 28, wherein, The substrate (130) includes an upper substrate (130b), a lower substrate (130a), and a ground plane (170) between the upper substrate and the lower substrate, and the formation of the cavity (140), the formation of the antenna element (120), the formation of the first edge contact (132), and the formation of the conductive via (122) include: The antenna element (120) is formed on the bottom surface of the lower substrate (130a); A ground plane (170) having at least one aperture is formed on the top surface of the lower substrate (130a); Cut at least one notch in the upper substrate and metallize the at least one notch; A notch is made in the upper substrate (130b) in a region adjacent to the notch, wherein the at least one notch forms the first edge contact (132) after the notch is made; The upper substrate (130b) is bonded to the lower substrate (130a), wherein the region cut from the upper substrate (130b) forms the cavity (140) after the bonding; and The conductive via (122) is formed through at least one opening in the ground plane (170).

30. A method for manufacturing an antenna array capable of being electronically steered, comprising: A plurality of cavities are formed within the substrate (130) and arranged spatially along the first outer surface (135) of the substrate (130); A plurality of antenna elements (120) are formed on a second outer surface (139) of the substrate (130) opposite to the first outer surface (135); A plurality of integrated circuit (IC) chips (110) are provided, each IC chip having a side surface having a corresponding second edge contact (112), and each IC chip including a beamforming component; For each of the cavities: A first edge contact (132) is formed on the side wall (144) of the cavity (140); One of the plurality of IC chips (110) is placed into the cavity (140); Electrically connect the corresponding first edge contact and second edge contact (112); and The beamforming component of the IC chip (110) therein is electrically connected to at least one of the corresponding antenna elements (120) via a conductive via (122), a conductive trace (168), and a first edge contact and a second edge contact (132, 112).

31. The method of claim 30, further comprising: A first interlocking feature is formed on the side surface of each of the IC chips (110); For each of the cavities: A second interlocking feature is formed on the sidewall (144), the second interlocking feature having a shape complementary to the first interlocking feature of the corresponding IC chip (110) to be placed therein; and The step of placing the corresponding IC chip (110) into the cavity (140) includes snapping the corresponding IC chip (110) into the cavity (140), so that the corresponding first interlock feature and the second interlock feature become interlocked.

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