Semiconductor device and method of forming a semiconductor device

Abstract

Semiconductor devices are described including a substrate and a first transistor located on the substrate. The first transistor includes a first gate structure, and the first gate structure includes a gate dielectric layer and a first work function layer located on the gate dielectric layer. The first gate structure also includes a cap layer located on the first work function layer. The semiconductor devices also include a second transistor located on the substrate, where the second transistor includes a second gate structure. The second gate structure includes a gate dielectric layer and a second work function layer located on the gate dielectric layer. The second gate structure also includes a first work function layer located on the second work function layer and a silicon cap layer located on the first work function layer. Embodiments of the invention also relate to methods of forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for forming semiconductor devices. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower cost continues to grow. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and fin field-effect transistors (finFETs). This scaling down has increased power consumption and parasitic capacitance in semiconductor devices. Summary of the Invention

[0003] Some embodiments of the present invention provide a semiconductor device, comprising: a substrate; a first transistor located on the substrate and including a first gate structure, wherein the first gate structure includes: a gate dielectric layer; a first power function layer located on the gate dielectric layer; and a capping layer located on the first power function layer; and a second transistor located on the substrate and including a second gate structure, wherein the second gate structure includes: the gate dielectric layer; a second power function layer located on the gate dielectric layer; the first power function layer located on the second power function layer; and the silicon capping layer located on the first power function layer.

[0004] Further embodiments of the present invention provide a semiconductor device, comprising: a substrate; a first full-to-all-gate field-effect transistor (GAA FET) located on the substrate, comprising: a first plurality of nanowires; a gate dielectric layer located on the first plurality of nanowires; and a first power function layer located on the gate dielectric layer; and a second full-to-all-gate field-effect transistor located on the substrate, comprising: a second plurality of nanowires; the gate dielectric layer located on the second plurality of nanowires; a second power function layer located on the gate dielectric layer; and the first power function layer located on the second power function layer.

[0005] Other embodiments of the present invention provide a method for forming a semiconductor device, comprising: depositing a gate dielectric layer on a plurality of nanowires formed in a first device region and a second device region; depositing a first power function material on the plurality of nanowires in the first device region and the second device region; removing a portion of the first power function material from the second device region to expose the gate dielectric layer, wherein the remaining portion of the first power function material forms a first power function layer; depositing a second power function material in the first device region and the second device region; removing a portion of the second power function material from the first device region to expose the first power function layer, wherein the remaining portion of the second power function material forms a second power function layer; and depositing a third power function layer in the first device region and the second device region, and on the first power function layer and the second power function layer. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A and Figures 1B to 1D Isometric views and cross-sectional views of a semiconductor device according to some embodiments are shown respectively.

[0008] Figure 2 This is a flowchart of a method for manufacturing a multi-threshold voltage semiconductor device according to some embodiments.

[0009] Figures 3A to 3C , Figures 4A to 4C , Figures 5A to 5D , Figures 6A to 6D Figures 7A to 7A Figure 7C , Figures 8A to 8C and Figures 9A to 9C Various views of a semiconductor device having multiple threshold voltages at various stages of its manufacturing process, according to some embodiments, are shown.

[0010] Figure 10 This is a flowchart of a method for forming multiple work function layers for a multi-threshold semiconductor device according to some embodiments.

[0011] Figures 11A to 11K Various cross-sectional views of a semiconductor device having multiple work function layers at various stages of its manufacturing process, according to some embodiments, are shown.

[0012] Figures 12A to 12B These are various views of a semiconductor device having a multi-threshold voltage device according to some embodiments.

[0013] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. As used herein, forming a first component on a second component means that the first component is formed in direct contact with the second component. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0015] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] It should be noted that references to "an embodiment," "embodiment," "exemplary embodiment," "exemplary," etc., in the specification refer to the fact that the described embodiment may include specific components, structures, or features, but each embodiment does not necessarily include specific components, structures, or features. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific component, structure, or feature is described in connection with an embodiment, whether explicitly described or not, implementing such a component, structure, or feature in conjunction with other embodiments is within the scope of knowledge of those skilled in the art.

[0017] It should be understood that the wording or terminology used herein is for descriptive and not restrictive purposes, so that those skilled in the art will interpret the terminology or terminology of this specification in light of the teachings herein.

[0018] As used herein, the term “selectivity” refers to the ratio of the etching rates of two materials under the same etching conditions.

[0019] As used herein, the term "high k" refers to a high dielectric constant. In the field of semiconductor device structure and manufacturing processes, high k refers to a dielectric constant greater than that of SiO2 (e.g., greater than 3.9).

[0020] As used herein, the term "p-type" is defined as a structure, layer, and / or region doped with a p-type dopant, such as boron.

[0021] As used herein, the term "n-type" is defined as a structure, layer, and / or region doped with an n-type dopant, such as phosphorus.

[0022] In some embodiments, the terms “about” and “basic” may indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%).

[0023] The present invention provides exemplary multi-threshold voltage field-effect transistor (FET) devices (e.g., gate-all-around (GAA) FETs, fin FETs, horizontal or vertical GAA fin FETs, or planar FETs) in semiconductor devices and / or integrated circuits (ICs) and exemplary methods of manufacturing thereof.

[0024] Multi-threshold voltage (MWV) integrated circuits (ICs) are commonly used in the semiconductor IC industry to optimize delay or power. A MWV IC can include several different devices, each with a different threshold voltage (e.g., operating voltage). For example, a MWV IC can include one or more low-threshold voltage devices and one or more high-threshold voltage devices. Methods for achieving different threshold voltages on semiconductor devices include variations in the work function layer thickness and ion implantation modulation. However, as technology nodes continue to shrink, functional density (e.g., the number of interconnect devices per chip region) has generally increased, while geometry (e.g., the smallest component (or line) that can be created using manufacturing processes) has decreased. For example, in a gate-all-around (GAA) FET, increasing the thickness of the work function layer to accommodate different threshold voltages consumes valuable IC device spacing, thus limiting the number of devices that can be fabricated on a single chip. On the other hand, varying the ion implantation in a GAA FET to achieve different threshold voltages is also challenging and can lead to non-compliance due to, for example, ion implantation shadowing effects.

[0025] Various embodiments of this invention describe methods for forming multi-threshold voltage devices. The embodiments described herein use a GAA FET as an example, but can be applied to other semiconductor structures, such as finFETs and planar FETs. The various embodiments described herein describe multiple deposition and patterning processes to form multilayer metal work function materials as work function layers in different device regions. For example, multiple devices with work function layers of different compositions can be formed on a substrate to form a semiconductor device with multiple threshold voltages. In some embodiments, work function layers formed from titanium silicon nitride (TiSiN) with various silicon atom concentrations can also be provided as aluminum diffusion layers. In some embodiments, multi-threshold voltage devices can be formed by implementing nitrogen-doped work function layers formed by various ammonium annealing processes. For example, nitrogen-doped work function layers can be formed from titanium aluminum carbonitride (TiAlCN). A double-layer hard mask can also be used to provide sufficient etch selectivity for different etchants during the manufacturing process. Additionally, multilayer work function materials can reduce gate resistance.

[0026] According to some embodiments, refer to Figures 1A to 1D A semiconductor device 100 having finFETs 102A-102D is described. Figure 1A An isometric view of a semiconductor device 100 according to some embodiments is shown. Figure 1B It shows along Figure 1A A cross-sectional view of line BB of semiconductor device 100. Figure 1C It shows Figure 1B Enlarged area C of the cross-sectional view. Figure 1D It shows along Figure 1A A cross-sectional view of line EE of semiconductor device 100 in the image.

[0027] In some embodiments, finFETs 102A-102D can be either p-type finFETs (PFETs) or n-type finFETs (NFETs), or one of each conductivity type of finFET. For example, finFETs 102A and 102B can be NFETs, while finFETs 102C and 102D can be PFETs. FinFETs 102A to 102D can have different threshold voltages by incorporating different work function metal layers. In some embodiments, finFET 102A can be an n-type low threshold voltage device, finFET 102B can be an n-type high threshold voltage device, finFET 102C can be a p-type high threshold voltage device, and finFET 102D can be a p-type low threshold voltage device. Although in Figures 1A to 1BFour finFETs are shown, but semiconductor device 100 may have any number of finFETs. Unless otherwise stated, the discussion of the elements with the same annotations, finFETs 102A-102D, applies to each other. The isometric views and cross-sectional views of semiconductor device 100 are shown for illustrative purposes and may not be drawn to scale.

[0028] Reference Figures 1A to 1B FinFETs 102A-102D can be formed on substrate 106. Substrate 106 can be a semiconductor material, such as, but not limited to, silicon. In some embodiments, substrate 106 comprises a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrate 106 comprises (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, indium gallium phosphide, gallium indium arsenide, gallium indium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide; or (iv) a combination thereof. Furthermore, substrate 106 can be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, substrate 106 can be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0029] The semiconductor device 100 may further include a fin structure 108 extending along the x-axis and through the finFETs 102A-102D. The fin structure 108 may include a fin base 108A and a fin top 108B disposed on the fin base 108A. In some embodiments, the fin base 108A may include a material similar to the substrate 106. The fin base 108A may be formed by photolithographic patterning and etching of the substrate 106. In some embodiments, the fin top 108B may include stacked fin portions 108B1, 108B2, 108B3, and 108B4 and an epitaxial region 110. Each of the stacked fin portions 108B1, 108B2, 108B3, and 108B4 may include a stack of semiconductor layers 122, which may be in the form of nanowires. Each semiconductor layer 122 may form a channel region located beneath the gate structure 112 of the finFETs 102A-102D.

[0030] In some embodiments, semiconductor layer 122 may comprise a semiconductor material similar to or different from substrate 106. In some embodiments, each of semiconductor layers 122 may comprise silicon germanium (SiGe) having Ge in the range of about 25 atomic percent to about 50 atomic percent (e.g., about 30 atomic percent, 35 atomic percent, or about 45 atomic percent), wherein any remaining atomic percent is Si, or may comprise Si without any real mass of Ge.

[0031] The semiconductor material of semiconductor layer 122 may be undoped or in-situ doped during its epitaxial growth process by using: (i) p-type dopants, such as boron, indium, or gallium; and / or (ii) n-type dopants, such as phosphorus or arsenic. For p-type in-situ doping, p-type doping precursors, such as diborane (B2H6), boron trifluoride (BF3), and / or other p-type doping precursors, may be used. For n-type in-situ doping, n-type doping precursors, such as phosphine (PH3), arsenic (AsH3), and / or other n-type doping precursors, may be used. Semiconductor layer 122 may have a corresponding vertical dimension 122t (e.g., thickness) along the z-axis, each vertical dimension ranging from about 6 nm to about 10 nm (e.g., about 7 nm, about 8 nm, or about 9.5 nm). Other dimensions and materials of semiconductor layer 122 are within the scope and spirit of the invention. Although in Figures 1A to 1B The diagram shows four semiconductor layers 122, but the semiconductor device 100 can have any number of semiconductor layers 122.

[0032] Reference Figures 1A to 1B An epitaxial fin region 110 may be grown on a region not located below the fin base 108A of the gate structure 112. In some embodiments, the epitaxial fin region 110 may have any geometry, such as a polygon or a circle. The epitaxial fin region 110 may include an epitaxially grown semiconductor material. In some embodiments, the epitaxially grown semiconductor material is the same material as the substrate 106. In some embodiments, the epitaxially grown semiconductor material includes a material different from the material of the substrate 106. The epitaxially grown semiconductor material may include: (i) a semiconductor material, such as germanium or silicon; (ii) a compound semiconductor material, such as gallium arsenide and / or aluminum gallium arsenide; or (iii) a semiconductor alloy, such as silicon germanium and / or gallium arsenide phosphide.

[0033] Reference Figure 1CIn some embodiments, each of the epitaxial fin regions 110 may have a height 110t. In some embodiments, the epitaxial fin height 110t may be equal to or different from the vertical dimension H2 of the fin tip 108B. In some embodiments, the epitaxial fin height 110t may be in the range of about 10 nm to about 100 nm (e.g., about 30 nm, about 50 nm, about 70 nm, or about 80 nm). Other dimensions of the epitaxial fin regions 110 are within the scope and spirit of the invention.

[0034] In some embodiments, the epitaxial fin region 110 may be grown by: (i) chemical vapor deposition (CVD), such as low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), or any suitable CVD; (ii) molecular beam epitaxy (MBE) process; (iii) any suitable epitaxial process; or (iv) a combination thereof. In some embodiments, the epitaxial fin region 110 may be grown by an epitaxial deposition / partial etching process, which repeats the epitaxial deposition / partial etching process at least once. This repeated deposition / partial etching process is also referred to as a cyclic deposition-etch (CDE) process.

[0035] The epitaxial fin regions 110 can be n-type for NFETs 102A-102B and p-type for PFETs 102C-102D. In some embodiments, the epitaxial fin regions 110 of finFETs 102A, 102B, 102C, and 102D can have the same or opposite doping types relative to each other. The p-type epitaxial fin regions 110 can contain SiGe and can be in-situ doped with p-type dopant, such as boron, indium, or gallium, during the epitaxial growth process. For p-type in-situ doping, p-type doping precursors, such as, but not limited to, diborane (B2H6), boron trifluoride (BF3), and / or other p-type doping precursors, can be used. In some embodiments, the n-type epitaxial fin regions 110 can contain Si and can be in-situ doped with n-type dopant, such as phosphorus or arsenic, during the epitaxial growth process. For n-type in-situ doping, n-type doping precursors, such as, but not limited to, phosphine (PH3), arsenic (AsH3), and / or other n-type doping precursors, can be used.

[0036] Reference Figure 1BThe epitaxial fin region 110 can form the source / drain (S / D) region of the finFETs 102A-102D. Each channel region in the semiconductor layer 122 of the stacked fin portions 108B1 to 108B4 can be located between a pair of S / D regions. Although the finFETs 102A-102D are shown as having a fin structure 108 with stacked fin portions 108B1 to 108B4 located on the fin base 108A, other fin structures of the finFETs 102A-102D (e.g., monolayer fin structures etched from or epitaxially grown on the substrate 106) are within the scope and spirit of the present invention.

[0037] In some embodiments, the fin base 108A and the fin top 108B may have corresponding vertical dimensions H1 and H2 (e.g., height) along the z-axis, each in the range of about 40 nm to about 60 nm (e.g., about 45 nm, about 50 nm, or about 55 nm). The vertical dimensions H1 and H2 may be equal to or different from each other, and may have dimensions such that the sum of H1 and H2 (i.e., the total height H of the fin structure 108) is... T The value is in the range of about 80 nm to about 120 nm (e.g., about 85 nm, about 90 nm, about 100 nm, or about 115 nm). In some embodiments, the fin structure 108 may have a horizontal dimension L1 (e.g., length) along the x-axis in the range of about 100 nm to about 1 μm (e.g., about 200 nm, about 300 nm, about 500 nm, about 750 nm, or about 900 nm). The horizontal dimension L1 of the fin structure 108 may be at least 100 nm to prevent strain relaxation in the fin structure 108, and therefore, to prevent strain relaxation in the channel region formed in the semiconductor layer 122 below the gate structure 112. Other dimensions and materials of the fin structure 108 are within the scope and spirit of the invention.

[0038] In some embodiments, the finFET 102A-102D may further include a gate structure 112 and a spacer 114. (Refer to...) Figures 1A to 1D The gate structure 112 can be a multilayer structure and can enclose the stacked fin portions 108B1 to 108B4. In some embodiments, each of the semiconductor layers 122 of the stacked fin portions 108B1 to 108B4 can be enclosed by a gate structure 112 or one or more layers of a gate structure 112. Therefore, the gate structure 112 can also be referred to as a "gate all-around (GAA) structure" or a "horizontal gate all-around structure", and the finFETs 102A-102D can also be referred to as "GAA FET" or "GAAfinFET".

[0039] Each gate structure 112 may include a gate dielectric layer 112A disposed on the semiconductor layer 122 and a gate electrode 112B disposed on the gate dielectric layer 112A. For example... Figure 1D As shown, the gate dielectric layer 112A can enclose each semiconductor layer 122, and thus, during the operation of the finFETs 102A-102D, the semiconductor layers 122 are electrically isolated from each other and electrically isolated from the conductive gate electrode 112B to prevent short circuits between the gate structure 112 and the S / D region. In some embodiments, the gate dielectric layer 112A may include (i) a silicon oxide, silicon nitride, and / or silicon oxynitride layer formed by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), electron beam evaporation, or other suitable processes; (ii) a high-k dielectric material, such as HfO2, titanium oxide (TiO2), tantalum oxide (Ta2O3), HfSiO4, zirconium oxide (ZrO2), zirconium silicate (ZrSiO2); (iii) a high-k dielectric material having an oxide of lithium (Li), beryllium (Be), magnesium (Mg), Ca, Sr, Sc, Y, Zr, Al, La, Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), Gd, terbium (Tb), Dy, holmium (Ho), Er, thulium (Tm), ytterbium (Yb), or argonium (Lu); or (iv) a combination thereof. High-k dielectric layers can be formed by ALD and / or other suitable methods.

[0040] Figure 1D A cross-sectional view of a PFET 102D is shown. In some embodiments, the PFET 102D may include a gate electrode 112B, which includes a gate barrier layer (not shown), a gate function layer 130D, and a gate metal fill layer 132. Figure 1D As shown, each of the semiconductor layers 122 can be enclosed by a gate barrier layer and a gate function layer 130D. Depending on the spacing between adjacent semiconductor layers 122 and the thickness of the layers of the gate structure 112, the semiconductor layers 122 can be enclosed by one or more layers of gate electrodes 112B filling the spacing between adjacent semiconductor layers 122. According to some embodiments, although Figure 1D The diagram shows that the gate metal fill layer 132 partially encloses the semiconductor layer 122, but the gate metal fill layer 132 may also enclose the semiconductor layer 122 to fill the gaps between adjacent semiconductor layers 122 (not shown).

[0041] In some embodiments, the gate barrier layer may serve as a nucleation layer for subsequent formation of the gate work function layers 130A-130D and / or may help prevent metal (e.g., Al) from sufficiently diffusing from the gate work function layers 130A-130D to the underlying layers (e.g., the gate dielectric layer 112A or oxide layer). Each gate barrier layer may comprise titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other suitable diffusion barrier materials, and may be formed by ALD, PVD, CVD, or other suitable metal deposition processes. In some embodiments, the gate barrier layer may comprise a substantially fluorine-free metal or a metal-containing film, and may be formed by ALD or CVD using one or more non-fluorine-based precursors. The substantially fluorine-free metal or fluorine-free metal-containing film may comprise fluorine contaminants in ionic, atomic, and / or molecular form in amounts less than 5 atomic percentages. In some embodiments, each gate barrier layer may have a thickness ranging from about 1 nm to about 10 nm. Other materials, formation methods, and thicknesses of the gate barrier layer are within the scope and spirit of the invention.

[0042] Each gate power function layer 130A-130D may include a single power function layer or a stack of power function layers. Multiple threshold voltages can be achieved by configuring the power function layers of the FinFETs 102A-102D, allowing the threshold voltages to differ between devices. In some embodiments, the power function layer 130A of the NFET 102A may include a titanium aluminum carbide layer, a silicon capping layer, and a titanium nitride layer. In some embodiments, the power function layer 130B of the NFET 102B may include a first titanium nitride layer, a titanium aluminum carbide layer, a silicon capping layer, and a second titanium nitride layer. In some embodiments, the power function layer 130C of the PFET 102C may include a tantalum nitride layer, a titanium aluminum carbide layer, a silicon capping layer, and a titanium nitride layer. In some embodiments, the power function layer 130D of the PFET 102D may include a tungsten carbonitride layer, a titanium aluminum carbide layer, a silicon capping layer, and a titanium nitride layer. Variations in the composition of the power function layers provide power function layers with different power function values ​​than each other. (Refer to...) Figures 11A to 11E The formation of the power function layers 130A-130D is described in further detail.

[0043] In some embodiments, each gate function layer 130A-130D may comprise any suitable material. In some embodiments, the stack of function layers may comprise aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN), titanium aluminum (TiAl), aluminum titanium nitride (TiAlN), tungsten nitride (WN), metal alloys, and / or combinations thereof. In some embodiments, each gate function layer 130A-130D may comprise an Al-doped metal, such as Al-doped Ti, Al-doped TiN, Al-doped Ta, or Al-doped TaN. The gate function layers 130A-130D may be formed using suitable processes such as ALD, CVD, PVD, plating, or combinations thereof. In some embodiments, each gate power function layer 130A-130D may have a thickness ranging from about 2 nm to about 15 nm (e.g., about 2 nm, about 3 nm, about 5 nm, about 10 nm, or about 15 nm). Other materials, formation methods, and thicknesses of the gate power function layers 130A-130D are within the scope and spirit of the present invention.

[0044] Each gate metal fill layer 132 may comprise a single metal layer or a stack of metal layers. The stack of metal layers may comprise metals different from each other. In some embodiments, each gate metal fill layer 132 may comprise a suitable conductive material such as Ti, silver (Ag), Al, titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), metal alloys, and / or combinations thereof. The gate metal fill layer 132 may be formed by ALD, PVD, CVD, or other suitable deposition processes. Other materials and methods of forming the gate metal fill layer 132 are within the scope and spirit of the invention. Although the gate structures 112 of the illustrated finFETs 102A-102D are similar, the finFETs 102A-102D can have gate structures with different materials and / or electrical characteristics (e.g., threshold voltage, work function) than each other. Furthermore, although the illustrated gate structure 112 has a horizontal GAA structure, other gate structures (e.g., vertical GAA structures or gate structures without a GAA structure) are also within the scope and spirit of this invention.

[0045] Reference Figures 1A to 1C According to some embodiments, spacer 114 may form a sidewall of gate structure 112 and have partial physical contact with gate dielectric layer 112A. Spacer 114 may include an insulating material, such as silicon oxide, silicon nitride, a low-k material, or a combination thereof. Spacer 114 may include a single layer or a stack of insulating layers. Spacer 114 may be a low-k material with a dielectric constant less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8). In some embodiments, spacer 114 may include a material composed of silicon, oxygen, carbon, and / or nitrogen. The concentrations of silicon, oxygen, carbon, and nitrogen in the material used for spacer 114 may depend on the desired dielectric constant used for spacer 114. Varying concentrations of silicon, oxygen, carbon, and nitrogen in the material may change the desired dielectric constant of spacer 114. In some embodiments, each spacer 114 may include a silicon oxynitride (SiOCN) layer, a silicon carbonitride (SiCN) layer, a silicon carbide (SiOC) layer, or a combination thereof. In some embodiments, each spacer 114 may include a stack of SiOCN layers disposed on a SiOC layer (the SiOC layer being disposed on a SiOCN layer). In some embodiments, each spacer 114 may have a thickness S ranging from about 5 nm to about 12 nm. t (For example, about 5nm, about 6nm, about 8nm, about 10nm, or about 12nm). Other materials and dimensions of spacer 114 are within the scope and spirit of the invention.

[0046] Figures 1C to 1D This is a cross-sectional view of a PFET 120D. (See diagram below.) Figure 1C As shown, an internal spacer structure 127 can be formed between the epitaxial fin region 110 and the power function layer 130D. The internal spacer structure 127 can reduce the parasitic capacitance of the finFET 102-102D. Each internal spacer structure 127 can have a low-k material with a dielectric constant less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8) or a high-k material with a dielectric constant in the range from about 4 to about 7. In some embodiments, the internal spacer structure 127 can include a stack of monolayers or dielectric layers. In some embodiments, the internal spacer structure 127 can include a suitable dielectric material composed of silicon, oxygen, carbon, and / or nitrogen. The concentrations of silicon, oxygen, carbon, and nitrogen in the dielectric material used for the internal spacer structure 127 can depend on the desired dielectric constant. Varying concentrations of silicon, oxygen, carbon, and nitrogen in the internal spacer structure 127 can change its desired dielectric constant. The internal spacer structure 127 can use SiOC, SiCN, SiOCN, SiN, silicon oxide (SiO2). x ), silicon oxynitride (SiO) yN) and / or combinations thereof are formed by deposition via ALD, flowable CVD (FCVD) or other suitable methods.

[0047] Reference Figures 1A to 1D The semiconductor device 100 may further include an etch stop layer (ESL) (not shown), an interlayer dielectric (ILD) layer 118, and a shallow trench isolation (STI) region 138. The ESL may protect the gate structure 112 and / or the epitaxial fin region 110. For example, this may be achieved by forming the ILD layer 118 and / or the S / D contact structure (…). Figures 1A to 1D This protection is provided during (not shown in the image). The ESL can be disposed on the sidewall of the spacer 114. In some embodiments, the ESL may include, for example, silicon nitride (SiN). x ), silicon dioxide (SiO) x Silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbonitride (SiCBN), or combinations thereof. In some embodiments, the ESL may comprise silicon nitride or silicon oxide formed by low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), or silicon oxide formed by a high aspect ratio process (HARP). In some embodiments, the ESL may have a thickness ranging from about 3 nm to about 30 nm. Other materials, formation methods, and thicknesses used for the ESL are within the scope and spirit of this invention.

[0048] The ILD layer 118 may be disposed on the ESL and may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon carbide). For example, flowable silicon oxide may be deposited using flowable CVD (FCVD). In some embodiments, the dielectric material is silicon oxide. In some embodiments, the ILD layer 118 may have a thickness 118t ranging from about 50 nm to about 200 nm. Other materials, thicknesses, and formation methods for the ILD layer 118 are within the scope and spirit of the invention.

[0049] STI region 138 can provide electrical isolation between finFETs 102A-102D having fin structures 108 and adjacent finFETs having different fin structures (not shown) located on substrate 106 and / or between adjacent active and passive elements (not shown) integrated or deposited on substrate 106. In some embodiments, STI region 138 may include a first protective pad 138A and a second protective pad 138B, and an insulating layer 138C disposed on the second protective pad 138B. The first protective pad 138A and the second protective pad 138B may include materials different from each other. Each of the first protective pad 138A and the second protective pad 138B may include an oxide or nitride material. In some embodiments, the first protective pad 138A may include a nitride material, the second protective pad 138B may include an oxide material, and can prevent sidewall oxidation of the fin top 108B during the process of forming the insulating layer 138C. In some embodiments, the insulating layer 138C may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. In some embodiments, each of the first protective pad 138A and the second protective pad 138B may have a thickness ranging from about 1 nm to about 2 nm. In some embodiments, the STI region 138 may have a vertical dimension 138 along the z-axis ranging from about 40 nm to about 60 nm (e.g., about 45 nm, about 50 nm, or about 55 nm). H (For example, height). In some embodiments, the vertical dimension is 138. H The total height H of the fin structure 108 can be T Half of it.

[0050] The cross-sectional shapes of the semiconductor device 100 and its elements (e.g., fin structure 108, gate structure 112, epitaxial fin region 110, spacer 114, internal spacer structure 127 and / or STI region 138) are illustrative and not limiting.

[0051] Figure 2 This is a flowchart of a method 200 for manufacturing a semiconductor device 100 according to some embodiments. For illustrative purposes, reference will be made to a method for manufacturing such a device. Figures 3A to 12B Description of the manufacturing process of the example semiconductor device 100 shown Figure 2 The operations shown are optional and may be performed in different orders depending on the specific application. It should be noted that method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes can be provided before, during, and after method 200, and only a few other processes are briefly described herein. For simplicity, Figure 3A to Figure 12B and Figures 1A to 1D Similar elements in the text are labeled with the same annotation.

[0052] Reference Figure 2 In operation 205, according to some embodiments, a fin structure is formed on a substrate. For example, a fin structure 108 having a fin base 108A and a fin tip 108B can be formed on a substrate 106, as shown in reference 105. Figures 3A to 3C As described. The formation of the fin structure 108 may include the formation of a fin base 108A and a fin tip 108B* on the substrate 106, such as Figures 3A to 3C As shown. The subsequent processing of the fin tip 108B* as described below can form the fin tip 108B, as referenced. Figures 1A to 1D As stated above.

[0053] The fin top 108B* may include a first semiconductor layer 320 and a second semiconductor layer 122 stacked in an alternating configuration. Each of the first semiconductor layer 320 and the second semiconductor layer 122 may be epitaxially grown on its underlying layer and may include semiconductor materials different from each other. In some embodiments, the first semiconductor layer 320 and the second semiconductor layer 122 may include semiconductor materials similar to or different from the substrate 106. In some embodiments, the first semiconductor layer 320 and the second semiconductor layer 122 may include semiconductor materials having different oxidation rates and / or etch selectivity than each other. In some embodiments, each of the first semiconductor layer 320 and the second semiconductor layer 122 may include silicon germanium (SiGe) having Ge in the range of about 25 atomic percent to about 50 atomic percent (e.g., about 30 atomic percent, 35 atomic percent, or about 45 atomic percent), with any remaining atomic percent being Si, or may include Si without any real mass Ge.

[0054] The first semiconductor layer 320 and / or the second semiconductor layer 122 may be undoped or in-situ doped during their epitaxial growth process by using (i) p-type dopants, such as boron, indium, or gallium; and / or (ii) n-type dopants, such as phosphorus or arsenic. For p-type in-situ doping, p-type doping precursors, such as diborane (B2H6), boron trifluoride (BF3), and / or other p-type doping precursors, may be used. For n-type in-situ doping, n-type doping precursors, such as phosphine (PH3), arsenic (AsH3), and / or other n-type doping precursors, may be used. The first semiconductor layer 320 and the second semiconductor layer 122 may have corresponding vertical dimensions 320t and 122t (e.g., thicknesses) along the z-axis, each in the range of about 6 nm to about 10 nm (e.g., about 7 nm, about 8 nm, or about 9.5 nm). The vertical dimensions 320t and 122t may be equal to or different from each other. Figures 3A to 3C The diagram shows four semiconductor layers 320 and 122, but the semiconductor device 100 can have any number of semiconductor layers 320 and 122.

[0055] Forming the fin base 108A and fin top 108B* may include forming a stack of materials for the first semiconductor layer 320 and the second semiconductor layer 122 on the substrate 106, and etching portions of the substrate 106 and the material stack by patterned hard mask layers 340 and 342 formed on the material stack. In some embodiments, the hard mask layer 340 may be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. In some embodiments, the hard mask layer 342 may be formed from silicon nitride using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced CVD (PECVD). Etching of the material stack may include dry etching, wet etching processes, or combinations thereof. Dry etching processes may include using oxygen-containing gases, fluorine-containing gases, chlorine-containing gases, bromine-containing gases, iodine-containing gases, other suitable etching gases, and / or plasma, or combinations thereof. Wet etching processes may include etching in solutions of dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH), or combinations thereof.

[0056] In some embodiments, the fin base 108A and the fin top 108B* may have corresponding vertical dimensions H1 and H2 (e.g., height) along the z-axis, each in the range of about 40 nm to about 60 nm (e.g., about 45 nm, about 50 nm, or about 55 nm). The vertical dimensions H1 and H2 may be equal to or different from each other, and may have such that the sum of H1 and H2 (i.e., the total height H of the fin structure 108) T The value is in the range of about 80 nm to about 120 nm (e.g., about 85 nm, about 90 nm, about 100 nm, or about 115 nm). In some embodiments, the fin structure 108 may have a horizontal dimension L1 (e.g., length) along the x-axis in the range of about 100 nm to about 1 μm (e.g., about 200 nm, about 300 nm, about 500 nm, about 750 nm, or about 900 nm). In some embodiments, the fin structure 108 may have a tapered cross-section along the yz plane, wherein the horizontal dimension W1 (e.g., width) along the y-axis of the fin base 108A is greater than the horizontal dimension W2 along the y-axis of the fin top 108B*. The horizontal dimensions W1 and W2 may be in the range of about 6 nm to about 20 nm (e.g., about 6 nm, about 8 nm, about 10 nm, about 15 nm, about 17 nm, or about 20 nm).

[0057] Reference Figure 2In operation 210, according to some embodiments, an STI region is formed on the substrate. (See also...) Figures 4A to 4C An STI region 138 having a first protective pad 138A, a second protective pad 138B, and an insulating layer 138C can be formed on the substrate 106. Forming the STI region 138 may include (i) in Figure 3A (ii) depositing a nitride material layer (not shown) for the first protective gasket 138A on the structure; (iii) depositing an oxide material layer (not shown) for the second protective gasket 138B on the nitride material layer; (iv) depositing an insulating material layer for the insulating layer 138C on the oxide material layer; (iv) annealing the insulating material layer of the insulating layer 138C; (iv) chemically mechanically polishing (CMP) the annealed layers of the nitride and oxide material layers and the insulating material; and (vi) etching back polishing the structure to form... Figure 4A The structure.

[0058] Layers of nitride and oxide materials can be deposited using suitable processes for depositing oxide and nitride materials, such as ALD or CVD. These oxide and nitride material layers can prevent oxidation of the sidewalls of the fin top 108B* during the deposition and annealing of the insulating material 138C used for the insulating layer.

[0059] In some embodiments, the insulating material layer for insulating layer 138C may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or a low-k dielectric material. In some embodiments, the insulating material layer may be deposited using a CVD process, a high-density plasma (HDP) CVD process, or using silane (SiH4) and oxygen (O2) as reaction precursors. In some embodiments, the insulating material layer may be formed using a subatmospheric pressure CVD (SACVD) process or a high aspect ratio process (HARP), wherein the process gas may include tetraethoxysilane (TEOS) and / or ozone (O3).

[0060] In some embodiments, the insulating material layer can be formed by depositing flowable silicon oxide using a flowable CVD (FCVD) process. The FCVD process can then be a wet annealing process. The wet annealing process can include annealing the deposited insulating material layer in vapor at a temperature ranging from about 200°C to about 700°C for a time ranging from about 30 min to about 120 min. The wet annealing process can then be a CMP process to remove the patterned hard mask layers 340 and 343, as well as a portion of the nitride, oxide, and insulating material for layers 138A-138C, such that the top surface of the nitride, oxide, and insulating material layers is aligned with the top surface 108s of the fin structure 108. Figures 4A to 4CThe CMP process is fundamentally coplanar. The CMP process can then be followed by an etching process to etch layers of nitrides, oxides, and insulating materials to form... Figure 4A The structure.

[0061] Etching of nitride, oxide, and insulating layers can be performed using dry etching, wet etching, or a combination thereof. In some embodiments, a dry etching process may include plasma dry etching using a gas mixture (containing octafluorocyclobutane (C4F8), argon (Ar), oxygen (O2), and helium (He); fluoroform (CHF3) and He; carbon tetrafluoride (CF4), difluoromethane (CH2F2), chlorine (Cl2), and O2, hydrogen bromide (HBr), O2, and He, or combinations thereof) at pressures ranging from about 1 mTorr to about 5 mTorr. In some embodiments, a wet etching process may include treatment with dilute hydrofluoric acid (DHF), ammonium peroxide mixtures (APM), sulfur peroxide mixtures (SPM), hot deionized water (DI water), or combinations thereof. In some embodiments, a wet etching process may include using ammonia (NH3) and hydrofluoric acid (HF) as etchants and inert gases such as Ar, xenon (Xe), He, or combinations thereof. In some embodiments, the flow rates of HF and NH3 used in the wet etching process can be in the range of about 10 sccm to about 100 sccm (e.g., about 20 sccm, 30 sccm, or 40 sccm, respectively). In some embodiments, the wet etching process can be carried out at a pressure in the range of about 5 mTorr to about 100 mTorr (e.g., about 20 mTorr, about 30 mTorr, or about 40 mTorr) and at a high temperature in the range of about 50°C to about 120°C.

[0062] In some embodiments, the first protective liner 138A and the second protective liner 138B may have corresponding thicknesses 138At and 138Bt in the range of about 1 nm to about 2 nm. In some embodiments, the STI region 138 may have a vertical dimension 138 along the z-axis in the range of about 40 nm to about 60 nm (e.g., about 45 nm, about 50 nm, or about 55 nm). H (For example, height). In some embodiments, the vertical dimension is 138. H The total height H of the fin structure 108 can be T Half of it. Other materials, methods of forming, and dimensions of STI region 138 are within the scope and spirit of this invention.

[0063] Reference Figure 2 In operation 215, according to some embodiments, a protective oxide layer is formed on the fin structure, and a polycrystalline silicon structure is formed on the protective oxide layer. For example, as... Figure 5AAs shown in Figure 5D, a protective oxide layer 134* can be formed on the fin structure 108 and the STI region 138, and polycrystalline silicon structures 112A*-112D* can be formed on the protective oxide layer 134*. The formation of the protective oxide layer 134* can include... Figure 4A The protective oxide layer 134* is deposited in a blanket manner on the structure followed by a high-temperature annealing process. The protective oxide layer 134* may comprise a suitable oxide material, such as silicon oxide, and can be blanket-deposited using a suitable deposition process, such as CVD, ALD, plasma-enhanced ALD (PEALD), physical vapor deposition (PVD), or electron beam evaporation. In some embodiments, the oxide material layer can be deposited using PEALD at an energy range from about 400 W to about 500 W and a temperature range from about 300 °C to about 500 °C. The deposition of the oxide material layer can then be a dry annealing process under an oxygen flow at a temperature range from about 800 °C to about 1050 °C. The oxygen precursor concentration can be in the range of about 0.5% to about 5% of the total gas flow rate. In some embodiments, the annealing process can be a rapid annealing process, wherein the annealing time can be between about 0.5 s and about 5 s (e.g., about 1 s, about 2 s, or about 5 s).

[0064] In some embodiments, the protective oxide layer 134* may have a vertical dimension 134t* along the z-axis (e.g., the thickness on the top surface of the fin structure 108) and a horizontal dimension 134s* along the y-axis (e.g., the thickness on the sidewall of the fin top 108B*), each in the range of about 1 nm to about 3 nm (e.g., about 1 nm or 2 nm). In some embodiments, the dimension 134t* may be equal to or greater than the dimension 134s*. Other oxide materials, formation methods, and thicknesses of the protective oxide layer 134* are within the scope and spirit of the invention. The presence of the protective oxide layer 134* allows for... Figure 5A The high aspect ratio spacing 646 (e.g., aspect ratio greater than 1:15, 1:18 or 1:20) between the adjacent polysilicon structures 112A*-112D* shown etches the polysilicon, while substantially not etching and / or damaging the fin structure 108 during the formation of the polysilicon structures 112A*-112D*.

[0065] In some embodiments, when the finFETs 102A-102D are used as non-input / output (non-I / O) devices in core circuitry (also referred to as "logic circuitry" or "memory circuitry") formed in the core region (also referred to as "logic region" or "memory region") of an integrated circuit (IC), the protective oxide layer 134* may be removed during a subsequent gate replacement process. In some embodiments, the non-I / O device may be a core device, logic device, and / or memory device not configured to directly handle input / output voltage / current. In some embodiments, the non-I / O device includes a logic gate, such as, for example, NAND, NOR, INVERTER, or a combination thereof. In some embodiments, the non-I / O device includes a memory device, such as a static random access memory (SRAM) device. In some embodiments, when the finFETs 102A-102B are used as I / O devices in peripheral circuitry (e.g., I / O circuitry) formed in the peripheral region (also referred to as "I / O region" or "high voltage region") of the IC, the protective oxide layer 134* may not be removed and may form part of the gate dielectric layer of the gate structure 112. I / O devices can be configured to process the input / output voltage / current of an IC and can withstand larger voltage or current swings than non-I / O devices.

[0066] The formation of the protective oxide layer 134* can then be as follows: Figures 5A to 5D The polysilicon structures 112A*-112D* shown are formed. During subsequent processing, the polysilicon structures 112A*-112D* can be replaced in a gate replacement process to form the gate structures 112 of the FinFETs 102A-102D, respectively. Figure 1A As shown. In some embodiments, the formation of the polysilicon structures 112A*-112D* may include blanket deposition of a polysilicon material layer on a deposited protective oxide layer 134* and a patterned hard mask layer 644 formed on the polysilicon material layer. Figures 5A to 5D (As shown) Etching of the polysilicon material layer. In some embodiments, the polysilicon material may be undoped, and the hard mask layer 644 may include an oxide layer and / or a nitride layer. The oxide layer may be formed using a thermal oxidation process, and the nitride layer may be formed using LPCVD or PECVD. The hard mask layer 644 can protect the polysilicon structures 112A*-112D* from damage by subsequent processing steps (e.g., during the formation of spacer 114, epitaxial fin region 110, and / or ILD layer 118).

[0067] The blanket deposition of a polycrystalline silicon material layer can include CVD, PVD, ALD, or other suitable deposition processes. In some embodiments, etching of the deposited polycrystalline silicon material layer can include dry etching, wet etching, or a combination thereof. In some embodiments, etching the deposited polycrystalline silicon material layer to form a polycrystalline silicon structure 112A*-112D* can include four etching steps. The first polycrystalline silicon etching step can include using a gas mixture containing hydrogen bromide (HBr), oxygen (O2), fluoroform (CHF3), and chlorine (Cl2). The second polycrystalline silicon etching step can include using a gas mixture containing HBr, O2, Cl2, and nitrogen (N2) at a pressure of 45 mTorr to 60 mTorr. The third polycrystalline silicon etching step can include using a gas mixture containing HBr, O2, Cl2, N2, and argon (Ar) at a pressure of about 45 mTorr to about 60 mTorr. The fourth polycrystalline silicon etching step can include using a gas mixture containing HBr, O2, Cl2, and N2 at a pressure of about 45 mTorr to about 60 mTorr. The first polysilicon etching step can have a higher polysilicon etching rate than the second, third, and / or fourth polysilicon etching steps. The first polysilicon etching step is used to etch unwanted portions of the polysilicon blanket deposition layer above the fin structure 108. The second, third, and fourth polysilicon etching steps are used to etch unwanted portions of the polysilicon blanket deposition layer within the high aspect ratio spacing 646.

[0068] In some embodiments, the vertical dimension G of the polycrystalline silicon structure 112A*-112D* along the z-axis H It can be in the range of about 100 nm to about 150 nm (e.g., about 100 nm, about 120 nm, about 135 nm, or 150 nm). In some embodiments, the horizontal dimension G of the polycrystalline silicon structure 112A*-112D* along the x-axis is... L It can be in the range from about 3nm to about 30nm (e.g., about 3nm, about 5nm, about 7nm, about 10nm, about 12nm, about 15nm, about 20nm, or about 30nm). The polycrystalline silicon structures 112A*-112D* can have a high aspect ratio equal to or greater than about 9 (e.g., about 10, about 12, about 15, about 18, or about 20), where the aspect ratio is the dimension G. H With size G L The ratio. In some embodiments, the horizontal dimension 648 (e.g., spacing) along the x-axis between adjacent polysilicon structures 112A*-112D* can range from about 40 nm to about 90 nm (e.g., about 40 nm, about 50 nm, about 60 nm, about 80 nm, or about 90 nm). In some embodiments, the horizontal dimension 648 between adjacent polysilicon structures can be different. The value of dimension 648 and dimension GL The sum of these values ​​is referred to as “one contact polysilicon pitch (1 CPP)”. In some embodiments, the horizontal dimension L1 of the fin structure along the x-axis can be at least 3 CPP to prevent strain relaxation in the fin structure 108, and thus, as described above, strain relaxation can be prevented in the channel region formed in the stacked fin portion of the second semiconductor layer 122 below the gate structure 112.

[0069] Reference Figure 2 In operation 220, according to some embodiments, spacers are formed on the sidewalls of the polysilicon structure, and the tops of the fins are etched. (See also...) Figures 6A to 6D Spacers 114 can be formed on the sidewalls of the polycrystalline silicon structures 112A*-112D*. Forming the spacers 114 can include using CVD, PVD, or ALD processes. Figure 5A The structure involves a blanket deposition of layers of insulating material (e.g., oxide, nitride, and / or silicon carbonitride), followed by photolithography and etching processes (e.g., active ion etching or other dry etching processes using chlorine or fluorine-based etchants). According to some embodiments, each spacer 114 may have a horizontal dimension S along the x-axis ranging from about 5 nm to about 12 nm. t (e.g., thickness). The formation of spacer 114 can then be achieved by etching a protective oxide layer 134* in areas never covered by the polysilicon structures 112A*-112D* and spacer 114 to form an oxide layer 134 located beneath the polysilicon structures 112A*-112D* (e.g., thickness). Figures 6A to 6D (As shown). The etching process may include a wet etching process using, for example, diluted HF.

[0070] Vertical etching of the portion of the fin top 108B* can be performed after the oxide layer 134 is formed. Vertical etching includes etching of the fin top 108B* that is not located beneath the spacer 114 and the polysilicon structures 112A*-112D*, and may include a bias etching process. The bias etching process can be performed at a pressure ranging from about 1 mTorr to about 1000 mTorr, a power ranging from about 50 W to 1000 W, a bias voltage ranging from about 20 V to about 500 V, a temperature ranging from about 40 °C to about 60 °C, and using HBr and / or Cl2 as the etching gas. During the bias etching process, the polysilicon structures 112A*-112D* can be protected from etching by the hard mask layer 644 and the spacer 114.

[0071] Reference Figure 2 In operation 225, according to some embodiments, a horizontal etching process is performed to form an internal spacer structure in the fin structure. (See also...) Figures 7A to 7CThe vertical etching of the portion of the fin top 108B* can then be followed by horizontal etching of the portion of the first semiconductor layer 320 below the polysilicon structure 112A*-112D* and spacer 114 to form a recessed region. Figure 7B yes Figure 7A The enlarged view of region 720 is shown. Figure 7C It is observed from the CC line. Figure 7B The diagram shows a cross-sectional view of the structure. Horizontal etching can be performed using dry etching, wet etching, or a combination thereof. The etching process may include multiple etching and cleanup process cycles, such as about 3 to about 20 etching and cleanup process cycles. The etching process in each cycle may include the use of a gas mixture containing hydrogen fluoride (HF), nitrogen trifluoride (NF3), a fluorine-based gas, and a chlorine-based gas. The gas ratio of the HF and NF3 gas mixture to the fluorine-based gas may range from about 2 to about 30 (e.g., about 2, about 5, about 10, about 15, about 20, or about 30). The gas ratio of the HF and NF3 gas mixture to the chlorine-based gas may range from about 2 to about 40 (e.g., about 2, about 5, about 10, about 15, about 20, about 30, or about 40). The cleanup process in each cycle may include the use of a gas mixture containing HF and nitrogen (N2). For subsequent cycles, the HF in the cleanup process may remove byproducts and / or clean the surface of the etched portion. In each cycle, the cleanup process may be longer than the etching process.

[0072] The process of forming the recessed region may subsequently involve blanket deposition of a dielectric material layer followed by horizontal etching of the blanket-deposited dielectric material layer to form the internal spacer structure 127 within the recessed region. In some embodiments, the blanket deposition process may include multiple deposition and etching process cycles. In each cycle, an etching process may be performed after the deposition process to prevent the formation of voids within the internal spacer structure 127 by removing any cracks that may have formed during the deposition of the dielectric material layer in the recessed region.

[0073] The internal spacer structure 127 may include a stack of monolayer or dielectric layers deposited by ALD, FCVD, or other suitable methods. The etching process in each cycle of the blanket deposition process of the dielectric material layer may include a dry etching process using a gas mixture of HF and NH3. The HF to NH3 gas ratio may be in the range of about 1 to about 20 (e.g., about 1, about 5, about 10, about 15, or about 20). The internal spacer structure 127 may include a suitable dielectric material composed of silicon, oxygen, carbon, and / or nitrogen. The carbon concentration in the dielectric material may be low and may be in the range of about 1% to about 15% (e.g., about 1.5%, about 2.5%, about 5%, about 10%, or about 13%), because a carbon concentration exceeding this range can result in longer etching times and reduced etching selectivity.

[0074] The horizontal etching process for blanket-deposited dielectric material layers to form the internal spacer structure 127 can be implemented using a dry etching process employing a gas mixture of HF and NH3. The HF to NH3 gas ratio can range from about 1 to about 20 (e.g., about 1, about 5, about 10, about 15, or about 20). In some embodiments, the internal spacer structure 127 may have a dimension 127t1 (e.g., thickness) along the x-axis in the range of about 3 nm to about 12 nm (e.g., about 3 nm, about 5 nm, about 8 nm, or about 10 nm). Other deposition methods and horizontal etching processes for forming the internal spacer structure 127, as well as other suitable dimensions of the internal spacer structure 127, are within the scope and spirit of the invention.

[0075] Reference Figure 2 In operation 230, epitaxial fin regions are formed on the fin structure, and nanowires are formed between the epitaxial fin regions. (Refer to...) Figures 8A to 8C The extended fin region 110 can grow on the exposed surface of the fin base 108A and Figure 7A The exposed surface of the second semiconductor layer 122 of the structure. Figure 8B yes Figure 8A The enlarged view of region 820 is shown. Figure 8C It is along the CC line Figure 8B A cross-sectional view of the structure.

[0076] In some embodiments, a portion of the epitaxial fin region 110 may be located below the spacer 114 and / or extend into the fin base 108A. In some embodiments, the epitaxial fin region 110 may be grown by: (i) CVD, such as low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), or any suitable CVD; (ii) molecular beam epitaxy (MBE) process; (iii) any suitable epitaxial process; or (iv) a combination thereof. In some embodiments, the epitaxial fin region 110 may be grown by an epitaxial deposition / partial etching process, which is repeated at least once. In some embodiments, the epitaxial fin region 110 may be grown by selective epitaxial growth (SEG), wherein an etching gas is added to promote selective growth of the semiconductor material on the exposed surfaces of the second semiconductor layer 122 and the fin base 108A, rather than on the insulating material.

[0077] In some embodiments, the epitaxial fin region 110 may be p-type or n-type. In some embodiments, the p-type epitaxial fin region 110 may include SiGe and may be in-situ doped with a p-type dopant, such as boron, indium, or gallium, during the epitaxial growth process. For p-type in-situ doping, p-type doping precursors may be used, such as, but not limited to, diborane (B2H6), boron trifluoride (BF3), and / or other p-type doping precursors. In some embodiments, the n-type epitaxial fin region 110 may include Si without any real Ge and may be in-situ doped with an n-type dopant, such as phosphorus or arsenic, during the epitaxial growth process. For n-type in-situ doping, n-type doping precursors may be used, such as, but not limited to, phosphine (PH3), arsine (AsH3), and / or other n-type doping precursors.

[0078] Each epitaxial fin region 110 can form an S / D region for the FinFET 102A-102D. A second semiconductor layer 122 located below the polysilicon structures 112A*-112D* and between adjacent S / D regions can form the channel region of the FinFET 102A-102D. In subsequent processing, the first semiconductor layer 320 of the stacked fin portions 108B1-108B4 below the polysilicon structures 112A*-112D* is replaced with one or more layers of the gate structure 112 (e.g., ...). Figures 7A to 7B As shown, a full-ring gate GAA structure can be formed to enclose each channel region.

[0079] In some embodiments, during the vertical etching process described in operation 225, the fin base 108A below the etched portion of the fin top 108B located between the spacers 114 can be recessed. The interface 848 between the epitaxial fin region 110 and the fin base 108A can be coplanar with or below the top surface of the STI region 138. Other dimensions and configurations of the epitaxial fin region 110 are within the scope and spirit of the invention.

[0080] The process for forming the epitaxial region 110 may subsequently involve removing the stacked fin portions 108B1-108B4 of the first semiconductor layer 320 to form a second semiconductor layer 122 in the shape of a nanowire, as shown below. Figure 8A to Figure 8C As shown. The first semiconductor layer 320 can be removed by an etching process performed at a pressure ranging from about 1 mTorr to about 1000 mTorr, a power ranging from 50 W to 1000 W, a bias voltage ranging from about 20 V to about 500 V, a temperature ranging from about 40 °C to about 60 °C, and using HBr and / or Cl2 as etching gases. Other etching methods are within the scope and spirit of this invention.

[0081] Removing the first semiconductor layer 320 may then be followed by forming an etch stop layer (ESL) (not shown) on the spacer 114 and the epitaxial fin region 110. The formation of the ILD layer 118 on the ESL may use a deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon carbide). For example, flowable silicon oxide may be deposited using an FCVD process. The deposition process may then be followed by thermal annealing of the deposited dielectric material layer in vapor at a temperature ranging from about 200°C to about 700°C for a duration ranging from about 30 min to about 120 min.

[0082] The process of forming the ILD layer 118 may subsequently remove the polysilicon structures 112A*-112D* using a dry etching process (e.g., reactive ion etching) or a wet etching process. In some embodiments, the gaseous etchant used in the dry etching process may include chlorine, fluorine, bromine, or combinations thereof. In some embodiments, ammonium hydroxide (NH4OH), sodium hydroxide (NaOH), and / or potassium hydroxide (KOH) wet etching may be used to remove the polysilicon structures 112A*-112D*, and the polysilicon structures 112A*-112D* may also be removed using dry etching followed by a wet etching process. Exposed portions of the oxide layer 134 may be removed using a dry etching process (e.g., reactive ion etching), a wet etching process (e.g., using diluted HF), or combinations thereof. In some embodiments, the gaseous etchant used in the dry etching process may include chlorine, fluorine, bromine, or combinations thereof. In some embodiments, the oxide layer 134 may not be removed.

[0083] Reference Figure 2 In operation 235, a gate dielectric layer is formed on the nanowire. (See reference...) Figure 9A to Figure 9C The gate dielectric layer 112A can be wrapped around the exposed nanowire-shaped second semiconductor layer 122 of the stacked fin portions 108B1-108B4. Forming the gate dielectric layer 112A can include a blanket deposition process of a suitable gate dielectric material layer. Figure 8A A blanket deposition of the gate dielectric material layer for the gate dielectric layer 112A is used in the structure. The gate dielectric layer 112A can be formed to have a thickness 112t in the range of about 1.5 nm to about 2 nm (e.g., about 1.5 nm, about 1.7 nm, about 1.8 nm, or about 2 nm). The gate dielectric material of the gate dielectric layer 112A is shown above. Figures 1A to 1D The description has been provided, and for simplicity, will not be described in detail here. In some embodiments, an interlayer dielectric is provided before depositing the gate dielectric layer 112A. Figures 9A to 9C (Not shown in the image). In some embodiments, the interlayer dielectric may have approximately The thickness. In some embodiments, the thickness of the interlayer dielectric can be approximately... Peace Treaty Between. In some embodiments, the thickness of the gate dielectric layer 112A can be between approximately Peace Treaty Between (for example, in about Peace Treaty Between or in the period Peace Treaty (between). For example, the thickness of the gate dielectric layer 112A can be approximately Other deposition methods and dimensions of the gate dielectric layer 112A are within the scope and spirit of this invention.

[0084] Reference Figure 2 In operation 240, according to some embodiments, a power function layer is formed on the gate dielectric layer. Power function layers 130A-130D are respectively formed as components of finFETs 102A-102D. Figure 10 This is a flowchart of a method 1000 for forming a functional layer on a gate dielectric layer according to some embodiments. Method 1000 may include multiple process cycles, wherein each process cycle may include one or more deposition, blocking, and etching processes. Method 1000 is an example for implementing operation 240. For illustrative purposes, reference will be made to... Figures 11A to 11K The exemplary manufacturing process described in the method 1000 illustrates the operation. Figures 11A to 11K yes Figure 9A Enlarged views of regions 930A-930D are shown to illustrate an exemplary manufacturing process for method 1000 used to form functional layers 130A-130D, and for simplicity... Figures 11A to 11K Other structures are omitted. Depending on the specific application, the operations in method 1000 may be performed in a different order or not at all. It should be noted that method 1000 may not produce a complete semiconductor device. Therefore, it should be understood that additional processes may be provided before, during, and after method 1000, and only some of these other processes are briefly described here.

[0085] Each function layer 130A-130D formed using method 1000 may include one or more function metal layers and may provide multiple threshold voltages on the finFETs 102A-102D, thereby allowing devices formed on the substrate 106 to have different threshold voltages. In some embodiments, finFETs 102A and 102B are NFETs, while finFETs 102C and 102D are PFETs. In some embodiments, finFETs 102A and 102D are low threshold voltage devices, while finFETs 102B and 102C are high threshold voltage devices. Multiple function layers can also reduce gate contact resistance by providing resistance matching between the layers. Resistance matching can be achieved by adjusting the deposition parameters of the function layers.

[0086] Reference Figure 10 In operation 1002, according to some embodiments, a first work function material and multiple layers are deposited on the gate dielectric layer. (See also...) Figure 11AA first power-function material 1102* and a hard mask layer 1104 are disposed on the gate dielectric layer 112A. A barrier layer 1106 is formed in region 930C and on the hard mask layer 1104. In some embodiments, the first power-function material 1102* and the hard mask layer 1104 are blanket-deposited on the gate dielectric layer 112A and Figures 9A to 9C Other exposed surfaces of the semiconductor structure shown. Thus, the first work function material 1102* and the hard mask layer 1104 are deposited in regions 930A-930D. In some embodiments, the first work function material 1102* may be a tantalum nitride layer. In some embodiments, the first work function material 1102* may be a work function layer for a p-type FinFET device. For example, the first work function material 1102* may include Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, Ag, TaC, TaSiN, TaCN, TiAl, TiAlN, WN, metal alloys, and / or combinations thereof. In some embodiments, the thickness of the first work function material 1102* may be approximately... Peace Treaty Between. For example, the first work function material 1102* can have approximately The thickness of the first function material 1102* is such that a greater thickness can provide sufficient variation in the threshold voltage of the semiconductor device, but also leaves a smaller deposition window for subsequent layers. The hard mask layer 1104 can be blanket-deposited on the first function material 1102*. In some embodiments, the hard mask layer 1104 can be formed of a suitable hard mask material, such as titanium nitride, silicon nitride, silicon carbonitride, and any suitable material. For example, the hard mask layer 1104 can be formed of titanium nitride. In some embodiments, the thickness of the hard mask layer 1104 can be approximately... Peace Treaty Between. For example, hard mask layer 1104 can have approximately The thickness of the first function material 1102* and the hard mask layer 1104 can be formed using deposition methods such as ALD, CVD, PVD, any suitable deposition method, and / or combinations thereof. In some embodiments, the first function material 1102* can be deposited at a temperature between about 225°C and about 325°C. For example, the deposition temperature can be between about 225°C and about 275°C, between about 275°C and about 300°C, between about 300°C and about 325°C, or any other suitable temperature. In some embodiments, the first function material 1102* can be deposited using pentamethyldimethylaminotantalum (PDMAT) and ammonia as precursors for depositing conformal tantalum nitride material. In some embodiments, the deposition chamber pressure can be between about 2 Torr and about 5 Torr. For example, the deposition chamber pressure can be between about 2 Torr and about 3 Torr, between about 3 Torr and about 5 Torr, or any other suitable chamber pressure.

[0087] In some embodiments, the hard mask layer 1104 may be one or more hard mask layers. For example, the hard mask layer 1104 may include a dual-layer structure comprising a first hard mask layer located on the first work function material 1102* and a second hard mask layer formed on the first hard mask layer. The first and second hard mask layers may be formed of different materials to improve etch selectivity, which in turn provides better protection for the underlying first work function material during subsequent etching processes. In some embodiments, the first hard mask layer may be a tantalum nitride layer, and the second hard mask layer may be a titanium nitride layer. In some embodiments, the first hard mask layer may have approximately Peace Treaty The thickness between [the specified values]. For example, the thickness of the first hard mask layer can be approximately [the specified value]. In some embodiments, the second hard mask layer may have a thickness similar to that of the first hard mask layer. For example, the thickness of the second hard mask layer may be approximately [missing information]. In some embodiments, the second hard mask layer may have a different thickness range than the first hard mask layer. For example, the second hard mask layer may have... to approximately The thickness is within the range of [specific range]. In some embodiments, the second hard mask layer may have approximately [specific thickness]. The thickness. Because the bilayer structure can be one or more types of materials, it can provide varying etch selectivity, thus providing protection against the use of multiple etchants in subsequent processes. In some embodiments, the hard mask layer formed from tantalum nitride can be formed by an ALD process using penta(dimethylamino)tantalum (PDMAT) and ammonia as precursors. The ALD process can include multiple pulse / purge cycles of the precursors, repeated until the nominal thickness of the hard mask layer is achieved. For example, the pulse / purge cycles used to form the tantalum nitride hard mask layer can include at least about 10 pulse / purge cycles to obtain a uniform layer. In some embodiments, additional pulse / purge cycles can be used to obtain a greater thickness. In some embodiments, the ALD process for forming the tantalum nitride hard mask layer can be performed at a chamber pressure between about 2 Torr and about 5 Torr. In some embodiments, titanium tetrachloride and ammonia can be used as precursors to form a titanium nitride hard mask layer via an ALD process. The pulse / purge cycles used in the ALD process for forming the titanium nitride hard mask layer can include at least about 30 pulse / purge cycles to achieve a uniform layer. In some embodiments, more pulse / purge cycles can be used to achieve a greater thickness. In some embodiments, the ALD process for forming the titanium nitride hard mask layer can be performed at a temperature between about 400°C and about 450°C. The hard mask layer can be removed after etching the underlying layer. For example, the titanium nitride hard mask layer can be removed by a suitable wet chemical etching process and a subsequent cleaning process, such as a cleaning process using deionized water, ammonium hydroxide, and hydrogen peroxide. In some embodiments, the tantalum nitride hard mask layer can be removed by a dry etching process, such as a plasma etching process using tantalum chloride.

[0088] A barrier layer 1106 may be formed on a hard mask layer 1104 in region 930C. The barrier layer 1106 can be formed by blanket deposition of a barrier material on the hard mask layer 1104 followed by a patterning process. For example, the barrier layer 1106 may be formed of a photoresist material, and forming the barrier layer 1106 may include a patterning process that exposes the deposited photoresist material to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element protecting the underlying hard mask layer 1104 in region 930C.

[0089] Reference Figure 10In operation 1004, according to some embodiments, an etching process is performed to remove portions of the deposited first function material to form a first function layer in the first device region. Referring to FIG11B, an etching process is performed to remove the hard mask layer 1104 and portions of the first function material not protected by the barrier layer 1106. In some embodiments, the hard mask material 1104 can be removed by a wet etching process. The hard mask layer 1104 can be etched away using chemical solutions such as ammonium hydroxide, hydrogen peroxide, any suitable etching solution, and / or combinations thereof. The hard mask layer 1104 can also be removed by dry etching. In some embodiments, the etching process continues until the underlying first function material 1102* is exposed. The exposed first function material 1102* can be removed by a dry etching process, such as a dry etching process including an etchant (containing an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas, an iodine-containing gas, other suitable etching gases, and / or plasma, or combinations thereof). In some embodiments, the first work function material 1102* formed using tantalum nitride can be etched away using tantalum chloride as a dry etching precursor. The etching process removing the portion of the first work function material 1102* can be performed until the underlying gate dielectric layer 112A is exposed, as shown below. Figure 11B As shown. The remaining first power function material 1102* is formed in the first device region (such as region 930C) as the first power function material 1102.

[0090] Reference Figure 10 In operation 1006, according to some embodiments, a second work function material is deposited on the gate dielectric layer and the first work function layer. (Refer to...) Figure 11C The second work function material 1108* is deposited on the exposed surface of the structure shown in FIG. 11B. In some embodiments, the second work function material 1108* may be different from the first work function material 1102*. For example, the first work function material 1102* may be formed of tantalum nitride, while the second work function material 1108* may be formed of titanium nitride. In some embodiments, the first work function material 1102* and the second work function material 1108* may be formed of the same material. In some embodiments, the thickness of the second work function material 1108* may be approximately Peace Treaty Between. For example, the second work function material 1108* can have approximately The thickness of the second work function material 1108*. A greater thickness allows for a sufficient change in the threshold voltage of the semiconductor device, but retains a smaller deposition window for any subsequently formed layers. For example... Figure 11CAs shown, the second function material 1108* can be deposited substantially conformally in regions 930A-930D. For example, the second function material 1108* can be deposited using a substantially conformal deposition method, such as ALD or CVD. In some embodiments, the second function material 1108* can be deposited at a temperature between about 400°C and about 450°C. For example, the deposition temperature can be between about 400°C and about 420°C, between about 420°C and about 435°C, between about 435°C and about 450°C, or any other suitable temperature. In some embodiments, the second function material 1108* can be deposited using titanium chloride and ammonia as precursors for depositing conformal titanium nitride material. In some embodiments, the deposition chamber pressure can be between about 2 Torr and about 10 Torr. For example, the deposition chamber pressure can be between about 2 Torr and about 5 Torr, between about 5 Torr and about 10 Torr, or any other suitable chamber pressure.

[0091] The barrier layer 1109 may be formed on the second work function material 1108* in region 930B. In some embodiments, the formation and composition of the barrier layer 1109 may be similar to those described above. Figure 11A The barrier layer 1106 described herein will not be described in detail here for simplicity. For example, the barrier layer 1109 may be a photoresist material and may be formed using patterning and etching processes.

[0092] Reference Figure 10 In operation 1008, according to some embodiments, an etching process is performed to remove a portion of the second function material to form a second function layer in the second device region. (Refer to...) Figure 11D A portion of the second function material 1108* can be removed from regions 930A, 930C, and 930D, and the remaining second function material 1108* forms a second function layer 1108 in region 930B. A barrier layer 1110 can be used to protect the underlying second function material 1108* while a suitable etching process removes the exposed second function material 1108* from regions 930A, 930C, and 930D. In some embodiments, the etching process for etching away the portions of the second function material 1108* can be a wet chemical etching process. For example, a chemical solution can be used to etch away the second function material 1108* formed using titanium nitride, such as ammonium hydroxide, hydrogen peroxide, any suitable etching solution, and / or combinations thereof. In some embodiments, a dry etching process can be used to remove portions of the second function material 1108*. The etching process can continue until the underlying gate dielectric layer is exposed in regions 930A and 930D, and the first function layer 1102 is exposed in region 930C. The remaining second power function material 1108* forms a second power function layer 1108 in a second device region (such as region 930B).

[0093] Reference Figure 10 In operation 1010, according to some embodiments, a third work function material is deposited on the gate dielectric layer and the first and second work function layers. (Refer to...) Figure 11E The third work function material 1110* is deposited in Figure 11D On the exposed surface of the semiconductor structure shown. For example, a third work function material 1110* is blanket-deposited on the gate dielectric layer 112A, the first work function layer 1102, the second work function layer 1108, and other exposed surfaces of the semiconductor structure. In some embodiments, the thickness of the third work function material 1110* can be approximately Peace Treaty Between. For example, the third work function material 1110* can have approximately The greater thickness of the third function material 1110* provides sufficient variation in the threshold voltage of the semiconductor device, but also leaves a smaller deposition window for subsequent layers. The third function material 1110* can be formed of the same or different function metal as the first function material 1102* or the second function material 1108*. For example, the third function material 1110* can be formed using tungsten carbonitride. In some embodiments, the third function material 1110* can be formed using titanium nitride or tantalum nitride. The third function material 1110* can be formed using a substantially conformal deposition process, such as ALD or CVD. In some embodiments, a barrier layer 1112 can be formed in region 930D ​​and on a portion of the third function material 1110*. In some embodiments, the formation and composition of the barrier layer 1112 can be similar to those described above. Figure 11A and Figure 11C The barrier layers 1106 and 1109 described herein are not described in detail here for simplicity. For example, barrier layer 1112 may be a photoresist material and may be formed using patterning and etching processes. Barrier layer 1112 may be used to protect the underlying third functional material 1110* during subsequent manufacturing processes.

[0094] Reference Figure 10 In operation 1012, according to some embodiments, an etching process is performed to remove a portion of the third function material to form a third function layer in the third device region. (Refer to...) Figure 11FA portion of the third function material 1110* can be removed from regions 930A, 930B, and 930C, and the remaining third function material 1110* forms a third function layer 1110 in region 930D. A barrier layer 1112 can be used to protect the underlying third function material 1110* while a suitable etching process removes the exposed third function material 1110* from regions 930A, 930B, and 930C. In some embodiments, the etching process for etching away the portions of the third function material 1110* can be a wet chemical etching process. For example, a chemical solution, such as an ozone deionized aqueous solution or any other suitable etching solution, can be used to etch away the third function material 1110* formed using tungsten carbonitride. In some embodiments, a dry etching process can also be used to remove portions of the third function material 1110*. The etching process can continue until the underlying gate dielectric layer in region 930A is exposed, the first function layer 1102 in region 930C is exposed, and the second function layer 1108 in region 930B is exposed. The remaining third power function material 1110* forms a third power function layer 1110 in a third device region (such as region 930D).

[0095] Reference Figure 10 In operation 1014, according to some embodiments, a fourth power function layer is deposited, and a silicon capping layer is formed on the gate dielectric layer in the fourth device region, as well as on the first power function layer, the second power function layer, and the third power function layer. (Refer to...) Figure 11G ,exist Figure 11F A fourth power function layer 1114 and a silicon capping layer 1116 are formed on the exposed surface of the semiconductor structure shown. Portions of the fourth power function layer 1114 and the silicon capping layer 1116 may be formed in a fourth device region (such as region 930A). In some embodiments, the fourth power function layer 1114 may be formed of titanium aluminum carbide. In some embodiments, the fourth power function layer may be formed of a material similar to or different from the first power function layer 1102, the second power function layer 1108, or the third power function layer 1110. In some embodiments, the thickness of the fourth power function layer 1114 may be approximately... Peace Treaty Between. For example, the fourth work function layer 1114 can have approximately The greater thickness of the fourth work function layer 1114 provides sufficient variation in the threshold voltage of the semiconductor device, but also leaves a smaller deposition window for subsequent layers, which may result in undesirable voids or defects. Figure 11GAs shown, the fourth function layer 1114 can be deposited substantially conformally in regions 930A-930D. For example, the fourth function layer 1114 can be deposited using a substantially conformal deposition method, such as ALD or CVD. In some embodiments, the fourth function layer 1114 can be deposited at a temperature between about 300°C and about 380°C. For example, the deposition temperature can be between about 300°C and about 340°C, between about 340°C and about 365°C, between about 365°C and about 385°C, or any other suitable temperature. In some embodiments, the fourth function layer 1114 can be deposited using titanium chloride and triethylaluminum as precursors for depositing conformally conformal titanium aluminum carbide materials. In some embodiments, the deposition chamber pressure can be between about 2 Torr and about 3 Torr, or any other suitable chamber pressure. For example, the deposition chamber pressure can be about 3 Torr.

[0096] A silicon capping layer 1116 can be formed on the fourth function layer 1114 by performing a processing process on the fourth function layer 1114. In some embodiments, the processing process may include an in-situ thermal treatment process using titanium chloride and silane as precursors. In some embodiments, the silicon capping layer 1116 may be formed of oxidized silicon, such as silicon dioxide. The silicon capping layer 1116 can prevent oxidation of the underlying fourth function layer 1114. The silicon capping layer 1116 can be formed by a suitable process, such as titanium chloride and silane treatment. In some embodiments, the processing process may be performed at a temperature between about 420°C and about 480°C. For example, the processing temperature may be between about 420°C and about 440°C, between about 440°C and about 460°C, between about 460°C and about 480°C, or any other suitable temperature. In some embodiments, the processing temperature may be about 450°C to prevent oxidation of the fourth function layer 1114. In some embodiments, the silicon capping layer 1116 may have a temperature of about 450°C. Peace Treaty The thickness between.

[0097] Reference Figure 10 In operation 1016, according to some embodiments, an adhesive layer is deposited. Referring to FIG11H, an adhesive layer 1118 may be formed on the silicon capping layer 1116 in regions 930A-930D. In some embodiments, the adhesive layer 1118 may be formed of titanium nitride, titanium, tantalum, tantalum nitride, any suitable adhesive material and / or combinations thereof. The adhesive layer 1118 may prevent peeling of the underlying layer and promote adhesion of the subsequently formed gate electrode. In some embodiments, the adhesive layer 1118 may be formed using a substantially conformal deposition process, such as ALD or CVD. In some embodiments, the adhesive layer 1118 may also affect the finFET threshold voltage and be considered as another work function layer. In some embodiments, the adhesive layer 1118 may have approximately Peace Treaty The thickness between. For example, adhesive layer 1118 may have a thickness between approximately Peace Treaty Between, in the agreement Peace Treaty Between or in the period Peace Treaty The thickness between [the specified values]. In some embodiments, the adhesive layer 1118 may have a thickness of about 15 [units]. A greater thickness of the adhesive layer 1118 can more effectively prevent fluorine from diffusing from subsequently deposited gate electrode material, such as tungsten deposited via a CVD process.

[0098] Thus, exemplary method 1000 forms power function layers 130A-130D in regions 930A-930D that can provide multiple threshold voltages for finFETs 102A-102D. For example... Figure 11H As shown, the power function layer 130A of NFET 102A may include a fourth power function layer 1114, a silicon capping layer 1116, and an adhesive layer 1118. The power function layer 130B of NFET 102B may include a second power function layer 1108, a fourth power function layer 1114, a silicon capping layer 1116, and an adhesive layer 1118. The power function layer 130C of PFET 102C may include a first power function layer 1102, a fourth power function layer 1114, a silicon capping layer 1116, and an adhesive layer 1118. The power function layer 130D of PFET 102D may include a third power function layer 1110, a fourth power function layer 1114, a silicon capping layer 1116, and an adhesive layer 1118. The variation in the composition of the power function layers 130A-130D provides different power function values, thereby generating different threshold voltages. Although the exemplary method 1000 forms a function layer in four GAA devices, it can be applied to form any suitable number of semiconductor devices, such as two semiconductor devices, six semiconductor devices or more.

[0099] In some embodiments, the power function layers 130A-130D may further include power function layers that not only provide multi-threshold voltage devices but also serve as diffusion barrier layers to prevent metal diffusion. For example, a silicon-doped titanium nitride power function layer can prevent aluminum (e.g., aluminum titanium carbide) from other power function layers from diffusing into the underlying gate dielectric. Figure 11I Work function layers 1120, 1122, and 1124, which can replace work function layers 1102, 1108, and 1110, are shown formed in regions 930B-930D. Work function layers 1120, 1122, and 1124 not only provide multiple threshold voltages for the FinFETs 102A-102D but also provide diffusion barrier layers to prevent metal diffusion. For simplicity, Figure 11I The one shown in the middle is the same as Figures 11A to 11HOther similar structural tags have the same annotations.

[0100] Power function layers 1120, 1122, and 1124 are formed in regions 930D, 930C, and 930B, respectively, and may be formed of titanium silicon nitride (TiSiN). In some embodiments, other suitable semiconductor materials, such as tantalum silicon nitride (TaSiN), may be used. In some embodiments, power function layers 1120, 1122, and 1124 may contain different silicon atom concentrations to provide multiple threshold voltages on finFETs 102B-102D. Since finFET 102A does not include a TiSiN power function layer, it has a different threshold voltage than finFETs 102B-102D. The thickness of power function layers 1120, 1122, and 1124 may be approximately [missing information - likely a number]. Peace Treaty Between. For example, the thickness of the power function layers 1120, 1122, and 1124 can be approximately The greater thickness of the power function layers 1120, 1122, and 1124 can provide a greater variation in the threshold voltage, but also leave a smaller window for subsequent material deposition into the trench.

[0101] You can use something like "about" Figure 10 and Figures 11A to 11H The deposition, barrier, and etching fabrication processes of the described method 1000 form functional layers 1120, 1122, and 1124 in regions 930B-930D, respectively. For example, a first functional material for forming functional layer 1120 can be disposed on gate dielectric layer 112A in regions 930A-930D in a cover manner. A barrier layer is formed in region 930D ​​but not in regions 930A-930C through patterning and etching processes. Figure 11I (Not shown in the image). The barrier layer may include one or more hard mask layers. For example, the barrier layer may include a bilayer structure comprising a first hard mask layer located on a deposited first work function material and a second hard mask layer formed on the first hard mask layer. The first and second hard mask layers may be formed of different materials to provide better etch selectivity, which in turn provides better protection for the underlying first work function material during subsequent etching processes. In some embodiments, the first hard mask layer may be a tantalum nitride layer, and the second hard mask layer may be a titanium nitride layer. In some embodiments, the first hard mask layer may have approximately Peace Treaty The thickness between [the specified values]. For example, the thickness of the first hard mask layer can be approximately [the specified value]. In some embodiments, the second hard mask layer may have a thickness similar to that of the first hard mask layer. For example, the thickness of the second hard mask layer may be approximately [missing information]. Because a dual-layer structure can contain more than one type of material, it can provide varying etch selectivity, thus offering protection against the use of multiple etchants in subsequent processes. The deposited first functional material can be removed from regions 930A-930C, where no barrier layer with a dual-layer structure exists, using one or more etch processes, and a functional layer 1120 is formed in region 930D. The barrier layer can be removed after the functional layer 1120 is formed.

[0102] Similarly, functional layers 1122 and 1124 can be formed in regions 930C and 930B, respectively, using one or more deposition, barrier, and etching processes. For example, a second functional material for forming functional layer 1122 can be blanket-deposited into regions 930A-930D, and a barrier layer can be formed on the deposited second functional material in region 930C, protecting the underlying second functional material while one or more etching processes remove the second functional material from regions 930A, 930B, and 930D ​​to form functional layer 1122. In some embodiments, the barrier layer can be a bilayer structure, which may include a tantalum nitride layer and a titanium nitride layer. A similar deposition, barrier, and etching process can be used to form functional layer 1124 in region 930B. For example, the third power function material can be blanket-deposited in regions 930A-930D, and a barrier layer can be formed on the deposited third power function material in region 930B. While the barrier layer protects the underlying third power function material, one or more etching processes remove the third power function material from regions 930A, 930C and 930D ​​to form power function layer 1124.

[0103] Work function layers 1120, 1122, and 1124 can be silicon-doped titanium nitride layers with the same or different silicon atom concentrations. For example, work function layer 1120 can have a higher silicon atom concentration than work function layers 1122 or 1124. In some embodiments, work function layer 1120 can have a silicon atom concentration between about 35% and about 50%. In some embodiments, work function layer 1122 can have a silicon atom concentration between about 20% and about 35%. In some embodiments, work function layer 1124 can have a silicon atom concentration between about 5% and about 20%. In some embodiments, work function layers 1120 and 1122 can be used to form a p-type low threshold voltage device 102D and a p-type standard threshold voltage device 102C, respectively. In some embodiments, work function layer 1124 can be used to form an n-type standard threshold voltage device 102B.

[0104] In some embodiments, the function layers 1120, 1122, and 1124 may be deposited using suitable deposition processes such as ALD, CVD, PVD, sputtering, any suitable deposition method, and / or combinations thereof. The function layers 1120, 1122, and 1124 may be deposited using a multi-cycle deposition process, such as an ALD process. The deposition process may include one or more deposition cycles using suitable precursors. For example, precursors may include titanium tetrachloride, silane, ammonia, any suitable precursor, and / or combinations thereof. In some embodiments, the deposition process may also include suitable pulse and purge cycles. For example, a deposition process for depositing silicon-doped titanium nitride may include first and second pulse / purge cycles. In some embodiments, the first pulse / purge cycle may include pulse and purge a first precursor of titanium tetrachloride, and subsequently pulse and purge a second precursor of ammonia for a nominal amount of time in the deposition chamber to allow a chemical reaction to form titanium nitride. The first pulse / purge cycle may then be a second pulse / purge cycle. The second pulse / purge cycle may be used to implant silicon into the titanium nitride formed in the first pulse / purge cycle. The second pulse / clean cycle can use suitable precursors, such as a first precursor of silane and a second precursor of ammonia. The second pulse / clean cycle can be repeated more than once to increase the silicon atom concentration in the titanium nitride layer. Performing more second pulse / clean cycles can provide a greater silicon concentration in the formed silicon-doped titanium nitride layer. Additionally, nominal durations of the first and second pulse / clean cycles can be implemented, thereby enabling the achievement of nominal depth and nominal silicon atom concentration. Other methods for doping silicon into the titanium nitride layer can be used. For example, the flow rate of the first precursor used in the second pulse / clean cycle can be increased to increase the silicon atom concentration in the formed silicon-doped titanium nitride layer. In some embodiments, the work function layer can be deposited at a temperature between about 400°C and about 500°C. In some embodiments, the cavity pressure used for depositing the work function layer can be between about 2 Torr and about 5 Torr.

[0105] In some embodiments, an ALD process comprising one or more deposition cycles can be used to form a functional layer 1120 in region 930D. Each deposition cycle may include at least one first pulse / purge cycle and at least one second pulse / purge cycle. For example, in each deposition cycle, the first pulse / purge cycle may be performed once, while the second pulse / purge cycle may be performed approximately three times, providing an increased silicon atom concentration. The deposition cycles may be repeated a nominal number of times, thereby enabling the nominal thickness of the functional layer to be achieved. For example, the deposition cycles may be performed approximately 10 to approximately 20 times. In some embodiments, the deposition cycles may be performed approximately 15 times. The thickness of the functional layer 1120 may be approximately... Peace Treaty Between. For example, the power function layer 1120 can have approximately The thickness.

[0106] In some embodiments, an ALD process comprising one or more deposition cycles can be used to form a functional layer 1122 in region 930C. Each deposition cycle may include at least one first pulse / clean cycle and at least one second pulse / clean cycle. For example, in each deposition cycle, the first pulse / clean cycle may be performed once, and the second pulse / clean cycle may be performed approximately twice. This can result in a lower silicon atom concentration in functional layer 1122 than in functional layer 1120. The deposition cycles can be repeated a nominal number of times, thereby achieving a nominal thickness of the functional layer. For example, the deposition cycles may be performed from approximately 10 to approximately 20 times. In some embodiments, the deposition cycles may be performed approximately 15 times. The thickness of functional layer 1122 can be approximately... Peace Treaty Between. For example, the work function layer 1122 can have approximately The thickness.

[0107] In some embodiments, the function layer 1124 can be formed using an ALD process comprising one or more deposition cycles. Each deposition cycle may include at least one first pulse / clean cycle and at least one second pulse / clean cycle. For example, in each deposition cycle, the first pulse / clean cycle may be performed once, while the second pulse / clean cycle may be performed at least once. This can result in a lower silicon atom concentration in the function layer 1124 compared to the silicon atom concentration in function layers 1120 or 1122. The deposition cycles can be repeated a nominal number of times, thereby achieving the nominal thickness of the function layer. For example, the deposition cycles may be performed from about 10 to about 20 times. In some embodiments, the deposition cycles may be performed about 15 times. The thickness of the function layer 1124 can be approximately... Peace Treaty Between. For example, the power function layer 1124 can have approximately The thickness.

[0108] In this way, a silicon-doped titanium nitride work function layer can be formed in regions 930B-930D. By implementing different numbers of pulse / purge cycles during deposition, the work function layers 1120, 1122, and 1124 can have different silicon atom concentrations. Different silicon atom concentrations can provide different threshold voltages for the FinFETs 102B-102D formed in regions 930B-930D, respectively. Due to the absence of the silicon-doped titanium nitride work function layer, the FinFET 102A formed in region 930A can also have a different threshold voltage than the FinFETs 102B-102D. Similar to the reference... Figures 11G to 11HThe described process allows for the formation of other suitable layers on the power-function layers 1120-1124. For example, additional power-function layers 1114, cover layers 1116, and adhesive layers 1118 can be formed in regions 930A-930D, and will not be described in detail here for simplicity.

[0109] Multithreshold voltage devices may include nitrogen-doped work function layers formed by performing one or more thermal annealing processes on deposited work function material. In some embodiments, the thermal annealing process includes a nitrogen annealing process using ammonia. In some embodiments, the nitrogen-doped work function layer may be formed of titanium aluminum carbon nitride (TiAlCN). In some embodiments, work function layers 130A-130D may include work function layers for multithreshold voltage devices, and each work function layer may include one or more sublayers. In some embodiments, multiple sublayers of the nitrogen-doped work function layer may be formed in a semiconductor device such as a finFET or a GAA FET. Each sublayer may be formed by depositing work function material in a nitrogen environment (such as a chamber filled with ammonia) and performing thermal treatment on the work function material. The deposition and treatment processes may be repeated to form another sublayer on top of the deposited sublayer. Repeated deposition and treatment processes can provide a nitrogen-doped work function layer in which nitrogen is uniformly distributed within the work function layer. Figure 11J Work function layers 1130, 1132, and 1134, which can be formed in regions 930B-930D, are shown. For simplicity, Figure 11J The one shown in the middle is the same as Figure 11A to Figure 11H Other similar structural tags have the same annotations.

[0110] Power function layers 130B, 130C, and 130D are formed in regions 930B, 930C, and 930D, respectively, and may include one or more layers of nitrogen-doped titanium aluminum carbide (TiAlCN). In some embodiments, other suitable semiconductor materials, such as nitrogen-doped tantalum aluminum carbide (TaAlCN), may be used. In some embodiments, power function layers 130B, 130C, and 130D may contain different numbers of sublayers to provide multiple threshold voltages on finFETs 102B-102D. The sublayers of the power function layers can be formed in a manner similar to that described above. Figures 11A to 11IThe process of deposition, blocking, and etching described herein is used to form the sublayer. In some embodiments, the sublayer can be treated by thermal treatment in an ammonia environment to combine the deposited work function material with nitrogen. Sublayers can be deposited on top of each other, wherein ammonia thermal treatment can be performed between the deposition of each sublayer. In this way, nitrogen can be distributed substantially uniformly in each sublayer. Because the finFET 102A does not include a nitrogen-doped work function layer, it can have a different threshold voltage than the finFETs 102B-102D. In some embodiments, the work function layer 1130 can have a nitrogen atom concentration between about 35% and about 50%. In some embodiments, the work function layer 1132 can have a nitrogen atom concentration between about 20% and about 35%. In some embodiments, the work function layer 1134 can have a silicon atom concentration between about 5% and about 20%.

[0111] The work function layer 130B of the FinFET 102B may include at least a nitrogen-doped work function layer 1134. The device may also include more than one nitrogen-doped work function layer to form devices with different threshold voltages. For example, the FinFET 102C may include nitrogen-doped work function layers 1132 and 1134. The FinFET 102D may include nitrogen-doped work function layers 1130, 1132, and 1134. The thickness of the nitrogen-doped work function layers 1130, 1132, and 1134 can be approximately... Peace Treaty Between. For example, the thickness of the power function layers 1130, 1132, and 1134 can be approximately The greater thickness of the power function layers 1130, 1132 and 1134 can provide a greater variation in threshold voltage, but also leave a smaller window for subsequent material deposition into the trench.

[0112] Work function layers 1130, 1132, and 1134 can be similar to those described above. Figures 11A to 11H The deposition, barrier, and etching processes described herein are used to form the structure. The heat treatment process can be performed in a nitrogen atmosphere between the deposition and barrier operations.

[0113] The nitrogen-doped work function layer 1130 can be formed in region 930D ​​by depositing a first work function material on the gate dielectric layer 112A in regions 930A-930D in a blanket manner, followed by in-situ heat treatment and one or more patterning and etching processes. In some embodiments, the work function layer 1130 can be formed of nitrogen-doped titanium aluminum carbide, and a titanium aluminum carbide layer can be deposited first as the first work function material and treated by a thermal annealing process in a nitrogen environment. In some embodiments, an ALD process can be used to deposit titanium aluminum carbide and any suitable precursor, such as titanium tetrachloride and triethylaluminum (TEA), can be used. The deposited first work function material can be heat-treated in a nitrogen environment. In some embodiments, an ammonia pulse can be introduced into the deposition chamber to create a nitrogen environment, and any other suitable nitrogen-containing precursor can be used. In some embodiments, the first work function material can be heat-treated at a temperature between about 430°C and about 470°C. For example, the annealing temperature can be about 450°C. The annealing temperature can be determined by the thermal budget of the device, and higher temperatures can result in a higher nitrogen atom concentration in the deposited work function layer.

[0114] In some embodiments, additional processing steps may be implemented. For example, an in-situ processing step may be implemented to prevent oxidation of the deposited work function material. In some embodiments, a processing step using titanium tetrachloride and silane may be implemented on the deposited titanium aluminum carbide material to prevent oxidation. The processing step may be implemented between about 430°C and about 470°C, such as at about 450°C. To remove the treated nitrogen-doped first work function material from regions 930A-930C, a barrier layer may be formed in region 930D ​​by patterning and etching processes. Figure 11J (Not shown in the diagram), without forming a barrier layer in regions 930A-930C. The barrier layer may include one or more hard mask layers. For example, the barrier layer may include a bilayer structure comprising a first hard mask layer located on a deposited first work function material and a second hard mask layer formed on the first hard mask layer. The bilayer hard mask layer may be similar to the one described above. Figure 11A The hard mask 1104 is described herein. The deposited first function material can be removed from regions 930A-930C where the barrier layer lacks a double-layer structure using one or more etching processes. The remaining first function material forms a function layer 1130 in region 930D. The barrier layer can be removed after the function layer 1130 has been formed. For example, the barrier layer can be removed by a suitable wet chemical etching process, a dry etching process, other suitable etching processes, and / or combinations thereof.

[0115] Nitrogen-doped work function layer 1132 can be formed in regions 930C and 930D ​​using a method similar to that used for work function layer 1130. In some embodiments, work function layer 1132 can be formed of nitrogen-doped titanium aluminum carbide, and titanium aluminum carbide layers can be deposited in regions 930A-930D as a second work function material. The deposited second work function material can be heat-treated in a nitrogen atmosphere. In some embodiments, ammonia can be pulsed into the deposition chamber to create a nitrogen atmosphere, and any other suitable nitrogen-containing precursor can be used. In some embodiments, the second work function material can be heat-treated at a temperature between about 370°C and about 430°C. For example, the annealing temperature can be about 400°C. Similar to the fabrication process of work function layer 1130, additional processing steps can be performed. For example, in-situ processing steps can be performed to prevent oxidation of the deposited work function material. The barrier layer can be removed after the work function layer 1132 is formed in regions 930C and 930D. For example, the barrier layer can be removed by a suitable wet chemical etching process, a dry etching process, other suitable etching processes, and / or combinations thereof.

[0116] Nitrogen-doped work function layer 1134 can be formed in regions 930B-930C using a method similar to that used for work function layers 1130 and 1132. In some embodiments, work function layer 1134 can be formed of nitrogen-doped titanium aluminum carbide, and the titanium aluminum carbide layer can be deposited as a third work function material in regions 930A-930D. The deposited third work function material can be heat-treated in a nitrogen environment, similar to the heat treatment performed on work function layers 1130 and 1132. In some embodiments, the third work function material can be heat-treated at a temperature between about 320°C and about 380°C. For example, the annealing temperature can be about 350°C. Similar to the manufacturing process of work function layer 1130, additional processing processes can be implemented. For example, in-situ processing processes can be implemented to prevent oxidation of the deposited work function material. The barrier layer can be removed after the work function layer 1134 is formed in regions 930B-930D. For example, the barrier layer can be removed by a suitable wet chemical etching process, a dry etching process, other suitable etching processes, and / or combinations thereof.

[0117] In this way, a nitrogen-doped titanium aluminum carbide work function layer can be formed in regions 930B-930D. The work function layers 130B-130D may include one or more sublayers formed from the nitrogen-doped work function layer. Different numbers of sublayers can provide different threshold voltages for the FinFETs 102B-102D formed in regions 930B-930D. Due to the absence of a nitrogen-doped work function layer (such as titanium aluminum carbide), the FinFET 102A formed in region 930A can also have a different threshold voltage than the FinFETs 102B-102D. Similar to the reference... Figures 11G to 11HThe described process allows for the formation of other suitable layers on the power-function layers 1130-1134. For example, additional power-function layers 1114, cover layers 1116, and adhesive layers 1118 can be formed in regions 930A-930D, and will not be described in detail here for simplicity.

[0118] Figure 11K A power function layer 130A-130D is shown formed on a gate dielectric layer 112A between spacers 114 and between each layer of the stack of semiconductor layers 122. Each of the gate dielectric layer 112A and the gate power function layers 130A-130D can enclose a nanowire-shaped semiconductor layer 122 formed by removing the first semiconductor layer 320. Depending on the spacing between adjacent semiconductor layers 122, the semiconductor layer 122 can be enclosed by the gate dielectric layer 112A and the power function layers 130A-130D, thereby filling the spacing between adjacent semiconductor layers 122.

[0119] Reference Figure 2 In operation 245, according to some embodiments, a gate electrode is formed on the power function layer. (Refer to...) Figures 12A to 12BA conductive material layer for the gate metal fill layer 132 is formed on the power function layers 130A-130D. The conductive material layer for the gate metal fill layer 132 may include suitable conductive materials such as titanium, silver, aluminum, tungsten, copper, ruthenium, molybdenum, tungsten nitride, cobalt, nickel, titanium carbide, titanium aluminum carbide, manganese, zirconium, metal alloys, and / or combinations thereof. The gate metal fill layer 132 may be formed by ALD, PVD, CVD, or other suitable deposition processes. Deposition of the gate metal fill layer 132 may continue until the opening between opposing spacers is filled with the gate metal fill layer 132. A chemical mechanical polishing process may remove excess gate metal fill layer 132, thereby making the top surfaces of the gate metal fill layer 132 and ILD 118 substantially coplanar. In some embodiments, other structures may be formed, such as barrier layers, gate contact structures, and S / D contact structures. One or more barrier layers may be formed prior to the deposition of the gate metal fill layer 132 to prevent diffusion and oxidation of the gate metal fill layer 132. The gate and S / D contact structures can be formed by forming openings in the gate metal fill layer 132 and the ILD 118. Gate contact structures and S / D contact structures can be formed, respectively connected to the gate metal fill layer 132 and the epitaxial fin region 110. Forming the contact structures can include depositing contact metal, followed by CMP of the deposited contact metal. Forming the contact metal can include depositing a metal layer within the openings and silicidening the deposited metal layer. The conductive materials used for the metal layers and / or contact metals can include titanium, aluminum, silver, tungsten, cobalt, copper, ruthenium, zirconium, nickel, titanium nitride, tungsten nitride, metal alloys, and / or combinations thereof, and can be formed by ALD, PVD, CVD, or other suitable deposition processes.

[0120] The various embodiments of this invention describe methods for forming multi-threshold voltage devices. Multiple deposition and patterning processes can be used in GAA FETs to form multilayer metal nitride work function materials as n-type work function layers. By forming different work function layer compositions through multiple deposition and patterning processes, GAA devices with different threshold voltages can be formed on the same substrate.

[0121] In some embodiments, the semiconductor device includes a substrate and a first transistor located on the substrate. The first transistor includes a first gate structure, and the first gate structure includes a gate dielectric layer and a first power function layer located on the gate dielectric layer. The first gate structure also includes a capping layer located on the first power function layer. The semiconductor device further includes a second transistor located on the substrate and having a second gate structure. The second gate structure includes a gate dielectric layer and a second power function layer located on the gate dielectric layer. The second gate structure also includes a first power function layer located on the second power function layer and a silicon capping layer located on the first power function layer.

[0122] In some embodiments, the semiconductor device includes a substrate and a first full-to-all-around gate field-effect transistor (GAA FET) on the substrate. The first GAA FET includes a first plurality of nanowires and a gate dielectric layer on the first plurality of nanowires. The first GAA also includes a first work function layer on the gate dielectric layer. The semiconductor device further includes a second GAA FET on the substrate. The second GAA FET further includes a second plurality of nanowires and a gate dielectric layer on the second plurality of nanowires. The second gate structure further includes a second work function layer on the gate dielectric layer and a first work function layer on the second work function layer.

[0123] In some embodiments, the method includes depositing a gate dielectric layer on a plurality of nanowires, the nanowires being formed in a first device region and a second device region. The method further includes depositing a first power function material on the plurality of nanowires in the first and second device regions, and removing a portion of the first power function material from the second device region to expose the gate dielectric layer, wherein the remaining portion of the first power function material forms the first power function layer. The method further includes depositing a second power function material in the first and second device regions, and removing a portion of the second power function material from the first device region to expose the first power function layer, wherein the remaining portion of the second power function material forms the second power function layer. The method further includes depositing a third power function layer in the first and second device regions and on the first and second power function layers.

[0124] Some embodiments of the present invention provide a semiconductor device, comprising: a substrate; a first transistor located on the substrate and including a first gate structure, wherein the first gate structure includes: a gate dielectric layer; a first power function layer located on the gate dielectric layer; and a capping layer located on the first power function layer; and a second transistor located on the substrate and including a second gate structure, wherein the second gate structure includes: the gate dielectric layer; a second power function layer located on the gate dielectric layer; the first power function layer located on the second power function layer; and a silicon capping layer located on the first power function layer. In some embodiments, the first power function layer comprises titanium aluminum carbide. In some embodiments, the second power function layer comprises titanium nitride. In some embodiments, the silicon capping layer comprises silicon dioxide. In some embodiments, the semiconductor device further includes a third transistor located on the substrate, the third transistor including: the gate dielectric layer; a third power function layer located on the gate dielectric layer; the first power function layer located on the third power function layer; and the silicon capping layer located on the first power function layer. In some embodiments, the third power function layer comprises tantalum nitride. In some embodiments, the semiconductor device further includes a fourth transistor located on the substrate, the fourth transistor comprising: the gate dielectric layer; a fourth power function layer located on the gate dielectric layer; a first power function layer located on the fourth power function layer; and a silicon capping layer located on the first power function layer. In some embodiments, the fourth power function layer comprises tungsten carbonitride. In some embodiments, the semiconductor device further includes an adhesive layer formed on the silicon capping layer. In some embodiments, the adhesive layer comprises titanium nitride.

[0125] Embodiments of the present invention also provide a semiconductor device, comprising: a substrate; a first full-to-all-gate field-effect transistor (GAA FET) located on the substrate, comprising: a first plurality of nanowires; a gate dielectric layer located on the first plurality of nanowires; and a first power function layer located on the gate dielectric layer; and a second full-to-all-gate field-effect transistor located on the substrate, comprising: a second plurality of nanowires; the gate dielectric layer located on the second plurality of nanowires; a second power function layer located on the gate dielectric layer; and the first power function layer located on the second power function layer. In some embodiments, the first power function layer and the second power function layer comprise titanium aluminum carbide and titanium nitride, respectively. In some embodiments, the semiconductor device further comprises a silicon capping layer located on the first power function layer. In some embodiments, the semiconductor device further comprises a gate metal fill layer located on the silicon capping layer. In some embodiments, the semiconductor device further includes: a third full-ring gate field-effect transistor, located on the substrate, comprising: a third plurality of nanowires; a gate dielectric layer located on the third plurality of nanowires; a third power function layer located on the gate dielectric layer; and a first power function layer located on the third power function layer; and a fourth full-ring gate field-effect transistor, located on the substrate, comprising: a fourth plurality of nanowires; a gate dielectric layer located on the fourth plurality of nanowires; a fourth power function layer located on the gate dielectric layer; and a first power function layer located on the fourth power function layer; wherein the first full-ring gate field-effect transistor and the second full-ring gate field-effect transistor are n-type field-effect transistors, while the third full-ring gate field-effect transistor and the fourth full-ring gate field-effect transistor are p-type field-effect transistors.

[0126] Embodiments of the present invention also provide a method comprising: depositing a gate dielectric layer on a plurality of nanowires formed in a first device region and a second device region; depositing a first power function material on the plurality of nanowires in the first device region and the second device region; removing a portion of the first power function material from the second device region to expose the gate dielectric layer, wherein the remaining portion of the first power function material forms a first power function layer; depositing a second power function material in the first device region and the second device region; removing a portion of the second power function material from the first device region to expose the first power function layer, wherein the remaining portion of the second power function material forms a second power function layer; and depositing a third power function layer in the first device region and the second device region, and on the first power function layer and the second power function layer. In some embodiments, depositing the first power function material comprises depositing tantalum nitride. In some embodiments, depositing the second power function material comprises depositing titanium nitride. In some embodiments, depositing the third power function layer comprises depositing titanium aluminum carbide. In some embodiments, the method further comprises performing a processing step on the third power function layer using titanium chloride and silane as precursors.

[0127] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor device, comprising: A gate dielectric layer is deposited on multiple nanowires, which are formed in a first device region and a second device region; A first work function material is deposited on the plurality of nanowires in the first device region and the second device region; A portion of the first power function material is removed from the second device region to expose the gate dielectric layer, wherein the remaining portion of the first power function material forms the first power function layer; A second work function material is deposited in the first device region and the second device region; A portion of the second power function material is removed from the first device region to expose the first power function layer, wherein the remaining portion of the second power function material forms the second power function layer; and A third power function layer is deposited in the first device region and the second device region, and on the first power function layer and the second power function layer.

2. The method according to claim 1, wherein, The deposition of the first work function material includes the deposition of tantalum nitride.

3. The method according to claim 1, wherein, The deposition of the second work function material includes the deposition of titanium nitride.

4. The method according to claim 1, wherein, The deposition of the third function layer includes the deposition of titanium aluminum carbide.

5. The method according to claim 1 further includes using titanium chloride and silane as precursors to perform a processing on the third work function layer.

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