Three-dimensional non-volatile memory devices and methods of manufacturing the same

Abstract

Provided are a three-dimensional nonvolatile memory device and a manufacturing method thereof. The three-dimensional nonvolatile memory device includes a substrate including a cell region and an extension region having a stepped structure, a vertical structure on the substrate, a stack structure having an electrode layer and an interlayer insulating layer on the substrate, an isolation insulating layer on the substrate and isolating the electrode layer, and a via wiring region adjacent to the cell region or the extension region and having a via passing through the substrate, wherein the cell region includes a main cell region in which normal cells are arranged and an edge cell region, the isolation insulating layer includes a main isolation insulating layer in the main cell region and an edge isolation insulating layer in the edge cell region, and a lower surface of the main isolation insulating layer is higher than an upper surface of the substrate and has a different depth from a lower surface of the edge isolation insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0017777, filed on February 13, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a non-volatile memory device and a method for manufacturing the same, and more specifically, to a non-volatile memory device and a method for manufacturing the same having a vertical channel structure with increased integration. Background Technology

[0004] Recently, the number of devices using non-volatile memory (NDRAM) has increased. For example, MP3 players, digital cameras, mobile phones, camcorders, flash memory cards, and solid-state drives (SSDs) can use NDRAM as storage devices. After a power outage and restart, NDRAM can retrieve the stored information. In NDRAM, flash memory can electrically erase all data within a cell. In other words, flash memory can be electrically erased and reprogrammed. Furthermore, flash memory is highly portable and cost-effective, thus it is widely used as a storage device. However, due to the demand for increased storage capacity, there is a need to increase the storage space of flash memory. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, a three-dimensional non-volatile memory device includes: a first substrate including a cell region and an extension region disposed on one side of the cell region in a first direction, wherein the extension region has a stepped structure; a vertical structure extending from the upper surface of the first substrate in a vertical direction; a stacked structure having an electrode layer and an interlayer insulating layer alternately stacked on the first substrate along the sidewall of the vertical structure; an isolation insulating layer extending on the first substrate in the first direction and isolating the electrode layers in a second direction intersecting the first direction; and a via wiring region adjacent to the cell region or the extension region and having a via through the first substrate, wherein the cell region includes a main cell region in which normal cells are disposed and an edge cell region at a peripheral portion of the cell region, the isolation insulating layer includes a main isolation insulating layer in the main cell region and an edge isolation insulating layer in the edge cell region, and the lower surface of the main isolation insulating layer is higher than the upper surface of the first substrate and has a depth different from the depth of the lower surface of the edge isolation insulating layer.

[0006] According to another exemplary embodiment of the present invention, a three-dimensional non-volatile memory device includes: a substrate including a cell region in which cells are disposed and an extension region disposed on one side of the cell region in a first direction, wherein the extension region has a stepped structure in the first direction; a vertical structure extending from the upper surface of the substrate in a vertical direction; a stacked structure having electrode layers and interlayer insulating layers alternately stacked on the substrate along the sidewalls of the vertical structure; and an isolation insulating layer extending on the substrate in the first direction and isolating the electrode layers in a second direction intersecting the first direction, wherein the cell region includes a main cell region in which normal cells are disposed and an edge cell region located at a peripheral portion of the cell region, the isolation insulating layer includes a main isolation insulating layer in the main cell region and an edge isolation insulating layer in the edge cell region, and at least two of the edge isolation insulating layers have different depths.

[0007] According to another exemplary embodiment of the present invention, a method for manufacturing a three-dimensional non-volatile memory device includes: forming at least one insulating layer and a support layer on a substrate, wherein the substrate includes a cell region and an extension region; forming a molding structure by alternately stacking an interlayer insulating layer and a sacrificial layer on the support layer; forming a vertical structure extending from the upper surface of the substrate in a vertical direction and passing through the at least one insulating layer, the support layer, and the molding structure; forming an isolation trench extending on the substrate in a first direction and separating the cell region and the extension region in a second direction intersecting the first direction; forming a spacer covering the lower surface and sidewalls of the isolation trench; exposing the at least one insulating layer by removing the lower surface of the spacer; and replacing the at least one insulating layer with a first conductive layer. A first horizontal layer is formed in contact with the channel layer of the vertical structure; the interlayer insulating layer and the sacrificial layer are exposed to the sidewalls of the isolation trench by removing the spacer in the isolation trench; a stacked structure having electrode layers and interlayer insulating layers alternately stacked along the sidewalls of the vertical structure is formed by replacing the sacrificial layer with a second conductive layer; and an isolation insulating layer is formed by filling the isolation trench with a buried insulating layer, wherein the cell region includes a main cell region in which normal cells are arranged and an edge cell region at the peripheral portion of the cell region, the isolation trench includes a main isolation trench in the main cell region and a plurality of edge isolation trenches in the edge cell regions, the main isolation trench exposes the at least one insulating layer, and some of the plurality of edge isolation trenches expose the substrate.

[0008] According to another exemplary embodiment of the present invention, a three-dimensional non-volatile memory device includes: a substrate including a first cell region and a second cell region; a first vertical structure extending in a vertical direction from an upper surface of the substrate in the first cell region; a second vertical structure extending in the vertical direction from an upper surface of the substrate in the second cell region; a stacked structure having an electrode layer and an interlayer insulating layer alternately stacked on the substrate along the sidewalls of the first vertical structure and the second vertical structure; a horizontal layer disposed on the upper surface of the substrate and penetrating the sidewall of the first vertical structure; and a material layer disposed on the upper surface of the substrate and contacting the sidewall of the second vertical structure. Attached Figure Description

[0009] The above and other features of the inventive concept will become clearer by describing in detail, in conjunction with the accompanying drawings, exemplary embodiments of the inventive concept:

[0010] Figure 1 This is an equivalent circuit diagram of a memory cell in a three-dimensional non-volatile memory device according to an exemplary embodiment of the present invention.

[0011] Figure 2 This is a top view of an exemplary embodiment of a three-dimensional non-volatile memory device according to the present invention.

[0012] Figure 3A yes Figure 2 An enlarged top view of a portion of the cell region of a three-dimensional non-volatile memory device;

[0013] Figure 3B It is along Figure 3A A cross-sectional view of the isolation trench structure taken by line I-I';

[0014] Figure 4 Is with Figure 3A A cross-sectional view of a three-dimensional non-volatile memory device corresponding to a cell region;

[0015] Figure 5A and Figure 5B They are Figure 4 Enlarged cross-sectional views of ranges A and B in a three-dimensional non-volatile memory device;

[0016] Figure 6A yes Figure 2 An enlarged top view of a portion of the cell region of a three-dimensional non-volatile memory device;

[0017] Figure 6B It is along Figure 6A A cross-sectional view of the structure of the isolation trench cut by line Ⅱ-Ⅱ';

[0018] Figure 7A and Figure 7B Is with Figure 6A A cross-sectional view of a three-dimensional non-volatile memory device corresponding to a cell region;

[0019] Figure 8 yes Figure 2 An enlarged top view of a portion of the cell region of a three-dimensional non-volatile memory device;

[0020] Figure 9A yes Figure 8 An enlarged top view of the area C;

[0021] Figure 9B It is along Figure 9A A cross-sectional view of a three-dimensional non-volatile memory device taken from line Ⅲ-Ⅲ';

[0022] Figure 9C It is along Figure 9A A cross-sectional view of the lower part of line IV-IV';

[0023] Figure 9D yes Figure 9A A cross-sectional view of the structure of a specific layer isolation trench in the extended region;

[0024] Figure 10 This is a cross-sectional view of a three-dimensional non-volatile memory device according to an exemplary embodiment of the present invention; and

[0025] Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and 16B This is a cross-sectional view of a method for manufacturing a three-dimensional non-volatile memory device according to an exemplary embodiment of the present invention. Detailed Implementation

[0026] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings may denote the same elements, and therefore their repeated descriptions may be omitted.

[0027] Figure 1 This is an equivalent circuit diagram of a memory cell of a three-dimensional non-volatile memory device 10 according to an exemplary embodiment of the present invention.

[0028] Reference Figure 1The three-dimensional non-volatile memory device 10 according to this embodiment may include a common source line CSL, multiple bit lines BL0 to BLm, and multiple cell strings CSTRs. The bit lines BL0 to BLm may be arranged in two dimensions, and the multiple cell strings CSTRs may be connected in parallel with the bit lines BL0 to BLm respectively. For example, multiple cell strings CSTRs may be connected to the bit line BLm, and another multiple cell strings CSTRs may be connected to the bit line BL0. The multiple cell strings CSTRs may be collectively connected to the common source line CSL.

[0029] Each cell string (CSTR) may include a first string select transistor (SSt1), a second string select transistor (SSt2), a memory cell transistor (MCT), and a ground select transistor (GST). Each memory cell transistor (MCT) may include a data storage element. Specifically, the first string select transistor (SSt1) and the second string select transistor (SSt2) may be connected in series with each other, the second string select transistor (SSt2) may be connected to a corresponding bit line BL0 to BLm, and the ground select transistor (GST) may be connected to the common source line (CSL). Additionally, the memory cell transistor (MCT) may be connected in series between the first string select transistor (SSt1) and the ground select transistor (GST). According to an exemplary embodiment of the present invention, each cell string (CSTR) may include one string select transistor. The first string select transistor (SSt1) and the second string select transistor (SSt2) may be connected to the first string select line (SSL1) and the second string select line (SSL2), respectively.

[0030] like Figure 1 As shown, each cell string CSTR may include a first pseudo-cell transistor DMC1 connected between the first string select transistor SSt1 and the memory cell transistor MCT, and a second pseudo-cell transistor DMC2 connected between the ground select transistor GST and the memory cell transistor MCT. For example, the first pseudo-cell transistor DMC1 may be connected to the uppermost memory cell transistor MCT, and the second pseudo-cell transistor DMC2 may be connected to the lowermost memory cell transistor MCT. The first pseudo-cell transistor DMC1 and the second pseudo-cell transistor DMC2 may be connected to the first pseudo-word line DWL1 and the second pseudo-word line DWL2, respectively. Additionally, the ground select transistor GST may be connected to the ground select line GSL. However, according to an exemplary embodiment of the present invention, at least one of the first pseudo-cell transistor DMC1 and the second pseudo-cell transistor DMC2 may be omitted.

[0031] Because a cell string (CSTR) comprises multiple memory cell transistors (MCTs) at different distances from the common source line (CSL), multilayer word lines WL0 to WLn can be arranged between the common source line (CSL) and bit lines BL0 to BLm. Furthermore, the gate electrodes of the memory cell transistors (MCTs) arranged at substantially the same distance from the common source line (CSL) can be commonly connected to one of the word lines WL0 to WLn, and are therefore at the same potential.

[0032] The three-dimensional non-volatile memory device 10 according to this embodiment is configured such that the depth of the isolation trench is different for each region, thereby preventing failures such as mold lifting due to not open (NOP), thus providing a three-dimensional non-volatile memory device with increased reliability. For example, in the main cell region where normal cells are arranged, the isolation trench can be formed to expose the substrate (see...). Figure 3B The support layer on 101) (see Figure 3B 105) or at least one insulating layer (see 105) Figure 3B (103-2). Additionally, a through hole is arranged therein (see...). Figure 10 Through-hole wiring area (see THV) Figure 3A The adjacent edge unit regions of THV-A (see THV-A) Figure 3A In CAe1), isolation trenches can be formed to expose substrate 101. Thus, by forming isolation trenches at different depths for each region, in future processes, such as in processes where at least one insulating layer 103-2 is replaced with a horizontal layer, it is possible to prevent issues such as those arising from the removal of molded structures (see CAe1). Figure 3B The failures such as molding lift that occur under the sacrificial layer (ST1) instead of at least one insulating layer 103-2 provide a three-dimensional non-volatile memory device with increased reliability.

[0033] Figure 2 This is a top view of a three-dimensional non-volatile memory device 100 according to an exemplary embodiment of the present invention, showing a planar structure of a chip.

[0034] Reference Figure 2 The three-dimensional non-volatile memory device (hereinafter referred to as "memory device") 100 according to this embodiment may include a cell region CA in which cells are arranged in an array structure, and an extension region EA arranged on both sides of the cell region CA in a first direction (e.g., the x direction).

[0035] Within the cell region CA, cells can be arranged in block units in a second direction (e.g., the y-direction). Additionally, at least one insulating layer can be arranged within the block (see...). Figure 3A The at least one insulating layer (such as DAm, DAe, etc.) extends in a first direction (x direction) and isolates the electrode layer in a second direction (y direction). For example, in the memory device 100 of this embodiment, about three insulating layers may be arranged in a block. However, the number of insulating layers in a block is not limited to this.

[0036] In cell region CA, for example, a via wiring region with via THV (see Figure 3A The THV-A can be arranged between blocks in the second direction (y direction). The portion of cell region CA adjacent to the via wiring region THV-A can correspond to the first edge cell region (see...). Figure 3A CAe1).

[0037] The extension region EA is formed by extending from the cell region CA in the first direction (x-direction) and may have a stepped structure, with the stepped structure having a lower height as it is farther from the cell region CA in the first direction (x-direction). The extension regions EA are arranged on both sides of the cell region CA in the first direction (x-direction), corresponding to a block of the cell region CA, but only one extension region EA can be used as an electrode pad for the electrode layer. Additionally, the via wiring region THV-A can also be arranged between the extension regions EA in the second direction (y-direction).

[0038] A stepped structure can be formed at the two outermost points of the chip in the second direction (y-direction). When the cell region CA is a quadrangular mat, the two outermost regions of the chip in the second direction (y-direction) are either the outer mat region MOA or the stepped structure region STA. The stepped structure of the outer mat region MOA can be formed together with the extended region EA, but the stepped structure of the outer mat region MOA may not have electrical functionality. The portion of the cell region CA adjacent to the outer mat region MOA is called the mat edge region MEA, and can correspond to the second edge cell region below (see...). Figure 6A CAe2).

[0039] For reference, a cell region CA may include a main cell region CAm and an edge cell region CAe. The main cell region CAm is the cell region CA in which normal cells performing normal storage functions are arranged. The main cell region CAm may be located in the central portion of the cell region CA. The edge cell region CAe is the region in which dummy cells are arranged or the region in which no normal cells are arranged. The edge cell region CAe may be located in the peripheral portion of the cell region CA. For example, the edge cell region CAe may include a first edge cell region CAe1 adjacent to the via wiring region THV-A, and a second edge cell region CAe2 adjacent to the pad outer region MOA. The second edge cell region CAe2 may be referred to as the pad edge region MEA. Furthermore, the first edge cell region CAe1 may include not only the region adjacent to the via wiring region THV-A, but also portions of the cell region CA corresponding to areas where no channel pattern is formed or where the channel pattern density is low. The first edge cell region CAe1 may be referred to, for example, as a tile-cut region.

[0040] Figure 3A yes Figure 2 An enlarged top view of a portion of the cell region CA of the memory device 100. Figure 3B It is along Figure 3A A cross-sectional view of the isolation trench structure taken from line I-I'. Figure 3B In the through-hole wiring area THV-A, the molded structure can be maintained without forming through-hole THV.

[0041] Reference Figure 3A and Figure 3B The cell region CA may include a main cell region CAm and a first edge cell region CAe1. The first edge cell region CAe1 may be adjacent to a via wiring region THV-A in which vias THV are arranged. The main cell region CAm may be arranged away from the via wiring region THV-A in a second direction (y direction). For example, the first edge cell region CAe1 may be located between the main cell region CAm and the via wiring region THV-A. In addition, a main insulating layer DAm extending in the first direction (x direction) may be arranged in the main cell region CAm, and a first edge insulating layer DAe1 extending in the first direction (x direction) may be arranged in the first edge cell region CAe1.

[0042] Although three first edge isolation insulation layers DAe1 are arranged in the first edge unit region CAe1, the number of first edge isolation insulation layers DAe1 is not limited to three. For example, two or fewer first edge isolation insulation layers DAe1 or four or more first edge isolation insulation layers DAe1 can be arranged in the first edge unit region CAe1. Figure 3AIn this context, although the via wiring region THV-A, the main cell region CAm, and the first edge cell region CAe1 are distinguished from each other based on their positions spaced apart from the main isolation insulating layer DAm and the first edge isolation insulating layer DAe1, the identification of the regions is not limited to this. For example, the via wiring region THV-A, the main cell region CAm, and the first edge cell region CAe1 can be distinguished from each other based on specific parts of the main isolation insulating layer DAm and the first edge isolation insulating layer DAe1.

[0043] In the memory device 100 of this embodiment, such as Figure 3B As shown, the structure of the trench for the main insulating layer DAm can differ from the structure of the trench for the first edge insulating layer DAe1. For example, in Figure 3B In this configuration, when the first trench to the third trench Te, starting from the through-hole wiring region THV-A, are trenches for the first edge isolation insulating layer DAe1, and the fourth trench Tm is a trench for the main isolation insulating layer DAm, the depth of the first trench Te can be greater than the depth of the fourth trench Tm. Additionally, the depth of the first trench Te can be greater than the depths of the second trench Te and the third trench Te. Specifically, the fourth trench Tm can be formed in a shape in which the bottom surface of the fourth trench Tm is recessed on the upper surface of the support layer 105 by passing through the molding structure ST1. However, the first trench Te can be formed in a shape in which the bottom surface of the first trench Te is recessed on the upper surface of the substrate 101 by passing through the molding structure ST1, the support layer 105, and at least one insulating layer 103-2. The molding structure ST1 can have a sacrificial layer (see...) Figure 11A SL) and interlayer insulation (see SL) and interlayer insulation (see SL) Figure 11A The structure consists of alternating stacked ILDs.

[0044] exist Figure 3B In the present invention, although the fourth trench Tm is formed in a shape extending to the upper surface portion of the support layer 105, according to an exemplary embodiment of the present invention, the fourth trench Tm may be formed in a shape extending to the upper surface portion of at least one insulating layer 103-2 by completely penetrating the support layer 105. Alternatively, the fourth trench Tm may extend to the upper surface portion of at least one insulating layer 103-2. Furthermore, the second trench Te and the third trench Te for the first edge insulating layer DAe1 may be formed at a depth similar to the depth of the fourth trench Tm for the main insulating layer DAm. However, according to an exemplary embodiment of the present invention, the second trench Te and the third trench Te may be formed at a depth substantially the same as the depth of the first trench Te, or at a depth between the depth of the fourth trench Tm and the depth of the first trench Te.

[0045] Various methods can be used to implement the method of forming trenches at a greater depth in the first edge cell region CAe1. For example, trenches in the first edge cell region CAe1 can be formed at a greater depth in the etching process by increasing the critical dimension (CD) of the mask used for trench etching in the first edge cell region CAe1. Alternatively, trenches in the first edge cell region CAe1 can be formed at a greater depth in the etching process by not forming a trench pattern in the first edge cell region CAe1 or by reducing the density of the trench pattern in the first edge cell region CAe1. However, it should be understood that the method of forming trenches at a greater depth is not limited to the methods described above.

[0046] For reference, vertical structures are not formed or are formed at a low density in the first edge cell region CAe1 adjacent to the via wiring region THV-A (see [link]). Figure 4 Therefore, in the first edge cell region CAe1, trenches can be formed to a greater depth than those in the main cell region CAm, depending on factors such as molding stress and / or etching load. In other words, when performing an etching process using a mask with the same CD, trenches can be formed in the first edge cell region CAe1 to a greater depth than those in the main cell region CAm.

[0047] According to an exemplary embodiment of the present invention, trenches in the edge cell region CAe can be formed at a depth substantially the same as the depth of trenches in the main cell region CAm. Furthermore, according to an exemplary embodiment of the present invention, trenches in the edge cell region CAe can be formed at a depth less than the depth of trenches in the main cell region CAm. (Referring to...) Figure 6A Figure 7 illustrates the formation of trenches at a smaller depth in more detail.

[0048] Figure 4 Is with Figure 3A A cross-sectional view of a three-dimensional non-volatile memory device 100 corresponding to the cell region CA, wherein the left part corresponds to the main cell region CAm, the middle part corresponds to the first edge cell region CAe1, and the right part corresponds to the through-hole wiring region THV-A. Figure 5A and Figure 5B They are Figure 4 Enlarged cross-sectional views of ranges A and B in the memory device 100.

[0049] Reference Figure 4 and Figure 5AThe memory device 100 of this embodiment may include a vertical structure VCS and a stacked structure ST on a substrate 101 in the main cell region CAm. The substrate 101 may have an upper surface FS extending in a first direction (x-direction) and a second direction (y-direction). The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. In the memory device 100 of this embodiment, the substrate 101 may be formed of, for example, polycrystalline silicon. However, the material of the substrate 101 is not limited to this. For example, the substrate 101 may be formed based on a single-crystal silicon wafer.

[0050] A first horizontal layer 103 extending parallel to the upper surface FS of substrate 101 can be formed on substrate 101. The first horizontal layer 103 can be formed by replacing at least one insulating layer 103-2 formed on substrate 101 with a conductive layer. For example, the first horizontal layer 103 can be formed of polysilicon. However, the material of the first horizontal layer 103 is not limited to this. The first horizontal layer 103 can have a structure that contacts the channel layer CL of the vertical structure VCS. For example, the channel layer CL can contact the end of the first horizontal layer 103. In other words, the first horizontal layer 103 can contact the channel layer CL through multiple insulating layers SMI passing through the sidewalls of the vertical structure VCS. The first horizontal layer 103 can form a common source line (see...). Figure 1 (CSL).

[0051] The thickness of the portion of the first horizontal layer 103 that contacts the channel layer CL can be greater than the thickness of the portion of the first horizontal layer 103 that extends between the support layer 105 and the substrate 101. In other words, the first portion of the first horizontal layer 103 can be thicker than the second portion of the first horizontal layer 103. For example, as Figure 5A As shown, the upper surface of the portion of the first horizontal layer 103 that contacts the channel layer CL may be higher than the lower surface of the support layer 105, and the lower surface of the portion of the first horizontal layer 103 that contacts the channel layer CL may be lower than the upper surface FS of the substrate 101.

[0052] The support layer 105 may be on the first horizontal layer 103. The support layer 105 may also extend parallel to the upper surface FS of the substrate 101. The support layer 105 may be formed of, for example, polysilicon. However, the material of the support layer 105 is not limited to this.

[0053] A stacked structure ST can be on the support layer 105. The stacked structure ST can extend from the cell region CA on the substrate 101 to the extension region EA in a first direction (x direction). A buffer insulating layer 110 can be between the stacked structure ST and the support layer 105. Multiple stacked structures ST can be on the substrate 101 and spaced apart from each other in a second direction (y direction). For example, a main isolation insulating layer DAm extending in the first direction (x direction) can be arranged in the second direction (y direction), and the stacked structures ST can be spaced apart from each other through the main isolation insulating layer DAm. In this document, the main isolation insulating layer DAm, referred to as the word line cutting region, can be formed by filling the trench with an insulating layer, and the lower surface of the main isolation insulating layer DAm can contact the upper surface FS of the substrate 101. Additionally, as Figure 3A As shown, the stacked structures ST can also be spaced apart from each other by the via wiring region THV-A. The vias THV that penetrate the substrate 101, the first horizontal layer 103, the support layer 105, the stacked structures ST and the flat insulating layer 150 can be provided in the via wiring region THV-A.

[0054] The stacked structure ST may include electrode layers EL and interlayer insulating layers ILD alternately stacked in a third direction (z-direction) orthogonal to the upper surface FS of the substrate 101. The thicknesses of the electrode layers EL may be substantially the same. The thickness of the interlayer insulating layer ILD may vary depending on the characteristics of the memory device. Alternatively, the thickness of the interlayer insulating layer ILD may be less than the thickness of the electrode layers EL. Each electrode layer EL may form an electrode pad in an extension region EA. In the memory device 100 of this embodiment, the electrode layers EL may be formed of tungsten (W), and the interlayer insulating layer ILD may be formed of an oxide film (e.g., a silicon oxide film). However, the materials of the electrode layers EL and the interlayer insulating layer ILD are not limited thereto.

[0055] The planar insulating layer 150 may cover the stacked structure ST. The planar insulating layer 150 may have a substantially flat upper surface. The planar insulating layer 150 may cover the electrode pads of the stacked structure ST or the stepped structure. The planar insulating layer 150 may include one or more insulating layers. The planar insulating layer 150 may be formed of an oxide film (e.g., a silicon oxide film). However, the material of the planar insulating layer 150 is not limited to this.

[0056] A vertical structure VCS can be formed on a substrate 101 and has a structure that extends through the stacked structure ST, the support layer 105, and the first horizontal layer 103. For example... Figure 9AAs shown in the top view, the vertical structure VCS can be arranged in a zigzag pattern in the first direction (x-direction). The vertical structure VCS can be arranged in the cell region CA. However, the arrangement of the vertical structure VCS is not limited to the cell region CA. For example, the vertical structure VCS can also be arranged in the extension region EA to support the molding structure in the replacement process. The vertical structure in the extension region EA (see...) Figure 9A The VCSd is also known as a pseudo-structure.

[0057] A vertical structure VCS may include a sidewall multiple insulating layer (SMI), a channel layer (CL), and a buried insulating layer (BI). The sidewall multiple insulating layer (SMI) is a data storage film and may include a tunnel insulating layer (T), a charge storage film (C), and a barrier insulating layer (B). The sidewall multiple insulating layer (SMI) may be located between the stacked structure (ST) and the channel layer (CL). The sidewall multiple insulating layer (SMI) may extend on the substrate 101 in the third direction (z-direction) and surround the sidewalls of the channel layer (CL).

[0058] The vertical structure VCS can be isolated by the first horizontal layer 103. More specifically, the first horizontal layer 103 can penetrate the sidewall multiple insulating layer SMI, such that a first portion of the sidewall multiple insulating layer SMI is disposed between the first horizontal layer 103 and the substrate 101, and a second portion of the sidewall multiple insulating layer SMI is disposed between the first horizontal layer 103 and the first upper interlayer insulating layer 160.

[0059] The channel layer CL can have a cylindrical or macaroni structure with a closed lower surface. In other words, the channel layer CL can include a bottom surface and a pair of sidewalls extending vertically from the bottom surface. The interior of the channel layer CL can be filled with a buried insulating layer BI. As described above, the first horizontal layer 103 can contact the lower sidewall of the channel layer CL. For example, the first horizontal layer 103 can contact the lower sidewall of the channel layer CL below the upper surface FS of the substrate 101.

[0060] The bit line electrode pad BP and the contact plug CP connected to the bit line electrode pad BP can be on the channel layer CL. The side surface of the bit line electrode pad BP can be surrounded by a sidewall multilayer insulating layer SMI. According to an exemplary embodiment of the present invention, the bit line electrode pad BP can be located on the upper surface of the channel layer CL and the upper surface of the sidewall multilayer insulating layer SMI, and the side surface of the bit line electrode pad BP can be surrounded by a first upper interlayer insulating layer 160.

[0061] The first upper interlayer insulation layer 160 may cover the upper surface of the vertical structure VCS and the upper surface of the flat insulation layer 150. Furthermore, the first upper interlayer insulation layer 160 may cover the flat insulation layer 150 in the extended region EA. A second upper interlayer insulation layer 170 may be on the first upper interlayer insulation layer 160 and cover the upper surface of the main insulating layer DAm. In the extended region EA, the vertical contact (see...) Figure 9A The VC can be connected to the corresponding electrode layer EL or electrode pad by passing through the first upper interlayer insulating layer 160 and the second upper interlayer insulating layer 170. For example... Figure 10 As shown, the vertical length of the vertical contact VC (e.g., its length in the third direction (z-direction)) can shorten as it approaches the element region CA. Additionally, the upper surface of the vertical contact VC can form substantially the same plane.

[0062] Sub-line SBL can be on the second upper interlayer insulation layer 170 in cell region CA and electrically connected to the corresponding vertical structure VCS via contact plug CP. In extension region EA, interconnects (see...) Figure 10 The ICL (interconnect line 180) can be on the second upper interlayer insulating layer 170 and connected to the vertical contact VC. The third upper interlayer insulating layer 180 can be on the second upper interlayer insulating layer 170 and cover the sub-bit line SBL and the interconnect line ICL. The bit line BL can be on the third upper interlayer insulating layer 180 and extend in the second direction (y direction) by intersecting the stack structure ST. The bit line BL can be connected to the sub-bit line SBL through the bit line contact plug BCP.

[0063] Reference Figure 4 and Figure 5B The memory device 100 of this embodiment may further include a vertical structure VCS and a stacked structure ST on a substrate 101 in the first edge cell region CAe1. However, the first edge cell region CAe1 may differ from the main cell region CAm in terms of the contact structure of at least one material layer 103-1, the vertical structure VCS, and the first edge isolation insulating layer DAe1. More specifically, at least one material layer 103-1 may include a second horizontal layer 103a and thin film insulating layers 103u and 103d on the upper and lower surfaces of the second horizontal layer 103a, respectively. The second horizontal layer 103a may be formed of, for example, W, and the thin film insulating layers 103u and 103d may be formed of an oxide film (e.g., a silicon oxide film). However, the materials of the second horizontal layer 103a and the thin film insulating layers 103u and 103d are not limited thereto.

[0064] At least one material layer 103-1 may contact the sidewall of the sidewall multi-insulator layer SMI of the vertical structure VCS. Therefore, the second horizontal layer 103a of at least one material layer 103-1 may not be electrically connected to the channel layer CL of the vertical structure VCS. In addition, since at least one material layer 103-1 does not penetrate the sidewall multi-insulator layer SMI, at least one material layer 103-1 may have a uniform thickness between the support layer 105 and the substrate 101.

[0065] In the first edge unit region CAe1, the first edge isolation insulating layer DAe1 may have a structure that is inserted into the upper part of the substrate 101 through the stacked structure ST, the support layer 105, and at least one material layer 103-1. Additionally, as... Figure 4 As shown, the cross-sectional shape of the lower surface of the first edge insulating layer DAe1 can be a semi-circular shape that is recessed downward from the upper surface FS of the substrate 101. However, the cross-sectional shape of the lower surface of the first edge insulating layer DAe1 is not limited to a recessed semi-circular shape. For example, according to an exemplary embodiment of the present invention, the cross-sectional shape of the lower surface of the first edge insulating layer DAe1 can be a recessed trapezoidal or quadrilateral shape. Since the first edge insulating layer DAe1 passes through at least one material layer 103-1, at least one material layer 103-1 can contact the sidewall of the first edge insulating layer DAe1.

[0066] In the memory device 100 of this embodiment, the first width or CD C1 of the main isolation insulating layer DAm in the second direction (y direction) may be smaller than the second width or CDC2 of the first edge isolation insulating layer DAe1 in the second direction (y direction). However, according to an exemplary embodiment of the present invention, the first width C1 of the main isolation insulating layer DAm may be substantially the same as the second width C2 of the first edge isolation insulating layer DAe1.

[0067] Figure 6A yes Figure 2 An enlarged top view of a portion of the cell region CA of the memory device 100. Figure 6B It is along Figure 6A A cross-sectional view of the isolation trench structure taken from line Ⅱ-Ⅱ'.

[0068] Reference Figure 6A and Figure 6B The cell region CA can include the main cell region CAm and the second edge cell region CAe2. For example... Figure 6A As shown, the second edge cell region CAe2 can be adjacent to the outer pad region MOA or the stepped structure region STA. As described above, the outer pad region MOA can be a region with a stepped structure at the two outermost regions of the chip in the second direction (y direction). The main cell region CAm can be located away from the outer pad region MOA in the second direction (y direction). In addition, a main isolation insulating layer DAm extending in the first direction (x direction) can be disposed in the main cell region CAm, and a second edge isolation insulating layer DAe2 extending in the first direction (x direction) can be disposed in the second edge cell region CAe2.

[0069] Although three second edge isolation insulation layers DAe2 are arranged in the second edge unit region CAe2, the number of second edge isolation insulation layers DAe2 is not limited to three. For example, two or fewer second edge isolation insulation layers DAe2 or four or more second edge isolation insulation layers DAe2 can be arranged in the second edge unit region CAe2. Furthermore, in Figure 6A In this context, although the outer pad region MOA is distinguished from the second edge cell region CAe2 based on its position spaced apart from the second edge isolation insulating layer DAe2, the distinction between the outer pad region MOA and the second edge cell region CAe2 is not limited to this. For example, the outer pad region MOA and the second edge cell region CAe2 can be distinguished based on the first appearance of the second edge isolation insulating layer DAe2.

[0070] In the memory device 100 of this embodiment, such as Figure 6B As shown, the structure of the trenches used for the main insulating layer DAm can differ from the structure of the trenches used for the second edge insulating layer DAm. For example, in Figure 6B In this configuration, when the first trench to the third trench Te, starting from the outer region MOA of the pad, are trenches for the second edge insulating layer DAe2, and the fourth trench Tm is a trench for the main insulating layer DAm, the depth of the first trench Te can be less than the depth of the fourth trench Tm. Specifically, the fourth trench Tm can be formed in a shape in which the bottom surface of the fourth trench Tm is recessed on the upper surface of the support layer 105 by passing through the molding structure ST1. However, the first trench Te can be formed in a shape in which the bottom surface of the first trench Te is a sacrificial layer on the underside of the molding structure ST1 (see...). Figure 11A The upper surface of the SL is recessed without completely penetrating the molded structure ST1.

[0071] For reference, in the outer pad region MOA, a flat insulating layer 150, such as an oxide film, covers the upper part of the stepped structure. However, in the second edge cell region CAe2, a non-stepped molded structure ST1 can be arranged. Therefore, in the second edge cell region CAe2 adjacent to the outer pad region MOA, trenches can be formed with a shallower depth than the trenches in the main cell region CAm, depending on the influence of factors such as molding stress and / or etching load.

[0072] like Figure 6BAs shown, the second trench Te and the third trench Te for the second edge insulating layer DAe2 can be formed at a depth similar to the depth of the fourth trench Tm for the main insulating layer DAm. However, according to an exemplary embodiment of the present invention, the second trench Te and the third trench Te can be formed at a depth substantially the same as the depth of the first trench Te or at a depth between the depth of the first trench Te and the depth of the fourth trench Tm. Alternatively, according to an exemplary embodiment of the present invention, the trenches in the second edge cell region CAe2 can be formed at a depth substantially the same as the trenches in the main cell region CAm. Furthermore, according to an exemplary embodiment of the present invention, the trenches in the second edge cell region CAe2 can be formed at a greater depth than the trenches in the main cell region CAm. For example, like the trenches for the first edge insulating layer DAe1, the trenches in the second edge cell region CAe2 can be formed to a depth that exposes the substrate 101. This can be done to prevent defects such as molding lift.

[0073] Figure 7A and Figure 7B Is with Figure 6A A cross-sectional view of the memory device 100 corresponding to the cell region CA, wherein, for convenience, the portion above the first upper interlayer insulating layer 160 is omitted in the drawing. (See also...) Figure 4 describe Figure 7A and Figure 7B And will simply repeat or omit the reference. Figure 4 The description is as follows.

[0074] Reference Figure 7A The memory device 100 of this embodiment may further include a vertical structure VCS and a stacked structure ST on a substrate 101 in the second edge cell region CAe2. However, the second edge cell region CAe2 may differ from the main cell region CAm regarding the contact structure of at least one insulating layer 103-2, the vertical structure VCS and at least one insulating layer 103-2, and the structure of the second edge isolation insulating layer DAe2. More specifically, at least one insulating layer 103-2 may include a horizontal insulating layer 103b and thin film insulating layers 103u and 103d on the upper and lower surfaces of the horizontal insulating layer 103b, respectively. The horizontal insulating layer 103b may be formed of a nitride film (e.g., a silicon nitride film), and the thin film insulating layers 103u and 103d may be formed of an oxide film (e.g., a silicon oxide film). However, the materials of the horizontal insulating layer 103b and the thin film insulating layers 103u and 103d are not limited thereto.

[0075] At least one insulating layer 103-2 may contact the sidewall of the sidewall multi-insulating layer SMI of the vertical structure VCS. Furthermore, since at least one insulating layer 103-2 does not penetrate the sidewall multi-insulating layer SMI, at least one insulating layer 103-2 may have a uniform thickness between the support layer 105 and the substrate 101. For example, in Figure 7A In this process, at least one insulating layer 103-2 has a uniform thickness, but in Figure 7B In the middle, the first horizontal layer 103 has a varying thickness at its penetrating sidewall multi-insulating layer SMI.

[0076] When the trench for isolation is formed in the second edge unit region CAe2, the molded structure is removed in a future horizontal layer replacement process (see...). Figure 11A In ST1), the sacrificial layer SL and interlayer insulation layer ILD do not penetrate the support layer 105. The final second edge isolation insulation layer DAe2 can have a structure in which the second edge isolation insulation layer DAe2 is filled vertically between the stacked structures ST and horizontally between the interlayer insulation layer ILD and the support layer 105. As a result, the second edge isolation insulation layer DAe2 can contact the channel layer CL or the buried insulation layer BI of the vertical structure VCS.

[0077] According to an exemplary embodiment of the present invention, in the second edge unit region CAe2, the second edge isolation insulation layer DAe2 may have a gap at the insulation layer portion extending toward the vertical structure VCS. Alternatively, according to an exemplary embodiment of the present invention, when the trench for isolation exposes only the interlayer insulation layer ILD and not the sacrificial layer SL, the second edge isolation insulation layer DAe2 may have a structure that does not contact the vertical structure VCS by slightly removing portions of the sacrificial layer SL and the interlayer insulation layer ILD at the portion adjacent to the trench in the horizontal layer replacement process. Furthermore, when the trench for isolation does not penetrate the support layer 105, the second edge isolation insulation layer DAe2 may have various structures other than those described above, depending on process variations in future processes such as the horizontal layer replacement process.

[0078] Reference Figure 7BThe memory device 100 of this embodiment may further include a vertical structure VCS and a stacked structure ST on the substrate 101 in the second edge cell region CAe2. The structure of the first horizontal layer 103, the vertical structure VCS and the contact structure of the first horizontal layer 103, and the structure of the second edge isolation insulating layer DAe2 may be substantially the same as those in the main cell region CAm. In other words, as in the main cell region CAm, trenches for isolation can be formed in the second edge cell region CAe2 up to the substrate 101, and in this case, a future horizontal layer replacement process can be performed in substantially the same manner as in the main cell region CAm. Therefore, the structure of the first horizontal layer 103, the vertical structure VCS and the contact structure of the first horizontal layer 103, and the second edge isolation insulating layer DAe2 may be formed in the second edge cell region CAe2 in a manner substantially the same as that in the main cell region CAm.

[0079] Figure 8 yes Figure 2 An enlarged top view of a portion of the cell region CA of the memory device 100. Figure 9A yes Figure 8 An enlarged top view of area C, Figure 9B It is along Figure 9A A cross-sectional view of the memory device 100 taken from line Ⅲ-Ⅲ'. Additionally, Figure 9C It is along Figure 9A A cross-sectional view of the lower part taken from line IV-IV'. Figure 9D yes Figure 9A A cross-sectional view of the structure of a specific layer isolation trench in the extended region EA.

[0080] Reference Figure 8 In the memory device 100 of this embodiment, the cells of a block unit can be arranged in the cell region CA in the second direction (y direction). Additionally, the extension regions EA can be arranged on both sides of the cell region CA in the first direction (x direction). The cell region CA of a block can use the extension region EA on either side in the first direction (x direction) as an electrode pad. For example, the cell region CA of the first block B1 on the right can use the first extension region EA-1 located on the lower side in the first direction (x direction) as an electrode pad, and the cell region CA of the second block B1 on the left can use the second extension region EA-II located on the upper side in the first direction (x direction) as an electrode pad.

[0081] Reference Figures 9A to 9DThe vertical structure VCS can be arranged in the cell region CA. Alternatively, the vertical structure VCSd can also be arranged in the extension region EA. As mentioned above, the vertical structure VCSd in the extension region EA can be a pseudo-structure. The vertical structure VCSd in the extension region EA can be arranged in a shape that surrounds the vertical contact VC connected to the electrode pads in the extension region EA.

[0082] Here, the dashed line LIE represents the lower portion of the stacked structure ST and can indicate the boundary between regions having at least one insulating layer 103-2 and regions without at least one insulating layer 103-2. For example, as... Figure 9C As shown, at least one insulating layer 103-2 is not present in the lower portion of the main insulating layer DAm, therefore, the support layer 105 can be formed directly on the substrate 101. Additionally, as shown by the dashed line LIE, at least one insulating layer 103-2 may not be present in the boundary portion between the cell region CA and the extended region EA.

[0083] The insulating layer DA can extend from the cell region CA to the extension region EA in the first direction (x direction). When the through-hole wiring region THV-A is arranged to the right of the first block BI, at least a portion of the cell region CA in the first block BI can correspond to the first edge cell region CAe1. Furthermore, the insulating layer DA in the first edge cell region CAe1 can correspond to the first edge insulating layer DAe1. For example, in... Figure 9A In the middle, the right isolation insulation layer DA can correspond to the first edge isolation insulation layer DAe1, and the left isolation insulation layer DA can correspond to the main isolation insulation layer DAm.

[0084] Therefore, as Figure 9B As shown, the left-side main insulating layer DAm and the first horizontal layer 103 in contact with the left-side main insulating layer DAm can have the same characteristics as... Figure 4 The main insulating layer DAm and the first horizontal layer 103 in the main unit region CAm have essentially the same structure. However, here, the main insulating layer DAm may not be in contact with the substrate 101. Additionally, the right-side first edge insulating layer DAe1 and at least one material layer 103-1 in contact with the right-side first edge insulating layer DAe1 may have the same structure as... Figure 4The first edge insulating layer DAe1 and at least one material layer 103-1 in the first edge unit region CAe1 have substantially the same structure. The first horizontal layer 103 and at least one material layer 103-1 may contact each other at the middle portion in the second direction (y direction). According to an exemplary embodiment of the present invention, when the main insulating layer DAm is slightly closer to the first edge unit region CAe1 in the second direction (y direction), only the first horizontal layer 103, which is initially formed by a replacement process, may be present, and at least one material layer 103-1 may be absent.

[0085] As described above, the stepped structure portion of the extended region EA can be covered by a flat insulating layer 150, such as an oxide film, and the thickness of the flat insulating layer 150 can increase as it moves further away from the cell region CA in the first direction (x direction). Typically, in the process of forming the isolation trench, the oxide film portion can be etched more easily than the portion of the molded structure ST1. Therefore, as... Figure 9D As shown, the depth of the trench can increase as it moves further away from the element region CA in the first direction (x-direction). Figure 9D In this context, the first ST to the fourth ST can represent the first to fourth stepped portions starting from the element region CA. However, the depth of the trench does not need to be continuously larger; for example, when the trench is a certain distance away from the element region CA, the depth of the trench can be substantially the same.

[0086] Figure 10 This is a cross-sectional view of a memory device 100 according to an exemplary embodiment of the present invention.

[0087] Reference Figure 10 In the memory device 100 of this embodiment, the cell region CA and the extension region EA can be arranged on the substrate 101, and the peripheral circuit region PCA can be arranged below the substrate 101. A structure or memory device having a cell region CA on the peripheral circuit region PCA can be called a cell-on-periphery (COP) structure or memory device.

[0088] The part of cell region CA and about Figure 4 The cell regions CAm and CAe1 are described in the same way. However, Figure 4 The element regions CAm and CAe1 can correspond to sections orthogonal to the first direction (x direction), while Figure 10 This part of the unit region CA can correspond to a section orthogonal to the second direction (y direction).

[0089] The extended area EA section and about Figure 9A The extended region EA is the same as described. However, Figure 9A The extended area EA corresponds to the top view, while Figure 10 This portion of the extended region EA can correspond to a section orthogonal to the second direction (y-direction). For example... Figure 10 As shown, the electrode layer EL extends in the first direction (x direction) and has a stepped structure in the extended region EA, and the exposed portion can correspond to the electrode pads of the electrode layer EL. Vertical contacts VC can be connected to such electrode pads. The vertical contacts VC can be connected to interconnects ICL thereon via contact plugs CP. Although in Figure 10 The electrode pads are exposed in one-layer units, but according to an exemplary embodiment of the present invention, the electrode pads can be exposed in two-layer units. In the structure of exposing the electrode pads in two-layer units, the extension region EA can be divided into two local extension regions, wherein odd-numbered layer electrode pads are exposed in one local extension region and even-numbered layer electrode pads are exposed in the other local extension region.

[0090] The peripheral circuit region PCA can be located beneath the substrate 101. In other words, the cell region CA can be stacked on the peripheral circuit region PCA. Therefore, the cell region CA can cover the peripheral circuit region PCA. The peripheral circuit region PCA can be formed on the substrate 201. The substrate 201 can be connected to the substrate 201. Figure 4 The substrate 101 is described in the same way as that described in the memory device 100 of this embodiment. In the memory device 100 of this embodiment, the substrate 201 may be formed based on a single-crystal silicon wafer. The substrate 201 may have an n-well region doped with n-type impurities and a p-well region doped with p-type impurities, and the active region may be defined in the n-well region and the p-well region separated by a device isolation layer.

[0091] In the peripheral circuit region PCA, high-voltage transistors and / or low-voltage transistors, as well as passive devices such as resistors and capacitors, can be arranged. For example, the peripheral circuit region PCA may include a peripheral circuit transistor PTR, which includes a peripheral circuit gate electrode PG and a source / drain region S / D. Additionally, the peripheral circuit region PCA may include peripheral circuit lines LM0, LM1, and LM2 connected to the peripheral circuit gate electrode PG and the source / drain region S / D. Figure 10 Although the peripheral circuit lines LM0, LM1, and LM2 are formed in a three-layer structure, the layered structure of the peripheral circuit lines LM0, LM1, and LM2 is not limited to this. The peripheral circuit transistor PTR can be connected to the peripheral circuit line LM0, and the peripheral circuit lines LM0, LM1, and LM2 can be connected to each other through vertical contacts VC0, VC1, and VC2.

[0092] The interlayer insulating layer 220 can be on the substrate 201 to cover the peripheral circuit lines LM0, LM1, and LM2 and the vertical contacts VC0, VC1, and VC2. Although in Figure 10The interlayer insulation layer 220 is shown as a single-layer structure, but depending on the layered structure of the peripheral circuit lines LM0, LM1 and LM2, the interlayer insulation layer 220 can have a multi-layer structure.

[0093] The via wiring region THV-A can be in the cell region CA or the extension region EA. As described above, a via THV can be formed in the via wiring region THV-A. Lines in the cell region CA can be connected to lines in the peripheral circuit region PCA through the via THV. A dielectric insulating layer 250 can be located between the substrate 101 and the peripheral circuit region PCA. The dielectric insulating layer 250 can be formed of, for example, an oxide film. However, the material of the dielectric insulating layer 250 is not limited to an oxide film.

[0094] Alternatively, the substrate 101 can be formed of polysilicon. For example, trench regions for the substrate can be formed on the dielectric insulating layer 250, and the substrate 101 can be formed by filling the trench regions with polysilicon. Thus, when the substrate 101 is formed of polysilicon, the peripheral circuit region PCA can be formed on the base substrate 201, and the substrate 101 can be formed on the dielectric insulating layer 250. Subsequently, cell regions CA and extension regions EA can be formed on the substrate 101, and vias THV can be formed in the via wiring regions THV-A, thereby implementing a COP structure.

[0095] Alternatively, substrate 101 can be formed from a monocrystalline silicon substrate. When substrate 101 is formed from a monocrystalline silicon substrate, peripheral circuit region PCA can be formed on base substrate 201, and cell region CA and extension region EA can be formed on substrate 101. Subsequently, a chip or wafer including substrate 101 can be stacked and bonded to a chip or wafer including base substrate 201, and then vias THV can be formed in via wiring region THV-A to implement a COP structure.

[0096] Figures 11A to 16B This is a cross-sectional view of a method for manufacturing a three-dimensional non-volatile memory device according to an exemplary embodiment of the present invention, wherein the figure numbered A (e.g., 11A) is a cross-sectional view of the main cell region CAm, and the figure numbered B (e.g., 11B) is a cross-sectional view of the first edge cell region CAe1. Both will be referred to together. Figure 4 And as described in Figure 7 Figures 11A to 16B And will simply repeat or omit the reference. Figure 4 The description is as shown in Figure 7.

[0097] Reference Figure 11A and Figure 11BAt least one insulating layer 103-2 and a support layer 105 are formed on a substrate 101. The at least one insulating layer 103-2 may include a horizontal insulating layer 103b and thin-film insulating layers 103u and 103d respectively on the upper and lower surfaces of the horizontal insulating layer 103b. For example, the horizontal insulating layer 103b may be formed of a silicon nitride film, and the thin-film insulating layers 103u and 103d may be formed of a silicon oxide film. Additionally, the support layer 105 may be formed of polycrystalline silicon. However, the materials of the at least one insulating layer 103-2 and the support layer 105 are not limited thereto.

[0098] A molded structure ST1 is formed on the support layer 105. The molded structure ST1 may include sacrificial layers SL and interlayer insulating layers ILD stacked vertically and alternately. In the molded structure ST1, the sacrificial layer SL may be formed of a material that is etch-selective to the interlayer insulating layer ILD. For example, the sacrificial layer SL may be formed of a silicon nitride film, and the interlayer insulating layer ILD may be formed of a silicon oxide film. However, the materials of the sacrificial layer SL and the interlayer insulating layer ILD are not limited to these.

[0099] A stepped molding structure ST1 is formed in the extension region EA and the outer pad region MOA through a trimming process. Subsequently, a material layer covering the molding structure ST1 is deposited on the entire surface of the substrate 101 and planarized to form a planar insulating layer 150. The planar insulating layer 150 can cover the molding structure ST1 in the cell region CA and the stepped molding structure ST1 in the extension region EA and the outer pad region MOA.

[0100] Vertical holes are formed through the molding structure ST1 in the unit region CA and the extension region EA. The vertical holes can be formed in a manner in which the upper part of the substrate 101 is recessed by passing through the molding structure ST1, the support layer 105, and at least one insulating layer 103-2. A sidewall multiple insulating layer SMI, a channel layer CL, and a buried insulating layer BI are formed in the vertical holes to form vertical structures VCS and VCSd.

[0101] A first upper interlayer insulating layer 160 is formed on the entire surface of substrate 101, covering the upper surfaces of vertical structures VCS and VCSd and a planar insulating layer 150. Subsequently, the first upper interlayer insulating layer 160, the planar insulating layer 150, and the molding structure ST1 are etched to form an isolation trench DT extending in a first direction (x-direction). The sacrificial layer SL and the interlayer insulating layer ILD of the molding structure ST1 may be exposed on the sidewalls of the isolation trench DT. The isolation trench DT may include a main isolation trench DTm in the main cell region CAm and a first edge isolation trench DTe1 in the first edge cell region CAe1. The first edge isolation trench DTe1 may be deeper than the main isolation trench DTm.

[0102] like Figure 11A and Figure 11B As shown, the main isolation trench DTm can be formed to expose at least one insulating layer 103-2 by passing through the molding structure ST1 and the support layer 105. The first edge isolation trench DTe1 can be formed in such a form that the upper part of the substrate 101 is recessed by passing through the molding structure ST1, the support layer 105 and at least one insulating layer 103-2.

[0103] Reference Figure 12A and Figure 12B A spacer material layer SP is formed on the entire surface of the substrate 101. The spacer material layer SP may cover the interior of the isolation trench DT, for example, the bottom surface and sidewalls of the isolation trench DT. Additionally, the spacer material layer SP may cover the upper surface of the first upper interlayer insulating layer 160. The spacer material layer SP may be formed of polysilicon. However, the material of the spacer material layer SP is not limited to this.

[0104] Reference Figure 13A and Figure 13B The lower surface of the spacer material layer SP is etched to expose the corresponding material layer through the lower surface of the isolation trench DT. The upper portion of the material layer exposed by etching the lower surface of the spacer material layer SP can be recessed. Specifically, in the main isolation trench DTm, at least one insulating layer 103-2 is exposed through the lower surface of the main isolation trench DTm by etching the lower surface of the spacer material layer SP, and the upper portion of at least one insulating layer 103-2 can be further recessed. In this case, for example, the upper portion of the horizontal insulating layer 103b can be recessed by removing the overlying thin film insulating layer 103u. In the first edge isolation trench DTe1, the substrate 101 is exposed through the lower surface of the first edge isolation trench DTe1 by etching the lower surface of the spacer material layer SP, and the upper portion of the substrate 101 can be further recessed.

[0105] Etching of the lower surface of the spacer material layer SP can be performed, for example, by an etch-back process. Typically, an etch-back process etches the entire spacer material layer SP to a uniform thickness. However, in the memory device manufacturing process of this embodiment, before the etch-back process, a thin protective film can be formed on the spacer material layer SP on the upper surface of the first upper interlayer insulating layer 160 and at the entrance of the isolation trench DT. Then, the etch-back process can be performed to etch only the lower surface portion of the spacer material layer SP. Here, the protective film can be a material layer containing, for example, carbon (C).

[0106] Reference Figure 14A and Figure 14BThe horizontal insulating layer 103b and sacrificial layer SL, exposed by etching the lower surface of the spacer material layer SP, are removed. Specifically, in the main isolation trench DTm, the horizontal insulating layer 103b is removed. In this case, an empty space is formed between the thin film insulating layers 103u and 103d. The horizontal insulating layer 103b and sacrificial layer SL are formed of silicon nitride film, and therefore can be removed by a pull-back process using an etchant containing phosphoric acid. In the first edge isolation trench DTe1, only the polysilicon substrate 101 is exposed. In this case, the horizontal insulating layer 103b and sacrificial layer SL are covered by the spacer material layer SP, and therefore the horizontal insulating layer 103b and sacrificial layer SL do not need to be etched.

[0107] In the process of removing the horizontal insulating layer 103b and the sacrificial layer SL, the thin film insulating layers 103u and 103d on the upper and lower surfaces of the horizontal insulating layer 103b can also be removed by dry etching. Additionally, in the process of removing the thin film insulating layers 103u and 103d, the sidewall multi-insulating layer SMI of the vertical structure VCS can also be removed, thereby exposing the channel layer CL of the vertical structure VCS. Figure 14A and Figure 14B The state before etching thin film insulating layers 103u and 103d is shown, and thus, the state in which the sidewall multiple insulating layers SMI of the vertical structure VCS are maintained is shown.

[0108] Reference Figure 15A and Figure 15B The portion of the horizontal insulating layer 103b and the sacrificial layer SL that has been removed is replaced with a conductive layer. Specifically, in the main isolation trench DTm, a conductive layer of polysilicon, for example, can replace the horizontal insulating layer 103b. For example, the conductive layer can be disposed in the space between the thin-film insulating layers 103u and 103d. Figure 15A and Figure 15B As shown, in the conductive layer replacement process, the conductive layer can be filled from the inside in the horizontal direction, resulting in a structure in which the lower part of the isolation trench DT is recessed inward. This is because in the conductive layer replacement process, the process is performed by repeatedly etching and depositing to form a void-free conductive layer. When such a process is performed continuously, the conductive layer can be filled up to the lower portion of the isolation trench DT.

[0109] By replacing the conductive layer, a first horizontal layer 103 can be formed in the main cell region CAm with the main isolation trench DTm, which contacts the channel layer CL of the vertical structure VCS. As described above, the first horizontal layer 103 can form the common source line CSL.

[0110] After the first horizontal layer 103 is formed, the spacer material layer SP is removed. By removing the spacer material layer SP, the sacrificial layer SL and the interlayer insulation layer ILD of the molded structure ST1 can be exposed again to the sidewalls of the isolation trench DT. At the lowest part of the first edge isolation trench DTe1, at least one insulation layer 103-2 can be exposed to the sidewalls of the first edge isolation trench DTe1.

[0111] Reference Figure 16A and Figure 16B The electrode layer EL can be formed by replacing the sacrificial layer SL of the molded structure ST1 with a conductive material (e.g., W). Forming the electrode layer EL by the replacement process can form a stacked structure ST in which the electrode layer EL and the interlayer insulating layer ILD are alternately stacked. In the first edge isolation trench DTe1, at least one material layer 103-1 can be formed by replacing the horizontal insulating layer 103b of at least one insulating layer 103-2 with W. The at least one material layer 103-1 may include, for example, a second horizontal layer 103a and thin film insulating layers 103u and 103d on the upper and lower surfaces of the second horizontal layer 103a, respectively. Additionally, at least one material layer 103-1 may contact the sidewall multiple insulating layer SMI of the vertical structure VCS. The first edge cell region CAe1 with the first edge isolation trench DTe1 is not a region where normal cells are arranged; therefore, the second horizontal layer 103a does not need to perform electrical functions.

[0112] Subsequently, an insulating layer DA can be formed by filling a portion of the insulating trench DT with an insulating layer. The insulating layer DA may include, for example, a main insulating layer DAm in the main cell region CAm and a first edge insulating layer DAe1 in the first edge cell region CAe1.

[0113] Subsequently, vertical contacts VC can be formed in the extension region EA, and contact plugs CP, sub-bit lines SBL, bit line contact plugs BCP, bit lines BL, and interconnect lines ICL can be formed in the cell region CA and the extension region EA. Additionally, vias THV can be formed in the via wiring region THV-A.

[0114] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A three-dimensional non-volatile memory device, comprising: A first substrate includes a unit region and an extension region disposed on one side of the unit region in a first direction, wherein the extension region has a stepped structure. A vertical structure that extends vertically from the upper surface of the first substrate; A stacked structure having electrode layers and interlayer insulating layers alternately stacked on the first substrate along the sidewalls of the vertical structure; An insulating layer extending on the first substrate in the first direction and isolating the electrode layer in a second direction intersecting the first direction; and A through-hole wiring region, which is adjacent to the cell region or the extension region, and has a through-hole passing through the first substrate. The unit region includes a main unit region in which normal units are arranged and an edge unit region in the peripheral portion of the unit region. The insulating layer includes a main insulating layer in the main unit region and an edge insulating layer in the edge unit region, and The lower surface of the main insulating layer is higher than the upper surface of the first substrate and has a depth different from that of the lower surface of the edge insulating layer.

2. The three-dimensional non-volatile memory device of claim 1, further comprising a support layer disposed beneath the stacked structure on the first substrate and extending parallel to the upper surface of the first substrate. in, The vertical structure includes a channel layer extending in the vertical direction and multiple insulating layers on the sidewalls of the channel layer. In the main unit region, a first horizontal layer is disposed below the support layer. The first horizontal layer extends parallel to the upper surface of the first substrate, passes through the sidewall multiple insulating layers, and contacts the channel layer. In the edge unit region, at least one material layer is disposed below the support layer, the at least one material layer extending parallel to the upper surface of the first substrate, and the at least one material layer includes any of the following: a first horizontal layer that passes through the sidewall multi-insulating layer and contacts the channel layer, a first insulating layer that contacts the sidewall multi-insulating layer, and a second horizontal layer that contacts the sidewall multi-insulating layer.

3. The three-dimensional non-volatile memory device of claim 1, further comprising a support layer disposed beneath the stacked structure on the first substrate and extending parallel to the upper surface of the first substrate. in, The edge unit region includes a first edge unit region adjacent to the via wiring region in the second direction and a second edge unit region adjacent to the outermost edge of the unit region. The edge isolation insulation layer includes a first edge isolation insulation layer in the first edge unit region and a second edge isolation insulation layer in the second edge unit region. At least one material layer is disposed in the edge unit region below the support layer and extending parallel to the upper surface of the first substrate. The lower surface of the first edge-isolating insulating layer is lower than the upper surface of the first substrate, and The at least one material layer includes a horizontal layer in contact with multiple insulating layers on the sidewalls of the vertical structure and a thin film insulating layer on the upper and lower surfaces of the horizontal layer.

4. The three-dimensional non-volatile memory device of claim 1, further comprising a support layer disposed beneath the stacked structure on the first substrate and extending parallel to the upper surface of the first substrate. in, At least one material layer extending below the support layer and parallel to the upper surface of the first substrate is disposed in the edge unit region, and The lower surface of the edge-isolated insulating layer is higher than the upper surface of the at least one material layer.

5. The three-dimensional non-volatile memory device according to claim 1, further comprising: A support layer is disposed beneath the stacked structure on the first substrate and extends parallel to the upper surface of the first substrate. The extended region and the edge unit region adjacent to the extended region include at least one material layer between the support layer and the first substrate. The main insulating layer extends into the extended region, and the depth of the main insulating layer in the extended region is greater than the depth in the cell region.

6. The three-dimensional non-volatile memory device according to claim 2, wherein, The first horizontal layer comprises polycrystalline silicon, and The second horizontal layer comprises tungsten.

7. The three-dimensional non-volatile memory device of claim 1, further comprising a support layer disposed beneath the stacked structure on the first substrate and extending parallel to the upper surface of the first substrate. in, The lower surface of the vertical structure is lower than the upper surface of the first substrate, and In the main unit region, the upper surface of the horizontal layer that contacts the channel layer of the vertical structure is higher than the lower surface of the support layer, and the lower surface of the horizontal layer is lower than the upper surface of the first substrate.

8. The three-dimensional non-volatile memory device according to claim 1, further comprising a peripheral circuit region on the second substrate, in, The peripheral circuit area is located below the first substrate, and The wires in the unit area are connected to the wires in the peripheral circuit area through the through-hole.

9. A three-dimensional non-volatile memory device, comprising: A substrate includes a cell region in which cells are arranged and an extension region disposed on one side of the cell region in a first direction, wherein the extension region has a stepped structure in the first direction. A vertical structure that extends vertically from the upper surface of the substrate; A stacked structure having electrode layers and interlayer insulating layers alternately stacked on the substrate along the sidewalls of the vertical structure; and An insulating layer extends on the substrate in the first direction and isolates the electrode layer in a second direction intersecting the first direction. The unit region includes a main unit region in which normal units are arranged and an edge unit region located in the peripheral portion of the unit region. The insulating layer includes a main insulating layer in the main unit region and an edge insulating layer in the edge unit region, and At least two of the edge isolation insulation layers have different depths.

10. The three-dimensional non-volatile memory device according to claim 9, wherein, The through-hole wiring region having through-holes through the substrate is arranged adjacent to the edge cell region. The lower surface of the main insulating layer is higher than the upper surface of the substrate, and The lower surface of the edge-isolated insulating layer adjacent to the through-hole wiring area is lower than the upper surface of the substrate.

11. The three-dimensional non-volatile memory device according to claim 9, wherein, The lower surface of the main insulating layer is higher than the upper surface of the substrate, and One of the edge insulating layers has its lower surface higher than the lower surface of the main insulating layer in a second direction.

12. The three-dimensional non-volatile memory device according to claim 9, further comprising: A support layer is disposed below the stacked structure on the substrate and extends parallel to the upper surface of the substrate; as well as At least one material layer is disposed between the support layer and the substrate and extends parallel to the upper surface of the substrate. The vertical structure includes a channel layer extending in the vertical direction and multiple insulating layers on the sidewalls of the channel layer. The at least one material layer includes any of the following: a first horizontal layer that passes through the sidewall multi-insulation layer and contacts the channel layer, a horizontal insulation layer that contacts the sidewall multi-insulation layer, and a second horizontal layer that contacts the sidewall multi-insulation layer.

13. A method for manufacturing a three-dimensional non-volatile memory device, the method comprising: At least one insulating layer and a support layer are formed on a substrate, wherein the substrate includes a unit region and an extension region; A molded structure is formed by alternately stacking interlayer insulating layers and sacrificial layers on the support layer; A vertical structure is formed that extends vertically from the upper surface of the substrate and passes through the at least one insulating layer, the support layer, and the molding structure; An isolation trench is formed that extends on the substrate in a first direction and separates the cell region and the extended region in a second direction intersecting the first direction; Forming spacers that cover the lower surface and sidewalls of the isolation trench; The at least one insulating layer is exposed by removing the lower surface of the spacer; A first horizontal layer in contact with the channel layer of the vertical structure is formed by replacing the at least one insulating layer with a first conductive layer. The interlayer insulation layer and the sacrificial layer are exposed to the sidewalls of the isolation trench by removing the spacers in the isolation trench; A stacked structure with electrode layers and interlayer insulating layers alternately stacked along the sidewalls of the vertical structure is formed by replacing the sacrificial layer with a second conductive layer; and An insulating layer is formed by filling the insulating trench with a buried insulating layer. The unit region includes a main unit region in which normal units are arranged and an edge unit region in the peripheral portion of the unit region. The isolation trench includes a main isolation trench in the main unit region and multiple edge isolation trenches in the edge unit region. The main isolation trench exposes the at least one insulating layer, and Some of the plurality of edge isolation trenches expose the substrate.

14. The method according to claim 13, wherein, The at least one insulating layer includes a horizontal insulating layer and thin film insulating layers on the upper and lower surfaces of the horizontal insulating layer, and Exposing the at least one insulating layer includes: The horizontal insulation layer is exposed through the lower surface of the isolation trench in the main unit region; and In the edge unit region, the substrate is exposed through the lower surface of the isolation trench and the at least one insulating layer is covered by the spacer.

15. The method of claim 14, wherein, Exposing the interlayer insulation layer and the sacrificial layer includes exposing at least one insulation layer to the sidewall of the isolation trench in the edge cell region. Forming the stacked structure includes forming a second horizontal layer by replacing the horizontal insulating layer with the second conductive layer, and The second horizontal layer is in contact with the sidewall multiple insulating layers of the vertical structure, and the thin film insulating layer is held on the upper and lower surfaces of the second horizontal layer.

16. The method of claim 13, wherein, The via wiring region, including vias passing through the substrate, is arranged adjacent to the edge cell region. The edge unit region includes a first edge unit region adjacent to the via wiring region in the second direction and a second edge unit region located at the outermost part of the unit region, and Exposing the at least one insulating layer includes: The horizontal insulation layer is exposed through the lower surface of the main isolation trench in the main unit region; and The substrate is exposed through the lower surface of the edge isolation trench in the first edge unit region.

17. The method according to claim 13, wherein, Forming the at least one insulating layer and the support layer includes: removing the at least one insulating layer at a first region corresponding to the isolation trench in the extended region and a second region corresponding to the boundary between the cell region and the extended region, and forming the support layer directly on the substrate.

18. The method according to claim 13, wherein, The lower surface of the vertical structure is lower than the upper surface of the substrate. Forming the first horizontal layer includes: in the main unit region, removing the sidewall multiple insulating layers of the vertical structure and exposing the channel layer, such that the first horizontal layer contacts the channel layer; The upper surface of the portion of the first horizontal layer that contacts the channel layer is higher than the lower surface of the support layer, and The lower surface of the portion is lower than the upper surface of the substrate.

19. The method of claim 13, further comprising: Before forming the vertical structure, the sacrificial layer is exposed in the first direction in the extended region, and the sacrificial layer is exposed in the second direction outside the unit region; as well as After the insulating layer is formed, a vertical contact element that contacts the electrode layer is formed in the extended region. The vertical contact is formed by forming a through-hole in the through-hole wiring region between the unit regions or between the extended regions, where the through-hole passes through the substrate and connects to a line in the peripheral circuit region that overlaps with the substrate.

20. A three-dimensional non-volatile memory device, comprising: A substrate comprising a first unit region and a second unit region disposed on one side of the first unit region in a first direction; A first vertical structure extends in the first unit region from the upper surface of the substrate in a vertical direction; A second vertical structure extends in the second unit region from the upper surface of the substrate in the vertical direction; A stacked structure having electrode layers and interlayer insulating layers alternately stacked on the substrate along the sidewalls of the first vertical structure and the second vertical structure; An insulating layer extends on the substrate in a second direction intersecting the first direction and isolates the electrode layer in the first direction; A horizontal layer is disposed on the upper surface of the substrate and penetrates the sidewall of the first vertical structure. as well as A material layer is disposed on the upper surface of the substrate and contacts the sidewall of the second vertical structure. The insulating layer includes a first insulating layer in the first unit region and a second insulating layer in the second unit region. The lower surface of the first insulating layer is higher than the upper surface of the substrate and has a depth different from that of the lower surface of the second insulating layer.

Images