Semiconductor device and method of manufacturing the same, power module, power conversion circuit, vehicle

Abstract

This invention discloses a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: a termination region, a transition region, and a cell region; the transition region surrounds the cell region, and the termination region surrounds the transition region; a semiconductor body includes a first surface and a second surface disposed opposite to each other; the first surface has a gate trench located in the cell region; a gate is located within the gate trench; a metal structure is located on the side of the first surface away from the second surface and in the transition region, the metal structure including at least one of a gate metal and a first source metal; a passivation layer is located in the transition region and the termination region, and is located on the side of the metal structure away from the first surface, covering at least a portion of the surface of the metal structure; the passivation layer has at least one break; the passivation layer includes a first oxide layer, a nitride layer, and a second oxide layer stacked sequentially; and a drain is located on the second surface. This invention can improve the reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) are widely used in power electronics, automotive, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] Trench-type silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) in related technologies have advantages such as high current density and small cell spacing. However, they are prone to failure during temperature cycling tests, resulting in low reliability. Summary of the Invention

[0004] This invention provides a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, to improve the reliability of semiconductor devices.

[0005] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a termination region, a transition region, and a cell region; the transition region surrounds the cell region, and the termination region surrounds the transition region; The semiconductor body includes a first surface and a second surface disposed opposite to each other; the first surface is provided with a gate trench located in the cell region; The gate is located within the gate trench; A metal structure is located on the side of the first surface away from the second surface and in the transition region, the metal structure comprising at least one of a gate metal and a first source metal; A passivation layer is located in the transition region and the terminal region, and on the side of the metal structure away from the first surface, and covers at least a portion of the surface of the metal structure; the passivation layer has at least one break; the passivation layer includes a first oxide layer, a nitride layer and a second oxide layer sequentially stacked on the side of the metal structure away from the first surface. The drain electrode is located on the second surface.

[0006] Optionally, the metal structure includes a third surface remote from the first surface, and the break in the passivation layer exposes the third surface.

[0007] Optionally, the surfaces of the passivation layer that are in contact with the fracture are located on the same plane.

[0008] Optionally, along the thickness direction of the semiconductor device, the projection of the fracture on the first surface does not overlap with the projection of the metal structure on the first surface; the passivation layer covers the metal structure.

[0009] Optionally, the semiconductor device further includes a first insulating layer that covers the passivation layer and the metal structure exposed by the break.

[0010] Optionally, the metal structure includes the gate metal and the first source metal; the semiconductor device further includes a gate line layer located between the gate metal and the first surface; the gate metal is disposed in contact with the gate line layer.

[0011] According to another aspect of the present invention, a method for fabricating a semiconductor device is provided. The semiconductor device includes: a termination region, a transition region, and a cell region; the transition region surrounds the cell region, and the termination region surrounds the transition region; the fabrication method includes: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; the first surface is provided with a gate trench located in the cell region; A gate is formed within the gate trench; A metal structure is formed on the side of the first surface away from the second surface, the metal structure being located in the transition region, the metal structure comprising at least one of a gate metal and a first source metal; A passivation layer is formed on the side of the metal structure away from the first surface. The passivation layer is located in the transition region and the terminal region and covers at least a portion of the surface of the metal structure. The passivation layer has at least one break. The passivation layer includes a first oxide layer, a nitride layer and a second oxide layer sequentially stacked on the side of the metal structure away from the first surface. A drain electrode is formed on the second surface.

[0012] Optionally, forming a passivation layer on the side of the metal structure away from the first surface includes: A passivation material layer is formed on the entire surface. The passivation material layer includes a first sub-part and a second sub-part. The first sub-part is located in the cell region, and the second sub-part is located in the terminal region. The second sub-part is the portion of the passivation material layer whose distance from the first surface is greater than or equal to the distance between the first sub-part and the first surface. Forming a photolithographic material layer covering the passivation material layer; Thin the photolithography material layer to expose the first sub-section and the second sub-section of the passivation material layer; Remove the first sub-part and the second sub-part to form the passivation layer; Remove the thinned photolithographic material layer.

[0013] Optionally, forming a passivation layer on the side of the metal structure away from the first surface includes: A passivation material layer is formed over the entire surface; A photolithographic material layer is formed that partially covers the passivation material layer, the photolithographic material layer exposing the portion of the passivation material layer located in the cell region and the portion corresponding to the fracture. Remove the photolithography material layer to expose the passivation material layer to form the passivation layer; Remove the photolithography material layer.

[0014] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device as described above, the substrate being used to support the semiconductor device.

[0015] According to another aspect of the present invention, a power conversion circuit is provided, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described above, the semiconductor device being electrically connected to the circuit board.

[0016] According to another aspect of the present invention, a vehicle is provided, including a load and a power conversion circuit as described above, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0017] The technical solution of this invention employs a semiconductor device comprising a termination region, a transition region, and a cell region; the transition region surrounds the cell region, and the termination region surrounds the transition region; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the first surface has a gate trench located in the cell region; a gate is located within the gate trench; a metal structure is located on the side of the first surface away from the second surface and in the transition region, the metal structure including at least one of a gate metal and a first source metal; a passivation layer is located in the transition region and the termination region, and is located on the side of the metal structure away from the first surface, covering at least a portion of the surface of the metal structure; the passivation layer has at least one fracture; the passivation layer includes a first oxide layer, a nitride layer, and a second oxide layer sequentially stacked on the side of the metal structure away from the first surface; and a drain is located on the second surface. The fracture in the passivation layer can divide the passivation layer into multiple smaller, dispersed structures, which on the one hand can reduce the stress generated during temperature cycling tests; on the other hand, it can also release stress through the fracture, thereby avoiding the risk of passivation layer fracture and improving the reliability of the semiconductor device. In addition, the passivation layer adopts a combination of multiple layers and a break, which can reduce the probability of semiconductor device failure during temperature cycling tests and high temperature, high humidity and high pressure reverse bias tests, thereby improving the reliability of semiconductor devices.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention; Figure 3 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention; Figures 4-20 A schematic diagram of the product structure corresponding to the main process flow of the semiconductor device fabrication method provided in the embodiments of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, with reference to... Figure 1 The semiconductor device includes: a terminal region NAA2, a transition region NAA1, and a cell region AA; the transition region NAA1 surrounds the cell region AA, and the terminal region NAA2 surrounds the transition region NAA1; the semiconductor device includes a semiconductor body 100, a gate 721, a metal structure 81, a passivation layer 82, and a drain 90. The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other; the first surface 101 is provided with a gate trench 72 located in the cell region AA; a gate 721 is disposed in the gate trench 72; a metal structure 81 is located on the side of the first surface 101 away from the second surface 102 and is located in the transition region NAA1, the metal structure 81 includes at least one of a gate metal 811 and a first source metal 812; a passivation layer 82 is located in the transition region NAA1 and the terminal region NAA2, and is located on the side of the metal structure 81 away from the first surface 101, and covers at least a portion of the surface of the metal structure 81; the passivation layer 82 is provided with at least one break 82A; the passivation layer 82 includes a first oxide layer 821, a nitride layer 822 and a second oxide layer 823 sequentially stacked on the side of the metal structure 81 away from the first surface 101; a drain 90 is located on the second surface 102.

[0024] Specifically, the semiconductor device is, for example, a silicon carbide MOSFET, wherein the material of the semiconductor body 100 can be a third-generation wide-bandgap semiconductor, including silicon carbide. In some embodiments, the semiconductor device can be an N-type MOSFET, and in other embodiments, the semiconductor device can also be a P-type MOSFET. When the semiconductor body is an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type; when the semiconductor device is a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. For example, regions with an N-type conductivity type can be formed by N-type doping, and the dopant ions for N-type doping can be phosphorus (P) ions or nitrogen (N) ions; regions with a P-type conductivity type can be formed by P-type doping, and the dopant ions for P-type doping can be aluminum (Al) ions or boron (B) ions.

[0025] In some embodiments, the semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body includes a first region 60 and a well region 50 located in cell region AA; the first region 60 is configured with a first conductivity type and located on the first surface 101, and the well region 50 is configured with a second conductivity type and located on the side of the first region 60 away from the first surface 101; the semiconductor body 100 also includes a second region 30 located on the side of the well region 50 away from the first surface 101. The semiconductor body 100 may include at least one epitaxial layer for forming the second region 30, the well region 50, and the first region 60. The first region 60 and the second region 30 have the same conductivity type, while the conductivity type of the well region 50 is different from that of the first region 60. For ease of description, the following description uses N-type as the first conductivity type and P-type as the second conductivity type. The first region 60 is used to provide a conductive channel between the well region 50 and the source metal, and has a low contact resistance with the source metal. When the semiconductor device is in the off state, the well region 50 blocks the conductive channel between the first region 60 and the second region 30. When the voltage applied between the gate 721 and the source metal is greater than the threshold voltage of the semiconductor device, the gate 721 attracts minority carriers (such as electrons) in the well region 50 to move towards the region of the gate 721, causing the portion of the well region 50 near the gate trench 72 to invert to the first conductivity type. That is, at this time, the first region 60, the portion of the well region 50 near the gate trench 72, and the second region 30 have the same conductivity type. When a voltage is applied between the source metal and the drain, current can be generated, and the semiconductor device is in the on state.

[0026] The semiconductor device contains multiple cells within its cellular region AA. Each cell can be understood as a MOSFET structure. By connecting multiple cells in parallel, the semiconductor device's current-carrying capacity is enhanced. Each cell corresponds to a gate trench 72. The semiconductor device also includes a gate oxide layer 71, which insulates the gate 721 from the conductive channel of the cell. The gate oxide layer 71 can be formed by thermal oxidation of the inner wall of the gate trench 72. In other words, the gate oxide layer 71 can be formed directly from the semiconductor body itself.

[0027] A metal structure 81 is provided in the transition region NAA1. The metal structure 81 may include a gate metal 811, which is used to connect the gates 721 of each cell. More specifically, a gate line layer 75 may be provided in the transition region NAA1. The material of the gate line layer 75 is the same as that of the gate 721, and they are integral structures. The gate metal 811 and the gate line layer 75 are in contact. The metal structure 81 may also include a first source metal 812. When the metal structure 81 includes the first source metal 812, the source metal of the semiconductor device includes a second source metal 74 located in the cell region AA and located on the first surface 101, as well as the first source metal 812. The second source metal 74 and the first source metal 812 may be integrally connected to be connected to the same potential. Of course, it is understood that the metal structure 81 may only include the gate metal 811 or only include the first source metal 812. A fourth region 84 is also provided in the transition region NAA1. The fourth region 84 surrounds the cell region AA, is located on the first surface 101 and is in contact with the first source metal 812. The fourth region 84 is configured with the second conductivity type and its ion doping concentration is greater than that of the well region 50. The fourth region 84 can protect the cells in the cell region AA and prevent the cells from being disturbed by external electric fields, etc.

[0028] In the terminal region NAA2, multiple field limiting rings 85 are provided. The field limiting rings 85 are located on the first surface, are configured as the second conductivity type, and surround the transition region NAA1. The field limiting rings 85 are used to modulate the electric field distribution at the fourth region 84 to prevent the electric field at the fourth region 84 from becoming too concentrated and causing breakdown when a high voltage is applied to the drain 90.

[0029] The transition region NAA1 and the termination region NAA2 require passivation layer 82 for protection. In traditional passivation layer 82 designs, the passivation layer 82 is a single, large-scale structure in both the transition region NAA1 and the termination region NAA2. Due to the high pressure between the passivation layer 82 and the metal structure 81, their coefficients of thermal expansion differ significantly. During temperature cycling reliability testing, the semiconductor device undergoes transitions between high and low temperatures. The inconsistent deformation of the metal structure 81 and the passivation layer 82 leads to high stress in the passivation layer 82. Since the passivation layer 82 is relatively brittle, it can crack under high stress, resulting in failure.

[0030] In this embodiment, the passivation layer 82 has at least one break 82A, meaning that the passivation layer 82 is not a large, monolithic structure, but rather divided into multiple smaller, dispersed structures. During temperature cycling tests, on the one hand, the smaller size of each dispersed passivation layer 82 results in less stress; on the other hand, the break 82A allows stress to be released, ensuring that the passivation layer 82 does not fracture, preventing semiconductor device failure, and improving the reliability of the semiconductor device. Furthermore, the thermal expansion coefficients of the first oxide layer 821 and the metal structure 81 are closer, thus the first oxide layer 821 can reduce the stress intensity of the nitride layer 822 on the metal structure 81. Simultaneously, the discontinuity of the passivation layer 82 structure reduces the probability of leakage at the interface under high temperature, high humidity, and high pressure reverse bias experiments. In addition, the nitride layer 822 improves the passivation layer 82's ability to isolate moisture, while the second oxide layer 823 improves the passivation layer 82's ability to isolate electric fields, further enhancing the reliability of the semiconductor device. In summary, using a combination of multiple passivation layers and break points in semiconductor devices can reduce the probability of failure during temperature cycling tests and high-temperature, high-humidity, high-voltage reverse bias tests, thereby improving the reliability of semiconductor devices.

[0031] The technical solution of this embodiment uses a semiconductor device including a termination region, a transition region, and a cell region; the transition region surrounds the cell region, and the termination region surrounds the transition region; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the first surface has a gate trench located in the cell region; a gate is located in the gate trench; a metal structure is located on the side of the first surface away from the second surface and in the transition region, the metal structure including at least one of a gate metal and a first source metal; a passivation layer is located in the transition region and the termination region, and is located on the side of the metal structure away from the first surface, and covers at least a portion of the surface of the metal structure; the passivation layer has at least one fracture; the passivation layer includes a first oxide layer, a nitride layer, and a second oxide layer sequentially stacked on the side of the metal structure away from the first surface; a drain is located on the second surface. The fracture in the passivation layer can divide the passivation layer into multiple smaller dispersed structures, which can reduce the stress generated during temperature cycling tests on the one hand, and release stress through the fracture on the other hand, thereby avoiding the risk of passivation layer fracture and improving the reliability of the semiconductor device. In addition, the passivation layer adopts a combination of multiple layers and a break, which can reduce the probability of semiconductor device failure during temperature cycling tests and high temperature, high humidity and high pressure reverse bias tests, thereby improving the reliability of semiconductor devices.

[0032] Optionally, such as Figure 1 As shown, the semiconductor body may further include a third region 20, which is located on the side of the second region 30 away from the first surface 101. The conductivity type of the third region 20 may be the same as that of the second region 30. That is, the third region 20 is of the first conductivity type, and its ion doping concentration may be lower than that of the second region 30. The third region 20 can be understood as a drift region, or an N-region, which can be used to withstand higher breakdown voltages when the semiconductor device is turned off.

[0033] Optionally, such as Figure 1 As shown, the semiconductor device also includes a fifth region 40, which is located on the first surface and is disconnected from the first region 60, the well region 50, and the second source metal 74. The fifth region 40 is of the second conductivity type and is used to provide a stable potential for the well region 50. The fifth region 40, the fourth region 84, and the field confinement ring 85 can have the same ion doping concentration and can be formed simultaneously.

[0034] Optionally, such as Figure 1 As shown, the semiconductor body 100 may further include a substrate 10, which is of a first conductivity type. Of course, in some embodiments, the semiconductor body may not include a substrate 10. When the semiconductor body 100 includes a substrate 10, the surface of the substrate 10 away from the first surface 101 is the second surface 102 of the semiconductor body 100.

[0035] Optionally, in some embodiments, the semiconductor body includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer is used to form a third region 20. The second epitaxial layer is used to form a second region 30, and a first region 60, a well region 50, a fifth region 40, a fourth region 84, and a field confinement ring 85 can be formed in the second epitaxial layer by means of ion implantation or the like.

[0036] Optionally, continue to refer to Figure 1 In some embodiments, the semiconductor device further includes a field oxide structure 76 located in the transition region NAA1 and the terminal region NAA2, the field oxide structure 76 being used to isolate the gate line layer 75 and the fourth region 84. The semiconductor device also includes a dielectric layer 73, the portion of which in the cell region AA is used to isolate the gate 721 and the second source metal 74. The portion of which in the transition region NAA1 is used to isolate the metal structure and the field oxide structure.

[0037] Optionally, continue to refer to Figure 1 In some embodiments, the metal structure 81 includes a third surface 81A away from the first surface 101, and the break 82A of the passivation layer 82 exposes the third surface 81A.

[0038] Specifically, the metal structure 81 is a relatively high protrusion compared to other structures on the first surface 101. In other words, the third surface 81A is the surface that the passivation layer 82 needs to cover with the greatest distance from the first surface 101. However, other parts of the transition region NAA1 and the terminal region NAA2 located on the first surface, such as the dielectric layer, are relatively close to the first surface. Therefore, the passivation layer 82 has a larger drop between the third surface 81A and the dielectric layer 73. Due to the higher gradient at the third surface 81A, it is more susceptible to stress and prone to cracking. In this embodiment, by providing a fracture surface 82A to expose the third surface 81A, the gradient of the passivation layer 82 is lowered, thereby further reducing the risk of cracking.

[0039] Furthermore, such as Figure 1 As shown, the fracture 82A exposes the corner corresponding to the third surface 81A, which is the position where the passivation layer 82 is furthest from the first surface 101 in the thickness direction of the semiconductor device, and there is still a certain distance between the third surface 81A. With this setting, the passivation layer 82 is not placed at the corner, which can avoid the passivation layer 82 at the corner from cracking and affecting the quality of the entire passivation layer 82, and further improve the reliability of the semiconductor device.

[0040] Optionally, continue to refer to Figure 1 The surfaces of the passivation layer 82 that are in contact with the fracture surface 82A are located on the same plane.

[0041] Specifically, in this embodiment, the surfaces where the passivation layer 82 contacts the fracture surface 82A are the surfaces where the passivation layer 82 is parallel to the first surface 101 and has the largest distance from the first surface 101. In this embodiment, this surface can be formed by self-aligned etching, thereby reducing the difficulty of fracture formation and thus reducing the manufacturing cost of the semiconductor device.

[0042] Alternatively, in some implementations, such as Figure 2 As shown, Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. In this embodiment, along the thickness direction of the semiconductor device, the projection of the fracture 82A onto the first surface 101 does not overlap with the projection of the metal structure 81 onto the first surface, and the passivation layer 82 covers the metal structure 81.

[0043] Specifically, in this embodiment, the fracture surface 82A is located outside the metal structure 81. This arrangement allows the passivation layer 82 to cover the metal structure 81, thereby better protecting it. The fracture surface 82A can be located in the terminal region NAA2, or it can be located in the transition region NAA1.

[0044] Optionally, in some embodiments, when multiple fracture surfaces 82A are provided, the dimensions of different fracture surfaces 82A can be the same, and the spacing between multiple fracture surfaces 82A on the same side of the cell region AA can be the same. In this embodiment, the spacing refers to the spacing along the arrangement direction of the cell region AA and the transition region NAA1.

[0045] Optionally, in some embodiments, the first oxide layer 821 and the second oxide layer 823 may be made of the same material, for example, both may be silicon oxide, and the nitride layer 822 may be made of silicon nitride.

[0046] Optionally, continue to refer to Figure 1 and Figure 2 The semiconductor device also includes a first insulating layer 83, which covers the passivation layer 82 and the metal structure 81 exposed by the break 82A.

[0047] Specifically, the first insulating layer 83, for example, is PI adhesive, which can further protect the metal structure in the semiconductor device, reduce the impact of external mechanical shock or water-oxygen corrosion on the internal structure, and further improve the reliability of the semiconductor device. Furthermore, it should be noted that the fracture surface in this embodiment can only be used for stress relief; that is, even if the fracture surface 82A exposes the metal structure 81, the external pads and other structures connected to the metal structure 81 are not connected to the metal structure 81 within the fracture surface 82A, and the fracture surface 82A is filled by the first insulating layer 83.

[0048] Based on the same inventive concept, this invention also provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in any embodiment of this invention, such as... Figure 3 As shown, Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. The method includes: Step S110: Provide a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body includes a first region and a well region located in the cell region; the first surface is provided with a gate trench located in the cell region; Specifically, the cell region AA contains multiple cells, each of which can be understood as a MOSFET structure. The transition region NAA1 can contain a fourth region to protect the cell region AA, while the terminal region NAA2 can modulate the electric field at the edge of the fourth region.

[0049] Step S120: Form a gate in the gate trench; Specifically, the gate is, for example, polysilicon.

[0050] Step S130: A metal structure is formed on the side of the first surface away from the second surface. The metal structure is located in the transition region and includes at least one of gate metal and first source metal. Specifically, the gate metal is connected to the gate and can be connected to the subsequent gate pad. The first source metal can be connected to the second source metal located in the cell region, making the source metal of the semiconductor device a single structure; the first source metal also contacts the fourth region, thereby providing a fixed potential to the fourth region.

[0051] Step S140: A passivation layer is formed on the side of the metal structure away from the first surface. The passivation layer is located in the transition region and the terminal region and covers at least a portion of the surface of the metal structure. The passivation layer is provided with at least one fracture. The passivation layer includes a first oxide layer, a nitride layer and a second oxide layer sequentially stacked on the side of the metal structure away from the first surface. Specifically, the passivation layer has at least one break, meaning that the passivation layer is not a large, monolithic structure, but rather divided into multiple smaller, dispersed structures, no longer possessing continuity. During temperature cycling tests, on the one hand, the smaller size of each dispersed passivation layer results in less stress; on the other hand, the presence of the break allows stress to be released, thus ensuring that the passivation layer does not fracture, preventing semiconductor device failure, and improving the reliability of the semiconductor device.

[0052] In step S150, a drain electrode is formed on the second surface.

[0053] The technical solution of this embodiment employs a semiconductor device fabrication method comprising: providing a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; a gate trench located in a cell region being formed on the first surface; forming a gate in the gate trench; forming a metal structure on the side of the first surface away from the second surface, the metal structure being located in a transition region, the metal structure including at least one of a gate metal and a first source metal; forming a passivation layer on the side of the metal structure away from the first surface, the passivation layer being located in the transition region and a terminal region, and covering at least a portion of the surface of the metal structure; the passivation layer having at least one break; the passivation layer comprising a first oxide layer, a nitride layer, and a second oxide layer sequentially stacked on the side of the metal structure away from the first surface; and forming a drain on the second surface. The passivation layer is not a large, monolithic structure, but is divided into multiple smaller, dispersed structures, no longer possessing continuity. During temperature cycling tests, on the one hand, the smaller size of each dispersed passivation layer results in less stress; on the other hand, due to the break, stress can be released through the break, thereby ensuring that the passivation layer does not fracture, avoiding semiconductor device failure, and improving the reliability of the semiconductor device. In addition, the passivation layer adopts a combination of multiple layers and a break, which can reduce the probability of semiconductor device failure during temperature cycling tests and high temperature, high humidity and high pressure reverse bias tests, thereby improving the reliability of semiconductor devices.

[0054] Optionally, Figures 4-20 A schematic diagram of the product structure corresponding to the main process flow of the semiconductor device fabrication method provided in the embodiments of the present invention. (Reference) Figures 4-20 The semiconductor body includes: like Figure 4 As shown, firstly, a first epitaxial layer is epitaxially grown on substrate 10. This first epitaxial layer is used to form the third region 20; that is, the conductivity type of the first epitaxial layer is a first conductivity type. Then, as... Figure 5 As shown, a second epitaxial layer is grown on the first epitaxial layer. The second epitaxial layer is used to form the second region 30, meaning that the conductivity type of the second epitaxial layer is the first conductivity type. Then, as... Figure 6 As shown, a trap region 50, a first region 60, a fourth region 84, a fifth region 40, and a field confinement ring 85 are formed through P-type ion implantation and N-type ion implantation. Then, as... Figure 7 As shown, the gate trench 72 is formed by dry etching. Then, as... Figure 8 As shown, the field oxygen structure 76 can be formed by depositing silicon dioxide and then etching a mask. Then, as... Figure 9 As shown, the gate oxide layer 71 can be formed by thermal oxidation, and the gate 721 and gate line layer 75 can be fabricated. Then, as... Figure 10As shown, a dielectric layer 73 is deposited, and a contact hole is formed on the dielectric layer 73. This contact hole is used to form a contact between the gate metal and the gate line layer 75. Then, as... Figure 11 As shown, metal materials are deposited and photolithography is used to form source metal and gate metal.

[0055] Then, optionally, forming a passivation layer on the side of the metal structure away from the first surface includes: A passivation material layer is formed on the entire surface. The passivation material layer includes a first sub-part located in the cell region and a second sub-part located in the terminal region. The first sub-part is located in the cell region, and the second sub-part is located in the terminal region. The second sub-part is the portion of the passivation material layer whose distance from the first surface is greater than or equal to the distance between the first sub-part and the first surface. Specifically, forming a passivation material layer over the entire surface includes: forming a first oxide layer. For example... Figure 12 As shown, firstly, a first oxide material layer 8211 is deposited over the entire surface. The material of the first oxide material layer 8211 is silicon dioxide, which is used to form the subsequent first oxide layer. Then, as... Figure 13 As shown, a nitride material layer 8221 is deposited over the entire surface. The material of the nitride material layer 8221 is silicon nitride, which is used for subsequent nitride layer formation. Then, as... Figure 14 As shown, a second oxide material layer 8231 is deposited over the entire surface. The material of the second oxide material layer 8231 is silicon dioxide, which is used to form the second oxide layer in the subsequent process.

[0056] In this embodiment, the first sub-part of the passivation material layer is the portion of the second source metal 74 located away from the first surface, and needs to be removed subsequently. The second sub-part is the portion of the passivation material layer located on the side of the first sub-part away from the first surface 101.

[0057] Subsequently, as Figure 15 As shown, a photolithographic material layer is formed to cover the passivation material layer; Specifically, the photolithography material layer 201 can be made of photoresist. The photolithography material layer 201 forms a full-surface coverage, meaning that the thickness of the photolithography material layer 201 needs to be greater than the thickness of the metal structure 81.

[0058] Then, as Figure 16 As shown, the photolithography material layer is thinned to expose the first and second sub-parts of the passivation material layer; Specifically, the photolithography material layer 201 can be thinned using methods such as dry etching. The thinned photolithography material layer 201 covers the portion of the passivation material layer other than the first and second sub-parts, which needs to be retained subsequently.

[0059] Then, as Figure 17 As shown, the first sub-part and the second sub-part are removed to form a passivation layer; Specifically, the exposed silicon dioxide, silicon nitride, and silicon dioxide can be removed sequentially by dry etching.

[0060] Then, as Figure 18 As shown, the thinned photolithography material layer is removed.

[0061] Specifically, the thinned photolithography material layer can be removed using dry etching, thus preserving the passivation layer. Figures 15 to 18 In the corresponding passivation layer formation step, a self-aligned method is used to form the passivation layer, eliminating the need for a mask, which can greatly reduce the fabrication cost of semiconductor devices.

[0062] Of course, in some other implementations, in Figure 14 After that, it could also be like this: Figure 19 As shown, a photolithographic material layer is formed that partially covers the passivation material layer. This photolithographic material layer exposes the portion of the passivation material layer located in the cell region, as well as the corresponding fracture portion. Specifically, in this embodiment, a photolithographic material layer 201 is formed in the area where the passivation material layer needs to be retained using a mask. The size and position of the photolithographic material layer 201 offer greater flexibility, allowing the fracture to be positioned at any location within the terminal and transition regions. In other words, the fracture position can be... Figure 15 The same or different can be found in the same parts. Then, you can press... Figure 17 and Figure 18 The passivation layer is formed in the following order: first, the portion of the passivation material layer that needs to be removed is removed, and then the photolithography material layer is removed. In this embodiment, a photomask is used to form the photolithography material layer, which allows for more precise control over the location and size of the fracture.

[0063] After the passivation layer is fabricated, such as Figure 20 As shown, a first insulating layer 83 is formed. This can be achieved by depositing PI adhesive and photolithography to form the first insulating layer 83. Finally, the back side is first polished, and then the drain 90 is fabricated. Figure 1 or Figure 2 The semiconductor device shown.

[0064] Based on the same inventive concept, the present invention also provides a power module. The power module includes a substrate and at least one semiconductor device as described in any embodiment of the present invention, with the substrate serving to support the semiconductor device. Therefore, the beneficial effects of this power module including any semiconductor device as described in any embodiment of the present invention will not be elaborated further here.

[0065] Based on the same inventive concept, this invention also provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this invention, with the semiconductor device electrically connected to the circuit board. Therefore, the beneficial effects of this power conversion circuit including any semiconductor device as described in any embodiment of this invention will not be elaborated further here.

[0066] Based on the same inventive concept, the present invention also provides a vehicle, which includes a load and the aforementioned power conversion circuit. The power conversion circuit is used to convert alternating current to direct current, alternating current to alternating current, direct current to direct current, or direct current to alternating current, and then input the converted direct current to the load. Therefore, the beneficial effects of the vehicle including the semiconductor device described in any embodiment of the present invention will not be elaborated further here.

[0067] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0068] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized by, The semiconductor device includes: a termination region, a transition region, and a cell region; the transition region surrounds the cell region, and the termination region surrounds the transition region; The semiconductor body includes a first surface and a second surface disposed opposite to each other; the first surface is provided with a gate trench located in the cell region; The gate is located within the gate trench; A metal structure is located on the side of the first surface away from the second surface and in the transition region, the metal structure comprising at least one of a gate metal and a first source metal; A passivation layer is located in the transition region and the terminal region, and on the side of the metal structure away from the first surface, and covers at least a portion of the surface of the metal structure; the passivation layer has at least one break; the passivation layer includes a first oxide layer, a nitride layer and a second oxide layer sequentially stacked on the side of the metal structure away from the first surface. The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, wherein The metal structure includes a third surface away from the first surface, and the passivation layer exposes the third surface at a break.

3. The semiconductor device of claim 2, wherein, The passivation layer and each surface in contact with the fracture are located on the same plane.

4. The semiconductor device of claim 1, wherein Along the thickness direction of the semiconductor device, the projection of the fracture on the first surface does not overlap with the projection of the metal structure on the first surface; the passivation layer covers the metal structure.

5. The semiconductor device of claim 1, wherein The semiconductor device further includes a first insulating layer that covers the passivation layer and the metal structure exposed by the break.

6. The semiconductor device of claim 1, wherein The metal structure includes the gate metal and the first source metal; the semiconductor device further includes a gate line layer located between the gate metal and the first surface; the gate metal is disposed in contact with the gate line layer.

7. A method of manufacturing a semiconductor device, characterized by The semiconductor device includes: a termination region, a transition region, and a cell region; the transition region surrounds the cell region, and the termination region surrounds the transition region; the fabrication method includes: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; the first surface is provided with a gate trench located in the cell region; A gate is formed within the gate trench; A metal structure is formed on the side of the first surface away from the second surface, the metal structure being located in the transition region, the metal structure comprising at least one of a gate metal and a first source metal; A passivation layer is formed on the side of the metal structure away from the first surface. The passivation layer is located in the transition region and the terminal region and covers at least a portion of the surface of the metal structure. The passivation layer has at least one break. The passivation layer includes a first oxide layer, a nitride layer and a second oxide layer sequentially stacked on the side of the metal structure away from the first surface. A drain electrode is formed on the second surface.

8. The method of producing a semiconductor device according to Claim 7, wherein The formation of a passivation layer on the side of the metal structure away from the first surface includes: A passivation material layer is formed on the entire surface. The passivation material layer includes a first sub-part and a second sub-part. The first sub-part is located in the cell region, and the second sub-part is located in the terminal region. The second sub-part is the portion of the passivation material layer whose distance from the first surface is greater than or equal to the distance between the first sub-part and the first surface. Forming a photolithographic material layer covering the passivation material layer; Thin the photolithography material layer to expose the first sub-section and the second sub-section of the passivation material layer; Remove the first sub-part and the second sub-part to form the passivation layer; Remove the thinned photolithographic material layer.

9. The method of producing a semiconductor device according to Claim 7, wherein The formation of a passivation layer on the side of the metal structure away from the first surface includes: A passivation material layer is formed over the entire surface; A photolithographic material layer is formed that partially covers the passivation material layer, the photolithographic material layer exposing the portion of the passivation material layer located in the cell region and the portion corresponding to the fracture. Remove the photolithography material layer to expose the passivation material layer to form the passivation layer; Remove the photolithography material layer.

10. A power module, characterized by It includes a substrate and at least one semiconductor device as described in any one of claims 1-6, wherein the substrate is used to support the semiconductor device.

11. A power conversion circuit, characterized by, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-6, wherein the semiconductor device is electrically connected to the circuit board.

12. A vehicle characterized by comprising: The device includes a load and a power conversion circuit as described in claim 11, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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