Allocate test resources to perform tests on memory components

Abstract

A request may be received to perform a test utilizing one or more memory components. Available test resources of a test platform associated with memory components may be determined. Desired characteristics of the one or more memory components specified by the test may be determined. The one or more of the available test resources of the test platform may be assigned to the test based on characteristics of respective memory components associated with the one or more of the available test resources and the desired characteristics of the one or more memory components for the test. Furthermore, the test may be performed utilizing the assigned one or more of the available test resources of the test platform.

Description

Technical Field

[0001] The present disclosure relates generally to a memory subsystem, and more particularly to allocating test resources that perform testing of memory components of the memory subsystem. Background Art

[0002] The memory subsystem may be a storage system, such as a solid-state drive (SSD) or a hard disk drive (HDD). The memory subsystem may be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1 An example environment is described for allocating test resources for performing tests of memory components according to some embodiments of the present disclosure.

[0005] Figure 2 is a flow chart of an example method of allocating test resources for performing testing of a memory component according to some embodiments of the present disclosure.

[0006] Figure 3 is a flow chart of an example method for allocating test resources based on characteristics of memory components and requested tests in accordance with some embodiments.

[0007] Figure 4 The allocation of test resources according to some embodiments of the present disclosure is described.

[0008] Figure 5 is a flow chart of an example method of allocating available test resources for testing of memory components according to some embodiments.

[0009] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0010] Aspects of the present disclosure are directed to the allocation of test resources for performing tests of memory components. A memory subsystem is also referred to below as a "memory device". An example of a memory subsystem is a storage device coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module coupled to a CPU via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs), among others. In some embodiments, a memory subsystem may be a hybrid memory / storage device subsystem. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem and may request to retrieve data from the memory subsystem.

[0011] Memory components that have been previously tested for use in the memory subsystem may be utilized in the memory subsystem. In conventional testing processes, memory components may be placed into a chamber (i.e., an oven) that tests memory components under various temperature conditions. For example, a single chamber may be used to test multiple memory components at a particular temperature at one time. The test process may direct various operations to be performed at the memory component at a particular temperature. Such operations may include, but are not limited to, read operations, write operations, and / or erase operations. The performance and behavior of the memory component may be observed while the test process is being performed. For example, performance characteristics (e.g., read or write latency) and reliability of data stored at the memory component may be measured and recorded during the test process. However, since the chamber may only apply a single temperature to the memory component at any particular time, testing of the memory component at many different temperatures may require a significant amount of time because a test process will need to be performed for each desired temperature. In addition, the chamber may only perform a single test process at a time. Thus, if many different conditions for a test process for a memory component are required, performing different tests of the memory component under different operating conditions (e.g., different temperatures) may utilize a significant amount of time.

[0012] Aspects of the present disclosure solve the above and other deficiencies by allocating test resources for performing tests of memory components. A distributed test platform may include multiple test resources. Each test resource may be a test socket containing a memory component. The test socket may further include a temperature control component for applying a specific temperature condition to the memory component contained in the test socket. The test platform may further include multiple test boards, each of which includes one or more of the test sockets. The test boards may be organized into groups or racks, and multiple racks may be at specific locations or sites. In this way, multiple sites may include racks of test boards containing multiple test sockets. The racks of the test platform may be coupled to a resource allocator (e.g., a server or other such computing device) via a network, and the resource allocator is used to control or perform tests at various test sockets of the test platform across different test boards, test racks, and sites or locations.

[0013] The test resources of the test platform can be used to perform multiple different test processes on the test platform at the same time. For example, a first subset of test sockets can be used to perform a first test, and a second subset of test sockets of the test platform can be used to perform a second test in parallel. In this way, the resource allocator can allocate or assign test sockets to be used for new tests of memory components. The new test can specify the specific characteristics or type of memory components to be used for the test and the specific temperature of the memory components to be applied to the test socket by the temperature control component. Such characteristics may include, but are not limited to, the type (e.g., design version) of the memory component and the usage characteristics of the memory component. The resource allocator can then assign the available test sockets of the test platform to the new test based on the characteristics specified by the new test and the additional information of the test platform. For example, the available test sockets can be further assigned based on the positions of the test sockets across various test racks or sites of the test platform and the temperature control component can be used to apply the temperature specified by the test. Therefore, the test platform can be a distributed collection of test sockets across different locations or sites. Different groups of test sockets of the test platform can be assigned to different tests based on the specific characteristics of the test sockets specified by different tests.

[0014] Advantages of the present disclosure include, but are not limited to, reducing the amount of time a test platform takes to perform testing of memory components. Furthermore, since many different tests can be performed at the test platform to test many different conditions (e.g., different temperatures) during the execution of many different sequences of operations, the testing of memory components can be considered more robust because the reliability and performance of the memory components can be tested by performing many different and parallel tests. As such, since many different tests of memory components can be performed more quickly, the reliability of the memory components can also be improved because any potential defects or flaws can be identified and later addressed in the design or manufacture of the memory components to be included in the memory subsystem.

[0015] Figure 1 An example environment for allocating test resources for performing tests of memory components according to some embodiments of the present disclosure is described. A test platform 100 may include one or more racks 110A, 110B, and 110N. Each of the racks 110A, 110B, and 110N may include a plurality of test boards 120, wherein each test board 120 includes one or more test sockets (i.e., test resources). The test platform 100 may include any number of racks or test sockets.

[0016] As shown, the test board 120 may include one or more test sockets. For example, the test board 120 may include a first test socket 121, a second test socket 122, and a third test socket 123. Although three test sockets are shown, the test board 120 may include any number of test sockets. Each test socket may include a memory component that has been embedded in a respective test socket. In addition, each test socket may include a temperature control component for applying a temperature condition to the embedded memory component. In some embodiments, the temperature control component may be a dual Peltier device (e.g., two Peltier devices) that utilizes the Peltier effect to apply a heating or cooling effect at the surface of the dual Peltier device coupled to the embedded memory component. In the same or alternative embodiments, the temperature control component may be placed on top of the memory component in the respective test socket.

[0017] As shown, each test rack 110A, 110B, and 110N may include a plurality of test boards 120. Each of the test boards 120 of a particular test rack may be coupled with a local test component. For example, each test rack 110A, 110B, and 110N may include local test components 111A, 111B, and 111N, respectively. Each of the local test components 111A, 111B, and 111N may receive instructions to execute a test or a portion of a test to be executed at a test socket of the respective test rack. For example, a resource allocator component 130 may receive (e.g., from a user) conditions for a test to be executed, and the resource allocator component 130 may determine a specific test socket across different test boards 120 at one or more of the test racks 110A, 110B, and 110N that may be used by the test. In some embodiments, the resource allocator component 130 may be provided by a server 131. In some embodiments, server 131 is a computing device or system coupled to local test components 111A, 111B, and 111N via a network.

[0018] The temperature control assembly of each test socket 121, 122, and 123 of each test board 120 can be used to apply different temperature conditions to respective embedded memory components. In addition, each test socket 121, 122, and 123 can be used to perform different operations at the embedded memory components.

[0019] Resource allocator component 130 can receive test input from user. Test input can specify the condition of the test to be performed with one or more memory components. For example, the test can specify the specific temperature condition to be applied to the memory component and the sequence of operations to be performed at the memory component under the specific temperature condition. Resource allocator 130 can retrieve a data structure, which identifies the available test sockets across the test platform 100 and the characteristics of the available test sockets. Subsequently, resource allocator component 130 can assign the test sockets at the test platform 100, which include embedded memory components that match or meet the conditions of the test. Resource allocator component 130 can then transmit the instruction to the local test component of the test rack including the test socket to be used for the test. Other details relative to resource allocator component 130 are described below.

[0020] Figure 2 An example method 200 for allocating test resources for performing tests of memory components according to some embodiments of the present disclosure is described. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The resource allocator component 130 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0021] As shown, at operation 210, the processing logic receives a request to perform a test using one or more memory components. For example, a user may provide a request to run a test of a memory component through a test platform. The test may specify an operation to be performed by the memory component. Such operations may include, but are not limited to, read operations, write operations, and erase operations. In some embodiments, the test specifies a sequence of multiple operations. The test may specify an operating condition under which an operation is to be performed at a specific memory component. When the operation is performed at the memory component, the operating condition may be a temperature condition of the memory component. In some embodiments, the test may specify a desired condition corresponding to an expected characteristic of the memory component to be used for the test. The expected characteristic of the memory component may include, but is not limited to, the number of operations that have been performed by the memory component. For example, the expected characteristic may specify a memory component that has had a more or less specific number of program-erase operations or cycles and a specific number of read operations. In some embodiments, the expected characteristic may include a previous temperature condition that has been applied to the memory component. For example, a previous temperature (i.e., a temperature profile of the memory component) under which an operation has been performed at a memory component for a previous test may be specified. In some embodiments, the test may specify a specific type of memory component to be used for the test. For example, a particular version (ie, design or manufacturing revision) of a memory component to be used for testing may be specified. In this way, a user may provide information specifying conditions under which testing of a memory component is to be performed at a test platform.

[0022] At operation 220, processing logic determines available test sockets of the test platform. For example, a test socket at a test board that is not currently being used to perform another test or is not scheduled as a test platform for performing another test can be identified. For example, the test platform may include several test sockets and a subset of the test sockets may be currently used by another test of the memory component, while a second subset of the test sockets is not currently being used by another test of the memory component. Therefore, the second subset of the test sockets may be considered as available test sockets. In some embodiments, the test may specify a time period in which the test is to be completed. The available test sockets in this case may be test sockets that can be used for testing within the time period. Thus, if a specific test socket is currently being used by the test and will then be scheduled as idle or available and the test can perform operations at a specific test socket within the specified time period, then the specific test socket may be considered as an available test socket. At operation 230, processing logic determines the characteristics of one or more memory components associated with the test. For example, as previously mentioned, the test may specify conditions for the test corresponding to the desired characteristics of the memory component to be used for the test. Therefore, the desired characteristics of the memory component to be used for the test may be provided by a request for the test. In some embodiments, the available test sockets may be test sockets that are not being used by another test and that match the expected characteristics of the memory component specified by the test. Thus, a first subset of the test sockets (i.e., test resources) of the test platform may be available test sockets that match the conditions specified by the test and a second subset of the test sockets may be test sockets that are unavailable and / or do not match the conditions specified by the test. Figure 3 Describes additional details relative to matching desired characteristics.

[0023] At operation 240, processing logic performs a test at an available test socket using one or more memory components based on the characteristics of the one or more memory components. For example, a test may be performed at a test socket that is not currently being used by another test and has characteristics that match the desired characteristics specified by the test. The test may be performed at different test sockets included in different test racks across the test platform. The execution of the test may apply different temperature conditions at different test sockets while performing different or the same sequence of operations at the test sockets. For example, a first socket may run a sequence of operations at a first temperature and a second test socket may run the same sequence of operations at a different second temperature. In some embodiments, a first test socket may run a first sequence of operations at a temperature and a second test socket may run a different second sequence of operations at the same temperature. In the same or alternative embodiments, the temperature conditions applied to a particular test socket may vary during the execution of the sequence of operations.

[0024] Figure 33 is a flow chart of an example method 300 for allocating test resources based on characteristics of a memory component and a requested test according to some embodiments. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The resource allocator component 130 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0025] As shown, at operation 310, processing logic receives an indication to perform a test using a memory component. For example, a user may specify conditions for the test to be performed using the memory component. The conditions may indicate desired characteristics of the memory component to be used for the test and temperature conditions to be applied to the utilized memory component. The test may further specify a sequence of operations to be performed at the memory component during the test. At operation 320, processing logic determines a test socket of the test platform that is available for use by the test. For example, a test socket that is not currently being used by the test or that is available to complete the test within a time threshold specified by the user may be identified throughout the test platform.

[0026] At operation 330, processing logic receives characteristics of memory components at available test sockets of the test platform. Characteristics may be execution profiles of each of the memory components currently embedded in the available test sockets. Execution profiles may identify a number of operations that have been performed at the memory component. Thus, the execution profiles may indicate a usage history of memory components for previous tests that have been performed at a test platform having a test socket that includes the memory component. In some embodiments, characteristics may be temperature profiles of each of the memory components currently embedded in the available test sockets. For example, the temperature profiles may indicate previous temperatures that have been applied to the memory component during previous tests and when the previous temperatures were applied to the memory component during previous tests. Thus, characteristics of the memory component may be based on previous tests that have utilized the test sockets or test resources that utilize the memory component.

[0027] In addition, at operation 340, the processing logic receives design information of the memory components at the available test sockets of the test platform. The design information may specify the design or manufacturing version of each memory component. The design or manufacturing version may indicate the specific design of the memory component or the time when the memory component is manufactured or made. Each different design of the memory component may cause a different structure of the memory component. In some embodiments, the design information may specify the settings (i.e., fine-tuning) that have been defined for the memory component. The settings may be values ​​that can be updated or changed and used to control the functionality of the memory component. Therefore, due to process changes or other such physical changes of the memory component and / or the settings that have been defined for the memory component, the design information may specify the design or manufacturing version of the memory component. At operation 350, the processing logic receives location information of the available test sockets of the test platform. The location information may specify a specific geographical location or site of a test rack containing each available test socket located there. The location information may further identify a specific test rack containing the available test sockets. Therefore, the location information can be used to identify a group of test sockets at a single geographical location or site or a group of test sockets available at a single test rack.

[0028] The received characteristic information, design information, and location information may be stored at a data structure at a server including a resource allocator component. The data structure may be updated as tests are executed at the test platform. For example, the data structure may be updated to reflect new characteristics of the memory component (e.g., a new execution profile or temperature profile) that change as new tests are executed. When the memory component is embedded in a test socket, the design information may be provided, and the location information may be provided by an administrator to be stored at the data structure.

[0029] As shown, at operation 360, processing logic may perform testing at available test sockets based on the characteristics and design information of the memory components at the available test sockets and the location information of the available test sockets. For example, test sockets having memory components with characteristics matching the desired characteristics of the test may be reserved or used for testing. Similarly, test sockets having memory components with design versions matching the desired design versions may be reserved or used for testing. In addition, groups of test sockets may be used for testing based on the locations of the test sockets. In combination Figure 4 Additional details regarding the location of utilizing the test sockets are described. Available test sockets that meet the conditions for the test (eg, match the desired characteristics or design information) and meet the location criteria may be used to perform the test.

[0030] Figure 4The allocation of test resources according to some embodiments of the present disclosure is described. The allocation of test resources may be performed by processing logic, which may include hardware (e.g., processing devices, circuits, dedicated logic, programmable logic, microcode, hardware of devices, integrated circuits, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the allocation of test resources is performed by Figure 1 The resource allocator component 130 executes.

[0031] In some embodiments, an available test socket that satisfies the conditions of the test may be selected based on location information of the available test sockets. The available test sockets may be selected based on a policy that specifies selecting an available test socket at a single geographic location or site. For example, as shown, the first location 410 may include a first test rack 411 and a second test rack 412. The second location 420 may include a third test rack 421. Each of the locations 410 and 420 may be a separate location. For example, the test racks of the first location 410 may be part of a first network coupled to a server including a resource allocator component and the remaining racks of the second location 420 may be part of a different second network coupled to the same server including a resource allocator component.

[0032] like Figure 4 , a test socket with an 'X' represents a test socket that is not available for the requested test. For example, such a test socket may be currently used by another test. As previously described, a policy may specify the selection of available test sockets at a single geographic location or site. If a test will use seven memory components at the available test sockets, then the seven test sockets at the first location 410 may be selected or reserved for testing in lieu of using or reserving any available test sockets at the second location 420. The utilization of the test sockets at a single site may cause the test to be performed in less time because the test data may be collected locally at the site and provided back to the resource allocator component. In some embodiments, a policy may specify the utilization of more test racks at a single site. For example, the test sockets used in the test may be located in multiple test racks at a single site or location. For example, if a test specifies that six test sockets will be utilized, then three of the utilized test sockets may be located at the first test rack 411 and the other three of the utilized test sockets may be located at the second test rack 412.

[0033] Figure 51 is a flow chart of an example method 500 for allocating available test resources for testing of memory components according to some embodiments. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The resource allocator component 130 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0034] As shown, at operation 510, processing logic receives a request to perform a test of a memory component at a test platform. At operation 520, processing logic determines test resources of the test platform associated with the memory component. For example, each test resource (i.e., a test socket) may include a separate memory component. The data structure may identify each test resource at the test platform. At operation 530, processing logic determines a subset of test resources that are not used by one or more other tests at the platform. For example, the test platform may be performing multiple tests of the memory component, each of which utilizes one or more test resources associated with the memory component. Test resources that are not currently being used by any other test may be identified. Subsequently, at operation 540, processing logic assigns test resources of the test platform for use by the test based on the determined subset of test resources. For example, one or more test resources that are not currently being used by another test may be assigned to the test. In some embodiments, one or more test resources that are not currently being used (e.g., available test resources or test sockets) may be selected to be used by the test as previously described.

[0035] In some embodiments, a request to perform a test may specify an amount of time that may elapse to complete the test. For example, a user may specify that the results of a test should be returned or completed within two days. Test resources of the test platform may then be assigned to the test based on test resources that are capable of completing the test within the elapsed time. For example, a request to perform a test within two days may be received while a specific test resource is currently being used by another test. If a specific test resource was completed two days ago by another test and if the requested test can be completed using the specific test resource in the remaining amount of time (e.g., from two days), then the specific test resource may be reserved for the requested test after the other test has been completed.

[0036] Figure 6An example machine of a computer system 600 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a computer system that includes, is coupled to, or utilizes a test platform (e.g., to execute a program corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0037] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0038] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0039] Processing device 602 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 to communicate via a network 620.

[0040] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to a memory subsystem.

[0041] In one embodiment, instructions 626 include instructions for implementing instructions corresponding to a resource allocator component (e.g., Figure 1 130) of the resource allocator component 130 of the present invention. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0042] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. At times, it has proven convenient, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0043] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0044] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0045] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0046] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes a mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0047] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method comprising: receiving a request to execute a test using one or more test memory components specified by the test; determining available test sockets of the test platform, wherein each available test socket is associated with a respective embedded memory component of the plurality of embedded memory components; determining desired characteristics of the one or more test memory components; assigning, by a processing device, one or more of the available test sockets to the test based on characteristics of the plurality of embedded memory components matching the expected characteristics of the one or more test memory components; and The test is performed utilizing the assigned one or more of the available test sockets. 2 . The method of claim 1 , wherein each available test socket includes the corresponding embedded memory component and a temperature control element. 3 . The method of claim 2 , wherein the test corresponds to an operation performed at the corresponding embedded memory component under a specific temperature condition applied to the corresponding embedded memory component by the temperature control element.

4. The method of claim 1 , wherein determining the available test sockets comprises: A subset of test sockets of the test platform that are not being used or reserved by a previous test at the test platform is determined, wherein another subset of test sockets that are being used or reserved by the previous test at the test platform is not available.

5. The method of claim 1 , wherein the expected characteristics of the one or more test memory components include indications of previous operations that have been performed using each of the plurality of embedded memory components and indications of previous temperature conditions that have been applied to each of the plurality of embedded memory components.

6. The method according to claim 1, further comprising: Locations of the available test sockets are determined, wherein the assignment of the one or more of the available test sockets is further based on the locations of the available test sockets.

7. A system comprising: Memory components; and A processing device operatively coupled to the memory component to perform the following operations: receiving a request to perform one or more tests testing memory components at a test platform; determining a test socket of the test platform associated with a corresponding embedded memory component; determining a subset of the test sockets that are not being used by one or more other tests at the test platform; and One or more of the test sockets are assigned for use by the test based on the determined subset of the test sockets based on characteristics of the respective embedded memory components matching expected characteristics specified by the test.

8. The system of claim 7, wherein each of the test sockets includes the respective embedded memory component and a temperature control element.

9. The system of claim 8, wherein the processing device is further configured to: The desired characteristic specified by the test is determined.

10. The system of claim 7, wherein the desired characteristics include indications of previous operations that have been performed with each of the respective embedded memory components and indications of previous temperature conditions that have been applied to each of the respective embedded memory components.

11. The system of claim 7, wherein the processing device is further configured to: Positions of test sockets in the subset of the test sockets are determined, wherein the assignment of the one or more of the test sockets of the test platform is further based on the positions of the subset of the test sockets.

12. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a request to execute a test using one or more test memory components specified by the test; determining available test sockets of the test platform, wherein each available test socket is associated with a respective embedded memory component of the plurality of embedded memory components; determining desired characteristics of the one or more test memory components; assigning one or more of the available test sockets to the test based on characteristics of the plurality of embedded memory components matching the expected characteristics of the one or more test memory components; and The test is performed utilizing the assigned one or more of the available test sockets.

13. The non-transitory computer-readable medium of claim 12, wherein each available test socket comprises the respective embedded memory component and a temperature control element.

14. The non-transitory computer-readable medium of claim 13, wherein the test corresponds to an operation performed at the respective embedded memory component under a particular temperature condition applied to the respective embedded memory component by the temperature control element.

15. The non-transitory computer readable medium of claim 12, wherein to determine the available test sockets, the operations further comprise: A subset of test sockets of the test platform that are not being used or reserved by a previous test at the test platform is determined, wherein another subset of test sockets that are being used or reserved by the previous test at the test platform is not available.

16. The non-transitory computer-readable medium of claim 12, wherein the expected characteristics of the one or more test memory components include indications of previous operations that have been performed with each of the plurality of embedded memory components and indications of previous temperature conditions that have been applied to each of the plurality of embedded memory components.

17. The non-transitory computer-readable medium of claim 12, the operations further comprising: Locations of the available test sockets are determined, wherein the assignment of the one or more of the available test sockets is further based on the locations of the available test sockets.

Images