Robot Control Using Deep Learning

Abstract

The present invention discloses robot control using deep learning, and specifically discloses devices, systems and techniques for using neural networks to perform complex multi-step tasks to facilitate robot execution when the robot has not been trained. In at least one embodiment, a hierarchical model is trained to infer a logical state from a world state and determine executable actions of the robot based on the logical state.

Description

Technical Field

[0001] At least one embodiment relates to a processing resource for facilitating a robot using a neural network to perform complex, multi-step tasks without previously trained robots. For example, at least one embodiment relates to a processor or computer system for training a hierarchical model to infer a logical state from a world state and determining executable actions for the robot based on the logical state. Background Art

[0002] Many techniques have been developed to allow robots to solve challenging problems purely from sensor data. These approaches are highly reactive, acting solely on sensor data. Any new environmental context presents challenges, and these approaches are often slow or unable to account for any new environmental factors when planning and executing actions. Development approaches based on decision trees or finite state machines have very high complexity and size requirements when extended to handle a variety of additional environmental situations. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram illustrating a system for implementing robotic execution according to at least one embodiment;

[0004] Figure 2 is a block diagram illustrating a hierarchical model for generating executable plans for robotic execution according to at least one embodiment;

[0005] Figure 3 shows an ordered list of operators and components of individual operators according to at least one embodiment;

[0006] Figure 4A is a block diagram illustrating calculation of an ideal logic state according to at least one embodiment;

[0007] Figure 4B is a block diagram illustrating a high-level strategy for implementing approximate logic state calculations, according to at least one embodiment;

[0008] Figure 5 is a block diagram illustrating a high-level strategy implemented using a neural network, according to at least one embodiment;

[0009] Figure 6A is a block diagram illustrating ideal action calculation according to at least one embodiment;

[0010] Figure 6B is a block diagram illustrating a low-level strategy for determining an optimal next action according to at least one embodiment;

[0011] Figure 7is a block diagram illustrating a low-level strategy implemented using a neural network according to at least one embodiment;

[0012] Figure 8 is a block diagram illustrating a task planner that implements an execution algorithm according to at least one embodiment;

[0013] Figure 9 is a process for implementing zero-snapshot task execution using high-level policies and low-level policies to determine actions according to at least one embodiment;

[0014] Figure 10A Inference and / or training logic according to at least one embodiment is shown;

[0015] Figure 10B Inference and / or training logic according to at least one embodiment is shown;

[0016] Figure 11 illustrates the training and deployment of a neural network according to at least one embodiment;

[0017] Figure 12 An example data center system is shown in accordance with at least one embodiment;

[0018] Figure 13A An example of an autonomous vehicle according to at least one embodiment is shown;

[0019] Figure 13B According to at least one embodiment, Figure 13A Examples of camera positions and fields of view for autonomous vehicles;

[0020] Figure 13C According to at least one embodiment Figure 13A A block diagram of an example system architecture for an autonomous vehicle;

[0021] Figure 13D is a diagram illustrating a method for one or more cloud-based servers and Figure 13A A diagram of a system for communicating between autonomous vehicles;

[0022] Figure 14 is a block diagram illustrating a computer system according to at least one embodiment;

[0023] Figure 15 is a block diagram illustrating a computer system according to at least one embodiment;

[0024] Figure 16 A computer system according to at least one embodiment is shown;

[0025] Figure 17 A computer system according to at least one embodiment is shown;

[0026] Figure 18A A computer system according to at least one embodiment is shown;

[0027] Figure 18B A computer system according to at least one embodiment is shown;

[0028] Figure 18C A computer system according to at least one embodiment is shown;

[0029] Figure 18D A computer system according to at least one embodiment is shown;

[0030] Figure 18E and Figure 18F illustrates a shared programming model in accordance with at least one embodiment;

[0031] Figure 19 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment.

[0032] Figure 20A-Figure 20B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment.

[0033] Figure 21A and Figure 21B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0034] Figure 22 A computer system according to at least one embodiment is shown;

[0035] Figure 23A A parallel processor according to at least one embodiment is shown;

[0036] Figure 23B shows a partition unit according to at least one embodiment;

[0037] Figure 23C illustrates a processing cluster according to at least one embodiment;

[0038] Figure 23D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0039] Figure 24 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0040] Figure 25 A graphics processor according to at least one embodiment is shown;

[0041] Figure 26 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0042] Figure 27 A deep learning application processor according to at least one embodiment is shown;

[0043] Figure 28 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0044] Figure 29 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0045] Figure 30 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0046] Figure 31 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0047] Figure 32 is a block diagram illustrating a graphics processing engine of a graphics processor according to at least one embodiment;

[0048] Figure 33 is a block diagram illustrating at least a portion of a graphics processor core according to at least one embodiment;

[0049] Figure 34A and Figure 34B Thread execution logic is shown that includes an array of processing elements of a graphics processor core, in accordance with at least one embodiment.

[0050] Figure 35 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0051] Figure 36 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0052] Figure 37 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0053] Figure 38 A streaming multiprocessor in accordance with at least one embodiment is shown.

[0054] Figure 39 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0055] Figure 40 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0056] Figure 41 includes an example illustration of a high-level computational pipeline 4010A for processing imaging data in accordance with at least one embodiment;

[0057] Figure 42A including an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0058] Figure 42B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0059] Figure 43A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0060] Figure 43B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model, according to at least one embodiment. DETAILED DESCRIPTION

[0061] Figure 1 is a block diagram illustrating a system for implementing robotic execution 110, according to at least one embodiment. In at least one embodiment, a task or goal 102 is specified by a user or other entity of a robotic system 114, and a set of actions or execution plan 106 is executed 110 to perform the task or goal 102. In at least one embodiment, the task or goal 102 is a defined series of constraints or conditions that dictate a resulting state of the robotic system 114. In at least one embodiment, the task or goal 102 is a set of numerical constraints or system states that define the configuration of the robotic system 114.

[0062] In at least one embodiment, the execution plan 106 is a set of states executed by the execution control 110 in order for the robotic system 114 to complete the task or goal 102. In at least one embodiment, the execution plan 606 is a set of states or system constraints that, when executed by the execution control 110, cause 116 the robotic system 114 to perform transition actions from state to state. In at least one embodiment, the execution plan 106 is a set of instructions that, when executed by the execution control 110, cause the robotic system 114 to perform actions.

[0063] In at least one embodiment, the execution control 110 is a control unit that causes the components of the robotic system 114 to perform actions. In at least one embodiment, the execution control 110 is a hardware or software component associated with the robotic system 114 that is responsible for controlling the movement or execution of the hardware or software components of the robotic system 114. In at least one embodiment, the execution control 110 receives an execution plan 106, which indicates a set of operations to be performed or a statement where the robotic system should transition between operations. In at least one embodiment, using the execution plan 106, the execution control 110 causes the robotic system 114 to perform actions to complete the task or goal 102.

[0064] In at least one embodiment, robotic system 114 is a set of hardware components that performs an action or series of actions to accomplish task or goal 102. In at least one embodiment, robotic system 114 is a set of hardware and software components that performs an action or series of actions automatically without human assistance. In at least one embodiment, robotic system 114 performs actions under the control of execution control 110, as described above. In at least one embodiment, execution control 110 executes actions 116 based on execution plan 106.

[0065] In at least one embodiment, an execution plan 106 for completing the task or goal 102 is determined by the hierarchical model 104. In at least one embodiment, the hierarchical model is a set of hardware or software instructions that, when executed, determine the execution plan 106 for the robotic system 114. In at least one embodiment, the hierarchical model 104 determines the robot state or the state of the environment based on information collected from the sensors 108. In at least one embodiment, the sensors 108 are cameras or other hardware or software information-gathering components that, when executed, observe information about the robotic system 114 or the environment in which the robotic system 114 resides.

[0066] In at least one embodiment, the hierarchical model 104 collects information from sensors 108 to determine environmental information or information about the robotic system 114 and to determine a set of states or actions to be executed in the execution plan 106. In at least one embodiment, the sensors 108 detect an unexpected event 112. In at least one embodiment, an unexpected event is an event for which the hierarchical model has not been trained to develop the execution plan 106. In at least one embodiment, the hierarchical model 104 develops the execution plan 106 in response to the unexpected event 112, even though the hierarchical model 104 has not been trained to develop the execution plan 106 for the unexpected event 112.

[0067] Figure 2is a block diagram illustrating a hierarchical model 202 for generating an executable plan 212 for implementing robotic execution, according to at least one embodiment. In at least one embodiment, as described above, the executable plan 212 is a set of states that indicates a sequence of states that, when transitioned between robotic systems, implements a task or goal as described above. In at least one embodiment, the executable plan is generated by the hierarchical model 202, as described above. In at least one embodiment, the hierarchical model is a set of software instructions that, when executed, generates the executable plan 212.

[0068] In at least one embodiment, the hierarchical model 202 uses the ordered list of operators 210 and the sensors 214 to develop an executable plan 212. In at least one embodiment, the ordered list of operators is a set of data that defines a list of individual symbolic operators in a planning domain D, where the operators correspond to actions that can be performed by the robotic system. In at least one embodiment, the individual symbolic operators are data that define conditions, effects, and low-level policies. In at least one embodiment, as described above, the sensors 214 are cameras or other information collecting hardware and software components that provide information about the environment or the robotic system to the hierarchical model 202. In at least one embodiment, the hierarchical model 202 uses the high-level policies 208 and low-level policies 206, along with the task planner 204, to develop the executable plan 212, where the high-level policies 208 identify the current logical state of the information from the sensors 214, and the low-level policies 206 identify which operator in the ordered list of operators 210 can be executed based on the logical state. In at least one embodiment, task planner 204 uses information from high-level policy 208 and low-level policy 204 to generate an executable plan 212 that includes an ordered list of operators that can be executed given a current logic state.

[0069] In at least one embodiment, as described above, the operator ordered list 210 is a set of operators, as described below, that indicate available operators that can be executed in the executable plan 212 to complete a task or goal by the robotic system. In at least one embodiment, the operator ordered list 210 is a set of constraints and associated software instructions that, when executed, cause the robotic system to perform an action. In at least one embodiment, the operator ordered list 210 is used by the hierarchical model 202 in conjunction with sensor 214 information to determine the executable plan 212.

[0070] In at least one embodiment, the hierarchical model includes a task planner 204. In at least one embodiment, the task planner is a set of instructions that, when executed, uses information generated by the low-level policies 206 and high-level policies 208 in the hierarchical model 202 to determine an executable plan. In at least one embodiment, the high-level policies 208 are a set of software instructions that, when executed, determine a set of predicates that constitute the current logical state of the environment as determined by the sensors 214. In at least one embodiment, an operator in the ordered list of operators 210 is directly computed from the current logical state determined by the high-level policies 208, as described above. In at least one embodiment, the high-level policies 208 determine the logical state of the robotic system and its environment based on the sensor 214 information and the operators being executed, which is then used by the task planner 204 to determine an executable plan using the actions determined by the low-level policies 206.

[0071] In at least one embodiment, low-level policy 206 is a neural network comprising a set of instructions that, when executed, determine one or more optimal actions to perform based on information provided by one or more sensors 214 and a current operator calculated by high-level policy 208. In at least one embodiment, low-level policy 206 determines the optimal action, where an action is one of one or more actions in an action space A associated with an operator calculated by high-level policy 208. In at least one embodiment, task planner 204 uses the optimal action determined by low-level policy 206 in conjunction with the logic state from high-level policy 208 to determine executable plan 212.

[0072] Figure 3 Components 306, 308, 310, 312 of an ordered list of operators 302 and individual operators 304 are shown in accordance with at least one embodiment. In at least one embodiment, the ordered list of operators 302 is a set of data that defines a list of individual symbolic operators 314 in a planning domain D that can be executed by the robotic system. In at least one embodiment, the individual symbolic operators 304 are data that define conditions 306, 308, effects 310, and low-level strategies 312.

[0073] In at least one embodiment, the precondition 306 of the operator 304 is a logical requirement specified as a data value. In at least one embodiment, the precondition 306 specifies a logical condition that must exist in the robotic system in order for the operator 304 to execute. In at least one embodiment, the run condition 308 is a logical requirement specified as a data value. In at least one embodiment, the run condition 308 specifies a logical condition that must exist during the execution of the action specified by the operator 304 in the robotic system.

[0074] In at least one embodiment, the effect 310 of an operator 304 is a data value that indicates the changes made to the robotic system when the action associated with the operator 304 is implemented. In at least one embodiment, the effect 310 of an operator 304 indicates the changes made to the robotic system when the action associated with the operator 304 is implemented during the execution of the plan. In at least one embodiment, the low-level policy 312 in the operator 304 is a set of instructions that, when executed, determine the actions to be taken by the robotic system given a logical state. In at least one embodiment, the low-level policy 312 in the operator 304 operates like a function that takes a state as input and determines the action to be taken during that state. In at least one embodiment, as described above, the symbolic task planner uses the preconditions 306 and effects 310 in each operator to determine a sequence of states that can be executed reactively even when sensors encounter interference or sensor noise (e.g., unexpected events).

[0075] Figure 4A is a block diagram illustrating an ideal logic state function 404 according to at least one embodiment. In at least one embodiment, the ideal logic state function L() 404 is a set of instructions that, when executed, start from a global underlying world state s t 402 Determine the ideal logical state l t 406. In at least one embodiment, the overall base world state 402 is a set of constant values ​​(e.g., object positions, force values, etc.) that defines a state representing the entire environment in which the robotic system (as described above) exists or is implemented. In at least one embodiment, as described below, the overall base world state 402 is not observable in practice.

[0076] In at least one embodiment, the ideal logic state function L() 404 is based on the basic world state s t 402 to determine the ideal logical state l t 406. In at least one embodiment, the ideal logic state 1 t 406 is a set of predicates p, where each p has a different argument consisting of symbols. In at least one embodiment, the ideal logical state l t 406 is a set of predicates p that specify a logical environment or world state based on the total base world state 402. In at least one embodiment, the ideal logical state function L() 404 is defined as l t =L(s t ), where the ideal logic state l t 406 is from the total basic world state s t402 calculated. In at least one embodiment, the hierarchical model will not be able to access the total base world state s t All of the information in 402 must be implemented as a result in the high-level strategy 418 to approximate the logical state function 412 .

[0077] Figure 4B is a block diagram illustrating a high-level strategy 418 for implementing an approximate logic state function 412 based on current and previously observed sensor data 408, according to at least one embodiment. In at least one embodiment, since the total base world state s is not accessible at runtime, t 402, or the total basic world state s cannot be fully observed t , therefore, it is necessary to use the approximate logic state function 412. In at least one embodiment, the approximate logic state function 412 is a set of instructions that, when executed, implements the approximate function So that:

[0078]

[0079] In at least one embodiment, as described above, neural network 410 is used to generate a 408 to learn an approximate logic state function to approximate the ideal logic state function L() 404. In at least one embodiment, the neural network 410 is a set of instructions and associated data values ​​that, when executed, learns or infers a function such as the approximate logic state function 412. In at least one embodiment, the neural network 410 is any type of neural network for inferring the approximate logic state function 412 and is described below in conjunction with Figure 5 Further description.

[0080] In at least one embodiment, as described above, the observation history 408 is a set of environmental states observed from the sensor, for a reasonable time window of length N, such that In at least one embodiment, as described above, the approximate logic state function 412 is used in conjunction with the ordered list of operators 414 to select the next operator that satisfies its preconditions or run conditions. In at least one embodiment, given the operator list 414, the current operator 420 can be determined from the approximate logic state 416. In at least one embodiment, the approximate logic state is a set of predicates p, where each p has different parameters consisting of symbols. In at least one embodiment, the approximate logic state 416 is determined by a neural network 410 that is trained to approximate the logic state function 412 in order to determine the current operator 420 from the ordered list of operators 414 to achieve the task or goal described above.

[0081] Figure 5 is a block diagram illustrating a high-level strategy implemented using a neural network, according to at least one embodiment. Figure 5 ) is a temporal convolutional neural network (TCN) or a variant of a temporal convolutional neural network. In at least one embodiment, a temporal convolutional network is a collection of instructions and associated data that captures different levels of relationships based on time when executed.

[0082] In at least one embodiment, a neural network (such as Figure 5 As shown) a set of observations x t As input 502, 504, the observations consist of RGB images and joint state readings q from the robot. t ,q t-1 ,q t-2 504, the RGB image is from the environment I rgb,t , I rgb,t-1 , I rgb,t-2 502. In at least one embodiment, each input image 502 is encoded using a convolutional layer (Conv) 508, 510, 512. In at least one embodiment, a convolutional layer 508, 510, 512 is a collection of instructions and associated data that, when executed, calculates a value based on a constant learning value and an input. In at least one embodiment, convolutional layers are further described herein.

[0083] In at least one embodiment, the outputs from the convolutional layers 508, 510, 512 are input to a temporal convolutional network (TCN) 514, as described above, to add temporal information to the spatial relationships identified in the convolutional layers 508, 510, 512. In at least one embodiment, the outputs from the TCN 514 are input to a single fully connected (FC) layer 516. In at least one embodiment, an FC layer is a set of instructions that, when executed, increase the dimensionality of the input. In at least one embodiment, the FC layer 516 increases the dimensionality of the arm joint angles to match the encoded input RGB image 502 features.

[0084] In at least one embodiment, the output from FC layer 516 is input into a trained function that maps from observations to potential world states Gaussian distribution on where μ520 and σ518 are the parameters of the distribution and are the parameters of the potential world state In at least one embodiment, a KL divergence loss is added between the Gaussian distributions to regularize the distributions.

[0085] In at least one embodiment, decoder z 526 is a set of instructions and associated data values ​​that, when executed, is trained to predict the current logic state, which is input to FC layer 528, as described above. In at least one embodiment, as described above, the output predicate p t 506 is generated by the fully connected layer 528. In at least one embodiment, Figure 5 The high-level policy network produces two auxiliary outputs: a depth image I depth,t 536 and semantic segmentation image I seg,t 534. In at least one embodiment, the depth image I depth,t 536 and semantic segmentation image I seg,t 534 is an image generated by the decoder or DeConv deconvolution layer 532 to facilitate learning by the neural network. In at least one embodiment, the DeConv or deconvolution layer 532 is a set of instructions and associated data values ​​that, when executed, perform the inverse operations of the convolution layers 508, 510, 512.

[0086] In at least one embodiment, training is performed via backpropagation 552 of loss values ​​to each neural network component. In at least one embodiment, backpropagation 552 is the process of updating the neural network weights using loss calculations, as further described herein. depth,t 536 and I seg 534 captures the auxiliary loss, thereby capturing the spatial relationship between entities and identifying objects. In at least one embodiment, the ground truth predicate p provided by the supervision is used t 544, Ground Truth I seg,t 546 and Ground Truth I depth,t 548 to calculate the final loss function c. In at least one embodiment, the final loss function c also integrates the values ​​of μ 520 and σ 518, which are Figure 5 The correct point in the high-level strategy of is obtained by sampling 522. In at least one embodiment, the sampling 522 is an instruction that captures the data value in the neural network when executed. In at least one embodiment, the final loss function c is defined as

[0087]

[0088] In at least one embodiment, BCE 538 is a set of instructions that, when executed, calculates binary cross entropy. In at least one embodiment, CE 540 is a set of instructions that, when executed, calculates cross entropy loss. In at least one embodiment, MSE 542 is a set of instructions that, when executed, calculates mean squared error. In at least one embodiment, λ depth ,λseg ,λ p and λ kl are hyperparameters, where hyperparameters are user-specifiable values.

[0089] Figure 6A is a block diagram illustrating the computation of an ideal action 606 by a ground truth strategy 604 according to at least one embodiment. Figure 3 As described, the logical operator o i represents or specifies an action a∈A, where A is the total action space. In at least one embodiment, each logical operator o i With perfect ground truth strategy 604 is associated. In at least one embodiment, the perfect ground truth strategy 604 is a set of instructions that, when executed, creates a given total base world state s t 602 calculates an ideal action 606, as described above. In at least one embodiment, an ideal action 606 or action is a set of motions or instructions that, when executed, causes the robotic system to move, grasp, or perform some other robotic subtask. In at least one embodiment, at runtime, the total base world state s t 602 is not available, so an approximate strategy 618 must be learned. In at least one embodiment, the total base world state s cannot be observed in practice. t All the information in 602 must therefore be used to learn an approximate policy 618 in the neural network 612 that implements the low-level policy 616.

[0090] Figure 6B is a block diagram illustrating a low-level strategy 616 for determining an optimal next action 622 according to at least one embodiment. In at least one embodiment, as described herein, the low-level strategy 616 is based on the current operator o as described above. i 610 and the approximate strategy learned by the neural network 612 618, Determine the best action 622. In at least one embodiment, a neural network is a collection of instructions and associated data that, when executed, learns or infers a function based on a history of observations. 608 and current operator o i 610 to define the approximation strategy 618. In at least one embodiment, the following is combined Figure 7 Further describe the neural network.

[0091] In at least one embodiment, the observation history described above 608 is a set of states previously observed by the sensor. In at least one embodiment, the neural network 612 uses the observation history 608 and current operator o i 610 to learn or reason about approximate strategies 618, so that:

[0092]

[0093] In at least one embodiment, the low-level strategy includes an approximate strategy 618, the approximate strategy is a deep neural network, the deep neural network will calculate the correct continuous (optimal) action 622, given the current operator o i The ground truth strategy 604 is approximated without the knowledge of 610.

[0094] Figure 7 is a diagram illustrating a low-level strategy implemented using a neural network according to at least one embodiment. ll In at least one embodiment, as Figure 7 As shown, the low-level strategy π is implemented ll The neural network is modeled as a temporal convolutional neural network (TCN) or a variant of a temporal convolutional neural network. In at least one embodiment, a temporal convolutional network is a collection of instructions and associated data that, when executed, captures different levels of relationships based on time.

[0095] In at least one embodiment, Figure 7 As shown, the low-level strategy π is implemented ll The neural network transforms a set of observations x t As input 702, 704, 754, the observations consist of RGB images, joint state readings q from the robot t ,q t-1 ,q t-2 and the current operator o 754, the RGB image is from the environment I rgb,t ,I rgb,t-1 ,I rgb,t-2 702. In at least one embodiment, as described above in conjunction with FIG. Figure 5 As described, the current operator o is partially composed of high-level strategies In at least one embodiment, the low-level policy π ll Output action a=q′ t 706. In at least one embodiment, action a=q′ t 706 is a set of positions in the joint configuration space of the robot after completing operator o 754.

[0096] In at least one embodiment, each input image 702 is encoded using a convolutional layer (Conv) 708, 710, 712. In at least one embodiment, the convolutional layers 708, 710, 712 are a collection of instructions and associated data that, when executed, calculate values ​​based on constant learned values ​​and inputs. In at least one embodiment, the convolutional layers are further described herein. In at least one embodiment, the outputs from the convolutional layers 708, 710, 712 are input to a temporal convolutional network (TCN) 714, as described above, to add temporal information to the spatial relationships identified in the convolutional layers 708, 710, 712. In at least one embodiment, the outputs from the TCN 714 are input to a single fully connected (FC) layer 716. In at least one embodiment, the FC layer is a set of instructions that, when executed, increase the dimensionality of the input. In at least one embodiment, the FC layer 716 increases the dimensionality of the arm joint angles to match the features of the encoded input RGB image 702.

[0097] In at least one embodiment, the output from FC layer 716 is input into a trained function that maps from observations to potential world states Gaussian distribution, so that where μ 720 and σ 718 are the parameters of the distribution and are the potential world states Sampling is performed 722, as described below. In at least one embodiment, a KL divergence loss is added between the Gaussian distributions to regularize the distributions for loss calculation and backpropagation 752, as described below.

[0098] In at least one embodiment, decoder z 726 is a set of instructions and associated data, as described above, which, when executed, is trained to predict the current logic state, which is input to FC layer 728. In at least one embodiment, as described above, the output action a=q′ t 706 is generated by the fully connected layer 728. In at least one embodiment, Figure 7 The low-level policy network produces two auxiliary outputs, which are similar to Figure 5 Advanced Policy Networks for Deep Image I depth,Ta 736 and semantic segmentation image I seg,Ta 734. In at least one embodiment, the depth image I depth,Ta 736 and semantic segmentation image I seg,Ta734 is an image generated by the decoder or DeConv deconvolution layer 732 to facilitate learning by the neural network. In at least one embodiment, the DeConv or deconvolution layer 732 is a set of instructions and associated data that, when executed, performs the inverse operations of the convolution layers 708, 710, 712.

[0099] In at least one embodiment, training is performed via backpropagation 752 of loss values ​​to each neural network component. In at least one embodiment, backpropagation 752 is the process of updating the neural network weights using loss calculations, as further described herein. depth 736 and I seg 734 captures the auxiliary loss to capture the spatial relationships between entities and recognize objects. In at least one embodiment, the ground truth predicate q′ provided by the supervision is used t 744, Ground Truth I seg,Ta 746 and Ground Truth I depth,Ta 748 to calculate the final loss function c. In at least one embodiment, the final loss function c also integrates the values ​​of μ 720 and σ 718, which are Figure 7 The correct point in the low-level strategy of is obtained by sampling 722. In at least one embodiment, the sample 722 is an instruction that captures the data value in the neural network when executed. In at least one embodiment, the final loss function c is defined as

[0100]

[0101] In at least one embodiment, CE 740 is a set of instructions that, when executed, calculates a cross entropy loss. In at least one embodiment, MSE 738, 742 is a set of instructions that, when executed, calculates a mean squared error. In at least one embodiment, λ depth ,λ seg ,λ p and λ kl are hyperparameters, where hyperparameters are user-specifiable values.

[0102] Figure 8 is a block diagram illustrating a task planner 802 that implements an execution algorithm 804, according to at least one embodiment. In at least one embodiment, as described above, the task planner 802 is a set of instructions that, when executed, determine a sequence of operations to be performed by the robotic system. In at least one embodiment, the task planner 802 uses the high-level model and the low-level model described above to determine the operators in the execution plan to be executed. In at least one embodiment, the execution algorithm 804 performs sensor measurements (as described above in conjunction with Figure 2), and uses those sensor measurements to determine the current logic state 1. In at least one embodiment, the execution algorithm 804, when executed, uses the current logic state 1 to determine the operator that should be executed.

[0103] In at least one embodiment, once the mission planner 802 determines the plan As described above, the prerequisites for each operator are back-propagated from the target state. In at least one embodiment, the target state is the final goal or task to be performed, as described above in conjunction with Figure 1 In at least one embodiment, the preconditions for each operator are back-propagated to enforce ordering, as described above in conjunction with Figure 3 As described, the effects associated with each operator are taken into account with respect to the preconditions of each later executed operator.

[0104] In at least one embodiment, the execution algorithm is executed for a given execution domain D and operation plan In at least one embodiment, the loop operation at line 02 of algorithm 804 is executed until the current logic state is 1. t Does not meet the target state L G In at least one embodiment, at line 03 of algorithm 804, the time step t is incremented. In at least one embodiment, at line 04 of algorithm 804, as described above, world observations x are collected from sensors. t In at least one embodiment, at line 05 of the execution algorithm 804, the current logic state is estimated by the high-level strategy as described above. In at least one embodiment, at line 06 of the execution algorithm 804, the current operator is obtained using a robust logic dynamic system. In at least one embodiment, the robust logic dynamic system is a set of instructions that, when executed, as described above in conjunction with Figure 3 As described, given the specified preconditions and effects, operators are constructed from the operator list. In at least one embodiment, at lines 07-13 of the execution algorithm 804, as described above, when compared with the current logic state l t When making comparisons, operators are sorted according to the preconditions and the running conditions. In at least one embodiment, at line 14 of the execution algorithm 804, as described above, the current action q t Determined by the low-level policy. In at least one embodiment, at line 15 of the execution algorithm 804, the current action q t By combining Figure 1 The system described is executed.

[0105] Figure 9The invention is a process of performing zero-shot task execution using high-level and low-level policies to determine an action according to at least one embodiment. Figure 9 The process shown implements Figure 8 In at least one embodiment, execution begins 902 by determining whether a goal has been achieved 904. In at least one embodiment, a goal is a final state indicating that a task has been satisfied, as described above in conjunction with Figure 1 As stated.

[0106] In at least one embodiment, if the goal is met 904, then completion 914 is performed. In at least one embodiment, if the goal has not been met 904, then the world state 906 is obtained from the sensors and camera, as described above in conjunction with Figure 1 and Figure 2 In at least one embodiment, the current logic state is determined 908 by the high-level policy, as described above. In at least one embodiment, the current logic state determined 908 by the high-level policy is used to determine the current action 910 by the low-level policy, as described above. In at least one embodiment, once the current action is determined 910 by the low-level policy, the current action is executed 912, as described above in conjunction with Figure 1 and Figure 8 described.

[0107] Reasoning and training logic

[0108] Figure 10A Inference and / or training logic 1015 is shown for performing inference and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Provides details regarding the inference and / or training logic 1015 .

[0109] In at least one embodiment, inference and / or training logic 1015 may include, but is not limited to, code and / or data storage 1001 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, training logic 1015 may include or be coupled to code and / or data storage 1001 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 1001 stores input / output data during training and / or inference using aspects of one or more embodiments and / or weight parameters during forward propagation of weight parameters for each layer of a neural network trained or used in conjunction with one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1001 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0110] In at least one embodiment, any portion of code and / or data storage 1001 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1001 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 1001 is internal or external to a processor, for example, or composed of DRAM, SRAM, flash memory, or some other type of storage, may depend on the available storage space on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0111] In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, code and / or data storage 1005 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in accordance with aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 1005 stores weight parameters and / or input / output data for each layer of the neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 1015 may include or be coupled to code and / or data storage 1005 for storing graph code or other software to control the timing and / or sequence in which weight and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0112] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 1005 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1005 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1005 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 1005 is internal or external to the processor, for example, whether it is composed of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0113] In at least one embodiment, code and / or data store 1001 and code and / or data store 1005 may be separate storage structures. In at least one embodiment, code and / or data store 1001 and code and / or data store 1005 may be the same storage structure. In at least one embodiment, code and / or data store 1001 and code and / or data store 1005 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data store 1001 and code and / or data store 1005 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0114] In at least one embodiment, inference and / or training logic 1015 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 1010 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 1020, which are functions of input / output and / or weight parameter data stored in code and / or data storage 1001 and / or code and / or data storage 1005. In at least one embodiment, activations are performed in response to executing instructions or other code, linear algebra and / or matrix-based mathematics performed by ALU 1010 to generate activations stored in activation storage 1020, wherein weight values ​​stored in code and / or data storage 1005 and / or in code and / or data storage 1001 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 1005 or code and / or data storage 1001 or other on-chip or off-chip storage.

[0115] In at least one embodiment, one or more ALUs 1010 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 1010 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, one or more ALUs 1010 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by an execution unit of a processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 1001, code and / or data storage 1005, and activation storage 1020 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 1020 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0116] In at least one embodiment, activation storage 1020 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 1020 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, whether activation storage 1020 is internal or external to the processor, for example, or comprises DRAM, SRAM, flash memory, or other storage types, can be selected based on the available on-chip or off-chip storage, the latency requirements for performing training and / or inference functions, the batch size of data used in inference and / or training neural networks, or some combination of these factors.

[0117] In at least one embodiment, Figure 10A The inference and / or training logic 1015 shown in FIG can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 10AThe illustrated inference and / or training logic 1015 may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0118] Figure 10B Inference and / or training logic 1015 is shown in accordance with at least one embodiment. In at least one embodiment, inference and / or training logic 1015 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 10B The inference and / or training logic 1015 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 10B The inference and / or training logic 1015 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 1015 includes, but is not limited to, code and / or data storage 1001 and code and / or data storage 1005, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 10B In at least one embodiment shown in FIG, code and / or data storage 1001 and code and / or data storage 1005 are each associated with dedicated computing resources, such as computing hardware 1002 and computing hardware 1006, respectively. In at least one embodiment, computing hardware 1002 and computing hardware 1006 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 1001 and code and / or data storage 1005, respectively, with the results of the functions being stored in activation storage 1020.

[0119] In at least one embodiment, each of the code and / or data stores 1001 and 1005 and the corresponding computing hardware 1002 and 1006 corresponds to a different layer of a neural network, such that activations from one "storage / compute pair 1001 / 1002" of code and / or data store 1001 and computing hardware 1002 are provided as input to the next "storage / compute pair 1005 / 1006" of code and / or data store 1005 and computing hardware 1006, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 1001 / 1002 and 1005 / 1006 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the inference and / or training logic 1015 after or in parallel with the storage / compute pairs 1001 / 1002 and 1005 / 1006.

[0120] Neural network training and deployment

[0121] Figure 11 The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 1106 is trained using a training dataset 1102. In at least one embodiment, the training framework 1104 is the PyTorch framework, while in other embodiments, the training framework 1104 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1104 trains the untrained neural network 1106 and enables it to be trained using the processing resources described herein to generate a trained neural network 1108. In at least one embodiment, the weights can be randomly selected or pre-trained using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0122] In at least one embodiment, untrained neural network 1106 is trained using supervised learning, where training dataset 1102 includes inputs paired with expected outputs for the inputs, or where training dataset 1102 includes inputs with known outputs and neural network 1106 is manually graded for outputs. In at least one embodiment, untrained neural network 1106 is trained in a supervised manner, processing inputs from training dataset 1102 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through untrained neural network 1106. In at least one embodiment, training framework 1104 adjusts the weights that control untrained neural network 1106. In at least one embodiment, training framework 1104 includes tools for monitoring the degree to which untrained neural network 1106 converges to a model (e.g., trained neural network 1108) suitable for generating correct answers (e.g., results 1114) based on input data (e.g., new dataset 1112). In at least one embodiment, the training framework 1104 iteratively trains the untrained neural network 1106 while adjusting the weights to improve the output of the untrained neural network 1106 using a loss function and an adjustment algorithm (e.g., stochastic gradient descent). In at least one embodiment, the training framework 1104 trains the untrained neural network 1106 until the untrained neural network 1106 reaches a desired accuracy. In at least one embodiment, the trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0123] In at least one embodiment, untrained neural network 1106 is trained using unsupervised learning, wherein untrained neural network 1106 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 1102 will include input data without any associated output data or "ground truth" data. In at least one embodiment, untrained neural network 1106 can learn groupings within training dataset 1102 and can determine how individual inputs relate to untrained dataset 1102. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 1108, which can perform operations useful for reducing the dimensionality of new dataset 1112. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for identifying data points in new dataset 1112 that deviate from the normal pattern of new dataset 1112.

[0124] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1102. In at least one embodiment, the training framework 1104 can be used to perform incremental learning, for example, through a transfer learning technique. In at least one embodiment, incremental learning enables the trained neural network 1108 to adapt to new datasets 1112 without forgetting the knowledge that was infused into the trained neural network 1108 during initial training.

[0125] Data Center

[0126] Figure 12 An example data center 1200 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 1200 includes a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0127] In at least one embodiment, Figure 12 As shown, the data center infrastructure layer 1210 may include a resource coordinator 1212, group computing resources 1214, and node computing resources ("node CRs") 1216(1)-1216(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 1216(1)-1216(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1218(1)-1218(N) (e.g., dynamic read-only memories, solid-state drives, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1216(1)-1216(N) may be a server having one or more of the above-mentioned computing resources.

[0128] In at least one embodiment, the grouped computing resources 1214 may include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1214 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0129] In at least one embodiment, resource coordinator 1212 may configure or otherwise control one or more nodes CR 1216 ( 1 )- 1216 (N) and / or grouped computing resources 1214 .

[0130] In at least one embodiment, resource coordinator 1212 may comprise a software design infrastructure ("SDI") management entity for data center 1200. In at least one embodiment, resource coordinator 1012 may comprise hardware, software, or some combination thereof.

[0131] In at least one embodiment, Figure 12 As shown, the framework layer 1220 includes a job scheduler 1222, a configuration manager 1224, a resource manager 1226, and a distributed file system 1228. In at least one embodiment, the framework layer 1220 may include a framework that supports software 1232 of the software layer 1230 and / or one or more applications 1242 of the application layer 1240. In at least one embodiment, the software 1232 or the application 1242 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1220 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 1228 for large-scale data processing (e.g., "big data"). TM(hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1232 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 1200. In at least one embodiment, the configuration manager 1224 may be capable of configuring different layers, such as the software layer 1230 and the framework layer 1220 including Spark and a distributed file system 1228 for supporting large-scale data processing. In at least one embodiment, the resource manager 1226 may be capable of managing the cluster or group computing resources mapped to or allocated to support the distributed file system 1228 and the job scheduler 1222. In at least one embodiment, the cluster or group computing resources may include the group computing resources 1214 on the data center infrastructure layer 1210. In at least one embodiment, the resource manager 1226 may coordinate with the resource coordinator 1212 to manage these mapped or allocated computing resources.

[0132] In at least one embodiment, the software 1232 included in the software layer 1230 may include software used by at least a portion of the node CRs 1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1228 of the framework layer 1220. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0133] In at least one embodiment, the one or more applications 1242 included in the application layer 1240 may include one or more types of applications used by at least a portion of the node CRs 1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1228 of the framework layer 1220. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0134] In at least one embodiment, any of configuration manager 1224, resource manager 1226, and resource coordinator 1212 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1200 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0135] In at least one embodiment, data center 1200 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1200. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks can be used to infer or predict information using the resources described above with respect to data center 1200.

[0136] In at least one embodiment, a data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0137] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Provides details about the reasoning and / or training logic 1015. In at least one embodiment, the reasoning and / or training logic 1015 may be configured to perform the following operations on the system: Figure 12 for use in inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0138] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be found in Figure 12 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0139] autonomous vehicles

[0140] Figure 13AAn example of an autonomous vehicle 1300 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1300 (alternatively referred to herein as "vehicle 1300") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 1300 can be a semi-tractor-trailer for hauling cargo. In at least one embodiment, vehicle 1300 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0141] Automated driving vehicles may be described according to the levels of automation defined by the National Highway Traffic Safety Administration ("NHTSA") and the Society of Automotive Engineers ("SAE") of the U.S. Department of Transportation's "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of this standard). In one or more embodiments, the vehicle 1300 may be capable of functioning according to one or more of the levels 1 to 5 of automated driving. For example, in at least one embodiment, the vehicle 1300 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0142] In at least one embodiment, the vehicle 1300 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1300 may include, but is not limited to, a propulsion system 1350, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1350 may be connected to a drive train of the vehicle 1300, which may include, but is not limited to, a transmission, to enable propulsion of the vehicle 1300. In at least one embodiment, the propulsion system 1350 may be controlled in response to receiving a signal from a throttle / accelerator 1352.

[0143] In at least one embodiment, when propulsion system 1350 is operating (e.g., when vehicle 1300 is traveling), a steering system 1354 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1300 (e.g., along a desired path or route). In at least one embodiment, steering system 1354 may receive signals from steering actuator 1356. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1346 may be used to operate vehicle brakes in response to signals received from brake actuator 1348 and / or brake sensors.

[0144] In at least one embodiment, the controller 1336 may include, but is not limited to, one or more system-on-chips ("SoCs") ( Figure 13A 1300 ). The controller 1336 may include a graphics processing unit (GPU) (not shown) and / or a graphics processing unit ("GPU") to provide signals (e.g., representing commands) to one or more components and / or systems of the vehicle 1300. For example, in at least one embodiment, the controller 1336 may send signals to operate vehicle brakes via a brake actuator 1348, to operate a steering system 1354 via one or more steering actuators 1356, and to operate a propulsion system 1350 via one or more throttles / accelerators 1352. In at least one embodiment, the one or more controllers 1336 may include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to implement autonomous driving and / or assist a driver in driving the vehicle 1300. In at least one embodiment, the one or more controllers 1336 may include a first controller for autonomous driving functionality, a second controller for functional safety functionality, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0145] In at least one embodiment, one or more controllers 1336 provide signals for controlling one or more components and / or systems of the vehicle 1300 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1358 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1360, one or more ultrasonic sensors 1362, one or more LIDAR sensors 1364, one or more inertial measurement unit (IMU) sensors 1366 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1396, one or more stereo cameras 1368, one or more wide angle cameras 1370 (e.g., fisheye cameras), one or more infrared cameras 1372, one or more surround cameras 1374 (e.g., 360 degree cameras), telemetry cameras (e.g., gyroscopes), and the like. Figure 13A Not shown), mid-range camera ( Figure 13A ), one or more speed sensors 1344 (e.g., for measuring the speed of the vehicle 1300), one or more vibration sensors 1342, one or more steering sensors 1340, one or more brake sensors (e.g., as part of a brake sensor system 1346), and / or other sensor types are received.

[0146] In at least one embodiment, one or more controllers 1336 may receive input (e.g., represented by input data) from a dashboard 1332 of the vehicle 1300 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1334, an audible annunciator, a speaker, and / or other components of the vehicle 1300. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 13A ), location data (e.g., the location of the vehicle 1300, such as on a map), directions, the locations of other vehicles (e.g., occupancy barriers), information about objects and the states of objects sensed by the one or more controllers 1336, etc. For example, in at least one embodiment, the HMI display 1334 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0147] In at least one embodiment, the vehicle 1300 further includes a network interface 1324 that can communicate over one or more networks using one or more wireless antennas 1326 and / or one or more modems. For example, in at least one embodiment, the network interface 1324 may be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 1326 can also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks (hereinafter referred to as "LPWAN") (e.g., protocols such as LoRaWAN and SigFox) to enable communication between objects in the environment (e.g., vehicles, mobile devices).

[0148] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Provides details about the reasoning and / or training logic 1015. In at least one embodiment, the reasoning and / or training logic 1015 may be configured to perform the following operations on the system: Figure 13A for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0149] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be found in Figure 13A for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0150] Figure 13B According to at least one embodiment, Figure 13A An example of camera locations and fields of view for an autonomous vehicle 1300 is shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on the vehicle 1300.

[0151] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1300. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0152] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0153] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to cut out stray light and reflections from within the vehicle 1300 (e.g., reflections from the dashboard reflecting in the windshield mirror) that may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars in each corner of the cabin.

[0154] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes a portion of the environment in front of the vehicle 1300 can be used for surround vision, as well as to help identify the forward path and obstacles with the assistance of one or more controllers 1336 and / or control SoCs, thereby providing information that is critical for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (e.g., traffic sign recognition).

[0155] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1370 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the road, or bicycles). Although Figure 13B Only one wide-angle camera 1370 is shown in FIG. 1 , however, in other embodiments, any number (including zero) of wide-angle cameras may be present on vehicle 1300. In at least one embodiment, any number of remote cameras 1398 (e.g., a remote stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, remote cameras 1398 may also be used for object detection and classification, as well as basic object tracking.

[0156] In at least one embodiment, any number of stereo cameras 1368 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1368 may include an integrated control unit including a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle 1300's environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1368 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1300 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1368 may be used in addition to those described herein.

[0157] In at least one embodiment, a camera having a field of view of a portion of the environment including the sides of the vehicle 1300 (e.g., a side-view camera) can be used for surround viewing to provide information for creating and updating occupancy grids and generating side collision warnings. For example, in at least one embodiment, the surround camera 1374 (e.g., Figure 13B Four surround cameras (shown) can be positioned on the vehicle 1300. In at least one embodiment, the one or more surround cameras 1374 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fish-eye lenses, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, four fish-eye lens cameras can be located on the front, rear, and sides of the vehicle 1300. In at least one embodiment, the vehicle 1300 can use three surround cameras 1374 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0158] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1300 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1398 and / or one or more mid-range cameras 1376, one or more stereo cameras 1368, one or more infrared cameras 1372, etc.), as described herein.

[0159] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B , details regarding the reasoning and / or training logic 1015 are provided herein. In at least one embodiment, the reasoning and / or training logic 1015 may be Figure 13B for use in a system for performing inference or prediction operations based at least in part on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein.

[0160] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be found in Figure 13B for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0161] Figure 13C According to at least one embodiment, Figure 13A A block diagram of an example system architecture for an autonomous vehicle 1300 is provided. In at least one embodiment, Figure 13C Each of one or more components, one or more features, and one or more systems of vehicle 1300 is shown as being connected via bus 1302. In at least one embodiment, bus 1302 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network internal to vehicle 1300 that facilitates control of various features and functions of vehicle 1300, such as brake actuation, acceleration, braking, steering, wipers, and the like. In one embodiment, bus 1302 may be configured with dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1302 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1302 may be an ASIL B compliant CAN bus.

[0162] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or in addition to CAN. In at least one embodiment, there may be any number of modular buses 1302, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control. In at least one embodiment, each bus of buses 1302 may communicate with any component of vehicle 1300, and two or more buses 1302 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chips ("SoCs") 1304 (e.g., SoC 1304(A) and SoC 1304(B)), each of one or more controllers 1336, and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors in vehicle 1300) and may be connected to a common bus, such as a CAN bus.

[0163] In at least one embodiment, the vehicle 1300 may include one or more controllers 1336, such as those described herein with respect to Figure 13AIn at least one embodiment, the controller 1336 can be used for a variety of functions. In at least one embodiment, the controller 1336 can be coupled to any of the various other components and systems of the vehicle 1300 and can be used to control the vehicle 1300, the artificial intelligence of the vehicle 1300, the infotainment and / or other functions of the vehicle 1300.

[0164] In at least one embodiment, the vehicle 1300 may include any number of SoCs 1304. In at least one embodiment, each of the SoCs 1304 may include, but is not limited to, a central processing unit ("CPU(s)") 1306, a graphics processing unit ("GPU(s")) 1308, one or more processors 1310, one or more caches 1312, one or more accelerators 1314, one or more data stores 1316, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1304 may be used to control the vehicle 1300 in various platforms and systems. For example, in at least one embodiment, the one or more SoCs 1304 may be combined in a system (e.g., a system of the vehicle 1300) with a high-definition ("HD") map 1322 that may be downloaded from one or more servers (e.g., a system of the vehicle 1300) via a network interface 1324. Figure 13C ) to obtain map refreshes and / or updates.

[0165] In at least one embodiment, one or more CPUs 1306 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1306 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1306 may include eight cores in a mutually coupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1306 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 1306 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 1306 may be active at any given time.

[0166] In at least one embodiment, one or more CPUs 1306 can implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware modules when idle to conserve dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core can be independently powered; each core cluster can be independently clock gated when all cores are clock gated or power gated; and / or each core cluster can be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1306 can further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state for the core, cluster, and CCPLEX input. In at least one embodiment, the processing core can support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0167] In at least one embodiment, one or more GPUs 1308 may include an integrated GPU (or alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1308 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1308 may utilize an enhanced tensor instruction set. In one embodiment, one or more GPUs 1308 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1308 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1308 may utilize a computing application programming interface (API). In at least one embodiment, one or more GPUs 1308 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0168] In at least one embodiment, one or more GPUs 1308 can be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1308 can be fabricated on Fin Field Effect Transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor can include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores can be partitioned into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor can include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0169] In at least one embodiment, one or more GPUs 1308 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as graphics double data rate type five synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory.

[0170] In at least one embodiment, one or more GPUs 1308 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1308 to directly access one or more CPU 1306 page tables. In at least one embodiment, when a memory management unit ("MMU") of a GPU in one or more GPUs 1308 experiences a miss, an address translation request may be sent to one or more CPUs 1306. In response, in at least one embodiment, one or more CPUs 1306 may look up the virtual-to-physical mapping of the address in its page table and transmit the translation back to the one or more GPUs 1308. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both one or more CPUs 1306 and one or more GPUs 1308, thereby simplifying programming of the one or more GPUs 1308 and porting applications to the one or more GPUs 1308.

[0171] In at least one embodiment, one or more GPUs 1308 may include any number of access counters that can track the frequency with which one or more GPUs 1308 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0172] In at least one embodiment, one or more SoCs 1304 may include any number of caches 1312, including those described herein. For example, in at least one embodiment, one or more caches 1312 may include a level 3 ("L3") cache available to one or more CPUs 1306 and one or more GPUs 1308 (e.g., connected to CPUs 1306 and GPUs 1308). In at least one embodiment, one or more caches 1312 may include a write-back cache that can track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0173] In at least one embodiment, one or more SoCs 1304 may include one or more accelerators 1314 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1304 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1308 and offload some tasks of one or more GPUs 1308 (e.g., freeing up more cycles of one or more GPUs 1308 to perform other tasks). In at least one embodiment, one or more accelerators 1314 may be used for target workloads that are sufficiently stable to withstand acceleration testing (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or region-based convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0174] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and often significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for safety and / or security-related events.

[0175] In at least one embodiment, a DLA can perform any function of one or more GPUs 1308, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1308. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1308 and / or one or more accelerators 1314.

[0176] In at least one embodiment, one or more accelerators 1314 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1338, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of the one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0177] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0178] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 1306. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0179] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0180] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, except on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on sequenced images or portions of images. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA, among other things. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0181] In at least one embodiment, one or more accelerators 1314 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1314. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0182] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0183] In at least one embodiment, one or more SoCs 1304 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, the real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the position and range of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0184] In at least one embodiment, one or more accelerators 1314 have broad uses for autonomous driving. In at least one embodiment, the PVA can be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power and low latency is well matched to algorithmic domains that require predictable processing. In other words, the PVA excels at semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, the PVA, such as in the vehicle 1300, may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0185] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm can be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching on the fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0186] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0187] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence score for each object detection. In at least one embodiment, the confidence score can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1366 associated with vehicle 1300 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1364 or one or more RADAR sensors 1360), etc.

[0188] In at least one embodiment, one or more SoCs 1304 may include one or more data stores 1316 (e.g., memory). In at least one embodiment, one or more data stores 1316 may be on-chip memory of one or more SoCs 1304 that may store neural networks to be executed on one or more GPUs 1308 and / or DLAs. In at least one embodiment, one or more data stores 1316 may have a capacity large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, one or more data stores 1316 may include an L2 or L3 cache.

[0189] In at least one embodiment, one or more SoCs 1304 may include any number of processors 1310 (e.g., embedded processors). In at least one embodiment, one or more processors 1310 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1304 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, one or more SoCs 1304 thermal and temperature sensor management, and / or one or more SoCs 1304 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1304 may use the ring oscillator to detect the temperature of one or more CPUs 1306, one or more GPUs 1308, and / or one or more accelerators 1314. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1304 into a lower power consumption state and / or place the vehicle 1300 into a driver's safe parking pattern (e.g., bringing the vehicle 1300 to a safe stop).

[0190] In at least one embodiment, one or more processors 1310 may further include a set of embedded processors that can be used as an audio processing engine, which can be an audio subsystem that can provide hardware with full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0191] In at least one embodiment, one or more processors 1310 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0192] In at least one embodiment, one or more processors 1310 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, one or more processors 1310 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1310 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0193] In at least one embodiment, one or more processors 1310 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce the final video, thereby generating the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1370, one or more surround cameras 1374, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1304, the neural network being configured to identify cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode, but are otherwise disabled.

[0194] In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from previous images to reduce noise in the current image.

[0195] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor can also be used for user interface composition when using an operating system desktop, without requiring one or more GPUs 1308 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1308 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1308 to improve performance and responsiveness.

[0196] In at least one embodiment, one or more of the SoCs 1304 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1304 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0197] In at least one embodiment, one or more of the SoCs 1304 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1304 may be configured to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 1364, one or more RADAR sensors 1360, etc., which may be connected via an Ethernet channel), data from the bus 1302 (e.g., vehicle 1300 speed, steering wheel position, etc.), data from one or more GNSS sensors 1358 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 1304 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload one or more of the CPUs 1306 from routine data management tasks.

[0198] In at least one embodiment, one or more SoCs 1304 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, providing a platform that can provide a flexible and reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1304 can be faster and more reliable than conventional systems, and even more energy and space efficient. For example, in at least one embodiment, one or more accelerators 1314, when combined with one or more CPUs 1306, one or more GPUs 1308, and one or more data storage devices 1316, can provide a fast and efficient platform for Level 3-5 autonomous driving vehicles.

[0199] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous driving vehicles.

[0200] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined together to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1320) may include text and word recognition, thereby allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that can recognize, interpret, and provide semantic understanding of the signs and pass this semantic understanding to a path planning module running on the CPU Complex.

[0201] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: Flashing lights indicate icy conditions" along with connected lights can be interpreted independently or collectively by multiple neural networks. In at least one embodiment, the warning sign itself can be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1308.

[0202] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1300. In at least one embodiment, an always-on sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1304 provide protection against theft and / or carjacking.

[0203] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1396 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1304 use the CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approaching speed of the emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 1358. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1362 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0204] In at least one embodiment, the vehicle 1300 may include one or more CPUs 1318 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1304 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1318 may include an X86 processor, for example, and the one or more CPUs 1318 may be used to perform any of a variety of functions, including, for example, arbitrating potential inconsistent results between ADAS sensors and the one or more SoCs 1304, and / or monitoring the status and health of one or more controllers 1336 and / or an information system on a chip ("information SoC") 1330.

[0205] In at least one embodiment, the vehicle 1300 may include one or more GPUs 1320 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1304 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1320 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input from sensors of the vehicle 1300 (e.g., sensor data).

[0206] In at least one embodiment, vehicle 1300 may further include a network interface 1324, which may include, but is not limited to, one or more wireless antennas 1326 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1324 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., a passenger's client device) via an internet cloud service (e.g., utilizing a server and / or other network devices). In at least one embodiment, a direct link may be established between vehicle 130 and another vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1300 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1300). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1300.

[0207] In at least one embodiment, the network interface 1324 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1336 to communicate over a wireless network. In at least one embodiment, the network interface 1324 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0208] In at least one embodiment, the vehicle 1300 may further include one or more data stores 1328, which may include, but are not limited to, off-chip (e.g., one or more SoCs 1304) storage. In at least one embodiment, the one or more data stores 1328 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0209] In at least one embodiment, the vehicle 1300 may further include one or more GNSS sensors 1358 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1358 may be used, including, for example, but not limited to, GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0210] In at least one embodiment, the vehicle 1300 may further include one or more RADAR sensors 1360. In at least one embodiment, the one or more RADAR sensors 1360 may be used by the vehicle 1300 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, the one or more RADAR sensors 1360 may use a CAN bus and / or bus 1302 (e.g., to transmit data generated by the one or more RADAR sensors 1360) for control and access to object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1360 may be suitable for front, rear, and side RADAR use. In at least one embodiment, the one or more RADAR sensors 1360 are pulse Doppler RADAR sensors.

[0211] In at least one embodiment, one or more RADAR sensors 1360 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, a long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 meters). In at least one embodiment, one or more RADAR sensors 1360 can help distinguish between static and moving objects and can be used by the ADAS system 1338 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1360 included in the long-range RADAR system may include, but are not limited to, a monostatic multi-mode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beam pattern designed to record the surroundings of the vehicle 1300 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas can extend the field of view, allowing for quick detection of vehicles 1300 entering or leaving the lane.

[0212] In at least one embodiment, as an example, a medium-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1360 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1338 for blind spot detection and / or lane change assistance.

[0213] In at least one embodiment, the vehicle 1300 may further include one or more ultrasonic sensors 1362. In at least one embodiment, one or more ultrasonic sensors 1362, which may be positioned at the front, rear, and / or side of the vehicle 1300, may be used for parking assistance and / or for creating and updating occupancy barriers. In at least one embodiment, a variety of ultrasonic sensors 1362 may be used, and different ultrasonic sensors 1362 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1362 may operate at an ASIL B functional safety level.

[0214] In at least one embodiment, the vehicle 1300 can include one or more LIDAR sensors 1364. In at least one embodiment, the one or more LIDAR sensors 1364 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1364 can operate at functional safety level ASIL B. In at least one embodiment, the vehicle 1300 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1364 that can use Ethernet channels (e.g., provide data to a Gigabit Ethernet switch).

[0215] In at least one embodiment, one or more LIDAR sensors 1364 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1364 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1364 may comprise small devices that can be embedded in the front, rear, sides, and / or corners of vehicle 1300. In at least one embodiment, one or more LIDAR sensors 1364 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and a range of 200 meters. In at least one embodiment, the forward-facing one or more LIDAR sensors 1364 may be configured for a horizontal field of view between 45 and 135 degrees.

[0216] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200 meters around vehicle 1300. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1300 to the object. In at least one embodiment, flash LIDAR can allow for the generation of a highly accurate and distortion-free image of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1300. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0217] In at least one embodiment, the vehicle 1300 may also include one or more IMU sensors 1366. In at least one embodiment, the one or more IMU sensors 1366 may be located at the center of the rear axle of the vehicle 1300. In at least one embodiment, the one or more IMU sensors 1366 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1366 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1366 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0218] In at least one embodiment, one or more IMU sensors 1366 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, one or more IMU sensors 1366 can enable vehicle 1300 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 and one or more GNSS sensors 1358 can be combined in a single integrated unit.

[0219] In at least one embodiment, the vehicle 1300 can include one or more microphones 1396 positioned within and / or around the vehicle 1300. In at least one embodiment, the one or more microphones 1396 can be used for emergency vehicle detection and identification, among other things.

[0220] In at least one embodiment, the vehicle 1300 may further include any number of camera types, including one or more stereo cameras 1368, one or more wide angle cameras 1370, one or more infrared cameras 1372, one or more surround cameras 1374, one or more long range cameras 1398, one or more mid range cameras 1376, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1300. In at least one embodiment, the type of camera used depends on the vehicle 1300. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1300. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1300 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may, by way of example but not limitation, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the herein previously referenced Figure 13A and Figure 13B Each camera can be described in more detail.

[0221] In at least one embodiment, vehicle 1300 may further include one or more vibration sensors 1342. In at least one embodiment, one or more vibration sensors 1342 may measure vibration of a component (e.g., an axle) of vehicle 1300. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1342 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0222] In at least one embodiment, the vehicle 1300 may include an ADAS system 1338. In at least one embodiment, the ADAS system 1338 may include, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1338 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions, and combinations thereof.

[0223] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1360, one or more LIDAR sensors 1364, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle in close proximity to the vehicle 1300 and automatically adjusts the speed of the vehicle 1300 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1300 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0224] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet) via a network interface 1324 and / or one or more wireless antennas 1326. In at least one embodiment, a direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while an indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1300 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of I2V and V2V information sources. In at least one embodiment, given information about vehicles ahead of vehicle 1300, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0225] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1360, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0226] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or braking on impending collisions.

[0227] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1300 crosses a lane marking. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1300 begins to leave the lane, the LKA system provides steering input or braking to correct the vehicle 1300.

[0228] In at least one embodiment, the BSW system detects and warns the driver of vehicles in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0229] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside the rear camera range while the vehicle 1300 is in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure application of vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0230] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1300 itself decides whether to follow the results of the primary or secondary computer (e.g., the first or second controller of controller 1336). For example, in at least one embodiment, the ADAS system 1338 can be a backup and / or auxiliary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1338 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary and secondary computers conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0231] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU to indicate the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0232] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the secondary computer provides a false alarm based, at least in part, on output from the primary computer and output from the secondary computer. In at least one embodiment, the neural network in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system identifies a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1304.

[0233] In at least one embodiment, the ADAS system 1338 may include an auxiliary computer that uses traditional computer vision rules to perform ADAS functions. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of a neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the main computer, and the different software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer will not cause a significant error.

[0234] In at least one embodiment, the output of the ADAS system 1338 can be input into the primary computer's perception module and / or the primary computer's dynamic driving task module. For example, in at least one embodiment, if the ADAS system 1338 indicates a forward collision warning due to an object directly ahead, the perception module can use this information when identifying the object. In at least one embodiment, as described herein, the secondary computer can have its own neural network that has been trained to reduce the risk of false positives.

[0235] In at least one embodiment, the vehicle 1300 may further include an infotainment SoC 1330 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1330 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1330 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1300. For example, the infotainment SoC 1330 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, a car, an in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a heads-up display ("HUD"), an HMI display 1334, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1330 may be further configured to provide information (e.g., visual and / or auditory) to a user of the vehicle 1300, such as information from an ADAS system 1338, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0236] In at least one embodiment, the infotainment SoC 1330 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1330 can communicate with other devices, systems, and / or components of the vehicle 1300 via the bus 1302. In at least one embodiment, the infotainment SoC 1330 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event of a failure of the main controller 1336 (e.g., the vehicle's 1300 main computer and / or backup computer). In at least one embodiment, the infotainment SoC 1330 can cause the vehicle 1300 to enter a driver-to-safety stop mode, as described herein.

[0237] In at least one embodiment, the vehicle 1300 may further include an instrument panel 1332 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1332 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument panel 1332 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1330 and the instrument panel 1332. In at least one embodiment, the instrument panel 1332 may be included as part of the infotainment SoC 1330, or vice versa.

[0238] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Provides details about the reasoning and / or training logic 1015. In at least one embodiment, the reasoning and / or training logic 1015 may be configured to perform the following operations on the system: Figure 13C for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0239] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be found in Figure 13C for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0240] Figure 13D In accordance with at least one embodiment, a cloud-based server and Figure 13A 13. A diagram of a system 1376 for communicating between autonomous vehicles 1300. In at least one embodiment, system 1376 may include, but is not limited to, one or more servers 1378, one or more networks 1390, and any number and type of vehicles, including vehicle 1300. In at least one embodiment, one or more servers 1378 may include, but are not limited to, multiple GPUs 1384(A)-1384(H) (collectively referred to herein as GPUs 1384), PCIe switches 1382(A)-1382(D) (collectively referred to herein as PCIe switches 1382), and / or CPUs 1380(A)-1380(B) (collectively referred to herein as CPUs 1380). The GPUs 1384, CPUs 1380, and PCIe switches 1382 may be interconnected with high-speed connections, such as, but not limited to, NVLink interfaces 1388 developed by NVIDIA and / or PCIe connections 1386. In at least one embodiment, the GPUs 1384 are connected via NVLink and / or NVSwitch SoC, and the GPUs 1384 and PCIe switches 1382 are connected via a PCIe interconnect. Although eight GPUs 1384, two CPUs 1380, and four PCIe switches 1382 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1378 may include, but is not limited to, any number of GPUs 1384, CPUs 1380, and / or PCIe switches 1382 in any combination. For example, in at least one embodiment, one or more servers 1378 may each include eight, sixteen, thirty-two, and / or more GPUs 1384.

[0241] In at least one embodiment, one or more servers 1378 may receive image data representing an image from a vehicle via one or more networks 1390 that depicts unexpected or altered road conditions, such as recently begun road construction. In at least one embodiment, one or more servers 1378 may transmit an updated neural network 1392 and / or map information 1394, including, but not limited to, information regarding traffic and road conditions, to the vehicle via one or more networks 1390. In at least one embodiment, updates to the map information 1394 may include, but not limited to, updates to the HD map 1322, such as information regarding construction sites, potholes, service roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1392 and / or map information 1394 may be generated by new training and / or experience derived from data received from any number of vehicles in the environment, and / or may be based at least on training performed at a data center (e.g., using one or more servers 1378 and / or other servers).

[0242] In at least one embodiment, one or more servers 1378 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1390, and / or the machine learning model can be used by one or more servers 1378 to remotely monitor the vehicle.

[0243] In at least one embodiment, one or more servers 1378 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1378 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1384, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1378 can include the deep learning infrastructure of a data center using CPU power.

[0244] In at least one embodiment, the deep learning infrastructure of one or more servers 1378 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or related hardware in the vehicle 1300. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1300, such as an image sequence and / or objects located within that image sequence by the vehicle 1300 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1300, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1300 is malfunctioning, the one or more servers 1378 may send a signal to the vehicle 1300 to instruct the vehicle's 1300 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0245] In at least one embodiment, one or more servers 1378 may include one or more GPUs 1384 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, for example, in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, hardware structure 1015 is used to execute one or more embodiments. Figure 10A and / or Figure 10B Provides details about the hardware structure 1015.

[0246] Computer system

[0247] Figure 14 1400 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, computer system 1400 may include, but is not limited to, components such as processor 1402, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 1400 may include a processor such as the Intel® processor 1402 available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1400 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0248] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0249] In at least one embodiment, the computer system 1400 may include, but is not limited to, a processor 1402, which may include, but is not limited to, one or more execution units 1408 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1400 is a single-processor desktop or server system, but in another embodiment, the computer system 1400 may be a multi-processor system. In at least one embodiment, the processor 1402 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1402 may be coupled to a processor bus 1410, which may transmit data signals between the processor 1402 and other components in the computer system 1400.

[0250] In at least one embodiment, processor 1402 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1402. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1406 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0251] In at least one embodiment, an execution unit 1408, including but not limited to logic for performing integer and floating point operations, is also located in the processor 1402. In at least one embodiment, the processor 1402 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1408 may include logic for processing a packed instruction set 1409. In at least one embodiment, by including the packed instruction set 1409 in the instruction set of a general-purpose processor, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1402. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0252] In at least one embodiment, execution unit 1408 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 1400 may include, but is not limited to, memory 1420. In at least one embodiment, memory 1420 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or another storage device. In at least one embodiment, memory 1420 may store instructions 1419 and / or data 1421 represented by data signals that may be executed by processor 1402.

[0253] In at least one embodiment, a system logic chip can be coupled to the processor bus 1410 and the memory 1420. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1416, and the processor 1402 can communicate with the MCH 1416 via the processor bus 1410. In at least one embodiment, the MCH 1416 can provide a high-bandwidth memory path 1418 to the memory 1420 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1416 can initiate data signals between the processor 1402, the memory 1420, and other components in the computer system 1400, and bridge data signals between the processor bus 1410, the memory 1420, and the system I / O interface 1422. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1416 may be coupled to the memory 1420 via a high-bandwidth memory path 1418 , and the graphics / video card 1412 may be coupled to the MCH 1416 via an Accelerated Graphics Port (“AGP”) interconnect 1414 .

[0254] In at least one embodiment, computer system 1400 may use system I / O interface 1422 as a proprietary hub interface bus to couple MCH 1416 to I / O controller hub ("ICH") 1430. In at least one embodiment, ICH 1430 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1420, chipset, and processor 1402. Examples may include, but are not limited to, an audio controller 1429, a firmware hub ("Flash BIOS") 1428, a wireless transceiver 1426, a data store 1424, a traditional I / O controller 1423 including a user input and keyboard interface, a serial expansion port 1427 (e.g., a Universal Serial Bus (USB) port), and a network controller 1434. In at least one embodiment, data store 1424 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0255] In at least one embodiment, Figure 14 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 14 A SoC may be shown. In at least one embodiment, Figure 14The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1400 are interconnected using a Compute Express Link (CXL) interconnect.

[0256] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations related to one or more embodiments. Figure 10A and / or Figure 10B Provides details about the reasoning and / or training logic 1015. In at least one embodiment, the reasoning and / or training logic 1015 may be Figure 14 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0257] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be found in Figure 14 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0258] Figure 15 1 is a block diagram illustrating an electronic device 1500 for utilizing a processor 1510 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1500 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0259] In at least one embodiment, electronic device 1500 may include, but is not limited to, a processor 1510 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1510 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, Universal Serial Bus ("USB") (Revision 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 15 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 15 An exemplary SoC may be shown. In at least one embodiment, Figure 15The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 15 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0260] In at least one embodiment, Figure 15 It may include a display 1524, a touch screen 1525, a touchpad 1530, a near field communication unit (“NFC”) 1545, a sensor hub 1540, a thermal sensor 1546, a fast chipset (“EC”) 1535, a trusted platform module (“TPM”) 1538, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1522, a DSP 1560, a drive 1520 (e.g., a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1550, a Bluetooth unit 1552, a wireless wide area network unit (“WWAN”) 1556, a global positioning system (GPS) unit 1555, a camera (“USB 3.0 camera”) 1554 (e.g., a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1515 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0261] In at least one embodiment, other components can be communicatively coupled to the processor 1510 through the components described herein. In at least one embodiment, an accelerometer 1541, an ambient light sensor ("ALS") 1542, a compass 1543, and a gyroscope 1544 can be communicatively coupled to the sensor hub 1540.

[0262] In at least one embodiment, thermal sensor 1539, fan 1537, keyboard 1536, and touchpad 1530 can be communicatively coupled to EC 1535. In at least one embodiment, speaker 1563, earphone 1564, and microphone ("mic") 1565 can be communicatively coupled to audio unit ("audio codec and class D amplifier") 1562, which in turn can be communicatively coupled to DSP 1560. In at least one embodiment, audio unit 1562 can include, for example, but not limited to, an audio encoder / decoder ("codec") and a class D amplifier. In at least one embodiment, SIM card ("SIM") 1557 can be communicatively coupled to WWAN unit 1556. In at least one embodiment, components such as WLAN unit 1550 and Bluetooth unit 1552, as well as WWAN unit 1556, can be implemented as a next generation form factor (NGFF).

[0263] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Provides details about the reasoning and / or training logic 1015. In at least one embodiment, the reasoning and / or training logic 1015 may be configured to perform the following operations on the system: Figure 15 for use in performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0264] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be found in Figure 15 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0265] Figure 16 Illustrated is a computer system 1600 in accordance with at least one embodiment. In at least one embodiment, the computer system 1600 is configured to implement the various processes and methods described throughout this disclosure.

[0266] In at least one embodiment, computer system 1600 includes, but is not limited to, at least one central processing unit ("CPU") 1602 connected to a communication bus 1610 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1600 includes, but is not limited to, main memory 1604 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1604 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1622 provides an interface to other computing devices and networks for receiving data using computer system 1600 and transmitting data to other systems.

[0267] In at least one embodiment, computer system 1600 includes, but is not limited to, input device 1608, parallel processing system 1612, and display device 1606, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1608 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0268] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Provides details about the reasoning and / or training logic 1015. In at least one embodiment, the reasoning and / or training logic 1015 may be configured to perform the following operations on the system: Figure 16 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0269] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be found in Figure 16 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0270] Figure 17 A computer system 1700 is shown according to at least one embodiment. In at least one embodiment, computer system 1700 includes, but is not limited to, a computer 1710 and a USB drive 1720. In at least one embodiment, computer 1710 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1710 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0271] In at least one embodiment, the USB disk 1720 includes, but is not limited to, a processing unit 1730, a USB interface 1740, and USB interface logic 1750. In at least one embodiment, the processing unit 1730 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1730 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1730 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1730 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1730 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0272] In at least one embodiment, USB interface 1740 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1740 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1740 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1750 can include any number and type of logic that enables processing unit 1730 to connect to a device (e.g., computer 1710) via USB connector 1740.

[0273] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Provides details about the reasoning and / or training logic 1015. In at least one embodiment, the reasoning and / or training logic 1015 may be configured to perform the following operations on the system: Figure 17 In some embodiments, the present invention relates to a method for performing inference or prediction operations based at least in part on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein.

[0274] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be found in Figure 17 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0275] Figure 18AAn exemplary architecture is shown in which a plurality of GPUs 1810(1)-1810(N) are communicatively coupled to a plurality of multi-core processors 1805(1)-1805(M) via high-speed links 1840(1)-1840(N) (e.g., a bus / point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1840(1)-1840(N) support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure.

[0276] Furthermore, in one embodiment, two or more GPUs 1810 are interconnected via high-speed links 1829(1)-1829(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 1840(1)-1840(N). Similarly, two or more multi-core processors 1805 may be connected via high-speed link 1828, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 18A All communications between the various system components shown in .

[0277] In one embodiment, each multi-core processor 1805 is communicatively coupled to processor memory 1801(1)-1801(M) via memory interconnects 1826(1)-1826(M), respectively, and each GPU 1810(1)-1810(N) is communicatively coupled to GPU memory 1820(1)-1820(N) via GPU memory interconnects 1850(1)-1850(N), respectively. In at least one embodiment, memory interconnects 1826 and 1850 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1801(1)-1801(M) and GPU memory 1820 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1801 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0278] As described herein, although the various multi-core processors 1805 and GPUs 1810 may be physically coupled to specific memories 1801, 1820, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1801(1)-1801(M) may each contain 64GB of system memory address space, and GPU memories 1820(1)-1820(N) may each contain 32GB of system memory address space, resulting in a total addressable memory size of 256GB when M=2 and N=4. Other values ​​of N and M are also possible.

[0279] Figure 18B Additional details are shown for the interconnection between the multi-core processor 1807 and the graphics acceleration module 1846 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1846 may include one or more GPU chips integrated on a line card that is coupled to the processor 1807 via a high-speed link 1840 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1846 may be selectively integrated on a package or chip with the processor 1807.

[0280] In at least one embodiment, processor 1807 includes multiple cores 1860A-1860D, each core having a translation lookaside buffer ("TLB") 1861A-1861D and one or more caches 1862A-1862D. In at least one embodiment, cores 1860A-1860D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, caches 1862A-1862D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1856 may be included in caches 1862A-1862D and shared by each group of cores 1860A-1860D. For example, one embodiment of processor 1807 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1807 and the graphics acceleration module 1846 are connected to the system memory 1814, which may include Figure 18A Processor memory 1801(1)-1801(M) in.

[0281] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1862A-1862D, 1856, and system memory 1814 via inter-core communication over a coherency bus 1864. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate over the coherency bus 1864 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1864 to snoop cache accesses.

[0282] In at least one embodiment, proxy circuitry 1825 communicatively couples graphics acceleration module 1846 to coherence bus 1864, thereby allowing graphics acceleration module 1846 to participate in a cache coherence protocol as a peer of cores 1860A-1860D. In particular, in at least one embodiment, interface 1835 provides connectivity to proxy circuitry 1825 via high-speed link 1840, and interface 1837 connects graphics acceleration module 1846 to high-speed link 1840.

[0283] In at least one embodiment, the accelerator integrated circuit 1836 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1831(1)-1831(N) of the graphics acceleration module. In at least one embodiment, the graphics processing engines 1831(1)-1831(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1831(1)-1831(N) may optionally include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1846 may be a GPU having multiple graphics processing engines 1831(1)-1831(N), or the graphics processing engines 1831(1)-1831(N) may be individual GPUs integrated on a common package, line card, or chip.

[0284] In at least one embodiment, the accelerator integrated circuit 1836 includes a memory management unit (MMU) 1839 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1814. In at least one embodiment, the MMU 1839 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1838 may store commands and data for efficient access by the graphics processing engines 1831(1)-1831(N). In at least one embodiment, a fetch unit 1844 may be used to keep data stored in the cache 1838 and graphics memory 1833(1)-1833(M) consistent with the core caches 1862A-1862D, 1856, and system memory 1814. As previously described, this task may be accomplished via proxy circuitry 1825 acting on behalf of cache 1838 and graphics memory 1833(1)-1833(M) (e.g., sending updates relating to modifications / accesses of cache lines on processor caches 1862A-1862D, 1856 to cache 1838 and receiving updates from cache 1838).

[0285] In at least one embodiment, a set of registers 1845 stores context data for threads executed by graphics processing engines 1831(1)-1831(N), and context management circuitry 1848 manages thread contexts. For example, context management circuitry 1848 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1848 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to context. In at least one embodiment, interrupt management circuitry 1847 receives and processes interrupts received from system devices.

[0286] In one implementation, the MMU 1839 translates virtual / effective addresses from the graphics processing engine 1831 into real / physical addresses in the system memory 1814. In at least one embodiment, the accelerator integrated circuit 1836 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1846 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1846 can be dedicated to a single application executing on the processor 1807, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1831 (1)-1831 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0287] In at least one embodiment, the accelerator integrated circuit 1836 acts as a bridge to the system for the graphics acceleration module 1846 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1836 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1831(1)-1831(N).

[0288] In at least one embodiment, because the hardware resources of graphics processing engines 1831(1)-1831(N) are explicitly mapped into the real address space seen by host processor 1807, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1836 is to physically separate graphics processing engines 1831(1)-1831(N) so that they appear to the system as independent units.

[0289] In at least one embodiment, one or more graphics memories 1833(1)-1833(M) are coupled to each graphics processing engine 1831(1)-1831(N), respectively, and N=M. In at least one embodiment, graphics memories 1833(1)-1833(M) store instructions and data that are processed by each graphics processing engine 1831(1)-1831(N). In at least one embodiment, graphics memories 1833(1)-1833(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0290] In one embodiment, to reduce data traffic on high-speed link 1840, a biasing technique is used to ensure that the data stored in graphics memory 1833(1)-1833(M) is the data most frequently used by graphics processing engines 1831(1)-1831(N), and preferably the data not used (at least not frequently) by cores 1860A-1860D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 1831(-1)-1831(N)) in caches 1862A-1862D, 1856, and system memory 1814.

[0291] Figure 18C Another exemplary embodiment is shown in which an accelerator integrated circuit 1836 is integrated within the processor 1807. In this embodiment, the graphics processing engines 1831(1)-1831(N) communicate directly with the accelerator integrated circuit 1836 via interface 1837 and interface 1835 (which may also be any form of bus or interface protocol) over a high-speed link 1840. In at least one embodiment, the accelerator integrated circuit 1836 may perform operations related to the graphics processing engine 1831(1)-1831(N). Figure 18B The operations described above are similar to those described above. However, due to its close proximity to the coherence bus 1864 and caches 1862A-1862D, 1856, higher throughput is possible. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1836 and a programming model controlled by the graphics acceleration module 1846.

[0292] In at least one embodiment, graphics processing engines 1831(1)-1831(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1831(1)-1831(N), thereby providing virtualization within a VM / partition.

[0293] In at least one embodiment, graphics processing engines 1831(1)-1831(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1831(1)-1831(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1831(1)-1831(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1831(1)-1831(N) to provide access to each process or application.

[0294] In at least one embodiment, the graphics acceleration module 1846 or individual graphics processing engines 1831(1)-1831(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1814 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1831(1)-1831(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0295] Figure 18D An exemplary accelerator integrated slice 1890 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1836. In at least one embodiment, the application is an effective address space 1882 in system memory 1814, which stores a process element 1883. In at least one embodiment, the process element 1883 is stored in response to a GPU call 1881 from an application 1880 executing on the processor 1807. In at least one embodiment, the process element 1883 contains the process state of the corresponding application 1880. In one embodiment, the work descriptor (WD) 1884 contained in the process element 1883 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1884 is a pointer to a job request queue in the effective address space 1882 of the application.

[0296] In at least one embodiment, the graphics acceleration module 1846 and / or the individual graphics processing engines 1831(1)-1831(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 1884 to the graphics acceleration module 1846 to start a job in a virtualized environment.

[0297] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns either a graphics acceleration module 1846 or an individual graphics processing engine 1831. In at least one embodiment, when a graphics acceleration module 1846 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when a graphics acceleration module 1846 is assigned, the operating system initializes the accelerator integrated circuit 1836 for the owned process.

[0298] In at least one embodiment, in operation, a WD fetch unit 1891 in the accelerator integrated slice 1890 fetches the next WD 1884, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1846. In at least one embodiment, data from the WD 1884 can be stored in registers 1845 and used by the MMU 1839, interrupt management circuitry 1847, and / or context management circuitry 1848, as shown. For example, one embodiment of the MMU 1839 includes segment / page roaming circuitry for accessing segment / page tables 1886 within the OS virtual address space 1885. In at least one embodiment, the interrupt management circuitry 1847 can process interrupt events 1892 received from the graphics acceleration module 1846. In at least one embodiment, when performing graphics operations, effective addresses 1893 generated by the graphics processing engines 1831(1)-1831(N) are converted to real addresses by the MMU 1839.

[0299] In one embodiment, registers 1845 are replicated for each graphics processing engine 1831(1)-1831(N) and / or graphics acceleration module 1846, and the registers 1845 can be initialized by the hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in the accelerator integration slice 1890. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0300]

[0301]

[0302] Example registers that may be initialized by the operating system are shown in Table 2.

[0303]

[0304] In at least one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or graphics processing engine 1831(1)-1831(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1831(1)-1831(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0305] Figure 18E1896 virtualizes the graphics acceleration module engine for the operating system 1895.

[0306] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1846. In at least one embodiment, there are two programming models in which the graphics acceleration module 1846 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0307] In at least one embodiment, in this model, the hypervisor 1896 owns the graphics acceleration module 1846 and makes its functionality available to all operating systems 1895. In at least one embodiment, for the graphics acceleration module 1846 to support virtualization through the hypervisor 1896, the graphics acceleration module 1846 may adhere to certain requirements, such as (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1846 must provide a context save and restore mechanism, (2) the graphics acceleration module 1846 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1846 provides the ability to preempt job processing, and (3) fairness between graphics acceleration module 1846 processes must be ensured when operating in a directed shared programming model.

[0308] In at least one embodiment, the application 1880 is required to make an operating system 1895 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1846 and can take the form of a graphics acceleration module 1846 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 1846.

[0309] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1836 (not shown) and the graphics acceleration module 1846 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1896 may selectively apply the current AMR value before placing the AMR into the process element 1883. In at least one embodiment, the CSRP is one of the registers 1845 that contains the effective address of an area in the application's effective address space 1882 for the graphics acceleration module 1846 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0310] Upon receiving the system call, the operating system 1895 can verify that the application 1880 has been registered and granted permission to use the graphics acceleration module 1846. Then, in at least one embodiment, the operating system 1895 calls the hypervisor 1896 using the information shown in Table 3.

[0311]

[0312] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1896 verifies that operating system 1895 has registered and been granted permission to use graphics acceleration module 1846. Then, in at least one embodiment, hypervisor 1896 places process element 1883 into a linked list of process elements of the corresponding graphics acceleration module 1846 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0313]

[0314]

[0315] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1890 registers 1845 .

[0316] like Figure 18FAs shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1801(1)-1801(N) and GPU memory 1820(1)-1820(N). In this implementation, operations executed on GPUs 1810(1)-1810(N) utilize the same virtual / effective memory address space to access processor memory 1801(1)-1801(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1801(1), a second portion is allocated to second processor memory 1801(N), a third portion is allocated to GPU memory 1820(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1801 and GPU memory 1820, thereby allowing any processor or GPU to access that memory using a virtual address that maps to any physical memory.

[0317] In one embodiment, bias / coherency management circuitry 1894A-1894E within one or more MMUs 1839A-1839E ensures cache coherency between the caches of one or more host processors (e.g., 1805) and GPU 1810 and implements biasing techniques that indicate physical memory where certain types of data should be stored. In at least one embodiment, while Figure 18F Multiple instances of bias / coherence management circuits 1894A- 1894E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1805 and / or within an accelerator integrated circuit 1836 .

[0318] One embodiment allows GPU memory 1820 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1820 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1805 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1820 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1810. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0319] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits of memory per GPU-attached page. In at least one embodiment, the bias table can be implemented in a stolen memory range of one or more GPU memories 1820, with or without a bias cache in GPU 1810 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0320] In at least one embodiment, the bias table entry associated with each access to GPU-attached memory 1820 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1810 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1820. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 1805 (e.g., via the high-speed link described herein). In at least one embodiment, requests from processor 1805 that find the requested page in the host processor bias complete the request similarly to a normal memory read. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 1810. In at least one embodiment, if the GPU is not currently using the page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in limited cases, a purely hardware-based mechanism.

[0321] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1805 bias to GPU bias, but not for the reverse migration.

[0322] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1805. In at least one embodiment, to access these pages, processor 1805 may request access from GPU 1810, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1805 and GPU 1810, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1805, and vice versa.

[0323] One or more hardware structures 1015 are used to implement one or more embodiments. Figure 10A and / or Figure 10B Details regarding one or more hardware structures 1015 are provided.

[0324] Figure 19An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0325] Figure 19 1900 is a block diagram illustrating an exemplary system on a chip integrated circuit 1900 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1900 includes one or more application processors 1905 (e.g., CPUs), at least one graphics processor 1910, and may additionally include an image processor 1915 and / or a video processor 1920, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1900 includes peripheral or bus logic that includes a USB controller 1925, a UART controller 1930, an SPI / SDIO controller 1935, and an I / O controller. 2 2S / I 2 2C controller 1940. In at least one embodiment, integrated circuit 1900 may include a display device 1945 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1950 and a Mobile Industry Processor Interface (MIPI) display interface 1955. In at least one embodiment, storage may be provided by a flash memory subsystem 1960, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1965 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1970.

[0326] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Details are provided regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 may be used in integrated circuit 1900 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0327] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be used in integrated circuit 1900 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0328] Figures 20A-20B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0329] Figures 20A-20B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 20A An exemplary graphics processor 2010 of a system on a chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 20B Another exemplary graphics processor 2040 of a system on a chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 20A The graphics processor 2010 is a low power graphics processor core. In at least one embodiment, Figure 20B The graphics processor 2040 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 2010, 2040 can be Figure 19 A variant of the graphics processor 1910.

[0330] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D through 2015N-1 and 2015N). In at least one embodiment, the graphics processor 2010 can execute different shader programs via separate logic, such that the vertex processor 2005 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 2005 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 2015A-2015N use the primitives and vertex data generated by the vertex processor 2005 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 2015A-2015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0331] In at least one embodiment, the graphics processor 2010 additionally includes one or more memory management units (MMUs) 2020A-2020B, one or more caches 2025A-2025B, and one or more circuit interconnects 2030A-2030B. In at least one embodiment, the one or more MMUs 2020A-2020B provide a mapping of virtual to physical addresses for the graphics processor 2010, including for the vertex processor 2005 and / or the fragment processors 2015A-2015N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 2025A-2025B. In at least one embodiment, the one or more MMUs 2020A-2020B may synchronize with other MMUs within the system, including with other MMUs. Figure 19 One or more MMUs associated with one or more application processors 1905, graphics processor 1915, and / or video processor 1920 enable each processor 1905-1920 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable graphics processor 2010 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0332] In at least one embodiment, graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F through 2055N-1 and 2055N), such as Figure 20B As shown, it provides a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2040 includes an inter-core task manager 2045 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2055A-2055N and a tiling unit 2058 to accelerate tile-based rendering operations, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0333] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10BProvides details about the inference and / or training logic 1015. In at least one embodiment, the inference and / or training logic 1015 may be implemented in an integrated circuit. Figure 20A and / or Figure 20B for performing inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function or architecture, or a neural network use case described herein.

[0334] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be integrated circuit Figure 20A and / or Figure 20B for use in performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0335] Figures 21A-21B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 21A Shows that can be included in Figure 19 Graphics core 2100 within graphics processor 1910, and in at least one embodiment, may be such as Figure 20B Unified shader cores 2055A-2055N are shown. Figure 21B A highly parallel general purpose graphics processing unit ("GPGPU") 2130 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0336] In at least one embodiment, graphics core 2100 includes a shared instruction cache 2102, texture units 2118, and cache / shared memory 2120, which are common to execution resources within graphics core 2100. In at least one embodiment, graphics core 2100 may include multiple slices 2101A-2101N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 2100. In at least one embodiment, slices 2101A-2101N may include support logic including a local instruction cache 2104A-2104N, a thread scheduler 2106A-2106N, a thread dispatcher 2108A-2108N, and a set of registers 2110A-2110N. In at least one embodiment, slices 2101A-2101N may include a set of additional function units (AFUs 2112A-2112N), floating point units (FPUs 2114A-2114N), integer arithmetic logic units (ALUs 2116A-2116N), address calculation units (ACUs 2113A-2113N), double-precision floating point units (DPFPUs 2115A-2115N), and matrix processing units (MPUs 2117A-2117N).

[0337] In at least one embodiment, the FPUs 2114A-2114N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2115A-2115N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2116A-2116N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2117A-2117N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 2117-2117N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 2112A-2112N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0338] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10BDetails are provided regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 can be used in graphics core 2100 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0339] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be used in graphics core 2100 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0340] Figure 21B A general purpose processing unit (GPGPU) 2130 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 2130 can be directly linked to other instances of GPGPU 2130 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 2130 includes a host interface 2132 to enable connection to a host processor. In at least one embodiment, host interface 2132 is a PCI Express interface. In at least one embodiment, host interface 2132 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2130 receives commands from the host processor and uses a global scheduler 2134 to assign execution threads associated with those commands to a group of compute clusters 2136A-2136H. In at least one embodiment, compute clusters 2136A-2136H share a cache memory 2138. In at least one embodiment, cache memory 2138 may serve as a higher level of cache for cache memory within compute clusters 2136A-2136H.

[0341] In at least one embodiment, the GPGPU 2130 includes memory 2144A-2144B coupled to the compute cluster 2136A-2136H via a set of memory controllers 2142A-2142B. In at least one embodiment, the memory 2144A-2144B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0342] In at least one embodiment, the computing clusters 2136A-2136H each include a set of graphics cores, e.g. Figure 21A The graphics core 2100 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each compute cluster 2136A-2136H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0343] In at least one embodiment, multiple instances of GPGPU 2130 can be configured to function as a compute cluster. In at least one embodiment, the communication used by compute clusters 2136A-2136H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2130 communicate via a host interface 2132. In at least one embodiment, GPGPU 2130 includes an I / O hub 2139 that couples GPGPU 2130 to a GPU link 2140, enabling direct connections to other instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2130 reside in separate data processing systems and communicate via a network device accessible through host interface 2132. In at least one embodiment, GPU link 2140 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 2132 .

[0344] In at least one embodiment, the GPGPU 2130 can be configured to train a neural network. In at least one embodiment, the GPGPU 2130 can be used within an inference platform. In at least one embodiment, where the GPGPU 2130 is used for inference, the GPGPU 2130 can include fewer compute clusters 2136A-2136H than when the GPGPU 2130 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 2144A-2144B can differ between the inference and training configurations, with the higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2130 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0345] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Details are provided regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 can be used in GPGPU 2130 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0346] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be used in GPGPU2130 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0347] Figure 22A block diagram of a computer system 2200 is shown, according to at least one embodiment. In at least one embodiment, computer system 2200 includes a processing subsystem 2201 having one or more processors 2202 and a system memory 2204, which communicates via an interconnect path that may include a memory hub 2205. In at least one embodiment, memory hub 2205 may be a separate component within a chipset assembly or may be integrated within one or more processors 2202. In at least one embodiment, memory hub 2205 is coupled to an I / O subsystem 2211 via a communication link 2206. In one embodiment, I / O subsystem 2211 includes an I / O hub 2207, which enables computer system 2200 to receive input from one or more input devices 2208. In at least one embodiment, I / O hub 2207 may enable a display controller, which may be included in one or more processors 2202, to provide output to one or more display devices 2210A. In at least one embodiment, the one or more display devices 2210A coupled to the I / O hub 2207 may include local, internal, or embedded display devices.

[0348] In at least one embodiment, the processing subsystem 2201 includes one or more parallel processors 2212 coupled to the memory hub 2205 via a bus or other communication link 2213. In at least one embodiment, the communication link 2213 can use any of a number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2212 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 2212 form a graphics processing subsystem that can output pixels to one of one or more display devices 2210A coupled via the I / O hub 2207. In at least one embodiment, the parallel processors 2212 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 2210B.

[0349] In at least one embodiment, a system storage unit 2214 can be connected to the I / O hub 2207 to provide a storage mechanism for the computer system 2200. In at least one embodiment, an I / O switch 2216 can be used to provide an interface mechanism to enable connections between the I / O hub 2207 and other components, such as a network adapter 2218 and / or a wireless network adapter 2219 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 2220. In at least one embodiment, the network adapter 2218 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2219 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0350] In at least one embodiment, the computer system 2200 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2207. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Figure 22 Communication paths for various components in a chip, such as NV-Link high-speed interconnect or interconnect protocol.

[0351] In at least one embodiment, one or more parallel processors 2212 include circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In at least one embodiment, the parallel processors 2212 include circuits optimized for general-purpose processing. In at least one embodiment, the components of the computer system 2200 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processors 2212, the memory hub 2205, the processor 2202, and the I / O hub 2207 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computer system 2200 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2200 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computer system.

[0352] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Provides details about the reasoning and / or training logic 1015. In at least one embodiment, the reasoning and / or training logic 1015 may be Figure 22 for use in system 2200 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0353] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be found in Figure 22 for use in system 2200 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0354] processor

[0355] Figure 23A 2300 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2300 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2300 is shown as a processor according to an exemplary embodiment. Figure 22 A variation of the one or more parallel processors 2212 shown.

[0356] In at least one embodiment, parallel processor 2300 includes parallel processing unit 2302. In at least one embodiment, parallel processing unit 2302 includes an I / O unit 2304 that enables communication with other devices, including other instances of parallel processing unit 2302. In at least one embodiment, I / O unit 2304 can be directly connected to other devices. In at least one embodiment, I / O unit 2304 connects to other devices using a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between memory hub 2305 and I / O unit 2304 forms a communication link 2313. In at least one embodiment, I / O unit 2304 is connected to a host interface 2306 and a memory crossbar switch 2316, where host interface 2306 receives commands for performing processing operations and memory crossbar switch 2316 receives commands for performing memory operations.

[0357] In at least one embodiment, when host interface 2306 receives command buffers via I / O unit 2304, host interface 2306 can direct work operations to execute those commands to front end 2308. In at least one embodiment, front end 2308 is coupled to scheduler 2310, which is configured to distribute commands or other work items to processing cluster array 2312. In at least one embodiment, scheduler 2310 ensures that processing cluster array 2312 is properly configured and in a valid state before distributing tasks to processing cluster array 2312. In at least one embodiment, scheduler 2310 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2310 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2312. In at least one embodiment, host software can validate workloads for scheduling on processing array 2312 via one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically distributed across the processing array 2312 by scheduler 2310 logic within a microcontroller that includes scheduler 2310 .

[0358] In at least one embodiment, processing cluster array 2312 may include up to "N" processing clusters (e.g., cluster 2314A, cluster 2314B, through cluster 2314N), where "N" represents a positive integer (which may be a different integer than the integer "N" used in other figures). In at least one embodiment, each cluster 2314A-2314N of processing cluster array 2312 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2310 may use various scheduling and / or work distribution algorithms to distribute work to clusters 2314A-2314N of processing cluster array 2312, which may vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling may be handled dynamically by scheduler 2310 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 2312. In at least one embodiment, different clusters 2314A-2314N of processing cluster array 2312 may be assigned to process different types of programs or to perform different types of computations.

[0359] In at least one embodiment, processing cluster array 2312 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2312 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2312 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0360] In at least one embodiment, processing cluster array 2312 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2312 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2312 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 2302 may transfer data from system memory via I / O units 2304 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2322) during processing and then written back to system memory.

[0361] In at least one embodiment, when parallel processing unit 2302 is used to perform graphics processing, scheduler 2310 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2314A-2314N of processing cluster array 2312. In at least one embodiment, portions of processing cluster array 2312 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2314A-2314N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2314A-2314N for further processing.

[0362] In at least one embodiment, the processing cluster array 2312 can receive processing tasks to be executed via the scheduler 2310, which receives commands defining the processing tasks from the front end 2308. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2310 can be configured to obtain an index corresponding to a task, or can receive the index from the front end 2308. In at least one embodiment, the front end 2308 can be configured to ensure that the processing cluster array 2312 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0363] In at least one embodiment, each of the one or more instances of parallel processing unit 2302 can be coupled to parallel processor memory 2322. In at least one embodiment, parallel processor memory 2322 can be accessed via memory crossbar 2316, which can receive memory requests from processing cluster array 2312 and I / O unit 2304. In at least one embodiment, memory crossbar 2316 can access parallel processor memory 2322 via memory interface 2318. In at least one embodiment, memory interface 2318 can include multiple partition units (e.g., partition unit 2320A, partition unit 2320B, through partition unit 2320N), which can each be coupled to a portion of parallel processor memory 2322 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2320A-2320N are configured to be equal to the number of memory cells, such that the first partition unit 2320A has a corresponding first memory cell 2324A, the second partition unit 2320B has a corresponding memory cell 2324B, and the Nth partition unit 2320N has a corresponding Nth memory cell 2324N. In at least one embodiment, the number of partition units 2320A-2320N may not be equal to the number of memory cells.

[0364] In at least one embodiment, memory units 2324A-2324N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2324A-2324N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2324A-2324N, allowing partition units 2320A-2320N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2322. In at least one embodiment, local instances of parallel processor memory 2322 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0365] In at least one embodiment, any of the clusters 2314A-2314N in the processing cluster array 2312 can process data to be written to any memory unit 2324A-2324N within the parallel processor memory 2322. In at least one embodiment, the memory crossbar 2316 can be configured to transmit the output of each cluster 2314A-2314N to any partition unit 2320A-2320N or another cluster 2314A-2314N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2314A-2314N can communicate with a memory interface 2318 via the memory crossbar 2316 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 2316 has connections to memory interface 2318 for communicating with I / O unit 2304, as well as connections to local instances of parallel processor memory 2322, thereby enabling processing units within different processing clusters 2314A-2314N to communicate with system memory or other memory that is not local to parallel processing unit 2302. In at least one embodiment, memory crossbar switch 2316 can use virtual channels to separate traffic flows between clusters 2314A-2314N and partition units 2320A-2320N.

[0366] In at least one embodiment, multiple instances of parallel processing unit 2302 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2302 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2302 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2302 or parallel processor 2300 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0367] Figure 23B is a block diagram of a partition unit 2320 according to at least one embodiment. In at least one embodiment, the partition unit 2320 is Figure 23A 2320N。In at least one embodiment, the partition unit 2320 includes an L2 cache 2321, a frame buffer interface 2325, and an ROP 2326 (raster operation unit). In at least one embodiment, the L2 cache 2321 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2316 and the ROP 2326. In at least one embodiment, the L2 cache 2321 outputs read misses and urgent write-back requests to the frame buffer interface 2325 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2325 for processing. In at least one embodiment, the frame buffer interface 2325 communicates with memory units in the parallel processor memory (such as Figure 23A interacts with one of the memory units 2324A-2324N (e.g., within parallel processor memory 2322).

[0368] In at least one embodiment, ROP 2326 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2326 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2326 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2326 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0369] In at least one embodiment, ROP 2326 is included within each processing cluster (e.g., Figure 23A In at least one embodiment, read and write requests for pixel data are transmitted through the memory crossbar 2316 rather than through the pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device such as a Figure 22 2202 for further processing, or by Figure 23A One of the processing entities within parallel processor 2300 is routed for further processing.

[0370] Figure 23C is a block diagram of a processing cluster 2314 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 23A In at least one embodiment, processing cluster 2314 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster.

[0371] In at least one embodiment, the operation of the processing cluster 2314 can be controlled by a pipeline manager 2332 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2332 Figure 23AScheduler 2310 receives instructions and manages the execution of these instructions via graphics multiprocessor 2334 and / or texture unit 2336. In at least one embodiment, graphics multiprocessor 2334 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within processing cluster 2314. In at least one embodiment, one or more instances of graphics multiprocessor 2334 may be included within processing cluster 2314. In at least one embodiment, graphics multiprocessor 2334 may process data, and data crossbar 2340 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, pipeline manager 2332 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via data crossbar 2340.

[0372] In at least one embodiment, each graphics multiprocessor 2334 within a processing cluster 2314 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0373] In at least one embodiment, instructions transmitted to the processing cluster 2314 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2334. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop of the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2334, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2334.

[0374] In at least one embodiment, the graphics multiprocessor 2334 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2334 can abandon the internal cache and use cache memory within the processing cluster 2314 (e.g., L1 cache 2348). In at least one embodiment, each graphics multiprocessor 2334 can also access a partition unit (e.g., Figure 23A L2 cache within partition units 2320A-2320N) of the graphics multiprocessor 2302 is shared across all processing clusters 2314 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2334 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2302 can be used as global memory. In at least one embodiment, processing cluster 2314 includes multiple instances of graphics multiprocessor 2334, which can share common instructions and data, which can be stored in L1 cache 2348.

[0375] In at least one embodiment, each processing cluster 2314 may include a memory management unit ("MMU") 2345 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2345 may reside in Figure 23A 2318. In at least one embodiment, the MMU 2345 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2345 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2334 or L1 cache 2348 or processing cluster 2314. In at least one embodiment, the physical address is processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0376] In at least one embodiment, the processing clusters 2314 can be configured such that each graphics multiprocessor 2334 is coupled to a texture unit 2336 to perform texture mapping operations, which determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2334, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2334 outputs processed tasks to a data crossbar 2340 to provide the processed tasks to another processing cluster 2314 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2316. In at least one embodiment, a preROP 2342 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 2334 and direct the data to a ROP unit, which can communicate with a partition unit (e.g., a partition unit) as described herein. Figure 23A In at least one embodiment, the PreROP 2342 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0377] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Details are provided regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 can be used in graphics processing cluster 2314 to perform inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0378] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be used in graphics processing cluster 2314 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0379] Figure 23DA graphics multiprocessor 2334 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2334 is coupled to a pipeline manager 2332 of a processing cluster 2314. In at least one embodiment, the graphics multiprocessor 2334 has an execution pipeline that includes, but is not limited to, an instruction cache 2352, an instruction unit 2354, an address mapping unit 2356, a register file 2358, one or more general purpose graphics processing unit (GPGPU) cores 2362, and one or more load / store units 2366. In at least one embodiment, the GPGPU cores 2362 and the load / store units 2366 are coupled to a cache memory 2372 and a shared memory 2370 via a memory and cache interconnect 2368.

[0380] In at least one embodiment, the instruction cache 2352 receives a stream of instructions to be executed from the pipeline manager 2332. In at least one embodiment, the instructions are cached in the instruction cache 2352 and dispatched for execution by the instruction unit 2354. In one embodiment, the instruction unit 2354 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2362. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2356 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 2366.

[0381] In at least one embodiment, register file 2358 provides a set of registers for the functional units of graphics multiprocessor 2334. In at least one embodiment, register file 2358 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2362, load / store unit 2366) connected to graphics multiprocessor 2334. In at least one embodiment, register file 2358 is divided between each functional unit such that a dedicated portion of register file 2358 is allocated to each functional unit. In at least one embodiment, register file 2358 is divided between the different warps being executed by graphics multiprocessor 2334.

[0382] In at least one embodiment, the GPGPU cores 2362 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2334. In at least one embodiment, the GPGPU cores 2362 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2362 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2334 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2362 may also include fixed-function or special-function logic.

[0383] In at least one embodiment, the GPGPU core 2362 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2362 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0384] In at least one embodiment, the memory and cache interconnect 2368 is an interconnect network that connects each functional unit of the graphics multiprocessor 2334 to the register file 2358 and the shared memory 2370. In at least one embodiment, the memory and cache interconnect 2368 is a crossbar interconnect that allows the load / store unit 2366 to perform load and store operations between the shared memory 2370 and the register file 2358. In at least one embodiment, the register file 2358 can operate at the same frequency as the GPGPU core 2362, resulting in very low latency for data transfers between the GPGPU core 2362 and the register file 2358. In at least one embodiment, the shared memory 2370 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2334. In at least one embodiment, the cache memory 2372 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2336. In at least one embodiment, the shared memory 2370 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2372, threads executing on GPGPU core 2362 may also programmatically store data in shared memory.

[0385] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0386] The reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10BDetails are provided regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 may be used in graphics multiprocessor 2234 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0387] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be used in the graphics multiprocessor 2334 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0388] Figure 24 A multi-GPU computing system 2400 is shown in accordance with at least one embodiment. In at least one embodiment, multi-GPU computing system 2400 may include a processor 2402 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2406A-D via a host interface switch 2404. In at least one embodiment, host interface switch 2404 is a PCI Express switch device that couples processor 2402 to a PCI Express bus, over which processor 2402 can communicate with GPGPUs 2406A-D. In at least one embodiment, GPGPUs 2406A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2416. In at least one embodiment, GPU-to-GPU links 2416 connect to each of GPGPUs 2406A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 2416 enable direct communication between each GPGPU 2406A-D without requiring communication through host interface bus 2404 to which processor 2402 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU link 2416, host interface bus 2404 remains available for system memory access or communication with other instances of multi-GPU computing system 2400, e.g., via one or more network devices. While in at least one embodiment, GPGPUs 2406A-D are connected to processor 2402 via host interface switch 2404, in at least one embodiment, processor 2402 includes direct support for P2P GPU link 2416 and can connect directly to GPGPUs 2406A-D.

[0389] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Details are provided regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 can be used in multi-GPU computing system 2400 to perform inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0390] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be used in the multi-GPU computing system 2400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0391] Figure 25 FIG2 is a block diagram of a graphics processor 2500 according to at least one embodiment. In at least one embodiment, graphics processor 2500 includes a ring interconnect 2502, a pipeline front end 2504, a media engine 2537, and graphics cores 2580A-2580N. In at least one embodiment, ring interconnect 2502 couples graphics processor 2500 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2500 is one of many processors integrated within a multi-core processing system.

[0392] In at least one embodiment, the graphics processor 2500 receives batches of commands via a ring interconnect 2502. In at least one embodiment, the incoming commands are interpreted by a command streamer 2503 in a pipeline front end 2504. In at least one embodiment, the graphics processor 2500 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2580A-2580N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2503 provides the commands to a geometry pipeline 2536. In at least one embodiment, for at least some media processing commands, the command streamer 2503 provides the commands to a video front end 2534, which is coupled to a media engine 2537. In at least one embodiment, the media engine 2537 includes a video quality engine (VQE) 2530 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2533 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2536 and the media engine 2537 each generate execution threads for thread execution resources provided by at least one graphics core 2580 .

[0393] In at least one embodiment, the graphics processor 2500 includes scalable thread execution resources featuring graphics cores 2580A-2580N (which may be modular and sometimes referred to as core slices), each graphics core having multiple sub-cores 2550A-2550N, 2560A-2560N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2500 may have any number of graphics cores 2580A. In at least one embodiment, the graphics processor 2500 includes a graphics core 2580A having at least a first sub-core 2550A and a second sub-core 2560A. In at least one embodiment, the graphics processor 2500 is a low-power processor having a single sub-core (e.g., 2550A). In at least one embodiment, the graphics processor 2500 includes multiple graphics cores 2580A-2580N, each graphics core including a set of first sub-cores 2550A-2550N and a set of second sub-cores 2560A-2560N. In at least one embodiment, each of the first sub-cores 2550A-2550N includes at least a first set of execution units 2552A-2552N and media / texture samplers 2554A-2554N. In at least one embodiment, each of the second sub-cores 2560A-2560N includes at least a second set of execution units 2562A-2562N and samplers 2564A-2564N. In at least one embodiment, each of the sub-cores 2550A-2550N, 2560A-2560N shares a set of shared resources 2570A-2570N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0394] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Details are provided regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 may be used in graphics processor 2500 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0395] In at least one embodiment, Figure 5 and Figure 7 The inference and / or training logic can be used in the graphics processor 2500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0396] Figure 26is a block diagram illustrating a microarchitecture for a processor 2600 that may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2600 may execute instructions including x86 instructions, ARM instructions, specialized instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2600 may include registers for storing packed data, such as the 64-bit wide MMX registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in integer and floating point form can operate with packed data elements that accompany single instruction multiple data ("SIMD") and streaming SIMD extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (generally referred to as "SSEx") technology can hold such packed data operands. In at least one embodiment, processor 2600 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0397] In at least one embodiment, the processor 2600 includes an in-order front end ("front end") 2601 to fetch instructions to be executed and prepare the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2601 may include several units. In at least one embodiment, an instruction prefetcher 2626 retrieves instructions from memory and provides the instructions to an instruction decoder 2628, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2628 decodes the received instructions into one or more operations called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions") that the machine can execute. In at least one embodiment, the instruction decoder 2628 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, the trace cache 2630 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2634 for execution. In at least one embodiment, when trace cache 2630 encounters a complex instruction, microcode ROM 2632 provides the microinstructions necessary to complete the operation.

[0398] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2628 may access the microcode ROM 2632 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2628. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2632. In at least one embodiment, the trace cache 2630 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2632 to complete one or more instructions in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2632 completes the micro-op sequencing for the instruction, the front end 2601 of the machine may resume fetching micro-ops from the trace cache 2630.

[0399] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2603 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. In at least one embodiment, the OOO engine 2603 includes, but is not limited to, an allocator / register renamer 2640, a memory microinstruction queue 2642, an integer / floating-point microinstruction queue 2644, a memory scheduler 2646, a fast scheduler 2602, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2604, and a simple floating-point scheduler ("simple FP scheduler") 2606. In at least one embodiment, the fast scheduler 2602, the slow / general purpose floating-point scheduler 2604, and the simple floating-point scheduler 2606 are also collectively referred to as "microinstruction schedulers 2602, 2604, 2606." In at least one embodiment, the allocator / register renamer 2640 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2640 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2640 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2642 for memory operations and an integer / floating-point microinstruction queue 2644 for non-memory operations, preceding the memory scheduler 2646 and the microinstruction schedulers 2602, 2604, and 2606. In at least one embodiment, the microinstruction schedulers 2602, 2604, and 2606 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2602 of at least one embodiment can schedule every half of the main clock cycle, while the slow / general floating-point scheduler 2604 and the simple floating-point scheduler 2606 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2602, 2604, 2606 arbitrate on dispatch ports to schedule microinstructions for execution.

[0400] In at least one embodiment, execution block 2611 includes, but is not limited to, integer register file / branch network 2608, floating point register file / branch network ("FP register file / branch network") 2610, address generation units ("AGUs") 2612 and 2614, fast arithmetic logic units ("fast ALUs") 2616 and 2618, slow arithmetic logic unit ("slow ALU") 2620, floating point ALU ("FP") 2622, and floating point move unit ("FP move") 2624. In at least one embodiment, integer register file / branch network 2608 and floating point register file / bypass network 2610 are also referred to herein as "register files 2608, 2610." In at least one embodiment, AGUs 2612 and 2614, fast ALUs 2616 and 2618, slow ALU 2620, floating-point ALU 2622, and floating-point move unit 2624 are also referred to herein as "execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624."

[0401] In at least one embodiment, execution block 2611 may include, but is not limited to, any number (including zero) and types of register files, branch networks, address generation units, and execution units (in any combination).

[0402] In at least one embodiment, register networks 2608 and 2610 may be arranged between microinstruction schedulers 2602, 2604, and 2606 and execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624. In at least one embodiment, integer register file / branch network 2608 performs integer operations. In at least one embodiment, floating-point register file / branch network 2610 performs floating-point operations. In at least one embodiment, each of register networks 2608 and 2610 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register networks 2608 and 2610 may communicate data with each other. In at least one embodiment, integer register file / branch network 2608 may include, but is not limited to, two separate register files: one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2610 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0403] In at least one embodiment, execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624 can execute instructions. In at least one embodiment, register networks 2608 and 2610 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2600 can include, but is not limited to, any number of execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624, and any combination thereof. In at least one embodiment, floating-point ALU 2622 and floating-point move unit 2624 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2622 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2616 and 2618. In at least one embodiment, fast ALUs 2616 and 2618 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2620, as slow ALU 2620 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by AGUs 2612 and 2614. In at least one embodiment, fast ALU 2616, fast ALU 2618, and slow ALU 2620 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2616, fast ALU 2618, and slow ALU 2620 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, floating point ALU 2622 and floating point move unit 2624 may be implemented to support a range of operands having bits of various widths, for example, 128-bit wide packed data operands may be operated on in conjunction with SIMD and multimedia instructions.

[0404] In at least one embodiment, microinstruction schedulers 2602, 2604, 2606 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2600, processor 2600 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0405] In at least one embodiment, "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0406] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Details are provided regarding the inference and / or training logic 1015. In at least one embodiment, some or all of the inference and / or training logic 1015 may be incorporated into the execution block 2611 and other memories or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more ALUs shown in the execution block 2611. Additionally, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the execution block 2611 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0407] Figure 27A deep learning application processor 2700 is shown in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2700 uses instructions that, if executed by the deep learning application processor 2700, cause the deep learning application processor 2700 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2700 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2700 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions, or both. In at least one embodiment, the deep learning application processor 2700 includes, but is not limited to, processing clusters 2710(1)-2710(12), inter-chip links (“ICLs”) 2720(1)-2720(12), inter-chip controllers (“ICCs”) 2730(1)-2730(2), second generation high bandwidth memory (“HBM2”) 2740(1)-2740(4), memory controllers (“Mem Ctrlr”) 2742(1)-2742(4), high bandwidth memory physical layer (“HBM PHY”) 2744(1)-2744(4), a management controller central processing unit (“management controller CPU”) 2750, serial peripheral interface, inter-integrated circuit, and general purpose input / output blocks (“SPI, I2C, GPIO”) 2760, a peripheral component interconnect express controller and direct memory access block (“PCIe controller and DMA”) 2770, and a sixteen-lane peripheral component interconnect express port (“PCI Express”). x 16”)2780.

[0408] In at least one embodiment, the processing cluster 2710 can perform deep learning operations, including inference or prediction operations based on weight parameters calculated by one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2710 can include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2700 can include any number and type of processing clusters 2700. In at least one embodiment, the inter-chip link 2720 is bidirectional. In at least one embodiment, the inter-chip link 2720 and the inter-chip controller 2730 enable multiple deep learning application processors 2700 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2700 can include any number (including zero) and type of ICLs 2720 and ICCs 2730.

[0409] In at least one embodiment, HBM2 2740 provides a total of 32GB of memory. In at least one embodiment, HBM2 2740(i) is associated with both a memory controller 2742(i) and an HBM PHY 2744(i), where "i" is an arbitrary integer. In at least one embodiment, any number of HBM2s 2740 can provide any type and amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2742 and HBM PHYs 2744.

[0410] In at least one embodiment, the SPI, I2C, GPIO 3360, PCIe controller 2760 and DMA 2770 and / or PCIe 2780 may be replaced with any number and type of blocks to implement any number and type of communication standards in any technically feasible manner.

[0411] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B Provides details regarding inference and / or training logic 1015. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2700. In at least one embodiment, the deep learning application processor 2700 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2700. In at least one embodiment, the processor 2700 can be used to perform one or more of the neural network use cases described herein.

[0412] Figure 28is a block diagram of a neuromorphic processor 2800 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2800 can receive one or more inputs from a source external to the neuromorphic processor 2800. In at least one embodiment, these inputs can be transmitted to one or more neurons 2802 within the neuromorphic processor 2800. In at least one embodiment, the neurons 2802 and their components can be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2800 can include, but is not limited to, thousands of instances of neurons 2802, although any suitable number of neurons 2802 can be used. In at least one embodiment, each instance of a neuron 2802 can include a neuron input 2804 and a neuron output 2806. In at least one embodiment, a neuron 2802 can generate an output that can be transmitted to the inputs of other instances of the neuron 2802. In at least one embodiment, the neuron input 2804 and the neuron output 2806 can be interconnected via a synapse 2808.

[0413] In at least one embodiment, the neurons 2802 and synapses 2808 can be interconnected so that the neuromorphic processor 2800 operates to process or analyze information received by the neuromorphic processor 2800. In at least one embodiment, the neuron 2802 can send an output pulse (or "trigger" or "spike") when the input received through the neuron input 2804 exceeds a threshold. In at least one embodiment, the neuron 2802 can sum or integrate the signal received at the neuron input 2804. For example, in at least one embodiment, the neuron 2802 can be implemented as a leaky integrate-and-trigger neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 2802 can generate an output (or "trigger") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, the leaky integrate-and-trigger neuron can sum the signal received at the neuron input 2804 into a membrane potential and can apply an application attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may trigger if multiple input signals are received at neuron input 2804 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2802 may be implemented using circuitry or logic that receives input, integrates the input into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2802 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2806 when the result of applying the transfer function to neuron input 2804 exceeds a threshold. In at least one embodiment, once neuron 2802 triggers, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2802 may resume normal operation after a suitable period of time (or recovery period).

[0414] In at least one embodiment, neurons 2802 can be interconnected via synapses 2808. In at least one embodiment, synapses 2808 can be operable to transmit a signal from an output of a first neuron 2802 to an input of a second neuron 2802. In at least one embodiment, a neuron 2802 can transmit information across more than one instance of synapse 2808. In at least one embodiment, one or more instances of a neuron output 2806 can be connected to an instance of a neuron input 2804 in the same neuron 2802 via an instance of synapse 2808. In at least one embodiment, an instance of a neuron 2802 that generates an output to be transmitted across an instance of synapse 2808 can be referred to as a "presynaptic neuron" relative to that instance of synapse 2808. In at least one embodiment, an instance of a neuron 2802 that receives an input transmitted across an instance of synapse 2808 can be referred to as a "postsynaptic neuron" relative to an instance of synapse 2808. In at least one embodiment, with respect to the various instances of synapses 2808, because an instance of neuron 2802 can receive input from one or more instances of synapses 2808 and can also transmit output through one or more instances of synapses 2808, a single instance of neuron 2802 can be both a "pre-synaptic neuron" and a "post-synaptic neuron."

[0415] In at least one embodiment, neurons 2802 may be organized into one or more layers. In at least one embodiment, each instance of a neuron 2802 may have a neuron output 2806 that may fan out to one or more neuron inputs 2804 via one or more synapses 2808. In at least one embodiment, the neuron output 2806 of a neuron 2802 in a first layer 2810 may be connected to the neuron input 2804 of a neuron 2802 in a second layer 2812. In at least one embodiment, layers 2810 may be referred to as "feed-forward layers." In at least one embodiment, each instance of a neuron 2802 in an instance of the first layer 2810 may fan out to each instance of a neuron 2802 in the second layer 2812. In at least one embodiment, the first layer 2810 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of a neuron 2802 in each instance of the second layer 2812 may fan out to fewer than all instances of a neuron 2802 in the third layer 2814. In at least one embodiment, the second layer 2812 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, neurons 2802 in the second layer 2812 can fan out to neurons 2802 in multiple other layers, including neurons 2802 in the second layer 2812. In at least one embodiment, the second layer 2812 can be referred to as a "recurrent layer." In at least one embodiment, the neuromorphic processor 2800 can include, but is not limited to, any suitable combination of recurrent layers and feedforward layers, including, but not limited to, sparsely connected feedforward layers and fully connected feedforward layers.

[0416] In at least one embodiment, the neuromorphic processor 2800 may include, but is not limited to, a reconfigurable interconnect architecture or a dedicated hardwired interconnect to connect synapses 2808 to neurons 2802. In at least one embodiment, the neuromorphic processor 2800 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2802 as needed based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2808 may be connected to neurons 2802 using an interconnect architecture such as a network on a chip or through dedicated connections. In at least one embodiment, the synaptic interconnect and its components may be implemented using circuitry or logic.

[0417] Figure 292900 includes one or more processors 2902 and one or more graphics processors 2908, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2902 or processor cores 2907. In at least one embodiment, system 2900 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0418] In at least one embodiment, the system 2900 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the system 2900 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2900 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2900 is a television or set-top box device having one or more processors 2902 and a graphical interface generated by one or more graphics processors 2908.

[0419] In at least one embodiment, one or more processors 2902 each include one or more processor cores 2907 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2907 is configured to process a specific instruction sequence 2909. In at least one embodiment, the instruction sequence 2909 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or be calculated using very long instruction words (VLIW). In at least one embodiment, the processor cores 2907 can each process a different instruction sequence 2909, which can include instructions that contribute to emulating other instruction sequences. In at least one embodiment, the processor cores 2907 can also include other processing devices, such as a digital signal processor (DSP).

[0420] In at least one embodiment, the processor 2902 includes a cache memory 2904. In at least one embodiment, the processor 2902 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2902. In at least one embodiment, the processor 2902 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can be shared among the processor cores 2907 using known cache coherence techniques. In at least one embodiment, the processor 2902 further includes a register file 2906. The processor can include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 2906 can include general purpose registers or other registers.

[0421] In at least one embodiment, one or more processors 2902 are coupled to one or more interface buses 2910 to transmit communication signals, such as address, data, or control signals, between the processors 2902 and other components in the system 2900. In at least one embodiment, the interface bus 2910 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2910 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2902 includes an integrated memory controller 2916 and a platform controller hub 2930. In at least one embodiment, the memory controller 2916 facilitates communication between memory devices and other components of the processing system 2900, while the platform controller hub (PCH) 2930 provides connections to input / output (I / O) devices via a local I / O bus.

[0422] In at least one embodiment, memory device 2920 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other suitable memory device for use as processor memory. In at least one embodiment, memory device 2920 can be used as system memory for processing system 2900 to store data 2922 and instructions 2921 for use when one or more processors 2902 execute applications or processes. In at least one embodiment, memory controller 2916 is also coupled to an optional external graphics processor 2912, which can communicate with one or more graphics processors 2908 in processor 2902 to perform graphics and media operations. In at least one embodiment, display device 2911 can be connected to processor 2902. In at least one embodiment, display device 2911 can include one or more internal display devices, such as in a mobile electronic device or laptop device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2911 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0423] In at least one embodiment, the platform controller hub 2930 enables peripheral devices to connect to the storage device 2920 and the processor 2902 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2946, a network controller 2934, a firmware interface 2928, a wireless transceiver 2926, a touch sensor 2925, and a data storage device 2924 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2924 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2925 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2926 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2928 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, a network controller 2934 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2910. In at least one embodiment, the audio controller 2946 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2900 includes an optional legacy I / O controller 2940 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 2900. In at least one embodiment, the platform controller hub 2930 can also be connected to one or more universal serial bus (USB) controllers 2942 that connect input devices such as a keyboard and mouse 2943 combination, a camera 2944, or other USB input devices.

[0424] In at least one embodiment, instances of the memory controller 2916 and the platform controller hub 2930 may be integrated into a discrete external graphics processor, such as the external graphics processor 2912. In at least one embodiment, the platform controller hub 2930 and / or the memory controller 2916 may be external to one or more processors 2902. For example, in at least one embodiment, the system 2900 may include an external memory controller 2916 and a platform controller hub 2930, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2902.

[0425] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10BDetails are provided regarding the inference and / or training logic 1015. In at least one embodiment, some or all of the inference and / or training logic 1015 may be incorporated into the graphics processor 2900. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more ALUs embodied in a 3D pipeline. Additionally, in at least one embodiment, the inference and / or training operations described herein may utilize a number of ALUs other than the ALUs. Figure 10A or Figure 10B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2900 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0426] Figure 30 is a block diagram of a processor 3000 having one or more processor cores 3002A-3002N, an integrated memory controller 3014, and an integrated graphics processor 3008, in accordance with at least one embodiment. In at least one embodiment, the processor 3...

Claims

1. A processor, comprising: One or more circuits for using one or more neural networks to cause one or more robotic devices to perform one or more modifications to the environment based at least in part on a subset of movements to be performed by the one or more robotic devices to perform the one or more modifications to the environment.

2. The processor of claim 1, wherein: The one or more neural networks determine a logic state describing one or more environmental conditions; The one or more environmental conditions are obtained by one or more sensors; The one or more neural networks determine one or more actions to assist in controlling the one or more robotic devices; as well as The one or more actions are determined based at least in part on the logic state. 3 . The processor of claim 2 , wherein the logic state comprises one or more predicates describing the one or more environmental conditions. The processor of claim 2 , wherein the sensor comprises a camera.

5. The processor of claim 2, wherein the one or more actions instruct the one or more robotic devices to change state.

6. The processor of claim 1, wherein the one or more environmental conditions include one or more unexpected events.

7. The processor of claim 2, wherein the one or more neural networks are based at least in part on a temporal convolutional network.

8. A system comprising: One or more circuits for using one or more neural networks to cause one or more robotic devices to perform one or more modifications to the environment based at least in part on a subset of movements to be performed by the one or more robotic devices to perform the one or more modifications to the environment.

9. The system of claim 8, wherein: The one or more robotic devices include mechanical and electrical components that perform the one or more modifications; The one or more neural networks determine one or more environmental conditions; The one or more environmental conditions include observations of the environment; The observations of the environment are obtained from one or more sensors; The one or more neural networks determine a logic state; as well as The one or more neural networks determine one or more actions to assist in controlling the one or more robotic devices.

10. The system of claim 9, wherein the one or more sensors include a camera. The system of claim 9 , wherein the logical state specifies a configuration of the environment.

12. The system of claim 9, wherein the one or more neural networks determine the one or more actions based at least in part on the logic state and the operator.

13. The system of claim 9, wherein the one or more environmental conditions include an unexpected event.

14. The system of claim 8, wherein the one or more modifications include one or more steps to be performed to achieve a goal.

15. The system of claim 8, wherein the one or more neural networks are based at least in part on a convolutional neural network.

16. A non-transitory machine-readable medium having stored thereon a set of instructions that, when executed by one or more processors, cause the one or more processors to at least: One or more neural networks are used to cause one or more robotic devices to perform the one or more modifications to the environment based at least in part on a subset of movements to be performed by the one or more robotic devices to perform the one or more modifications to the environment.

17. The non-transitory machine-readable medium of claim 16, wherein: The one or more neural networks determine a logic state describing one or more environmental conditions; The one or more environmental conditions are obtained by one or more sensors; The one or more neural networks determine one or more actions that, when executed, help control the one or more robotic devices; as well as The one or more actions are determined based at least in part on the logic state and the operator.

18. The non-transitory machine-readable medium of claim 17, wherein the logic state comprises one or more predicates describing the one or more environmental conditions.

19. The non-transitory machine-readable medium of claim 17, wherein the one or more actions instruct the one or more robotic devices to change state.

20. The non-transitory machine-readable medium of claim 17, wherein the operator comprises a condition and an effect.

21. The non-transitory machine-readable medium of claim 17, wherein the one or more environmental conditions include one or more unexpected events.

22. The non-transitory machine-readable medium of claim 16, wherein the one or more neural networks are based at least in part on a temporal convolutional network.

23. The non-transitory machine-readable medium of claim 16, wherein the one or more neural networks generate one or more loss values, the one or more loss values ​​being used to train the one or more neural networks.

24. A method comprising: One or more neural networks are used to cause one or more robotic devices to perform the one or more modifications to the environment based at least in part on a subset of movements to be performed by the one or more robotic devices to perform the one or more modifications to the environment.

25. The method of claim 24, wherein: The one or more neural networks determine a logic state describing one or more environmental conditions; The one or more environmental conditions are obtained by one or more sensors; The one or more neural networks determine one or more actions that, when executed, help control the one or more robotic devices; as well as The one or more actions are determined based at least in part on the logic state and the operator.

26. The method of claim 25, wherein the sensor comprises a hardware and software device that collects information about the one or more environmental conditions.

27. The method of claim 25, wherein the logical state comprises one or more predicates describing the one or more environmental conditions.

28. The method of claim 25, wherein the one or more actions instruct the one or more robotic devices to change state.

29. The method of claim 25, wherein the one or more environmental conditions include an unexpected event.

30. The method of claim 24, wherein the one or more neural networks generate one or more loss values, the one or more loss values ​​being used to train the one or more neural networks.

31. The method of claim 24, wherein the one or more neural networks are based at least in part on a temporal convolutional neural network.

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