Display device

Abstract

A display device is provided. The display device includes a substrate, a pixel structure, a lighting circuit portion, a driver integrated circuit portion, a first lighting line, a second lighting line, and a connecting electrode. The substrate includes a display area and a pad area. The pixel structure is located on the substrate in the display area to emit light. The lighting circuit portion is located on the substrate in the pad area and is electrically connected to the pixel structure. The first lighting line is spaced apart from a first side of the driver integrated circuit portion in a first direction and is connected to the lighting circuit portion. The second lighting line is spaced apart from a second side of the driver integrated circuit portion facing the first side in a second direction opposite to the first direction. The connecting electrode electrically connects the first lighting line and the second lighting line to each other.

Description

Technical Field

[0001] Exemplary embodiments of the present disclosure generally relate to a display device. For example, an embodiment of the present disclosure relates to a display device including a lighting circuit portion. Background Art

[0002] Flat panel display devices are used as display devices to replace cathode ray tube display devices due to their light and thin characteristics. As non-limiting representative examples of such flat panel display devices, there are liquid crystal display devices and organic light emitting diode display devices.

[0003] In the manufacturing process of the display device, an illumination inspection may be performed to inspect the pixel structure included in the display device. In this case, when the display device is an organic light emitting diode display device, the pixel structure may include an anode, an organic light emitting layer located on the anode, a cathode located on the organic light emitting layer, and the like. In addition, in order to perform the illumination inspection, an illumination circuit unit, an illumination line electrically connected to the illumination circuit unit to send an illumination inspection signal, and a connection electrode configured to connect the illumination lines to each other may be provided in the display device. However, in the process of forming the anode by forming a preliminary electrode layer and partially etching the preliminary electrode layer, the etchant used in the etching process may etch a portion of the connection electrode. In other words, undercuts may be generated in the connection electrode due to the etchant. When the insulating layer is located on the partially etched connection electrode, the insulating layer may be cut due to the undercut on the side surface of the connection electrode. In this case, the connection electrode may be exposed to the outside, and the connection electrode exposed to the outside may be corroded. Therefore, the illumination inspection may not be accurately performed. Summary of the invention

[0004] Some example embodiments provide a display device including a lighting circuit portion.

[0005] According to some exemplary embodiments, a display device includes a substrate, a pixel structure, a lighting circuit unit, a driver integrated circuit unit, a first lighting line, a second lighting line, and a connecting electrode. The substrate includes a display area and a pad area. The pixel structure is located on the substrate in the display area to emit light. The lighting circuit unit is located on the substrate in the pad area and is electrically connected to the pixel structure. The driver integrated circuit unit surrounds at least a portion of the lighting circuit unit. The first lighting line is spaced apart from a first side of the driver integrated circuit unit in a first direction and is connected to the lighting circuit unit. The second lighting line is spaced apart from a second side of the driver integrated circuit unit facing the first side in a second direction opposite to the first direction. The connecting electrode electrically connects the first lighting line and the second lighting line to each other.

[0006] In an exemplary embodiment, each of the first lighting line and the second lighting line may not overlap with the driving integrated circuit part.

[0007] In an exemplary embodiment, the driving integrated circuit part may have a rectangular shape including an opening when viewed in a plan view, and the lighting circuit part may be located in the opening.

[0008] In exemplary embodiments, the driving integrated circuit part and the lighting circuit part may be spaced apart from each other.

[0009] In an exemplary embodiment, the substrate may further include a first circuit region, a second circuit region, and an illumination line region. A driver integrated circuit portion having an opening may be located in the first circuit region. An illumination circuit portion located inside the opening of the driver integrated circuit portion may be located in the second circuit region. The illumination line region may be between the first circuit region and the second circuit region, and a first illumination line may be located in the illumination line region.

[0010] In example embodiments, the connection electrode may be located between the substrate and the driving integrated circuit part in the first circuit region.

[0011] In example embodiments, the display device may further include a sensing structure on the pixel structure.

[0012] In an exemplary embodiment, the sensing structure may include a sensing electrode, a first insulating layer on the sensing electrode, and a sensing connection electrode on the first insulating layer.

[0013] In an exemplary embodiment, the sensing electrode and the connection electrode may both include the same material.

[0014] In an exemplary embodiment, the first insulating layer may extend in a direction from the display region to the pad region to cover the sensing electrode in the display region, and may cover the connecting electrode in the pad region.

[0015] In exemplary embodiments, the first insulating layer may directly contact a bottom surface of the driving integrated circuit part and a top surface of the connection electrode in the pad region.

[0016] In an exemplary embodiment, the display device may further include a semiconductor element between the substrate and the pixel structure in the display region.

[0017] In example embodiments, the semiconductor element may include an active layer on a substrate, a gate electrode on the active layer, and a source electrode and a drain electrode on the gate electrode.

[0018] In example embodiments, the first illumination line and the second illumination line may be located on the same layer as the source electrode and the drain electrode, and the first illumination line and the second illumination line may include the same material.

[0019] In example embodiments, the connection electrode may be located on the same layer as the gate electrode and may include the same material as the gate electrode.

[0020] In an exemplary embodiment, the display device may further include a first planarization layer between the substrate and the pixel structure, and a second planarization layer on the first planarization layer.

[0021] In an exemplary embodiment, the first planarization layer may have a first opening formed in a portion of the pad region. The second planarization layer may have a second opening overlapping the first opening. The driving integrated circuit portion may be located inside the first opening and the second opening.

[0022] In an exemplary embodiment, in the pad region, the first contact hole may pass through the first and second planarization layers and expose a portion of the first illumination line, and the second contact hole may pass through the first and second planarization layers and expose a portion of the second illumination line. The connection electrode may be connected to the first illumination line and the second illumination line through the first contact hole and the second contact hole, respectively.

[0023] In exemplary embodiments, the display device may further include an insulating pattern surrounding at least a portion of the connection electrode.

[0024] In example embodiments, the insulating pattern may include the same material as the second planarization layer.

[0025] Since the display device according to the exemplary embodiment of the present disclosure includes the first connection electrode and the second connection electrode formed in parallel (e.g., simultaneously) with the first sensing electrode and the second sensing electrode in the same process, the first connection electrode and the second connection electrode are formed after the lower electrode is formed, so that the etchant used to form the lower electrode may not contact (e.g., physically contact) the first connection electrode and the second connection electrode. For example, in some embodiments, the undercut phenomenon caused by the etchant may not occur in the first connection electrode and the second connection electrode, and the first insulating layer may completely cover the first connection electrode and the second connection electrode, so that the first connection electrode and the second connection electrode are not exposed to the outside. Therefore, the first connection electrode and the second connection electrode are not exposed to the outside, so that the first connection electrode and the second connection electrode may not be corroded, and the lighting inspection of the display device can be accurately performed.

[0026] In some embodiments, the display device includes a first connection electrode and a second connection electrode formed in parallel (e.g., simultaneously) with the first gate electrode or the second gate electrode in the same process, and the first interlayer insulating layer and the second interlayer insulating layer completely cover the first connection electrode and the second connection electrode, so that the etchant used to form the lower electrode may not contact (e.g., physically contact) the first connection electrode and the second connection electrode. For example, in some embodiments, an undercut phenomenon due to the etchant may not occur in the first connection electrode and the second connection electrode, and the first interlayer insulating layer or the second interlayer insulating layer may completely cover the first connection electrode and the second connection electrode, so that the first connection electrode and the second connection electrode are not exposed to the outside. Therefore, the first connection electrode and the second connection electrode are not exposed to the outside, so that the first connection electrode and the second connection electrode may not be corroded.

[0027] In addition, the display device includes the first insulating pattern and the second insulating pattern, so that the etchant used to form the lower electrode may not contact (e.g., physically contact) both sides of each of the first connection electrode and the second connection electrode in the process of forming the lower electrode. For example, since both sides of each of the first connection electrode and the second connection electrode may be etched by the etchant to a relatively large extent, which causes an undercut phenomenon, both sides of each of the first connection electrode and the second connection electrode may be covered with the first insulating pattern and the second insulating pattern, so that the undercut phenomenon can be prevented or reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Exemplary embodiments can be understood in more detail from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 2 It is shown Figure 1 A partial enlarged plan view of the 'A' area;

[0031] Figure 3 is along Figure 1 The line I-I' and Figure 2 A cross-sectional view taken along line II-II';

[0032] Figure 4 Is used to describe Figure 3 A plan view of a sensing structure included in a display device;

[0033] Figure 5 is a cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure;

[0034] Figure 6 It is shown Figure 5 A cross-sectional view of an example of a display device;

[0035] Figure 7 is a partially enlarged plan view showing a display device according to an exemplary embodiment of the present disclosure;

[0036] Figure 8 is along Figure 1 The line I-I' and Figure 7 A cross-sectional view taken along line III-III';

[0037] Fig. 9 is a partially enlarged plan view showing a display device according to an exemplary embodiment of the present disclosure;

[0038] Fig.10 is along Figure 1 The line I-I' and Fig. 9 A cross-sectional view taken along line IV-IV'; and

[0039] Figures 11 to 23 is a view illustrating a method of manufacturing a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] Hereinafter, a display device and a method of manufacturing the display device according to an exemplary embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar reference numerals indicate the same or similar elements.

[0041] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present disclosure, Figure 2 It is shown Figure 1 A partial enlarged plan view of the 'A' area, Figure 3 is along Figure 1 The line I-I' and Figure 2 A cross-sectional view taken along line II-II', and Figure 4 It is shown Figure 3 A plan view of a sensing structure included in a display device.

[0042] refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 The display device 100 may include a substrate 110, a buffer layer 115, a semiconductor element 250, a first lighting line 715, a second lighting line 710, a third lighting line 725, a fourth lighting line 720, a first planarization layer 270, a line pattern 215, a connection pattern 235, a second planarization layer 275, a first connection electrode 730, a second connection electrode 740, a pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, a sensing structure 380, a driving integrated circuit portion 600, a lighting circuit portion 700, a pad electrode 470, etc.

[0043] In some embodiments, the semiconductor element 250 may include an active layer 130, a gate insulating layer 150, a first gate electrode 170, a first interlayer insulating layer 190, a second gate electrode 175, a second interlayer insulating layer 195, a source electrode 210, and a drain electrode 230, and the pixel structure 200 may include a lower electrode 290, an organic light emitting layer 330, and an upper electrode 340. In some embodiments, the thin film encapsulation structure 450 may include a first inorganic thin film encapsulation layer 451, an organic thin film encapsulation layer 452, and a second inorganic thin film encapsulation layer 453, and as Figure 3 and Figure 4 As shown in , the sensing structure 380 may include an insulating layer 381, a first sensing electrode 382, ​​a second sensing electrode 384, a first insulating layer 395, a sensing connection electrode 386, and a second insulating layer 398. The display device 100 may also include a display area 10 and a pad area 60. In some embodiments, the display area 10 may include a plurality of pixel areas 30, and as shown in FIG. Figure 1 and Fig.12 As shown in , the pad region 60 may include a first circuit region 80, a second circuit region 70, and an illumination line region 90. In an exemplary embodiment, the first circuit region 80 may surround at least a portion of the second circuit region 70. For example, the first circuit region 80 may substantially surround the second circuit region 70 and the illumination line region 90, and the illumination line region 90 may substantially surround the second circuit region 70. In an exemplary embodiment, the first planarization layer 270 and the second planarization layer 275 may include a first contact hole 732, a second contact hole 731, a third contact hole 742, and a fourth contact hole 741. For example, as Figure 2 and Figure 3 As shown in , the first contact hole 732 and the third contact hole 742 may be formed in the first planarization layer 270 and the second planarization layer 275 positioned in the illumination line region 90, and the second contact hole 731 and the fourth contact hole 741 may be formed in the first planarization layer 270 and the second planarization layer 275 positioned in the pad region 60.

[0044] Reference again Figure 1 , Figure 2 and Figure 3 , the pixel structure 200 may be located in each of the pixel regions 30, and light may be emitted from the organic light emitting layer 330. An image may be displayed in the display region 10 through the pixel structure 200.

[0045] The pad electrode 470 may be located on one side of the pad region 60, and the pad electrodes 470 may be spaced apart from each other in a first direction D1 (or a second direction D2 opposite to the first direction D1) parallel (e.g., substantially parallel) to the top surface of the display device 100. In some embodiments, the pad electrode 470 may be electrically coupled to an external device that generates a plurality of pixel signals (e.g., gate signals, data signals, emission control signals, gate initialization signals, power supply voltages, etc.), and the pad electrode 470 may be electrically coupled to the driver integrated circuit portion 600. The driver integrated circuit portion 600 may also be electrically coupled to the pixel structure 200, and a pixel signal (e.g., a data signal) may be provided to the pixel structure 200 through the pad electrode 470 and the driver integrated circuit portion 600.

[0046] The lighting circuit portion 700 may be located in the second circuit region 70. For example, the lighting circuit portion 700 may be spaced apart from the pad electrode 470 in a third direction D3 that is perpendicular (e.g., substantially perpendicular) to the first direction D1 and the second direction D2. The lighting circuit portion 700 may include a lighting semiconductor element, and may be coupled to the first lighting line 715 and the third lighting line 725. For example, in some embodiments, some of the semiconductor elements may be directly coupled to the first lighting line 715 and the third lighting line 725. In some embodiments, the lighting circuit portion 700 may be electrically coupled to the pixel structure 200.

[0047] The driver integrated circuit portion 600 may be located in the first circuit area 80. The driver integrated circuit portion 600 may surround at least a portion of the lighting circuit portion 700. In an exemplary embodiment, the driver integrated circuit portion 600 may substantially surround the lighting circuit portion 700 and may be spaced apart from the outer periphery of the lighting circuit portion 700. For example, in some embodiments, the lighting circuit portion 700 may be located in an opening defined by the driver integrated circuit portion 600. In some embodiments, the interval space between the lighting circuit portion 700 and the driver integrated circuit portion 600 may be defined as an illumination line area 90. For example, in some embodiments, the driver integrated circuit portion 600 may have a rectangular shape including an opening, and the lighting circuit portion 700 may be located in the opening, but the present disclosure is not limited thereto. The driver integrated circuit portion 600 may include a driving semiconductor element, a driving capacitor, etc., and may receive an input signal (e.g., a data signal) and a driving power from an external device. The driver integrated circuit portion 600 may provide an output signal to the pixel structure 200 based on the input signal. Therefore, the driver integrated circuit portion 600 may control the driving of the pixel structure 200.

[0048] The first lighting wire 715 and the third lighting wire 725 may be located in the lighting wire area 90. A first end of the first lighting wire 715 may be coupled to the lighting circuit portion 700, and a second end of the first lighting wire 715 opposite to the first end may overlap with the first contact hole 732. In some embodiments, a first end of the third lighting wire 725 may be coupled to the lighting circuit portion 700, and a second end of the third lighting wire 725 opposite to the first end may overlap with the third contact hole 742.

[0049] The second illumination line 710 and the fourth illumination line 720 may be adjacent to the first illumination line 715 and the third illumination line 725 in the pad region 60. A first end of the second illumination line 710 may overlap with the second contact hole 731, and a second end of the second illumination line 710 opposite to the first end may be coupled to one of the pad electrodes 470. In some embodiments, a first end of the fourth illumination line 720 may overlap with the fourth contact hole 741, and a second end of the fourth illumination line 720 opposite to the first end may be coupled to another of the pad electrodes 470.

[0050] Each of the first connection electrode 730 and the second connection electrode 740 may be located in a portion of the pad region 60, a portion of the first circuit region 80, and a portion of the illumination line region 90. In an exemplary embodiment, each of the first connection electrode 730 and the second connection electrode 740 may be located below the driver integrated circuit portion 600 to overlap with a portion of the driver integrated circuit portion 600. For example, a first end of the first connection electrode 730 may be coupled to the first illumination line 715 through a first contact hole 732, and a second end of the first connection electrode 730 opposite to the first end may be coupled to the second illumination line 710 through a second contact hole 731. In some embodiments, the first connection electrode 730 may couple the first illumination line 715 to the second illumination line 710. In some embodiments, a first end of the second connection electrode 740 may be coupled to the third illumination line 725 through a third contact hole 742, and a second end of the second connection electrode 740 opposite to the first end may be coupled to the fourth illumination line 720 through a fourth contact hole 741. For example, in some embodiments, the second connection electrode 740 may couple the third illumination line 725 to the fourth illumination line 720.

[0051] For example, an illumination gate signal applied to a gate electrode of a semiconductor element included in the illumination circuit portion 700 may be provided to the second illumination line 710. In some embodiments, an illumination emission voltage applied to a source electrode of the semiconductor element may be provided to the fourth illumination line 720. In some embodiments, when the illumination gate signal is applied to the gate electrode through the second illumination line 710, the first connection electrode 730, and the first illumination line 715, the illumination emission voltage may be applied to the pixel structure 200 through the fourth illumination line 720, the second connection electrode 740, the third illumination line 725, and the source and drain electrodes of the semiconductor element, and light may be emitted from the organic light emitting layer 330 of the pixel structure 200. Through this process, illumination inspection of the pixel structure 200 may be performed.

[0052] Although it has been described that one lighting emission voltage and one lighting gate signal are provided to the lighting circuit section 700 according to the embodiment of the present disclosure, the configuration of the embodiment of the present disclosure is not limited thereto. For example, the display device 100 may further include an additional lighting line connected to the lighting circuit section 700, and may provide a lighting emission voltage and an additional lighting gate signal having different voltage levels.

[0053] In some embodiments, although for convenience, the first lighting line 715, the second lighting line 710, the third lighting line 725 and the fourth lighting line 720 and the first connection electrode 730 and the second connection electrode 740 are Figure 2 700 , but the first lighting line 715 , the second lighting line 710 , the third lighting line 725 , and the fourth lighting line 720 and the first connection electrode 730 and the second connection electrode 740 may be symmetrically arranged on the right side of the lighting circuit portion 700 .

[0054] Reference again Figure 3 , a substrate 110 including a transparent or opaque material may be provided. The substrate 110 may be a flexible transparent resin substrate. For example, the substrate 110 may have a configuration in which a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer are sequentially stacked. The first barrier layer and the second barrier layer may include an inorganic material such as, for example, silicon oxide, and may prevent or reduce the penetration of water and / or moisture through the first organic layer and the second organic layer. In some embodiments, the first organic layer and the second organic layer may include an organic insulating material such as, for example, a polyimide-based resin, and may be flexible.

[0055] Since the substrate 110 is thin and flexible, the substrate 110 can be formed on a rigid glass substrate to support the formation of the semiconductor element 250, the pixel structure 200, the thin film encapsulation structure 450, etc. For example, after the buffer layer 115 is arranged on the second barrier layer, an upper structure (e.g., a semiconductor element 250, a pixel structure 200, a thin film encapsulation structure 450, etc.) can be formed on the buffer layer 115. After the upper structure is formed, the glass substrate can be removed. For example, in some embodiments, due to the flexible physical properties of the substrate 110, it may be difficult to form the upper structure directly on the substrate 110. In view of this situation, the upper structure can be formed by using a rigid glass substrate, and then the glass substrate is removed, so that the first organic layer, the first barrier layer, the second organic layer, and the second barrier layer can be used as the substrate 110.

[0056] The display device 100 includes a display area 10 including a pixel area 30 and a pad area 60 including a first circuit area 80, an illumination line area 90 and a second circuit area 70, so that the substrate 110 can also be divided into a display area 10 including a pixel area 30 and a pad area 60 including a first circuit area 80, a second circuit area 70 and an illumination line area 90.

[0057] In some embodiments, the substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (F-doped quartz substrate), a soda-lime glass substrate, a non-alkali glass substrate, or the like.

[0058] Although the substrate 110 has been described as having four layers, the configuration of the embodiments of the present disclosure is not limited thereto. For example, in some exemplary embodiments, the substrate 110 may include a single layer or multiple layers.

[0059] The buffer layer 115 may be located on the substrate 110. For example, the buffer layer 115 may be located over the entire display region 10 and the pad region 60 on the substrate 110. The buffer layer 115 may prevent or reduce diffusion of metal atoms or impurities from the substrate 110 to the semiconductor element 250, and may control a heat transfer rate (e.g., may reduce a heat transfer rate) during a crystallization process for forming the active layer 130 to obtain a substantially uniform active layer 130. In some embodiments, when the surface of the substrate 110 is uneven, the buffer layer 115 may be used to improve the flatness of the surface of the substrate 110 (e.g., the buffer layer 115 may flatten the surface of the substrate 110). Depending on the type or composition of the substrate 110, at least two buffer layers 115 may be disposed on the substrate 110, or the buffer layer 115 may not be disposed (e.g., the buffer layer 115 may be omitted). The buffer layer 115 may include a silicon compound, a metal oxide, or the like.

[0060] The active layer 130 may be located in the display region 10 (or the pixel region 30) on the buffer layer 115. The active layer 130 may include a metal oxide semiconductor, an inorganic semiconductor (e.g., an amorphous silicon semiconductor or a polycrystalline silicon semiconductor), an organic semiconductor, etc. The active layer 130 may have a source region, a drain region, and a channel region located between the source region and the drain region.

[0061] The gate insulating layer 150 may be located on the active layer 130. The gate insulating layer 150 may cover the active layer 130 in the display region 10 on the buffer layer 115, and may extend in a fourth direction D4 (e.g., a direction opposite to the third direction D3), which is a direction extending from the display region 10 to the pad region 60. In some embodiments, the gate insulating layer 150 may be located above the entire display region 10 and the pad region 60 on the buffer layer 115. For example, the gate insulating layer 150 may appropriately or sufficiently cover the active layer 130 on the buffer layer 115, and may have a substantially flat top surface without (or substantially without) generating steps around the active layer 130. In some embodiments, the gate insulating layer 150 may be disposed along the contour of the active layer 130 with a uniform (e.g., substantially uniform) thickness to cover the active layer 130 on the buffer layer 115. The gate insulating layer 150 may include a silicon compound, a metal oxide, or the like. In some exemplary embodiments, the gate insulating layer 150 may have a multi-layer structure including a plurality of insulating layers. The plurality of insulating layers may include materials different from each other and may have thicknesses different from each other.

[0062] The first gate electrode 170 may be located in the display area 10 on the gate insulating layer 150. The first gate electrode 170 may be located at a portion of the active layer 130 disposed below the gate insulating layer 150 (e.g., to overlap with the channel region of the active layer 130). The first gate electrode 170 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other. In some exemplary embodiments, the first gate electrode 170 may have a multilayer structure including a plurality of metal layers. The plurality of metal layers may include materials different from each other and may have thicknesses different from each other.

[0063] The first interlayer insulating layer 190 may be located on the first gate electrode 170. The first interlayer insulating layer 190 may cover the first gate electrode 170 in the display region 10 on the gate insulating layer 150, and may extend in the fourth direction D4. In some embodiments, the first interlayer insulating layer 190 may be located above the entire display region 10 and the pad region 60 on the gate insulating layer 150. For example, the first interlayer insulating layer 190 may appropriately or sufficiently cover the first gate electrode 170 on the gate insulating layer 150, and may have a substantially flat top surface without (or substantially without) generating a step around the first gate electrode 170. In some embodiments, the first interlayer insulating layer 190 may be disposed along the contour of the first gate electrode 170 with a uniform (e.g., substantially uniform) thickness to cover the first gate electrode 170 on the gate insulating layer 150. The first interlayer insulating layer 190 may include a silicon compound, a metal oxide, etc. In some exemplary embodiments, the first interlayer insulating layer 190 may have a multilayer structure including a plurality of insulating layers. The plurality of insulating layers may include materials different from each other and may have thicknesses different from each other.

[0064] The second gate electrode 175 may be located in the display area 10 on the first interlayer insulating layer 190. The second gate electrode 175 may be located at a portion of the first interlayer insulating layer 190 where the first gate electrode 170 is disposed. In some embodiments, the first gate electrode 170 and the second gate electrode 175 may be used as a capacitor. The second gate electrode 175 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other. In some exemplary embodiments, the second gate electrode 175 may have a multilayer structure including a plurality of metal layers. The plurality of metal layers may include materials different from each other and may have thicknesses different from each other.

[0065] The second interlayer insulating layer 195 may be located on the second gate electrode 175. The second interlayer insulating layer 195 may cover the second gate electrode 175 in the display region 10 on the first interlayer insulating layer 190, and may extend in the fourth direction D4. In some embodiments, the second interlayer insulating layer 195 may be located above the entire display region 10 and the pad region 60 on the first interlayer insulating layer 190. For example, the second interlayer insulating layer 195 may appropriately or sufficiently cover the second gate electrode 175 on the first interlayer insulating layer 190, and may have a substantially flat top surface without (or substantially without) generating a step around the second gate electrode 175. In some embodiments, the second interlayer insulating layer 195 may be disposed along the contour of the second gate electrode 175 with a uniform (e.g., substantially uniform) thickness to cover the second gate electrode 175 on the first interlayer insulating layer 190. The second interlayer insulating layer 195 may include a silicon compound, a metal oxide, etc. In some exemplary embodiments, the second interlayer insulating layer 195 may have a multilayer structure including a plurality of insulating layers. The plurality of insulating layers may include materials different from each other and may have thicknesses different from each other.

[0066] The source electrode 210 and the drain electrode 230 may be located in the display area 10 on the second interlayer insulating layer 195. The source electrode 210 may be coupled to the source region of the active layer 130 through a contact hole formed by removing a first portion of the gate insulating layer 150, a first portion of the first interlayer insulating layer 190, and a first portion of the second interlayer insulating layer 195, and the drain electrode 230 may be coupled to the drain region of the active layer 130 through a contact hole formed by removing a second portion of the gate insulating layer 150, a second portion of the first interlayer insulating layer 190, and a second portion of the second interlayer insulating layer 195. Each of the source electrode 210 and the drain electrode 230 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. The foregoing materials may be used alone or in combination with each other. In some exemplary embodiments, each of the source electrode 210 and the drain electrode 230 may have a multilayer structure including a plurality of metal layers. The plurality of metal layers may include materials different from each other and may have thicknesses different from each other.

[0067] Therefore, a semiconductor element 250 can be set, which includes an active layer 130, a gate insulating layer 150, a first gate electrode 170, a first interlayer insulating layer 190, a second gate electrode 175, a second interlayer insulating layer 195, a source electrode 210 and a drain electrode 230, and is located between the substrate 110 and the pixel structure 200 in the display area 10.

[0068] Although the semiconductor element 250 has been described as having a top gate structure, the configuration of the embodiments of the present disclosure is not limited thereto. For example, the semiconductor element 250 may have a bottom gate structure.

[0069] In addition, although the display device 100 has been described as including one semiconductor element, the configuration of the embodiment of the present disclosure is not limited thereto. For example, the display device 100 may include at least one semiconductor element and at least one capacitor.

[0070] refer to Figure 2 and Figure 3 , the first lighting line 715 may be located in the lighting line area 90 on the second interlayer insulating layer 195. The first lighting line 715 may be spaced apart from the first side of the driver integrated circuit portion 600 in the first direction D1, and may extend in the first direction D1 so as to be connected to the lighting circuit portion 700. In an exemplary embodiment, the first lighting line 715 may not overlap the driver integrated circuit portion 600. The first lighting line 715 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other. In some exemplary embodiments, the first lighting line 715 may have a multilayer structure including a plurality of metal layers. The plurality of metal layers may include materials different from each other and may have thicknesses different from each other.

[0071] The second illumination line 710 may be located in the pad region 60 on the second interlayer insulating layer 195. The second illumination line 710 may be spaced apart from the second side of the driver integrated circuit portion 600 opposite to the first side in the second direction D2, and may extend in the second direction D2 and the fourth direction D4 to be connected to the pad electrode 470. In an exemplary embodiment, the second illumination line 710 may not overlap the driver integrated circuit portion 600. The second illumination line 710 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other. In some exemplary embodiments, the second illumination line 710 may have a multilayer structure including a plurality of metal layers. The plurality of metal layers may include materials different from each other and may have thicknesses different from each other.

[0072] In an exemplary embodiment, the source electrode 210, the drain electrode 230, the first illumination line 715, the second illumination line 710, the third illumination line 725, and the fourth illumination line 720 may be located on the same layer and may include the same (e.g., substantially the same) material. For example, each of the source electrode 210, the drain electrode 230, the first illumination line 715, the second illumination line 710, the third illumination line 725, and the fourth illumination line 720 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum alloy, aluminum nitride (AlN), or the like. x), silver-containing alloys, tungsten nitride (WN x ), copper-containing alloys, molybdenum-containing alloys, titanium nitride (TiN x ), chromium nitride (CrN x ), tantalum nitride (TaN x ), strontium ruthenium oxide (SrRu x O y ), zinc oxide (ZnO x ), indium tin oxide (ITO), tin oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ), indium zinc oxide (IZO), etc.

[0073] In some exemplary embodiments, the protective insulating layer may be located on the second interlayer insulating layer 195, the source and drain electrodes 210 and 230, the first, second, third, and fourth illumination lines 715, 710, 725, and 720. The protective insulating layer may cover the source and drain electrodes 210 and 230 in the display region 10 on the second interlayer insulating layer 195, and may cover the first, second, third, and fourth illumination lines 715, 710, 725, and 720 in the pad region 60 on the second interlayer insulating layer 195. In exemplary embodiments, the protective insulating layer may include an inorganic insulating material.

[0074] The first planarization layer 270 may be located on the second interlayer insulating layer 195, the source electrode 210 and the drain electrode 230, and the first, second, third, and fourth illumination lines 715, 710, 725, and 720. The first planarization layer 270 may be located in a portion of the pad region 60 on the second interlayer insulating layer 195 and in the display region 10. In some embodiments, the first planarization layer 270 may extend in the fourth direction D4 to cover the source electrode 210 and the drain electrode 230 in the display region 10 on the second interlayer insulating layer 195, and may cover the first, second, third, and fourth illumination lines 715, 710, 725, and 720 in the pad region 60. In addition, the first planarization layer 270 may include a first opening 274 that exposes a top surface of the second interlayer insulating layer 195 located in the first circuit region 80.

[0075] The first planarization layer 270 may have a relatively thick thickness. In some embodiments, the first planarization layer 270 may have a substantially flat top surface. In order to achieve such a flat top surface of the first planarization layer 270, a planarization process may be additionally performed on the first planarization layer 270. In some embodiments, the first planarization layer 270 may be arranged on the second interlayer insulating layer 195 with a uniform (e.g., substantially uniform) thickness along the contours of the source electrode 210 and the drain electrode 230 and the first illumination line 715, the second illumination line 710, the third illumination line 725, and the fourth illumination line 720. The first planarization layer 270 may be formed of an organic insulating material and / or an inorganic insulating material. In an exemplary embodiment, the first planarization layer 270 may include an organic insulating material. For example, the first planarization layer 270 may include a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, etc.

[0076] The line pattern 215 and the connection pattern 235 may be located in the display region 10 on the first planarization layer 270. The line pattern 215 may transmit a gate signal, a data signal, an emission control signal, a gate initialization signal, a power supply voltage, etc. The connection pattern 235 may be located in the display region 10 on the first planarization layer 270 while being spaced apart from the line pattern 215. The connection pattern 235 may be coupled to the drain electrode 230 through a contact hole formed by removing a portion of the first planarization layer 270 located in the display region 10, and the connection pattern 235 may electrically couple the lower electrode 290 to the drain electrode 230. In some embodiments, the connection pattern 235 may not be coupled to the drain electrode 230, and when viewed in another cross-sectional view of the display device 100, the connection pattern 235 may electrically couple the semiconductor element 250 to another semiconductor element through the contact hole. Each of the line pattern 215 and the connection pattern 235 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other. In some exemplary embodiments, each of the line pattern 215 and the connection pattern 235 may have a multi-layer structure including a plurality of metal layers. The plurality of metal layers may include materials different from each other and may have thicknesses different from each other.

[0077] The second planarization layer 275 may be located on the line pattern 215, the connection pattern 235, and the first planarization layer 270. The second planarization layer 275 may be located in a portion of the pad region 60 on the first planarization layer 270 and in the display region 10. For example, the second planarization layer 275 may extend in the fourth direction D4 to cover the line pattern 215 and the connection pattern 235 in the display region 10 on the first planarization layer 270, and may be located on the first planarization layer 270 in the pad region 60. In some embodiments, the second planarization layer 275 may include a second opening 279 that exposes a top surface of the second interlayer insulating layer 195 located in the first circuit region 80.

[0078] The second planarization layer 275 may have a relatively thick thickness. In this case, the second planarization layer 275 may have a substantially flat top surface. In order to achieve such a flat top surface of the second planarization layer 275, a planarization process may be additionally performed on the second planarization layer 275. In some embodiments, the second planarization layer 275 may be disposed on the first planarization layer 270 along the contours of the line pattern 215 and the connection pattern 235 with a uniform (e.g., substantially uniform) thickness. The second planarization layer 275 may be formed of an organic insulating material and / or an inorganic insulating material. In an exemplary embodiment, the second planarization layer 275 may include an organic insulating material.

[0079] The lower electrode 290 may be located in the display area 10 on the second planarization layer 275. The lower electrode 290 may be coupled to the connection pattern 235 through a contact hole formed by removing a portion of the second planarization layer 275, and the lower electrode 290 may be electrically coupled to the semiconductor element 250. The lower electrode 290 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The aforementioned materials may be used alone or in combination with each other. In some exemplary embodiments, the lower electrode 290 may have a multilayer structure including a plurality of metal layers. The plurality of metal layers may include materials different from each other and may have thicknesses different from each other.

[0080] The pixel defining layer 310 may be located in the display region 10 on the second planarization layer 275. In some embodiments, the pixel defining layer 310 may not be located in the pad region 60. The pixel defining layer 310 may expose a portion of the lower electrode 290 in the display region 10. The pixel defining layer 310 may be formed of an organic insulating material and / or an inorganic insulating material. In an exemplary embodiment, the pixel defining layer 310 may include an organic insulating material.

[0081] The organic light emitting layer 330 may be located on the lower electrode 290. The organic light emitting layer 330 may be formed by using at least one of a plurality of light emitting materials for emitting light of different colors (e.g., red light, green light, blue light, etc.) according to pixels. In some embodiments, the organic light emitting layer 330 may be formed by stacking a plurality of light emitting materials for generating light of different colors such as red light, green light, and blue light to emit white light as a whole. In this case, a color filter may be located on the organic light emitting layer 330 on the lower electrode 290. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. In some embodiments, the color filter may include a yellow color filter, a cyan color filter, and / or a magenta color filter. The color filter may include a photosensitive resin and / or a color photoresist.

[0082] The upper electrode 340 may be located above the entire display area 10 on the substrate 110. The upper electrode 340 may be arranged along the contours of the organic light-emitting layer 330 and the pixel defining layer 310. The upper electrode 340 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The aforementioned materials may be used alone or in combination with each other. In some exemplary embodiments, the upper electrode 340 may have a multilayer structure including a plurality of metal layers. The plurality of metal layers may include materials different from each other and may have thicknesses different from each other.

[0083] Thus, the pixel structure 200 including the lower electrode 290 , the organic light emitting layer 330 , and the upper electrode 340 may be provided.

[0084] The first inorganic thin film encapsulation layer 451 may be located in the display region 10 on the upper electrode 340. For example, the first inorganic thin film encapsulation layer 451 may be disposed along the contour of the upper electrode 340 in the display region 10. The first inorganic thin film encapsulation layer 451 may prevent or reduce degradation of the pixel structure 200 due to penetration of moisture, oxygen, etc. In addition, the first inorganic thin film encapsulation layer 451 may be used to protect the pixel structure 200 from external impact. The first inorganic thin film encapsulation layer 451 may include an inorganic insulating material having flexibility.

[0085] The organic thin film encapsulation layer 452 may be located in the display region 10 on the first inorganic thin film encapsulation layer 451. The organic thin film encapsulation layer 452 may improve the flatness of the display device 100 and may protect the pixel structure 200 together with the first inorganic thin film encapsulation layer 451. The organic thin film encapsulation layer 452 may include an organic insulating material having flexibility.

[0086] The second inorganic thin film encapsulation layer 453 may be located on the organic thin film encapsulation layer 452. The second inorganic thin film encapsulation layer 453 may be disposed along the contour of the organic thin film encapsulation layer 452 with a uniform (e.g., substantially uniform) thickness to cover the organic thin film encapsulation layer 452 in the display area 10. The second inorganic thin film encapsulation layer 453 may prevent or reduce the degradation of the pixel structure 200 due to the penetration of moisture, oxygen, etc. together with the first inorganic thin film encapsulation layer 451. In some embodiments, the second inorganic thin film encapsulation layer 453 may be used together with the first inorganic thin film encapsulation layer 451 and the organic thin film encapsulation layer 452 to protect the pixel structure 200 from external impact. The second inorganic thin film encapsulation layer 453 may include an inorganic insulating material having flexibility.

[0087] Thus, a thin film encapsulation structure 450 including a first inorganic thin film encapsulation layer 451, an organic thin film encapsulation layer 452, and a second inorganic thin film encapsulation layer 453 may be provided. In some embodiments, the thin film encapsulation structure 450 may have a five-layer structure in which the first to fifth thin film encapsulation layers are stacked or a seven-layer structure in which the first to seventh thin film encapsulation layers are stacked.

[0088] Reference again Figure 3 and Figure 4 , the insulating layer 381 may be located on the second inorganic thin film encapsulation layer 453, the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195. The insulating layer 381 may be located on the second inorganic thin film encapsulation layer 453 in the display region 10, and may extend in the fourth direction D4 to be disposed along the contours of the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195 in the pad region 60. For example, in some embodiments, the insulating layer 381 may be located over the entire display region 10 and the pad region 60 on the substrate 110. For example, the insulating layer 381 may be disposed on the second inorganic thin film encapsulation layer 453, the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195 with a uniform (e.g., substantially uniform) thickness along the contours of the second inorganic thin film encapsulation layer 453, the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195.

[0089] In an exemplary embodiment, in the first circuit region 80, the top surface of the insulating layer 381 may be in direct contact (e.g., physical contact) with the first connection electrode 730, and the bottom surface of the insulating layer 381 may be in direct contact (e.g., physical contact) with the second interlayer insulating layer 195. The insulating layer 381 may include a silicon compound, a metal oxide, etc. In some exemplary embodiments, the insulating layer 381 may have a multilayer structure including a plurality of insulating layers. The plurality of insulating layers may include materials different from each other and may have thicknesses different from each other.

[0090] The insulating layer 381 may be provided on the thin film encapsulation structure 450, or may not be provided, depending on the type or composition of the insulating layer 381. When the insulating layer 381 is not provided, the first sensing electrode 382 and the second sensing electrode 384 may be directly formed on (e.g., in physical contact with) the thin film encapsulation structure 450. In this case, the bottom surface of the first connection electrode 730 and the bottom surface of the second connection electrode 740 may be in direct contact with (e.g., in physical contact with) the second interlayer insulating layer 195 in the first circuit region 80.

[0091] The first sensing electrode 382 and the second sensing electrode 384 may be located in the display area 10 on the insulating layer 381. Each of the first sensing electrodes 382 may extend in the third direction D3 (or the fourth direction D4), and the first sensing electrodes 382 may be spaced apart from each other in the first direction D1 (or the second direction D2). The second sensing electrode 384 may be located between two adjacent first sensing electrodes 382 among the first sensing electrodes 382, ​​while being spaced apart from each other in the third direction D3. For example, each of the first sensing electrode 382 and the second sensing electrode 384 may include a carbon nanotube (CNT), a transparent conductive oxide (such as ZnO x 、ITO、SnO x 、InO x 、GaO x , IZO and / or indium gallium zinc oxide (IGZO)), graphene, silver nanowire (Ag nanowire; AgNW), Cu, Cr, etc.

[0092] The first connection electrode 730 and the second connection electrode 740 may be on the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195 located in the pad region 60 while being spaced apart from each other. Each of the first connection electrode 730 and the second connection electrode 740 may be disposed along the contours of the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195 in the pad region 60, and may be located between the driving integrated circuit portion 600 and the substrate 110 (or the insulating layer 381) in the first circuit region 80. As described above, when the insulating layer 381 is not provided, each of the first connection electrode 730 and the second connection electrode 740 may be in direct contact (e.g., in physical contact) with the second interlayer insulating layer 195. The first connection electrode 730 may be coupled to the first illumination line 715 and the second illumination line 710 through the first contact hole 732 and the second contact hole 731 formed in the first planarization layer 270 and the second planarization layer 275, respectively. For example, in some embodiments, the first connection electrode 730 may electrically couple the first lighting line 715 to the second lighting line 710. In addition, the second connection electrode 740 may be respectively coupled to the third lighting line 725 and the fourth lighting line 720 through the third contact hole 742 and the fourth contact hole 741 formed in the first planarization layer 270 and the second planarization layer 275. For example, in some embodiments, the second connection electrode 740 may electrically couple the third lighting line 725 to the fourth lighting line 720.

[0093] Each of the first connection electrode 730 and the second connection electrode 740 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The aforementioned materials may be used alone or in combination with each other. In some exemplary embodiments, each of the first connection electrode 730 and the second connection electrode 740 may have a multilayer structure including a plurality of metal layers. The plurality of metal layers may include materials different from each other and may have thicknesses different from each other.

[0094] In an exemplary embodiment, the first sensing electrode 382 , the second sensing electrode 384 , the first connection electrode 730 , and the second connection electrode 740 may include the same (eg, substantially the same) material.

[0095] For example, in order to perform lighting inspection, there may be a lighting circuit unit 700, a lighting line electrically connected to the lighting circuit unit 700 to send a lighting inspection signal, and a connecting electrode configured to connect the lighting lines to each other in an existing display device. In an existing display device, the connecting electrode configured to connect the lighting lines to each other is formed in parallel (e.g., simultaneously) with the line pattern 215 and the connecting pattern 235 in the same process. In some embodiments, in the process of forming the lower electrode 290 by forming a preliminary electrode layer and partially etching the preliminary electrode layer, the etchant used in the etching process may etch a portion of the connecting electrode. For example, in some embodiments, undercuts may be generated in the connecting electrode due to the etchant. When the insulating layer is located on the partially etched connecting electrode, the insulating layer may be cut due to the undercut on the side surface of the connecting electrode. In this case, the connecting electrode may be exposed to the outside, and the connecting electrode exposed to the outside may be corroded. Therefore, the lighting inspection may not be accurately performed.

[0096] In the exemplary embodiment of the present disclosure, since the first connection electrode 730 and the second connection electrode 740 are formed in parallel (e.g., simultaneously) with the first sensing electrode 382 and the second sensing electrode 384 in the same process, the first connection electrode 730 and the second connection electrode 740 are formed after the lower electrode 290, so that the first sensing electrode 382 and the second sensing electrode 384 may not be in contact (e.g., physically in contact) with the etchant used to form the lower electrode 290. Therefore, an undercut phenomenon due to the etchant may not occur in the first connection electrode 730 and the second connection electrode 740, and the first insulating layer 395 may completely cover the first connection electrode 730 and the second connection electrode 740.

[0097] The first insulating layer 395 may be located on the insulating layer 381, the first sensing electrode 382, ​​the second sensing electrode 384, the first connection electrode 730, and the second connection electrode 740. The first insulating layer 395 may cover the first sensing electrode 382 and the second sensing electrode 384 in the display area 10 on the insulating layer 381, and may extend in the fourth direction D4 to cover the first connection electrode 730 and the second connection electrode 740 in the pad area 60 on the insulating layer 381. For example, in some embodiments, the first insulating layer 395 may be located over the entire display area 10 and the pad area 60 on the insulating layer 381. For example, the first insulating layer 395 may be disposed along the contours of the first sensing electrode 382 and the second sensing electrode 384 and the first connection electrode 730 and the second connection electrode 740 with a uniform (e.g., substantially uniform) thickness to cover the first sensing electrode 382 and the second sensing electrode 384 and the first connection electrode 730 and the second connection electrode 740 on the insulating layer 381. In some embodiments, the first insulating layer 395 may appropriately or sufficiently cover the first sensing electrode 382 and the second sensing electrode 384 and the first connection electrode 730 and the second connection electrode 740 on the insulating layer 381, and may have a substantially flat top surface without (or substantially without) generating steps around the first sensing electrode 382 and the second sensing electrode 384 and the first connection electrode 730 and the second connection electrode 740. In an exemplary embodiment, the first insulating layer 395 may be in direct contact (e.g., physical contact) with the bottom surface of the driving integrated circuit portion 600, the top surface of the first connection electrode 730, and the top surface of the second connection electrode 740 in the pad region 60. The first insulating layer 395 may include a silicon compound, a metal oxide, or the like. For example, the first insulating layer 395 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon carbide oxide (SiO x C y ), Silicon Carbon Nitride (SiC x N y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), titanium oxide (TiO x ) etc. In some exemplary embodiments, the first insulating layer 395 may have a multilayer structure including a plurality of insulating layers. The plurality of insulating layers may include materials different from each other and may have thicknesses different from each other.

[0098] The sensing connection electrodes 386 may be located in the display region 10 on the first insulating layer 395. Each of the sensing connection electrodes 386 may electrically connect two second sensing electrodes 384 adjacent to each other in the first direction D1 among the second sensing electrodes 384 through a contact hole formed by removing a portion of the first insulating layer 395. For example, the sensing connection electrodes 386 may include the same (e.g., substantially the same) material as the first sensing electrodes 382 and the second sensing electrodes 384.

[0099] The second insulating layer 398 may be located on the first insulating layer 395 and the sensing connection electrode 386. The second insulating layer 398 may cover the sensing connection electrode 386 in the display area 10 on the first insulating layer 395, and may not be located in the pad area 60. The second insulating layer 398 may include an organic insulating material or an inorganic insulating material. In some exemplary embodiments, the second insulating layer 398 may be formed in the pad area 60.

[0100] Thus, a sensing structure 380 including an insulating layer 381 , a first sensing electrode 382 , a second sensing electrode 384 , a first insulating layer 395 , a sensing connection electrode 386 , and a second insulating layer 398 may be provided.

[0101] For example, the sensing structure 380 may be substantially transparent. Light emitted from the organic light emitting layer 330 may pass through the sensing structure 380. In addition, the sensing structure 380 may sense a portion of a user's body, an object, etc. located above the top surface of the display device 100 through the first sensing electrode 382, ​​the second sensing electrode 384, and the sensing connection electrode 386. For example, in some embodiments, an external device may generate a sensing signal, and the sensing signal generated from the external device may be transmitted to the first sensing electrode 382, ​​the second sensing electrode 384, and the sensing connection electrode 386. The external device may receive the sensing signal transmitted to the first sensing electrode 382, ​​the second sensing electrode 384, and the sensing connection electrode 386 to sense a portion of a user's body, an object, etc. located above the front surface of the display device 100. In an exemplary embodiment, the first sensing electrode 382 and the second sensing electrode 384 may include a proximity sensor electrode for sensing the proximity of a user and / or an object relative to the top surface of the display device 100, or a touch sensor electrode for sensing a touch of a portion of the user's body.

[0102] The driving integrated circuit portion 600 may be located in the first circuit region 80 on the first insulating layer 395. In an exemplary embodiment, the driving integrated circuit portion 600 may be located inside the first opening 274 and the second opening 279. A first side of the driving integrated circuit portion 600 (e.g., a portion of an inner side surface of the driving integrated circuit portion 600) and the first lighting line 715 may be adjacent to each other, and a second side of the driving integrated circuit portion 600 (e.g., a portion of an outer side surface of the driving integrated circuit portion 600) and the second lighting line 710 may be adjacent to each other.

[0103] As mentioned above, it can provide Figures 1 to 4 The display device 100 shown in FIG.

[0104] Since the display device 100 according to the exemplary embodiment of the present disclosure includes the first connection electrode 730 and the second connection electrode 740 formed in parallel (e.g., simultaneously) with the first sensing electrode 382 and the second sensing electrode 384 in the same process, the first connection electrode 730 and the second connection electrode 740 are formed after the lower electrode 290 is formed, so that the etchant used to form the lower electrode 290 may not contact (e.g., physically contact) the first connection electrode 730 and the second connection electrode 740. For example, in some embodiments, an undercut phenomenon due to the etchant may not occur in the first connection electrode 730 and the second connection electrode 740, and the first insulating layer 395 may completely cover the first connection electrode 730 and the second connection electrode 740, so that the first connection electrode 730 and the second connection electrode 740 are not exposed to the outside. Therefore, the first connection electrode 730 and the second connection electrode 740 are not exposed to the outside, so that the first connection electrode 730 and the second connection electrode 740 may not be corroded, and the lighting inspection of the display device 100 may be accurately performed.

[0105] Although the display device 100 according to the present disclosure has been described as an organic light emitting diode display device, the configuration of the embodiments of the present disclosure is not limited thereto. In some exemplary embodiments, the display device 100 may include a liquid crystal display device (LCD), a field emission display device (FED), a plasma display device (PDP), and / or an electrophoretic image display device (EPD).

[0106] Figure 5 is a cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure, and Figure 6 It is shown Figure 5 sectional view of an example of a display device. In addition to the position of the first connection electrode 730, Figure 5 The display device 800 shown in FIG. 8 may have the same Figures 1 to 4 The configuration of the display device 100 described above is substantially the same or similar configuration. Figure 5This will not be repeated or referenced here. Figures 1 to 4 Redundant description of components where the components described are substantially the same or similar.

[0107] refer to Figure 5 , the display device 800 may include a substrate 110, a buffer layer 115, a semiconductor element 250, a first illumination line 715, a second illumination line 710, a third illumination line 725, a fourth illumination line 720, a first planarization layer 270, a line pattern 215, a connection pattern 235, a second planarization layer 275, a first connection electrode 730, a second connection electrode 740, a pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, a sensing structure 380, a driver integrated circuit part 600, a lighting circuit part 700, a pad electrode 470, etc. In some embodiments, the semiconductor element 250 may include an active layer 130, a gate insulating layer 150, a first gate electrode 170, a first interlayer insulating layer 190, a second gate electrode 175, a second interlayer insulating layer 195, a source electrode 210, and a drain electrode 230. In some embodiments, the display device 800 may include a display region 10 and a pad region 60. In some embodiments, the display region 10 may include the pixel region 30 , and the pad region 60 may include the first circuit region 80 , the second circuit region 70 , and the illumination line region 90 .

[0108] The first connection electrode 730 may be located in the pad region 60 on the gate insulating layer 150. The first illumination line 715 may be coupled to the first portion of the first connection electrode 730 through a first contact hole 732 formed in a first portion of the first interlayer insulating layer 190 and a first portion of the second interlayer insulating layer 195, and the second illumination line 710 may be coupled to the second portion of the first connection electrode 730 opposite to the first portion through a second contact hole 731 formed in a second portion of the first interlayer insulating layer 190 and a second portion of the second interlayer insulating layer 195. For example, in some embodiments, the first connection electrode 730 may electrically couple the first illumination line 715 to the second illumination line 710. The first connection electrode 730 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. The foregoing materials may be used alone or in combination with each other. In some exemplary embodiments, the first connection electrode 730 may have a multilayer structure including a plurality of metal layers. The plurality of metal layers may include materials different from each other and may have thicknesses different from each other.

[0109] In an exemplary embodiment, the first gate electrode 170, the first connection electrode 730, and the second connection electrode 740 may be located on the same layer and may include the same (e.g., substantially the same) material. For example, in the first circuit region 80, a dummy electrode may be further provided between the first connection electrode 730, the second connection electrode 740, and the substrate 110. When the first connection electrode 730 and the second connection electrode 740 are located on the same layer as the first gate electrode 170, the dummy electrode may be located on the same layer as the second gate electrode 175, the source electrode 210 and the drain electrode 230, or the line pattern 215 and the connection pattern 235.

[0110] In some exemplary embodiments, Figure 6 As shown in , the second gate electrode 175, the first connection electrode 730, and the second connection electrode 740 may be located on the same layer and may include the same (e.g., substantially the same) material. For example, in the first circuit region 80, a dummy electrode may be further provided between the first connection electrode 730, the second connection electrode 740, and the substrate 110. When the first connection electrode 730 and the second connection electrode 740 are located at the same layer as the second gate electrode 175, the dummy electrode may be located at the same layer as the first gate electrode 170, the source electrode 210, and the drain electrode 230, or the line pattern 215 and the connection pattern 235.

[0111] Since the display device 800 according to the exemplary embodiment of the present disclosure includes the first connection electrode 730 and the second connection electrode 740 formed in parallel (e.g., simultaneously) in the same process as the first gate electrode 170 or the second gate electrode 175, the first interlayer insulating layer 190 and the second interlayer insulating layer 195 completely cover the first connection electrode 730 and the second connection electrode 740, so that the etchant used to form the lower electrode 290 may not contact (e.g., physically contact) the first connection electrode 730 and the second connection electrode 740. For example, in some embodiments, an undercut phenomenon due to the etchant may not occur in the first connection electrode 730 and the second connection electrode 740, and the first interlayer insulating layer 190 or the second interlayer insulating layer 195 may completely cover the first connection electrode 730 and the second connection electrode 740, so that the first connection electrode 730 and the second connection electrode 740 are not exposed to the outside. Therefore, the first connection electrode 730 and the second connection electrode 740 are not exposed to the outside, so that the first connection electrode 730 and the second connection electrode 740 may not be corroded, and an illumination inspection may be accurately performed on the display device 800 .

[0112] Figure 7 is a partially enlarged plan view showing a display device according to an exemplary embodiment of the present disclosure, and Figure 8 is along Figure 1 The line I-I' and Figure 7In addition to the first insulating pattern 276 and the second insulating pattern 277, Figure 7 and Figure 8 The display device 900 shown in FIG. Figures 1 to 4 The configuration of the display device 100 described above is substantially the same or similar configuration. Figure 7 and Figure 8 This will not be repeated or referenced here. Figures 1 to 4 Redundant description of components where the components described are substantially the same or similar.

[0113] refer to Figure 7 and Figure 8 , the display device 900 may include a substrate 110, a buffer layer 115, a semiconductor element 250, a first illumination line 715, a second illumination line 710, a third illumination line 725, a fourth illumination line 720, a first planarization layer 270, a line pattern 215, a connection pattern 235, a second planarization layer 275, a first connection electrode 730, a first insulation pattern 276, a second connection electrode 740, a second insulation pattern 277, a pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, a sensing structure 380, a driver integrated circuit part 600, a lighting circuit part 700, a pad electrode 470, etc. In some embodiments, the semiconductor element 250 may include an active layer 130, a gate insulation layer 150, a first gate electrode 170, a first interlayer insulation layer 190, a second gate electrode 175, a second interlayer insulation layer 195, a source electrode 210, and a drain electrode 230. In some embodiments, the display device 900 may include a display region 10 and a pad region 60. In some embodiments, the display region 10 may include the pixel region 30 , and the pad region 60 may include the first circuit region 80 , the second circuit region 70 , and the illumination line region 90 .

[0114] The first connection electrode 730 and the second connection electrode 740 may be on the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195 located in the pad region 60 while being spaced apart from each other. Each of the first connection electrode 730 and the second connection electrode 740 may be disposed along the contours of the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195 in the pad region 60. Each of the first connection electrode 730 and the second connection electrode 740 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other.

[0115] In exemplary embodiments, the line pattern 215 , the connection pattern 235 , and the first and second connection electrodes 730 and 740 may include the same (eg, substantially the same) material.

[0116] The first insulating pattern 276 surrounding at least a portion of the first connection electrode 730 may be located in the first circuit region 80 on the second interlayer insulating layer 195. For example, the first insulating pattern 276 may cover both sides of the first connection electrode 730 in the first circuit region 80. The first insulating pattern 276 may include an organic insulating material. For example, the first insulating pattern 276 may include a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, etc.

[0117] A second insulating pattern 277 surrounding at least a portion of the second connection electrode 740 may be located in the first circuit region 80 on the second interlayer insulating layer 195. For example, the second insulating pattern 277 may cover both sides of the second connection electrode 740 in the first circuit region 80. The second insulating pattern 277 may include an organic insulating material.

[0118] In exemplary embodiments, the second planarization layer 275 , the first insulating pattern 276 , and the second insulating pattern 277 may include the same (eg, substantially the same) material, and may be formed in parallel (eg, simultaneously) in the same process by using a half-tone mask.

[0119] The display device 900 according to the exemplary embodiment of the present disclosure includes the first insulating pattern 276 and the second insulating pattern 277, so that the etchant used to form the lower electrode 290 may not contact (e.g., physically contact) both sides of each of the first connection electrode 730 and the second connection electrode 740 in the process of forming the lower electrode 290. For example, since both sides of each of the first connection electrode 730 and the second connection electrode 740 may be etched by the etchant to a relatively large extent, which causes an undercut phenomenon, both sides of each of the first connection electrode 730 and the second connection electrode 740 may be covered with the first insulating pattern 276 and the second insulating pattern 277, so that the undercut phenomenon can be prevented or reduced.

[0120] Fig. 9 is a partially enlarged plan view showing a display device according to an exemplary embodiment of the present disclosure, and Fig.10 is along Figure 1 The line I-I' and Fig. 9 In addition to the first insulating pattern 271 and the second insulating pattern 272, Fig. 9 and Fig.10 The display device 1000 shown in FIG. 1 may have the same Figures 1 to 4 The configuration of the display device 100 described above is substantially the same or similar configuration. Fig. 9 and Fig.10 This will not be repeated or referenced here. Figures 1 to 4 Redundant description of components where the components described are substantially the same or similar.

[0121] refer to Fig. 9 and Fig.10 , the display device 1000 may include a substrate 110, a buffer layer 115, a semiconductor element 250, a first illumination line 715, a second illumination line 725, a first planarization layer 270, a line pattern 215, a connection pattern 235, a second planarization layer 275, a first insulation pattern 271, a second insulation pattern 272, a pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, a sensing structure 380, a driver integrated circuit portion 600, a lighting circuit portion 700, a pad electrode 470, etc. In some embodiments, the semiconductor element 250 may include an active layer 130, a gate insulating layer 150, a first gate electrode 170, a first interlayer insulating layer 190, a second gate electrode 175, a second interlayer insulating layer 195, a source electrode 210, and a drain electrode 230. In some embodiments, the display device 1000 may include a display region 10 and a pad region 60. In some embodiments, the display region 10 may include the pixel region 30 , and the pad region 60 may include the first circuit region 80 , the second circuit region 70 , and the illumination line region 90 .

[0122] The first lighting wire 715 may be located in the pad region 60 on the second interlayer insulating layer 195. In an exemplary embodiment, the first lighting wire 715 may overlap the lighting wire region 90 and the first circuit region 80. A first end of the first lighting wire 715 may be coupled to the lighting circuit portion 700, and a second end of the first lighting wire 715 opposite to the first end may be coupled to one of the pad electrodes 470.

[0123] The second lighting wire 725 may be located in the pad region 60 on the second interlayer insulating layer 195 while being spaced apart from the first lighting wire 715. In an exemplary embodiment, the second lighting wire 725 may overlap the lighting wire region 90 and the first circuit region 80. A first end of the second lighting wire 725 may be coupled to the lighting circuit portion 700, and a second end of the second lighting wire 725 opposite to the first end may be coupled to another of the pad electrodes 470.

[0124] Each of the first illumination line 715 and the second illumination line 725 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other.

[0125] In an exemplary embodiment, the source electrode 210 , the drain electrode 230 , and the first and second illumination lines 715 and 725 may be located on the same layer and may include the same (eg, substantially the same) material.

[0126] The first insulating pattern 271 covering the first illumination line 715 may be located in the first circuit region 80 on the second interlayer insulating layer 195. For example, the first insulating pattern 271 may completely cover the first illumination line 715 in the first circuit region 80. The first insulating pattern 271 may include an organic insulating material. For example, the first insulating pattern 271 may include a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, etc.

[0127] The second insulating pattern 272 covering the second lighting line 725 may be located in the first circuit region 80 on the second interlayer insulating layer 195. For example, the second insulating pattern 272 may completely cover the second lighting line 725 in the first circuit region 80. The second insulating pattern 272 may include an organic insulating material.

[0128] In exemplary embodiments, the first planarization layer 270 , the first insulating pattern 271 , and the second insulating pattern 272 may include the same (eg, substantially the same) material, and may be formed in parallel (eg, simultaneously) in the same process by using a half-tone mask.

[0129] The display device 1000 according to an exemplary embodiment of the present disclosure includes the first and second insulating patterns 271 and 272 so that an etchant used to form the lower electrode 290 may not contact (eg, physically contact) the first and second illumination lines 715 and 725 in a process of forming the lower electrode 290 .

[0130] In addition, the lighting line coupling the pad electrode 470 to the lighting circuit part 700 is integrally formed so that the line resistance can be relatively reduced.

[0131] Figures 11 to 23 is a view illustrating a method of manufacturing a display device according to an exemplary embodiment of the present disclosure.

[0132] refer to Fig.11 and Fig.12 , a rigid glass substrate 105 may be provided. A substrate 110 including a transparent material or an opaque material may be formed on the glass substrate 105. The substrate 110 may be a transparent resin substrate having flexibility. In an exemplary embodiment, the substrate 110 may have a configuration in which a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer are sequentially stacked. The first barrier layer and the second barrier layer may be formed by using an inorganic material such as silicon oxide. In some embodiments, the first organic layer and the second organic layer may be formed by using an organic insulating material such as a polyimide-based resin. In some embodiments, each of the first barrier layer and the second barrier layer may prevent or reduce the penetration of moisture through the first organic layer and the second organic layer.

[0133] like Figure 1 and Fig.12 As shown in , the substrate 110 may include a display region 10 including a pixel region 30 and a pad region 60 including a first circuit region 80 , an illumination line region 90 , and a second circuit region 70 .

[0134] The buffer layer 115 may be formed on the substrate 110. For example, the buffer layer 115 may be formed over the entire display region 10 and the pad region 60 on the substrate 110. The buffer layer 115 may be formed by using a silicon compound, a metal oxide, or the like.

[0135] The active layer 130 may be formed in the display region 10 on the buffer layer 115. The active layer 130 may be formed by using a metal oxide semiconductor, an inorganic semiconductor, an organic semiconductor, etc. The active layer 130 may have a source region, a drain region, and a channel region between the source region and the drain region.

[0136] The gate insulating layer 150 may be formed on the active layer 130. The gate insulating layer 150 may cover the active layer 130 in the display region 10 on the buffer layer 115, and may extend in the fourth direction D4. For example, in some embodiments, the gate insulating layer 150 may be formed over the entire display region 10 and the pad region 60 on the buffer layer 115. For example, the gate insulating layer 150 may appropriately or sufficiently cover the active layer 130 on the buffer layer 115, and may have a substantially flat top surface without (or substantially without) generating steps around the active layer 130. In some embodiments, the gate insulating layer 150 may be formed along the contour of the active layer 130 with a uniform (e.g., substantially uniform) thickness to cover the active layer 130 on the buffer layer 115. The gate insulating layer 150 may be formed by using a silicon compound, a metal oxide, or the like.

[0137] The first gate electrode 170 may be formed in the display region 10 on the gate insulating layer 150. The first gate electrode 170 may be formed at a portion of the gate insulating layer 150 where the active layer 130 is disposed. The first gate electrode 170 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other.

[0138] Reference Fig.13, a first interlayer insulating layer 190 may be formed on the first gate electrode 170. The first interlayer insulating layer 190 may cover the first gate electrode 170 in the display region 10 on the gate insulating layer 150, and may extend in the fourth direction D4. For example, in some embodiments, the first interlayer insulating layer 190 may be formed over the entire display region 10 and the pad region 60 on the gate insulating layer 150. For example, the first interlayer insulating layer 190 may appropriately or sufficiently cover the first gate electrode 170 on the gate insulating layer 150, and may have a substantially flat top surface without (or substantially without) generating a step around the first gate electrode 170. In some embodiments, the first interlayer insulating layer 190 may be formed along the contour of the first gate electrode 170 with a uniform (e.g., substantially uniform) thickness to cover the first gate electrode 170 on the gate insulating layer 150. The first interlayer insulating layer 190 may be formed by using a silicon compound, a metal oxide, or the like.

[0139] The second gate electrode 175 may be formed in the display region 10 on the first interlayer insulating layer 190. The second gate electrode 175 may be formed at a portion of the first interlayer insulating layer 190 where the first gate electrode 170 is disposed. The second gate electrode 175 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other.

[0140] A second interlayer insulating layer 195 may be formed on the second gate electrode 175. The second interlayer insulating layer 195 may cover the second gate electrode 175 in the display region 10 on the first interlayer insulating layer 190, and may extend in the fourth direction D4. For example, in some embodiments, the second interlayer insulating layer 195 may be formed over the entire display region 10 and the pad region 60 on the first interlayer insulating layer 190. For example, the second interlayer insulating layer 195 may appropriately or sufficiently cover the second gate electrode 175 on the first interlayer insulating layer 190, and may have a substantially flat top surface without (or substantially without) generating a step around the second gate electrode 175. In some embodiments, the second interlayer insulating layer 195 may be formed along the contour of the second gate electrode 175 with a uniform (e.g., substantially uniform) thickness to cover the second gate electrode 175 on the first interlayer insulating layer 190. The second interlayer insulating layer 195 may be formed by using a silicon compound, a metal oxide, or the like.

[0141] After forming the second interlayer insulating layer 195 , contact holes exposing the source and drain regions of the active layer 130 may be formed by removing the first and second portions of the gate insulating layer 150 , the first and second portions of the first interlayer insulating layer 190 , and the first and second portions of the second interlayer insulating layer 195 .

[0142] refer to Fig.14 and Fig.15 , a source electrode 210 and a drain electrode 230 may be formed in the display region 10 on the second interlayer insulating layer 195. The source electrode 210 may be coupled to the source region of the active layer 130 through a contact hole formed by removing a first portion of the gate insulating layer 150, a first portion of the first interlayer insulating layer 190, and a first portion of the second interlayer insulating layer 195, and the drain electrode 230 may be coupled to the drain region of the active layer 130 through a contact hole formed by removing a second portion of the gate insulating layer 150, a second portion of the first interlayer insulating layer 190, and a second portion of the second interlayer insulating layer 195. Each of the source electrode 210 and the drain electrode 230 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The aforementioned materials may be used alone or in combination with each other.

[0143] Thus, the semiconductor element 250 including the active layer 130 , the gate insulating layer 150 , the first gate electrode 170 , the first interlayer insulating layer 190 , the second gate electrode 175 , the second interlayer insulating layer 195 , the source electrode 210 , and the drain electrode 230 may be formed.

[0144] In the process of forming the semiconductor element 250 , the lighting semiconductor element may be formed in parallel (eg, simultaneously) in the second circuit region 70 . Therefore, the lighting circuit portion 700 may be formed in the second circuit region 70 .

[0145] The first lighting line 715 and the third lighting line 725 may be formed in the lighting line region 90 on the second interlayer insulating layer 195 while being spaced apart from each other. Each of the first lighting line 715 and the third lighting line 725 may extend in the first direction D1 in the lighting line region 90 on the second interlayer insulating layer 195 so as to be coupled to the lighting circuit portion 700. Each of the first lighting line 715 and the third lighting line 725 may be formed by using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. The aforementioned materials may be used alone or in combination with each other.

[0146] The second lighting wire 710 and the fourth lighting wire 720 may be formed in the pad region 60 on the second interlayer insulating layer 195 while being spaced apart from each other. Each of the second lighting wire 710 and the fourth lighting wire 720 may extend in the second direction D2 and the fourth direction D4 so as to be coupled to the pad electrode 470. Each of the second lighting wire 710 and the fourth lighting wire 720 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other.

[0147] In an exemplary embodiment, the source electrode 210, the drain electrode 230, the first illumination line 715, the second illumination line 710, the third illumination line 725, and the fourth illumination line 720 may be formed in parallel (e.g., simultaneously) on the same layer by using the same (e.g., substantially the same) material. For example, the source electrode 210, the drain electrode 230, the first illumination line 715, the second illumination line 710, the third illumination line 725, and the fourth illumination line 720 may be formed in parallel (e.g., simultaneously) by forming a first preliminary electrode layer on the entire second interlayer insulating layer 195 and partially etching the first preliminary electrode layer.

[0148] Each of the source electrode 210, the drain electrode 230, the first illumination line 715, the second illumination line 710, the third illumination line 725, and the fourth illumination line 720 may include Au, Ag, Al, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, W, Cu, Mo, Sc, Nd, Ir, aluminum alloy, AlN x , silver alloy, WN x , copper alloy, molybdenum alloy, TiN x CrN x 、TaN x 、SrRu x O y 、ZnO x 、ITO、SnO x 、InO x 、GaO x , IZO, etc.

[0149] Reference Fig.16, a first planarization layer 270 may be formed on the second interlayer insulating layer 195, the source electrode 210 and the drain electrode 230, and the first, second, third, and fourth illumination lines 715, 710, 725, and 720. The first planarization layer 270 may be formed in a portion of the pad region 60 and the display region 10 on the second interlayer insulating layer 195. For example, in some embodiments, the first planarization layer 270 may extend in the fourth direction D4 to cover the source electrode 210 and the drain electrode 230 in the display region 10 on the second interlayer insulating layer 195, and may cover the first, second, third, and fourth illumination lines 715, 710, 725, and 720 in the pad region 60. In some embodiments, the first planarization layer 270 may have a first opening 274 that exposes a top surface of the second interlayer insulating layer 195 located in the first circuit region 80. In some embodiments, a contact hole exposing a portion of the drain electrode 230, a contact hole exposing a portion of the first illumination line 715, a contact hole exposing a portion of the second illumination line 710, a contact hole exposing a portion of the third illumination line 725, and a contact hole exposing a portion of the fourth illumination line 720 can be formed in parallel (e.g., simultaneously) in the process of forming the first opening 274.

[0150] The first planarization layer 270 may have a relatively thick thickness. In this case, the first planarization layer 270 may have a substantially flat top surface. In order to achieve such a flat top surface of the first planarization layer 270, a planarization process may be additionally performed on the first planarization layer 270. The first planarization layer 270 may be formed by using an organic insulating material. For example, the first planarization layer 270 may include a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, etc.

[0151] refer to Fig.17 , the line pattern 215 and the connection pattern 235 may be formed in the display region 10 on the first planarization layer 270 while being spaced apart from each other. The connection pattern 235 may be coupled to the drain electrode 230 through a contact hole formed by removing a portion of the first planarization layer 270 located in the display region 10. Each of the line pattern 215 and the connection pattern 235 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other.

[0152] The second planarization layer 275 may be formed on the line pattern 215, the connection pattern 235, and the first planarization layer 270. The second planarization layer 275 may be located in a portion of the pad region 60 on the first planarization layer 270 and in the display region 10. For example, in some embodiments, the second planarization layer 275 may extend in the fourth direction D4 to cover the line pattern 215 and the connection pattern 235 in the display region 10 on the first planarization layer 270, and may be formed on the first planarization layer 270 in the pad region 60. In some embodiments, the second planarization layer 275 may have a second opening 279 that exposes a top surface of the second interlayer insulating layer 195 located in the first circuit region 80. In some embodiments, a contact hole exposing a portion of the connection pattern 235, a contact hole overlapping with a contact hole of the first planarization layer 270 exposing a portion of the first illumination line 715, a contact hole overlapping with a contact hole of the first planarization layer 270 exposing a portion of the second illumination line 710, a contact hole overlapping with a contact hole of the first planarization layer 270 exposing a portion of the third illumination line 725, and a contact hole overlapping with a contact hole of the first planarization layer 270 exposing a portion of the fourth illumination line 720 can be formed in parallel (e.g., simultaneously) in the process of forming the second opening 279.

[0153] In some embodiments, a contact hole of the first planarization layer 270 that exposes a portion of the first illumination line 715 and a contact hole of the second planarization layer 275 that overlaps with the contact hole may be defined as a first contact hole 732, a contact hole of the first planarization layer 270 that exposes a portion of the second illumination line 710 and a contact hole of the second planarization layer 275 that overlaps with the contact hole may be defined as a second contact hole 731, a contact hole of the first planarization layer 270 that exposes a portion of the third illumination line 725 and a contact hole of the second planarization layer 275 that overlaps with the contact hole may be defined as a third contact hole 742, and a contact hole of the first planarization layer 270 that exposes a portion of the fourth illumination line 720 and a contact hole of the second planarization layer 275 that overlaps with the contact hole may be defined as a fourth contact hole 741 (see Fig. 20 ).

[0154] The second planarization layer 275 may have a relatively thick thickness. In this case, the second planarization layer 275 may have a substantially flat top surface. In order to achieve such a flat top surface of the second planarization layer 275, a planarization process may be additionally performed on the second planarization layer 275. The second planarization layer 275 may be formed by using an organic insulating material.

[0155] refer to Fig.18, a lower electrode 290 may be formed in the display region 10 on the second planarization layer 275. The lower electrode 290 may be coupled to the connection pattern 235 through a contact hole formed by removing a portion of the second planarization layer 275. The lower electrode 290 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other.

[0156] The pixel defining layer 310 may be formed in the display region 10 on the second planarization layer 275. For example, in some embodiments, the pixel defining layer 310 may not be formed in the pad region 60. The pixel defining layer 310 may expose a portion of the lower electrode 290 in the display region 10. The pixel defining layer 310 may be formed by using an organic insulating material.

[0157] An organic light emitting layer 330 may be formed on the lower electrode 290. The organic light emitting layer 330 may be formed by using at least one of a plurality of light emitting materials for emitting light of different colors according to pixels. In some embodiments, the organic light emitting layer 330 may be formed by stacking a plurality of light emitting materials for generating light of different colors such as red light, green light, and blue light to emit white light as a whole.

[0158] The upper electrode 340 may be formed over the entire display area 10 on the substrate 110. The upper electrode 340 may be formed along the contours of the organic light emitting layer 330 and the pixel defining layer 310. The upper electrode 340 may be formed by using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. The aforementioned materials may be used alone or in combination with each other.

[0159] Thus, the pixel structure 200 including the lower electrode 290 , the organic light emitting layer 330 , and the upper electrode 340 may be formed.

[0160] The first inorganic thin film encapsulation layer 451 may be formed in the display region 10 on the upper electrode 340. For example, the first inorganic thin film encapsulation layer 451 may be formed along the contour of the upper electrode 340 in the display region 10. The first inorganic thin film encapsulation layer 451 may be formed by using an inorganic insulating material having flexibility.

[0161] An organic thin film encapsulation layer 452 may be formed in the display region 10 on the first inorganic thin film encapsulation layer 451. The organic thin film encapsulation layer 452 may be formed by using an organic insulating material having flexibility.

[0162] The second inorganic thin film encapsulation layer 453 may be formed on the organic thin film encapsulation layer 452. The second inorganic thin film encapsulation layer 453 may be formed along the contour of the organic thin film encapsulation layer 452 with a uniform (e.g., substantially uniform) thickness to cover the organic thin film encapsulation layer 452 in the display area 10. The second inorganic thin film encapsulation layer 453 may be formed by using an inorganic insulating material having flexibility.

[0163] Thus, a thin film encapsulation structure 450 including a first inorganic thin film encapsulation layer 451 , an organic thin film encapsulation layer 452 , and a second inorganic thin film encapsulation layer 453 may be formed.

[0164] refer to Fig.19 and Fig. 20 , an insulating layer 381 may be formed on the second inorganic thin film encapsulation layer 453, the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195. The insulating layer 381 may be formed on the second inorganic thin film encapsulation layer 453 in the display region 10, and may extend in the fourth direction D4 to be formed along the contours of the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195 in the pad region 60. In some embodiments, the insulating layer 381 may be formed over the entire display region 10 and the pad region 60 on the substrate 110. For example, the insulating layer 381 may be formed on the second inorganic thin film encapsulation layer 453, the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195 with a uniform (e.g., substantially uniform) thickness along the contours of the second inorganic thin film encapsulation layer 453, the second planarization layer 275, the first planarization layer 270, and the second interlayer insulating layer 195. The insulating layer 381 may have an opening exposing the first contact hole 732, an opening exposing the second contact hole 731, an opening exposing the third contact hole 742, and an opening exposing the fourth contact hole 741. The insulating layer 381 may be formed by using a silicon compound, a metal oxide, or the like.

[0165] refer to Figure 2 , Figure 4 and Fig.21 , first sensing electrodes 382 and second sensing electrodes 384 may be formed in the display area 10 on the insulating layer 381. Each of the first sensing electrodes 382 may extend in the third direction D3, and the first sensing electrodes 382 may be spaced apart from each other in the first direction D1. The second sensing electrode 384 may be formed between two adjacent first sensing electrodes 382 among the first sensing electrodes 382, ​​while being spaced apart from each other in the third direction D3. For example, each of the first sensing electrode 382 and the second sensing electrode 384 may be formed by using CNT, a transparent conductive oxide (such as ZnO x 、ITO、SnO x 、InO x 、GaO x, IZO and / or IGZO), graphene, AgNW, Cu, Cr, etc.

[0166] The first connection electrode 730 and the second connection electrode 740 may be formed on the second planarization layer 275, the first planarization layer 270, and the insulating layer 381 located in the pad region 60 while being spaced apart from each other. Each of the first connection electrode 730 and the second connection electrode 740 may be formed along the contours of the second planarization layer 275, the first planarization layer 270, and the insulating layer 381 in the pad region 60, and may be formed between the driving integrated circuit portion 600 and the insulating layer 381 in the first circuit region 80. The first connection electrode 730 may be coupled to the first illumination line 715 and the second illumination line 710 through the first contact hole 732 and the second contact hole 731 formed in the first planarization layer 270 and the second planarization layer 275, respectively. In addition, the second connection electrode 740 may be coupled to the third illumination line 725 and the fourth illumination line 720 through the third contact hole 742 and the fourth contact hole 741 formed in the first planarization layer 270 and the second planarization layer 275, respectively.

[0167] Each of the first connection electrode 730 and the second connection electrode 740 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The foregoing materials may be used alone or in combination with each other.

[0168] In an exemplary embodiment, the first sensing electrode 382 and the second sensing electrode 384 and the first connection electrode 730 and the second connection electrode 740 may be formed in parallel (e.g., simultaneously) by using the same (e.g., substantially the same) material. For example, the first sensing electrode 382 and the second sensing electrode 384 and the first connection electrode 730 and the second connection electrode 740 may be formed in parallel (e.g., simultaneously) by forming a second preliminary electrode layer on the entire insulating layer 381 and partially etching the second preliminary electrode layer.

[0169] Reference Fig. 22, a first insulating layer 395 may be formed on the insulating layer 381, the first sensing electrode 382, ​​the second sensing electrode 384, the first connection electrode 730, and the second connection electrode 740. The first insulating layer 395 may cover the first sensing electrode 382 and the second sensing electrode 384 in the display region 10 on the insulating layer 381, and may extend in the fourth direction D4 to cover the first connection electrode 730 and the second connection electrode 740 in the pad region 60 on the insulating layer 381. In some embodiments, the first insulating layer 395 may be formed over the entire display region 10 and the pad region 60 on the insulating layer 381. For example, the first insulating layer 395 may be formed along the contours of the first sensing electrode 382 and the second sensing electrode 384 and the first connection electrode 730 and the second connection electrode 740 with a uniform (e.g., substantially uniform) thickness to cover the first sensing electrode 382 and the second sensing electrode 384 and the first connection electrode 730 and the second connection electrode 740 on the insulating layer 381. In some embodiments, the first insulating layer 395 may appropriately or sufficiently cover the first sensing electrode 382 and the second sensing electrode 384 and the first connection electrode 730 and the second connection electrode 740 on the insulating layer 381, and may have a substantially flat top surface without (or substantially without) generating steps around the first sensing electrode 382 and the second sensing electrode 384 and the first connection electrode 730 and the second connection electrode 740. The first insulating layer 395 may be formed by using a silicon compound, a metal oxide, or the like. For example, the first insulating layer 395 may include SiO x 、SiN x 、SiO x N y 、SiO x C y 、SiC x N y 、AlO x 、AlN x 、TaO x , HfO x 、ZrO x 、TiO x wait.

[0170] Sensing connection electrodes 386 may be formed in the display region 10 on the first insulating layer 395. Each of the sensing connection electrodes 386 may be coupled to two second sensing electrodes 384 adjacent to each other in the first direction D1 among the second sensing electrodes 384 through a contact hole formed by removing a portion of the first insulating layer 395. For example, the sensing connection electrodes 386 may be formed by using the same (e.g., substantially the same) material as the first sensing electrodes 382 and the second sensing electrodes 384.

[0171] A second insulating layer 398 may be formed on the first insulating layer 395 and the sensing connection electrode 386. The second insulating layer 398 may cover the sensing connection electrode 386 in the display region 10 on the first insulating layer 395, and may not be formed in the pad region 60. The second insulating layer 398 may be formed by using an organic insulating material or an inorganic insulating material.

[0172] Thus, a sensing structure 380 including the insulating layer 381 , the first sensing electrode 382 , the second sensing electrode 384 , the first insulating layer 395 , the sensing connection electrode 386 , and the second insulating layer 398 may be formed.

[0173] refer to Fig.23 The driving integrated circuit portion 600 may be formed in the first circuit region 80 on the first insulating layer 395. In an exemplary embodiment, the driving integrated circuit portion 600 may be formed inside the first opening 274 and the second opening 279.

[0174] After forming the driver integrated circuit portion 600, the glass substrate 105 may be removed from the substrate 110. Thus, a Figures 1 to 4 The display device 100 shown in FIG.

[0175] The subject matter of the present disclosure can be applied to various suitable electronic devices including display devices. For example, the subject matter of the present disclosure can be applied to vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0176] The foregoing is an illustration of exemplary embodiments and should not be construed as limiting thereof. Although some exemplary embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made to the exemplary embodiments without substantially departing from the spirit and scope of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims and their equivalents. Therefore, it will be understood that the foregoing is an illustration of various exemplary embodiments and should not be construed as being limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate, comprising a display area and a pad area; a pixel structure located on the substrate in the display area to emit light; a lighting circuit portion, located on the substrate in the pad region and electrically coupled to the pixel structure; A driver integrated circuit portion surrounding at least a portion of the lighting circuit portion; a first lighting line spaced apart from a first side of the driving integrated circuit portion in a first direction and coupled to the lighting circuit portion; a second illumination line spaced apart from a second side of the driver integrated circuit portion facing the first side in a second direction opposite to the first direction; as well as The connecting electrode electrically connects the first lighting line and the second lighting line to each other.

2. The display device according to claim 1, wherein: Each of the first lighting line and the second lighting line does not overlap with the driving integrated circuit portion.

3. The display device according to claim 1, wherein: The driver integrated circuit portion has a rectangular shape including an opening when viewed in a plan view, and The lighting circuit portion is located in the opening.

4. The display device according to claim 1, wherein: The driving integrated circuit portion and the lighting circuit portion are spaced apart from each other.

5. The display device according to claim 1, wherein: The substrate further comprises: A first circuit region, wherein the driver integrated circuit portion having an opening is located in the first circuit region; a second circuit region, wherein the lighting circuit portion located inside the opening of the driver integrated circuit portion is located in the second circuit region; and an illumination line region between the first circuit region and the second circuit region, wherein the first illumination line is located in the illumination line region, The connecting electrode is located between the substrate and the driving integrated circuit portion in the first circuit region.

6. The display device according to claim 1, further comprising a sensing structure located on the pixel structure, in, The sensing structure comprises: Sensing electrodes; A first insulating layer, located on the sensing electrode; and The sensing connection electrode is located on the first insulating layer.

7. The display device according to claim 6, wherein: The sensing electrode and the connecting electrode both include the same material, and The first insulating layer extends in a direction from the display area to the pad area to cover the sensing electrode in the display area, and covers the connecting electrode in the pad area.

8. The display device according to claim 6, wherein: The first insulating layer directly contacts a bottom surface of the driving integrated circuit part and a top surface of the connecting electrode in the pad region.

9. The display device according to claim 1, further comprising a semiconductor element located between the substrate and the pixel structure in the display area, in, The semiconductor element comprises: An active layer, located on the substrate; a gate electrode located on the active layer; and A source electrode and a drain electrode are located on the gate electrode, and The first illumination line and the second illumination line are located on the same layer as the source electrode and the drain electrode, and the first illumination line and the second illumination line include the same material.

10. The display device according to claim 1, further comprising: A first planarization layer, located between the substrate and the pixel structure; as well as a second planarization layer, located on the first planarization layer, wherein the first planarization layer has a first opening formed in a portion of the pad region, and the second planarization layer has a second opening overlapping the first opening, The driving integrated circuit is located inside the first opening and the second opening. wherein, in the pad region, a first contact hole passes through the first planarization layer and the second planarization layer and exposes a portion of the first illumination line, and a second contact hole passes through the first planarization layer and the second planarization layer and exposes a portion of the second illumination line, and The connection electrode is coupled to the first lighting line and the second lighting line through the first contact hole and the second contact hole, respectively.

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