Electronic system, stacked memory device and operating method thereof

Abstract

Disclosed are an electronic system, a stacked memory device, and an operating method thereof. The stacked memory device includes a buffer semiconductor die, multiple memory semiconductor dies, multiple through-silicon vias (TSVs), a FIM front-end circuit, and multiple FIM back-end circuits. The buffer semiconductor die is configured to communicate with a host device. The memory semiconductor die is stacked on the buffer semiconductor die and includes multiple memory banks. The TSVs electrically connect the buffer semiconductor die to the memory semiconductor die. The FIM front-end circuit receives multiple FIM instructions for FIM operations from the host device and stores the FIM instructions. FIM operations include data processing based on internal data read from the memory banks. The FIM back-end circuits are each included in the memory semiconductor die. Under the control of the FIM front-end circuit, the FIM back-end circuit executes FIM operations corresponding to the multiple FIM instructions stored in the FIM front-end circuit.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2020-0021140 filed on February 20, 2020, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate generally to semiconductor integrated circuits, and more particularly, to a stacked memory device that performs a function-in-memory (FIM) operation and a method of operating the stacked memory device. Background Art

[0003] Memory bandwidth and latency are performance bottlenecks in many processing systems. Memory capacity can be increased by using a stacked memory device in which multiple semiconductor devices are stacked in a package of a memory chip. The stacked semiconductor dies can be electrically connected using through-silicon vias (also known as "through-silicon vias") or through-substrate vias (TSVs). Such stacking technology can increase memory capacity and / or suppress bandwidth and / or latency losses. Each access to the stacked memory device by an external device involves data communication between the stacked semiconductor dies. In this case, inter-device bandwidth and inter-device latency losses occur for each access, thereby increasing bandwidth and latency. Therefore, when the task of the external device requires multiple accesses to the stacked memory device, the inter-device bandwidth and inter-device latency have a significant impact on the processing efficiency and power consumption of the system. Summary of the Invention

[0004] Some example embodiments provide a stacked memory device that efficiently performs a function-in-memory (FIM) operation or a processing-in-memory (PIM) operation.

[0005] Some example embodiments provide a system including a stacked memory device and a method of operating the stacked memory device to efficiently perform an FIM operation.

[0006] According to an example embodiment, a stacked memory device includes a buffer semiconductor die, a plurality of memory semiconductor dies, a plurality of through-silicon vias (TSVs), a function-in-memory (FIM) front-end circuit, and a plurality of FIM back-end circuits. The buffer semiconductor die is configured to communicate with a host device. The plurality of memory semiconductor dies are stacked on the buffer semiconductor die, and the plurality of memory semiconductor dies include a plurality of memory banks. The plurality of TSVs electrically connect the buffer semiconductor die to the plurality of memory semiconductor dies. The FIM front-end circuit is configured to receive a plurality of FIM instructions for FIM operations from the host device and store the plurality of FIM instructions. FIM operations include data processing based on internal data read from the plurality of memory banks. The plurality of FIM back-end circuits are respectively included in the plurality of memory semiconductor dies. Under the control of the FIM front-end circuit, the plurality of FIM back-end circuits execute FIM operations corresponding to the plurality of FIM instructions stored in the FIM front-end circuit.

[0007] According to an example embodiment, a system includes a stacked memory device and a host device configured to control the stacked memory device. The stacked memory device includes a buffer semiconductor die, a plurality of memory semiconductor dies, a plurality of through-silicon vias electrically connecting the buffer semiconductor die to the plurality of memory semiconductor dies, a FIM front-end circuit, and a plurality of FIM back-end circuits.

[0008] According to an example embodiment, a method for operating a stacked memory device is provided, the stacked memory device including a buffer semiconductor die configured to communicate with a host device and a plurality of memory semiconductor dies including a plurality of memory banks. The buffer semiconductor die and the plurality of memory semiconductor dies are stacked. The method includes: transmitting a plurality of function-in-memory (FIM) instructions for FIM operations from the host device to the stacked memory device, wherein the FIM operations include data processing based on internal data read from the plurality of memory banks; storing the plurality of FIM instructions in a FIM front-end circuit included in the buffer semiconductor die or the plurality of memory semiconductor dies; and executing the FIM operations corresponding to the FIM instructions stored in the FIM front-end circuit under the control of the FIM front-end circuit using a plurality of FIM back-end circuits respectively included in the plurality of memory semiconductor dies.

[0009] Stacked memory devices, systems, and methods according to example embodiments may reduce power consumption and latency of stacked memory devices and systems by performing memory-intensive or data-intensive data processing using a FIM back-end circuit integrated in the stacked memory device.

[0010] Additionally, the stacked memory device, system, and method according to example embodiments may reduce data processing time by performing data processing in parallel using bank FIM circuits respectively assigned to memory banks.

[0011] Furthermore, the stacked memory device, system, and method according to example embodiments may efficiently perform complex data processing and enhance system performance by storing FIM instructions in a FIM front-end circuit and performing FIM operations based on the stored FIM instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Example embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0013] Figure 1 is a perspective view of a system including a stacked memory device according to example embodiments.

[0014] Figure 2 is a flowchart illustrating a method of operating a stacked memory device according to example embodiments.

[0015] Figure 3 is a block diagram illustrating a function-in-memory (FIM) front-end circuit included in a stacked memory device according to example embodiments.

[0016] Figure 4 is a block diagram illustrating a FIM back-end circuit included in a stacked memory device according to example embodiments.

[0017] Figure 5 is a diagram illustrating a high bandwidth memory (HBM) device according to example embodiments.

[0018] Figure 6 is a diagram illustrating an example interface of a system including an HBM device according to example embodiments.

[0019] Figure 7A and Figure 7B is a diagram illustrating a format of a command address signal of an HBM device according to example embodiments.

[0020] Figure 8 is a diagram illustrating a stacked memory device according to example embodiments.

[0021] Figure 9 It is shown that the Figure 8 Block diagram of the FIM channel control circuit in the stacked memory device.

[0022] Figure 10 It is shown that the Figure 8 A block diagram of an example embodiment of a bank FIM circuit in a stacked memory device.

[0023] Figure 11 is a diagram illustrating FIM instructions stored in a stacked memory device according to example embodiments.

[0024] Figure 12 is a diagram illustrating FIM control signals of a stacked memory device according to example embodiments.

[0025] Figure 13 is a diagram illustrating an address map of a system including a stacked memory device according to example embodiments.

[0026] Figure 14 is a diagram illustrating data processing performed by a stacked memory device according to example embodiments.

[0027] Figures 15A to 15G is a diagram illustrating a data path of an FIM operation in a stacked memory device according to example embodiments.

[0028] Figures 16A to 18B is a diagram illustrating an example operation of a stacked memory device according to example embodiments.

[0029] Figure 19 is a diagram illustrating a stacked memory device according to example embodiments.

[0030] Figure 20 It is shown that the Figure 19 Block diagram of the FIM channel control circuit in the stacked memory device.

[0031] Figure 21 is a diagram illustrating FIM instructions stored in a stacked memory device according to example embodiments.

[0032] Figure 22 is a diagram illustrating FIM control signals of a stacked memory device according to example embodiments.

[0033] Figures 23A to 24B is a diagram illustrating an operation of a stacked memory device according to example embodiments.

[0034] Figures 25 to 27 is a diagram illustrating a package structure of a stacked memory device according to example embodiments.

[0035] Figure 28 is a perspective view of a semiconductor package including a stacked memory device according to example embodiments. DETAILED DESCRIPTION

[0036] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. In the accompanying drawings, like reference numerals refer to like elements throughout. Repetitive descriptions may be omitted.

[0037] Figure 1 is an exploded perspective view of a system including a stacked memory device according to example embodiments.

[0038] Reference Figure 1 , the system 10 includes a stacked memory device 1000 and a host device 2000 .

[0039] The stacked memory device 1000 may include a buffer semiconductor die 1010 or a logic semiconductor die 1010 and a plurality of memory semiconductor dies 1070 and 1080 stacked with the buffer semiconductor die 1010 . Figure 1 A non-limiting example of one buffer semiconductor die and two memory semiconductor dies is shown. Any number of buffer semiconductor dies and memory semiconductor dies may be included. For example, two or more buffer semiconductor dies and one, three or more memory semiconductor dies may be included in a stacked structure. In addition, Figure 1 A non-limiting example of memory semiconductor die 1070 and 1080 being stacked vertically with buffer semiconductor die 1010 is shown. Figure 25 As described, the memory semiconductor dies 1070 and 1080 excluding the buffer semiconductor die 1010 may be vertically stacked, and the buffer semiconductor die 1010 may be electrically connected to the memory semiconductor dies 1070 and 1080 through an interposer and / or a base substrate.

[0040] The buffer semiconductor die 1010 may include a memory interface MIF 1020 and logic circuits for accessing the memory integrated circuits MEM 1071 and 1081 formed in the memory semiconductor dies 1070 and 1080, respectively. The logic circuits may include a control circuit CTRL 1030 and a global buffer GBF 1040. Furthermore, the buffer semiconductor die 1010 may include a function-in-memory (FIM) front-end circuit FFEC 100 according to example embodiments. In some example embodiments, the FIM front-end circuit 100 may be included in multiple memory semiconductor dies 1070 and 1080. The FIM front-end circuit 100 may receive multiple FIM instructions for FIM operations from the host device 2000 and store the multiple FIM instructions. The FIM operations may include data processing based on internal data read from multiple memory banks included in the memory semiconductor dies 1070 and 1080.

[0041] The memory interface 1020 may perform communication with an external device such as the host device 2000 through the interconnection device 12. The control circuit 1030 may control the overall operation of the stacked memory device 1000. The global buffer 1040 may temporarily store data and information exchanged between the host device 2000 and the stacked memory device 1000.

[0042] The memory semiconductor dies 1070 and 1080 may include memory integrated circuits 1071 and 1081, respectively. As described below, each of the memory integrated circuits 1071 and 1081 may include a plurality of memory banks configured to store data. Furthermore, the memory integrated circuits 1071 and 1081 may include a plurality of FIM back-end circuits 200 according to example embodiments. The plurality of FIM back-end circuits 200 may execute FIM operations corresponding to a plurality of FIM instructions stored in the FIM front-end circuit 100 under the control of the FIM front-end circuit 100.

[0043] The host device 2000 may include a host interface HIF 2110 and processor cores CR1 2120 and CR2 2130. The host interface 2110 may perform communication with an external device such as the stacked memory device 1000 through the interconnection device 12.

[0044] Figure 1 A processing system 10 according to at least one example embodiment of the present inventive concepts is shown. The processing system 10 may include any of a variety of computing systems, including a notebook or tablet computer, a desktop computer, a server, a network router, a switch or hub, a computing-capable cellular phone, a personal digital assistant, etc. Figure 1 , the processing system 10 includes a host device 2000 and a stacked memory device 1000 coupled via an interconnect device 12. The processing system 10 may also include various other components, such as one or more display components, a storage device, an input device (e.g., a mouse or keyboard), and the like. In some example embodiments, the host device 2000 may be an integrated circuit (IC) package, and the stacked memory device 1000 may be an IC package separate from the IC package of the host device 2000. In some example embodiments, the host device 2000 and the stacked memory device 1000 may be IC packages in which a semiconductor die 2100 of the host device 2000 and a semiconductor die of the stacked memory device 1000 are electrically connected via an interposer or the like. However, it will be understood that the host device 2000 is external to the stacked memory device 1000 and may therefore be referred to herein as an "external device."

[0045] The host device 2000 may be a device including one or more processor cores 2120 and 2130. For example, the processor cores 2120 and 2130 may include a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, etc., or a combination thereof.

[0046] The interconnection device 12 can be implemented according to various interconnection architectures or bus architectures, such as a Peripheral Component Interconnect Express (PCI-E) architecture, a HyperTransport architecture, a Quick Path Interconnect (QPI) architecture, etc. The interconnection device 12 includes one or more conductors to electrically connect the transceiver circuit in the memory interface 1020 of the stacked memory device 1000 and the transceiver circuit in the host interface 2110 of the host device 2000. The conductors may include electrical conductors (such as traces or cables of a printed circuit board (PCB)), optical conductors (such as optical fibers), or a combination thereof.

[0047] The memory integrated circuits 1071 and 1081 in the memory semiconductor dies 1070 and 1080 may include various memory cell architectures, including but not limited to volatile memory architectures such as dynamic random access memory (DRAM), thyristor random access memory (TRAM) and static random access memory (SRAM), or non-volatile memory architectures such as read-only memory (ROM), flash memory, ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), etc.

[0048] In some example embodiments, a memory controller may be included in the stacked memory device 1000. For example, the memory interface 1020 may include a memory controller. The memory controller may include a receiver and line driver, a memory request buffer, scheduling logic, row / column decoding logic, refresh logic, data input and data output buffers, a clock generator, etc. In some example embodiments, the memory controller may be included in the host device 2000.

[0049] Figure 1 The stacked memory device 1000 in FIG. 1 may be implemented in a vertical stack arrangement whereby power and signals are transmitted between the buffer semiconductor die 1010 and the memory semiconductor dies 1070 and 1080 using dense through-silicon vias (TSVs) or other vertical interconnects. Figure 1 A central row of TSVs is shown, but the TSVs may be dispersed differently throughout the floorplan of the buffer semiconductor die 1010 and / or the memory semiconductor dies 1070 and 1080 .

[0050] Figure 2 is a flowchart illustrating a method of operating a stacked memory device according to example embodiments.

[0051] Reference Figure 1 and Figure 2 , a plurality of function-in-memory (FIM) instructions for a FIM operation including data processing based on internal data read from a plurality of memory banks may be transmitted from the host device 2000 to the stacked memory device 1000 .

[0052] The stacked memory device 1000 may store a plurality of FIM commands in the FIM front-end circuit 100 included in the buffer semiconductor die 1010 or the plurality of memory semiconductor dies 1070 and 1080 ( S200 ).

[0053] The stacked memory device 1000 may perform a FIM operation corresponding to a FIM instruction stored in the FIM front-end circuit 100 under the control of the FIM front-end circuit 100 using the plurality of FIM back-end circuits 200 respectively included in the plurality of memory semiconductor dies 1070 and 1080 ( S300 ).

[0054] Thus, the stacked memory device 1000, the system 10, and the method of operating the stacked memory device 1000 according to example embodiments can reduce power consumption and latency of the stacked memory device 1000 and the system 10 by performing memory-intensive or data-intensive data processing using the FIM back-end circuit 200 integrated in the stacked memory device 1000. Furthermore, data processing time can be reduced by performing data processing in parallel using bank FIM circuits respectively assigned to memory banks. Furthermore, by storing FIM instructions in the FIM front-end circuit 100 and performing FIM operations based on the stored FIM instructions, complex data processing can be efficiently performed and the performance of the system 10 can be enhanced.

[0055] Figure 3 is a block diagram illustrating a function-in-memory (FIM) front-end circuit included in a stacked memory device according to example embodiments.

[0056] Reference Figure 3 The buffer semiconductor die BSD may include a test logic TLOG, a memory interface MIF, a through silicon via TSV, a direct access (DA) terminal, and the like.

[0057] In some example embodiments, Figure 2 As shown in FIG, the FIM front-end circuit FFEC may be formed or included in the buffer semiconductor die BSD. In other exemplary embodiments, as will be described below with reference to Figure 27 As described, the FIM front-end circuit FFEC may be included in a plurality of memory semiconductor dies.

[0058] Multiple memory banks can form multiple channels that can be independently accessed by a host device. In this case, the FIM front-end circuit FFEC can include multiple FIM channel control circuits FCCC0-FCCC7 corresponding to the multiple channels, respectively. Each of the FIM channel control circuits FCCC0-FCCC7 can control the FIM operation corresponding to each of the multiple channels in the memory bank.

[0059] For ease of illustration and description, Figure 3 Eight FIM channel control circuits FCCC0 to FCCC7 corresponding to eight channels are shown. The number of FIM channel control circuits can be determined according to the channel configuration between the stacked memory device and the host device. Figure 3 It is shown that the FIM channel control circuits FCCC0 ˜ FCCC7 are disposed at an edge portion of the buffer semiconductor die BSD, but example embodiments are not limited to the illustrated layout.

[0060] Figure 4 is a block diagram illustrating a FIM back-end circuit included in a stacked memory device according to example embodiments.

[0061] Figure 4 1 and 2. The diagram shows a plurality of memory banks BNK0 to BNK3 and a FIM back-end circuit FBEC corresponding to one channel formed or included in the memory semiconductor die MSD. For ease of illustration and description, Figure 4 Four memory banks are shown as an example. However, the number of memory banks corresponding to one channel may be determined according to the system configuration. In addition, for ease of illustration and description, Figure 4 A configuration corresponding to one channel in one memory semiconductor die is shown as an example. However, the memory banks included in one memory semiconductor die may form two or more channels. In this case, two or more FIM back-end circuits corresponding to the two or more channels may be included in one memory semiconductor die.

[0062] Reference Figure 4 The FIM backend circuit FBEC corresponding to each channel may include a plurality of memory bank FIM circuits BFC0-BFC3 and an operation controller ALUCON.

[0063] Multiple bank FIM circuits BFC0-BFC3 can be assigned to each of the memory banks BNK0-BNK3 to perform FIM operations associated with the assigned memory bank. The first to fourth bank FIM circuits BFC0-BFC3 can perform data processing based on internal data read from the first to fourth memory banks BNK0-BNK3 and provided via the first to fourth local input-output lines LIOL0-LIOL3, respectively. For example, the first bank FIM circuit BFC0 can receive internal data from the first memory bank BNK0 via the first local input-output line LIOL0 to perform data processing based on the internal data. In addition, the first to fourth bank FIM circuits BFC0-BFC3 can control data communication via the global input-output line GIOL.

[0064] The operation controller ALUCON can generate a FIM die control signal SFD based on the internal instruction signal instr and the FIM channel control signal SFC corresponding to the multiple FIM instructions to control the multiple memory bank FIM circuits BFC0 to BFC3. The internal instruction signal instr and the FIM channel control signal SFC can be obtained from Figure 3 The corresponding FIM channel control circuit is provided. Figures 8 to 12 The internal instruction signal instr, the FIM channel control signal SFC, and the FIM die control signal SFD are further described.

[0065] Figure 5 is a diagram illustrating a high bandwidth memory (HBM) device according to example embodiments.

[0066] Reference Figure 5 , HBM device 1001 may include a stack of multiple DRAM semiconductor dies 1100, 1200, 1300, and 1400. The stacked HBM device 1001 can be optimized with multiple independent interfaces called channels. According to the HBM standard, each DRAM stack can support up to 8 channels. Figure 5 An example stack is shown that includes four DRAM semiconductor dies 1100, 1200, 1300, and 1400, and each DRAM semiconductor die supports two channels, CHANNEL0 and CHANNEL1. Figure 5 As shown in FIG, a fourth memory semiconductor die 1400 may include two memory integrated circuits 1401 and 1402 corresponding to two channels. Each of the two channels CHANNEL0 and CHANNEL1 may be divided into two pseudo channels. In this case, one memory semiconductor die includes four FIM back-end circuits FBEC0 to FBEC3 corresponding to the four pseudo channels (i.e., two channels included in one memory semiconductor die).

[0067] Each channel of the HBM device 1001 can provide access to an independent set of DRAM banks. Requests from one channel cannot access data attached to a different channel. The channels are independently clocked and do not need to be synchronized.

[0068] The HBM 1001 may also include a buffer semiconductor die 1010 disposed at the bottom of the stack structure to provide signal routing and / or other functions. Figure 3 As described, the FIM front-end circuit FFEC may be formed in the buffer semiconductor die 1010. The FIM front-end circuit FFEC may include a plurality of FIM channel control circuits corresponding to the plurality of channels, respectively.

[0069] Figure 6 is a diagram illustrating an example interface of a system including an HBM device according to example embodiments.

[0070] Reference Figure 6 , the system 11 may include an HBM device 1001 and a host device 2000 connected via a plurality of channels CH0-CHn. Each of the channels CH0-CHn may include two pseudo channels PC0 and PC1. For example, Figure 6 As shown in FIG, the signal lines corresponding to one channel CH0 may include a data line PC0 DQ of a first pseudo channel PC0, a data line PC1DQ of a second pseudo channel PC1, and a command-address line CA. The command-address line CA may include a row command-address line ROW CA for transmitting a valid command, a precharge command, etc., and a column command-address line COLUMN CA for transmitting a read command, a write command, etc.

[0071] A typical memory channel includes a command-address (CA) interface and a data (DQ) interface that can be controlled independently of the interfaces of other channels. Figure 6 As shown in , an independent DQ interface and a shared CA interface are included. A pseudo channel can be selected by a time-sharing scheme, and corresponding commands and addresses can be transmitted through the pseudo channel corresponding to the same memory channel. In the present invention, "channel" refers to a "pseudo channel" that can be controlled independently.

[0072] For example, in a 4H-HBM device comprising four stacked memory semiconductor dies, each memory semiconductor die may include two channels or four pseudo channels, and each pseudo channel may include 16 memory banks. In other words, each memory semiconductor die may include 64 memory banks, and the 64 memory banks may be divided into four pseudo channels. In the case of a 4H-HBM device, the FIM front-end circuit FFEC may include 16 FIM channel control circuits corresponding to the 16 pseudo channels, and each memory semiconductor die may include four FIM back-end circuits FBEC corresponding to four pseudo channels.

[0073] Figure 7A and Figure 7B is a diagram illustrating an example format of command-address signals of an HBM device according to example embodiments.

[0074] Figure 7A Shown by Figure 6 The row command-address line ROW CA transmits the row no operation command RNOP, the valid command ACT or the activation command ACT and the precharge command PRE. Figure 7B Shown by Figure 6 The column command-address line COLUMN CA transmits the column no-operation command CNOP, the read command RD and the write command WR.

[0075] Reference Figure 7A and 7B , the command and address transmitted from the host device to the HBM device can be represented by a combination of row CA signals R[0] to R[5] and column CA signals C[0] to C[7]. "H" indicates a logic high level, "L" indicates a logic low level, RA0 to RA14 indicate bits of a row address, BA0 to BA4 indicate bits of a bank address, "V" indicates either a logic high level or a logic low level, CA1 to CA5 indicate bits of a column address, SID indicates an identifier of a memory semiconductor die, and PAR indicates a parity bit.

[0076] For example, the active command ACT may be transmitted during two clock cycles including two rising edges and / or two falling edges, while the precharge command PRE, the read command RD, and the write command WR may be transmitted during one clock cycle. The active command ACT may include bank addresses BA0-BA4 and row addresses RA0-RA14, the precharge command PRE may include bank addresses BA0-BA4, and the read command RD and the write command WR may include bank addresses BA0-BA4 and column addresses CA1-CA5.

[0077] Figure 7A and Figure 7BThe combinations of command-address signals shown in are non-limiting examples, and various combinations may be used.

[0078] A system including a stacked memory device according to example embodiments may operate in at least one of a sequential execution mode and a batch execution mode. In the sequential execution mode, the FIM front-end circuit may execute one FIM instruction among a plurality of FIM instructions stored in the FIM front-end circuit based on a command and an address included in a command-address signal. In the batch execution mode, the FIM front-end circuit may sequentially execute the plurality of FIM instructions stored in the FIM front-end circuit regardless of the command-address signal.

[0079] In the following, reference will be made to Figures 8 to 18B Describes example embodiments associated with sequential execution mode and will refer to Figures 19 to 24B Example embodiments associated with a batch execution mode are described.

[0080] Figure 8 is a diagram illustrating a stacked memory device according to example embodiments.

[0081] Figure 8 The configuration of the buffer semiconductor die BSD and the configuration of the memory semiconductor die MSD corresponding to one channel or one pseudo channel are shown. Figure 8 DRAM is described as an example, and example embodiments may be applied to volatile memory architectures such as DRAM, TRAM, and SRAM, or nonvolatile memory architectures such as ROM, flash memory, FRAM, PRAM, MRAM, etc. Even in Figure 8 Although omitted, the buffer semiconductor die BSD and the memory semiconductor die MSD may also be electrically connected through TSVs and signals may be transmitted through the TSVs.

[0082] Reference Figure 8The buffer semiconductor die BSD may include a physical layer PHY 310, a FIM channel control circuit FCCC110, a command-address (CA) TSV driver 321, a TSV controller 322, a data (DQ) TSV driver 323, and a FIM TSV driver 324. The memory semiconductor die MSD may include a CA TSV buffer 421, a TSV controller 422, a DQ TSV driver 423, a FIM TSV driver 424, a data bus (DBUS) controller 442, a DBUS driver 443, a CA decoder 410, a bank control circuit 430, a row decoder circuit (RDEC) 460, a column decoder circuit (CDEC) 470, a bank cell array or a memory cell array 480, read-write circuits (IOSA / WRDRV) 491 and 492, and FIM back-end circuits 210 and 212. The FIM back-end circuits 210 and 212 may include an operation controller ALUCON 210 and a plurality of bank FIM circuits (BFCs) 212 a ˜ 212 h .

[0083] The memory cell array 480 may include a plurality of memory cell arrays 480a-480h. The row decoder circuit 460 may include a plurality of row decoders RDEC 460a-460h connected to the plurality of memory cell arrays 480a-480h, respectively. The column decoder circuit 470 may include a plurality of column decoders CDEC 470a-470h connected to the plurality of memory cell arrays 480a-480h, respectively. The memory control circuit 430 may include a plurality of memory controllers 430a-430h corresponding to the plurality of memory cell arrays 480a-480h, respectively. The read-write circuits 491 and 492 may include a plurality of input-output sense amplifiers IOSA 491a-491h and a plurality of write drivers WRDRV 492a-492h corresponding to the plurality of memory cell arrays 480a-480h, respectively.

[0084] The physical layer 310 may receive a command-address signal CA from the host device and transmit the command-address signal CA to the CA decoder 410 through the CA TSV driver 321 and the CA TSV buffer 421. In addition, the physical layer 310 may receive data DQ from the host device to transmit the data DQ to the data bus DBUS through the DQ TSV drivers 323 and 423 and the data bus driver 443, and receive the data DQ from the data bus DBUS to transmit the data DQ to the host device.

[0085] The CA decoder 410 may receive a command-address signal CA to generate an internal command signal cmd, a bank address bnk_addr, a row address row_addr, and a column address col_addr. The CA decoder 410 may include a mode register circuit MREG412 to store setting values for controlling the memory semiconductor die MSD. Multiple bank controllers 430a-430h may be enabled (or "enabled") based on the bank address bnk_addr, and the enabled bank controllers may generate an active control signal act_ctrl, a precharge control signal pre_ctrl, a refresh control signal ref_ctrl, a read control signal rd_ctrl, and a write control signal wr_ctrl based on the internal command signal cmd. The row address row_addr, the valid control signal act_ctrl, the precharge control signal pre_ctrl and the refresh control signal ref_ctrl can be provided to the row decoder circuit 460, the column address col_addr can be provided to the column decoder circuit 470, and the read control signal rd_ctrl and the write control signal wr_ctrl can be provided to the read-write circuits 491 and 492.

[0086] The row decoders 460a-460h corresponding to the bank address bnk_addr can decode the row address row_addr to enable the word line corresponding to the row address row_addr. The column decoders 470a-470h corresponding to the bank address bnk_addr can decode the column address col_addr to enable the bit line corresponding to the column address col_addr.

[0087] The input-output sense amplifiers 491a-491h corresponding to the bank address bnk_addr can output the bank data bnk_dt read from the enabled bank cell array through the column decoder. The write drivers 492a-492h corresponding to the bank address bnk_addr can write the bank data bnk_dt to the enabled bank cell array through the column decoder.

[0088] The data bus controller 442 may generate a data bus control signal dbus_ctrl and a TSV disable signal tsv_dis based on the internal command signal cmd and the data bus disable signal dbus_dis. The TSV controllers 322 and 422 may generate a TSV read control signal tsv_rd_ctrl and a TSV write control signal tsv_wr_ctrl based on the internal command signal cmd and the TSV disable signal tsv_dis.

[0089] The FIM channel control circuit 110 can store multiple FIM instructions instr_in based on the command-address signal CA and the data signal DQ from the host device. The multiple FIM instructions instr_in can be provided by the data signal DQ transmitted from the host device. In addition, the FIM channel control circuit FCCC 110 can receive configuration information conf transmitted via the data signal DQ and store the configuration information conf.

[0090] The FIM channel control circuit FCCC 110 may decode a plurality of FIM instructions (instr_in) stored in the FIM channel control circuit 110 to generate an internal instruction signal (instr), and may decode a command-address signal (CA) transmitted from a host device to generate an internal command signal (cmd). Furthermore, the FIM channel control circuit FCCC 110 may generate FIM channel control signals (SFC) based on configuration information (conf) stored in the FIM channel control circuit FCCC 110. The FIM channel control signals (SFC) may include a multi-bank enable signal (mb_en), a bank disable signal (bnk_dis), an operation circuit enable signal (alu_en), and a reset signal (rst).

[0091] The operation controller 210 in the FIM back-end circuits 210 and 212 may generate FIM die control signals SFD for controlling the plurality of memory bank FIM circuits 212 a to 212 h based on the internal instruction signal instr corresponding to the plurality of FIM instructions instr_in stored in the FIM channel control circuit FCCC 110. The FIM die control signals SFD may include a data bus disable signal dbus_dis, a memory bank read disable signal bnk_rd_dis, a memory bank write disable signal bnk_wr_dis, a data bus multiplexer control signal dbmux_ctrl, an operation circuit control signal alu_ctrl, and a register control signal reg_ctrl.

[0092] The bank FIM circuits 212 a ˜ 212 h in the FIM back-end circuits 210 and 212 may be respectively assigned to memory banks to perform FIM operations associated with the assigned memory banks based on the FIM die control signal SFD.

[0093] Each of the bank FIM circuits 212a-212h can perform data processing based on internal data provided from the memory bank via the corresponding input-output sense amplifier. Furthermore, each of the bank FIM circuits 212a-212h can output stored data to the data bus DBUS or write the stored data to the memory bank via the corresponding write driver. Furthermore, each of the bank FIM circuits 212a-212h can store data received via the data bus DBUS or the corresponding input-output sense amplifier. The aforementioned FIM operations may include data processing such as write operations, read operations, and input-output operations.

[0094] Figure 9 It is shown that the Figure 8 A block diagram of an example embodiment of a FIM channel control circuit in a stacked memory device.

[0095] Reference Figure 9 The FIM channel control circuit FCCC corresponding to each channel may include a FIM decoder FIMDEC, a FIM controller FIMCON, a FIM instruction queue FIMIQ and a FIM instruction decoder INSDEC.

[0096] The FIM decoder FIMDEC may decode the command-address signal CA transmitted from the host device to generate an internal command signal cmd and an internal address signal. The internal address signal may include a bank address bnk_addr, a row address row_addr, and a column address col_addr.

[0097] The FIM controller FIMCON may generate a queue control signal based on the internal command signal cmd and the internal address signals bnk_addr, row_addr, and col_addr. The queue control signal may include a queue input control signal in_ctrl and a queue output control signal out_ctrl.

[0098] The FIM controller FIMCON may include a FIM control register FCREG configured to store configuration information conf included in a data signal DQ from a host device based on an internal command signal cmd and internal address signals bnk_addr, row_addr, and col_addr. The FIM controller FIMCON may generate FIM channel control signals SFC (i.e., a multi-bank enable signal mb_en, a bank disable signal bnk_dis, an operation circuit enable signal alu_en, and a reset signal rst) based on the configuration information conf stored in the FIM control register FCREG to control the FIM backend circuit corresponding to each channel. The FIM control register FCREG may be initialized in response to the reset signal rst.

[0099] The FIM command queue FIMIQ may store the FIM command instr_in included in the data signal DQ transmitted from the host device based on the queue input control signal in_ctrl, and output the stored FIM command instr_out based on the queue output control signal out_ctrl.

[0100] The FIM instruction decoder INSDEC may decode the FIM instruction instr_out output from the FIM instruction queue FIMIQ to generate an internal instruction signal instr, and transmit the internal instruction signal instr to a FIM back-end circuit corresponding to each channel.

[0101] Figure 10 It is shown that the Figure 8 A block diagram of an example embodiment of a bank FIM circuit in a stacked memory device.

[0102] Reference Figure 10 The bank FIM circuit BFC corresponding to each memory bank may include an operation circuit ALU, a register file REGFL, and a data path control circuit. The data path control circuit may include a data bus multiplexer DBMUX and an input multiplexer INMUX.

[0103] The operation circuit ALU may perform data processing on at least one of the first source data src1 , the second source data src2 , and the third source data src3 based on the operation circuit control signal alu_ctrl to generate processing result data dst.

[0104] The register file REGFL can store processing result data dst provided by the operation circuit ALU based on the register control signal reg_ctrl. In addition, the register file REGFL can output at least one of first register output data reg_out0, second register output data reg_out1, and third register output data reg_out2 based on the register control signal reg_ctrl. The register file REGFL can be initialized in response to the reset signal rst.

[0105] The data path control circuit including the data bus multiplexer DBMUX and the input multiplexer INMUX may control connections between the input of the operation circuit ALU, the output of the register file REGFL, the memory bank, and the data bus DBUS to communicate with the buffer semiconductor die BSD.

[0106] The data bus multiplexer DBMUX can output data on the data bus DBUS or bank data bnk_dt from the memory bank as operation data alu_dt based on the data bus multiplexer control signal dbmux_ctrl. In addition, the data bus multiplexer DBMUX can output data on the data bus DBUS as bank data bnk_dt to be written to the memory bank, or output bank data bnk_dt read from the memory bank to the data bus DBUS based on the data bus multiplexer control signal dbmux_ctrl.

[0107] The input multiplexer INMUX can receive at least one of the operation data alu_dt, the memory data bnk_dt, the second register output data reg_out1 and the third register output data reg_out2, and provide at least one of the first source data src1, the second source data src2 and the third source data src3 to the operation circuit ALU based on the input multiplexer control signal inmux_ctrl.

[0108] Each operation circuit enable signal per_alu_en may be a signal independently provided to each bank FIM circuit BFC. The corresponding bank FIM circuit BFC may be enabled in response to the each operation circuit enable signal per_alu_en. In multi-bank FIM mode, multiple per operation circuit enable signals per_alu_en[0:m] provided to the multiple bank FIM circuits BFC0 to BFCm may be activated simultaneously or in the same clock cycle, and parallel data processing may be performed by the multiple bank FIM circuits BFC0 to BFCm. In single-bank FIM mode, one of the multiple per operation circuit enable signals per_alu_en[0:m] may be selectively activated, and data processing may be performed by the selected bank FIM circuit.

[0109] Figure 11 is a diagram illustrating an example embodiment of FIM instructions stored in a stacked memory device according to an example embodiment. Figure 11 The example embodiment corresponds to a sequential execution mode.

[0110] Reference Figure 11 , the FIM instruction queue may include an instruction field INSTR, a destination field DST, first to third source fields SRC1, SRC2, and SRC3, and a mask field MASK. In addition, for each FIM instruction in the sequential execution mode, a read command RD and a write command WR, a FIM operation description within the memory semiconductor die, a read data path RDP, and a write data path WDP transmitted from the host device HOST to the stacked memory device MEM are in Figure 11 is shown in .

[0111] In sequential execution mode, according to the read command RD or the write command WR, the instructions stored in the FIM instruction queue can be executed one by one, the storage data read from the memory storage body can be transmitted to the operation circuit in the storage body FIM circuit, and / or the data from the register file can be stored in the memory storage body.

[0112] exist Figure 11 In the example, REGx, REGy, and REGz indicate the addresses or data of the registers included in the register file REGFL. Figure 8IOSA and WRDRV indicate read data (or corresponding address) and write data (or corresponding address) of a memory bank. DBUS indicates data of a data bus or a device identifier of the data bus. Regarding the read data path RDP and the write data path WDP, DISABLE indicates that the corresponding data path is disabled, BANK indicates the corresponding memory bank, ALU indicates an operation circuit included in the corresponding memory bank FIM circuit, and DBUS indicates a data bus.

[0113] An identifier of the FIM instruction may be stored in the instruction field INSTR, and information about corresponding data (eg, a device identifier or address) may be stored in the destination field DST and the first to third source fields SRC1 , SRC2 , and SRC3 .

[0114] The MAC instruction instructs a FIM operation to perform multiplication and addition on the data corresponding to the addresses in the source fields SRC1, SRC2, and SRC3, and to store the resultant data dst at the address in the destination field DST. The MUL instruction instructs a FIM operation to perform multiplication on the data corresponding to the addresses in the source fields SRC1 and SRC2, and to store the resultant data dst at the address in the destination field DST. The ADD / SUB instruction instructs a FIM operation to perform addition / subtraction on the data corresponding to the addresses in the source fields SRC1 and SRC2, and to store the resultant data dst at the address in the destination field DST. The LOAD instruction instructs a FIM operation to load the data corresponding to the address in the source field SRC1 to the address in the destination field DST. The STORE instruction instructs a FIM operation to write the data corresponding to the address in the source field SRC1 to the address in the destination field DST. The MOV instruction instructs a FIM operation to move the data corresponding to the address in the source field SRC1 to the address in the destination field DST. The JUMP instruction indicates an FIM operation of setting a currently executed program counter PCNT to "JUMP TARGET" among a plurality of FIM instructions stored in the FIM instruction queue.

[0115] The mask field MASK stores a mask value to selectively enable multiple memory bank FIM circuits. For example, when the mask value is "000000", the operation circuits ALU in multiple memory bank FIM circuits can be enabled at the same time, and data processing (all alu operations) of multiple memory bank FIM circuits can be performed simultaneously, such as in the same clock cycle. On the contrary, when the mask value is between "110000" and "111111", only one operation circuit ALU corresponding to the mask value in a memory bank FIM circuit can be enabled, and data processing of a memory bank FIM circuit can be performed at each time (single alu operation). Each of the above operation circuit enable signals per_alu_en[0:m] can be generated based on the mask value.

[0116] Figure 12 is a diagram illustrating FIM control signals of a stacked memory device according to example embodiments.

[0117] Reference Figure 12 , the FIM controller may generate a FIM channel control signal SFC, the FIM instruction decoder may generate an internal instruction signal instr, and the operation controller (ALUCON) may generate a FIM die control signal SFD.

[0118] The FIM channel control signals SFC may include a multi-bank enable signal mb_en, a bank disable signal bnk_dis, an operation circuit enable signal alu_en, a reset signal rst, a queue input control signal in_ctrl, and a queue output control signal out_ctrl. The FIM die control signals SFD may include a data bus disable signal dbus_dis, a bank read disable signal bnk_rd_dis, a bank write disable signal bnk_wr_dis, a data bus multiplexer control signal dbmux_ctrl, a per-operation circuit enable signal per_alu_en, an input multiplexer control signal inmux_ctrl, an operation circuit control signal alu_ctrl, and a register control signal reg_ctrl.

[0119] Return to reference Figures 8 to 10 When the multi-bank enable signal mb_en is activated, the bank address bnk_addr may be ignored, and all memory banks may be selected to perform a multi-bank operation. When the multi-bank enable signal mb_en is activated, the operation controller 210 may perform a FIM operation on all memory banks corresponding to each channel. Conversely, when the multi-bank enable signal mb_en is deactivated, a FIM operation may be performed on one memory bank among the memory banks corresponding to each channel.

[0120] When the bank disable signal bnk_dis is activated, the bank controllers 430a-430h may be disabled and the internal command signal cmd may be ignored. When the operation circuit enable signal alu_en is activated, the operation controller 210 may be enabled. When the reset signal rst is activated, the values stored in the FIM control register FCREG and the register file REGFL may be initialized, and the FIM channel control circuit 110 in the FIM front-end circuit may switch the stacked memory device from the FIM mode for performing FIM operations to the normal mode for performing normal operations.

[0121] The FIM command queue FIMIQ can store the FIM command instr_in included in the data signal transmitted from the host device based on the queue input control signal in_ctrl, and output the FIM command instr_out based on the queue output control signal out_ctrl. The FIM command decoder INSDEC can decode the FIM command instr_out from the FIM command queue FIMIQ to generate an internal command signal instr.

[0122] When the data bus disable signal dbus_dis is activated, the data bus controller 442 can electrically disconnect the data bus DBUS from the DQ. When the bank read disable signal bnk_rd_dis is activated, the read control signal rd_ctrl of the read command RD can be disabled, and when the bank write disable signal bnk_wr_dis is activated, the write control signal wr_ctrl of the write command WR can be disabled. The data on the data bus DBUS can be transmitted to the operation circuit ALU as operation data alu_dt. The input multiplexer INMUX, the operation circuit ALU, and the register file REGFL can be independently enabled for the memory bank FIM circuits BFC0 to BFC15 based on the corresponding per-operation circuit enable signal per_alu_en[0:15]. The data transmitted from the input multiplexer INMUX to the operation circuit ALU can be selected based on the input multiplexer control signal inmux_ctrl. The operation circuit ALU can perform data processing on at least one of the first source data src1, the second source data src2, and the third source data src3 based on the operation circuit control signal alu_ctrl to generate processing result data dst. The register file REGFL can store the processing result data dst provided from the operation circuit ALU based on the register control signal reg_ctrl.

[0123] Figure 12Each operation circuit enable signal per_alu_en[0:15] shown in indicates a case where the number of memory banks corresponding to each channel is 16, and the number of each operation circuit enable signals may be determined according to the channel configuration.

[0124] Figure 13 is a diagram illustrating an example embodiment of address mapping for a system including a stacked memory device according to an example embodiment, Figure 14 is a diagram illustrating example data processing performed by a stacked memory device according to example embodiments.

[0125] Reference Figure 13 The host device can allocate a portion of the system address space to set the FIM control address indicating the FIM command queue and the FIM control register. The host device can use normal operation commands and the FIM control address to control the reading and writing operations of FIM commands and configuration information.

[0126] For example, a specific row address row0 of all memory banks can be assigned to the FIM control address. The FIM control address row0 can indicate the FIM instruction queue and the FIM control register regardless of the bank address. The column addresses col0 to col31 combined with the FIM control address row0 can indicate a storage location in the FIM instruction queue, and the column address col32 combined with the FIM control address row0 can indicate the FIM control register.

[0127] Figure 13 The lower right portion of FIG. 1 shows an example embodiment of configuration information stored in the FIM control register. The configuration information stored in the FIM control register may include information about a multi-bank enable signal mb_en, an operation circuit enable signal alu_en, a reset signal rst, a program counter pcnt[0:15], a jump count jump_count, a jump target jump_target, and a batch enable signal batch_en.

[0128] When the multi-bank enable signal mb_en is activated, all memory banks can be activated or precharged simultaneously or in the same clock cycle by the active command ACT or the precharge command PRE. When the operation circuit enable signal alu_en is activated, the operation controller ALUCON can be enabled to perform FIM operations. When the reset signal rst is activated, the values stored in the FIM control register FCREG and the register file REGFL can be initialized. The program counter pcnt[0:15] can be managed by memory bank to indicate the index INDEX of the FIM instruction queue currently to be executed. The jump count jump_count can indicate the number of times the JUMP instruction is executed, and the jump target jump_target can indicate the change in the value of the program counter pcnt[0:15]. Activation of the batch enable signal batch_en can indicate batch execution mode, and deactivation of the batch enable signal batch_en can indicate sequential execution mode.

[0129] exist Figure 13 An example embodiment of a FIM instruction sequence stored in a FIM instruction queue is shown in the lower left portion of FIG. Figure 11 The descriptions are basically the same, and duplicate descriptions are omitted.

[0130] Figure 13 The FIM instruction sequence in corresponds to Figure 14 Matrix-vector multiplication as shown in .

[0131] The data on the data bus DBUS can be stored in the register files REGFL of all bank FIM circuits via MOV instructions with indexes 0 to 31. Each register file REGFL can include multiple data registers REG0 to REG32. The data on the data bus DBUS can be sequentially stored in the data registers REG0 to REG31 via MOV instructions with indexes 0 to 31. The result data of multiplication and addition can be sequentially accumulated in the data register REG32 via MAC instructions with indexes 32 to 63.

[0132] In this way, as Figure 14 As shown in FIG, the final processing result data of the multiplication and addition of the M×N matrix composed of the data in the row 1 of the plurality of memory banks bank0 to bank15 and the N×1 vector composed of the data in the data registers REG0 to REG31 corresponding to the plurality of memory banks bank0 to bank15 can be stored as an M×1 vector in the data register REG32. As described above, when the mask value is "000000", the FIM operation can be performed on all memory banks corresponding to each channel.

[0133] Thereafter, the data accumulated in the data register REG32 corresponding to the plurality of memory banks bank0 to bank15 can be sequentially read out to the data bus DBUS through the MOV instructions of indexes 64 to 80. As described above, when the mask value is between "110000" and "111111", the FIM operation can be performed on one memory bank among the memory banks corresponding to each channel.

[0134] Figures 15A to 15G is a diagram illustrating a data path of an FIM operation in a stacked memory device according to example embodiments.

[0135] The data paths corresponding to various FIM instructions are in Figures 15A to 15G Shown in. Figures 15A to 15G The FIM instructions and control signals in the same as above are omitted. The CSL instruction can be generated by the column decoder 470a~470h based on the column address col_addr and applied to Figure 8 Column selection signals for the memory cell arrays 480a to 480h in FIG.

[0136] Reference Figure 15A The data read out from the memory bank BNK can be output to the input-output sense amplifier IOSA, and the bank data can be provided as the first source data src1 to the operation circuit ALU through the input multiplexer INMUX. The second register output data reg_out1 and the third register output data reg_out2 from the register file REGFL can be provided as the second source data src2 and the third source data src3 to the operation circuit ALU through the input multiplexer INMUX. The operation circuit ALU can perform a MAC operation based on the first to third source data src1-src3 to generate processing result data dst, and can store the processing result data dst in the register file REGFL.

[0137] Reference Figure 15BFirst register output data reg_out0 from register file REGFL can be provided as operation data alu_dt to input multiplexer INMUX via data bus multiplexer DBMUX, and operation data alu_dt can be provided as first source data src1 to operation circuit ALU via input multiplexer INMUX. Second register output data reg_out1 and third register output data reg_out2 from register file REGFL can be provided as second source data src2 and third source data src3 to operation circuit ALU via input multiplexer INMUX. Operation circuit ALU can perform a MAC operation based on the first to third source data src1-src3 to generate processing result data dst, and the processing result data dst can be stored in register file REGFL.

[0138] Reference Figure 15C Data transmitted from the host device may be provided as operation data alu_dt to the input multiplexer INMUX via the physical layer PHY, the DQ TSV driver DTDRV in the buffer semiconductor die BSD, the DQ TSV driver DTDRV in the memory semiconductor die MSD, the data bus driver DBDRV, and the data bus multiplexer DBMUX. The operation data alu_dt may be provided as first source data src1 to the operation circuit ALU via the input multiplexer INMUX. Second register output data reg_out1 and third register output data reg_out2 from the register file REGFL may be provided as second source data src2 and third source data src3 to the operation circuit ALU via the input multiplexer INMUX. The operation circuit ALU may perform a MAC operation based on the first to third source data src1-src3 to generate processing result data dst, and the processing result data dst may be stored in the register file REGFL.

[0139] Reference Figure 15D , a LOAD instruction may be executed so that data read from the memory bank BNK may be loaded into the operation circuit ALU through the input-output sense amplifier IOSA and the input multiplexer INMUX, and the loaded data may be ultimately stored in the register file REGFL.

[0140] Reference Figure 15E , a STORE instruction can be executed so that the data output from the register file REGFL can be written into the memory storage body BNK through the data bus multiplexer DBMUX and the write driver WRDRV.

[0141] Reference Figure 15F, a MOV instruction can be executed so that data output from the register file REGFL can be transmitted to the host device through the data bus driver DBDRV, the DQ TSV driver DTDRV in the memory semiconductor die MSD, the DQ TSV driver DTDRV in the buffer semiconductor die BSD and the physical layer PHY.

[0142] Reference Figure 15G , a MOV instruction can be executed so that data transmitted from the host device can be loaded into the operation circuit ALU through the physical layer PHY, the DQ TSV driver DTDRV in the buffer semiconductor die BSD, the DQ TSV driver DTDRV in the memory semiconductor die MSD, the data bus driver DBDRV, the data bus multiplexer DBMUX and the input multiplexer INMUX, and the loaded data can be finally stored in the register file REGFL.

[0143] 16A to 18B is a diagram illustrating an example operation of a stacked memory device according to example embodiments.

[0144] Figure 16A An example FIM instruction sequence is shown that sequentially includes MOV, MAC, MOV, and MOV instructions stored in FIM instruction queues at indices 0-3. Figure 16B is a diagram showing the implementation of a stacked memory device Figure 16A Timing diagram of the operation of the FIM instruction sequence.

[0145] Reference Figure 16A , the MOV instruction of index 0 indicates a FIM operation in which the same data transmitted from the host device is stored in the register files of all memory banks corresponding to each channel. The MAC instruction of index 1 indicates a FIM operation in which the operation circuits corresponding to multiple memory banks perform a MAC operation simultaneously or in the same clock cycle based on the read data from the multiple memory banks and the data stored in the register files corresponding to the multiple memory banks. The MOV instruction of index 2 indicates a FIM operation in which the data corresponding to the mask value "110000" of the register file is output to the data bus DBUS, and the MOV instruction of index 3 indicates a FIM operation in which the data corresponding to the mask value "110001" of the register file is output to the data bus DBUS. In this way, even in multi-bank FIM mode, FIM operations for multiple memory banks can be restricted according to the mask value.

[0146] Reference Figure 16B, based on the command signal CMD and the address signal ADDR transmitted from the host device, the stacked memory device may perform a FIM entry operation at time points T1 to T4 to convert the operation mode from the normal mode in which the normal operation of the stacked memory device is performed to the FIM mode in which the FIM operation is performed, and perform a FIM exit operation at time points T11 to T13 to convert the operation mode from the FIM mode to the normal mode. Even if Figure 16B The command signal CMD and the address signal ADDR are different from each other, and can also be used as described above. Figure 7A and Figure 7B The command-address signal in which the described command and address are combined provides the command and address from the host device.

[0147] The stacked memory device can operate in a multi-bank FIM mode and a sequential execution mode at time points T5 to T10. The stacked memory device can perform parallel data processing for multiple memory banks in the multi-bank FIM mode. In addition, the stacked memory device can execute one FIM instruction from among multiple FIM instructions stored in the FIM front-end circuit based on a command-address signal, such that the one FIM instruction corresponds to a command and an address included in the command-address signal.

[0148] Reference Figure 8 、 Figure 9 、 Figure 10 、 Figure 16A and Figure 16B At time point T1, the FIM channel control circuit 110 may activate the bank disable signal bnk_dis based on the valid command ACT, the bank address bank0, and the row address row0. When the bank disable signal bnk_dis is activated, the row decoder circuit 460 may ignore the received command. The row address row0 may correspond to the bank address as shown in FIG. Figure 13 Describes the FIM control address.

[0149] At time point T2, based on the write command WR, the bank address bank0 and the column address col0, the FIM channel control circuit 110 can receive and store multiple FIM instructions INSTR through the data signal DQ transmitted from the host device. The column address col0 corresponds to the address of the FIM instruction queue FIMIQ.

[0150] At time T3, the FIM channel control circuit 110 receives and stores configuration information CONF via a data signal DQ transmitted from the host device based on a write command WR, the bank address bank0, and the column address col32. The column address col32 corresponds to the address of the FIM control register FCREG. The FIM channel control circuit 110 activates the multi-bank enable signal mb_en and the operation circuit enable signal alu_en based on the stored configuration information CONF.

[0151] At time point T4 , based on the precharge command PRE and the bank address bank0 , the FIM channel control circuit 110 may deactivate the bank disable signal bnk_dis, and the bank control circuit 430 may perform a precharge operation for all memory banks corresponding to each channel.

[0152] The FIM operation may be performed after the FIM entry operations at time points T1 to T4 are completed.

[0153] At a time point T5 , based on the active command ACT, the bank address bank0 , the row address row1 , and the activated multi-bank enable signal mb_en, the bank control circuit 430 may activate a word line corresponding to the row address row1 for all memory banks.

[0154] At time point T6, based on the write command WR, the memory bank address bank0 and the column address col0, the MOV instruction stored in the FIM instruction queue FIMIQ at index 0 can be executed. The column address col0 corresponds to the index 0 of the FIM instruction queue FIMIQ. Here, the operation controller 210 can activate the memory bank write disable signal bnk_wr_dis to prevent data from being written to the memory bank, and can activate the data bus multiplexer control signal dbmux_ctrl to electrically connect the data bus DBUS and the input multiplexer INMUX. All each operation circuit enable signal per_alu_en[0:15] can be activated (0xFFFF) according to the mask value "000000". Therefore, the register input data reg_in of the data signal DQ transmitted from the host device can be stored in the data register REG0 of the register stack REGFL corresponding to all memory banks.

[0155] At time point T7, based on the read command RD, the memory bank address bank0 and the column address col1, the MAC instruction stored in the FIM instruction queue FIMIQ of index 1 can be executed. The column address col1 corresponds to the index 1 of the FIM instruction queue FIMIQ. Here, the operation controller 210 can activate the data bus disable signal dbus_dis so that the data read from the memory bank can be prevented from being output to the data bus DBUS. All each operation circuit enable signals per_alu_en[0:15] can be activated (0xFFFF) according to the mask value "000000". Therefore, the operation circuit ALU corresponding to all memory banks can perform a MAC operation based on the data read from the row address row1 of the memory bank and the data stored in the registers REG0 and REG32, and the processing result data can be stored in the register REG32.

[0156] At time point T8, based on the read command RD, the memory address bank0 and the column address col2, the MOV instruction stored in the FIM instruction queue FIMIQ of index 2 can be executed. The column address col2 corresponds to index 2 of the FIM instruction queue FIMIQ. Here, the operation controller 210 can activate the memory read disable signal bnk_rd_dis to prevent data from being read out of the memory memory. Even if the multi-memory enable signal mb_en is still activated, only one per-operation circuit enable signal (0x0000) can be activated according to the mask value "110000". Therefore, only one memory FIM circuit corresponding to the activated per-operation circuit enable signal among the memory FIM circuits 212a~212h can be activated, and the register output data reg_out can be output from the data register REG32 of the register stack REGFL of the activated memory FIM circuit to the data bus DBUS.

[0157] At time point T9, based on the read command RD, the memory address bank0 and the column address col3, the MOV instruction stored in the FIM instruction queue FIMIQ of index 3 can be executed. The column address col3 corresponds to the index 3 of the FIM instruction queue FIMIQ. Here, the operation controller 210 can activate the memory read disable signal bnk_rd_dis to prevent data from being read out of the memory memory. Even if the multi-memory enable signal mb_en is still activated, only the other each operation circuit enable signal (0x0001) can be activated according to the mask value "110001". Therefore, only the other memory FIM circuit corresponding to the activated each operation circuit enable signal among the memory FIM circuits 212a~212h can be activated, and the register output data reg_out can be output from the data register REG32 of the register stack REGFL of the activated memory FIM circuit to the data bus DBUS.

[0158] At a time point T10 , based on a precharge command PRE and a bank address bank0 , the bank control circuit 430 may perform a precharge operation on all memory banks corresponding to each channel.

[0159] The FIM exit operation may be performed after all FIM instructions stored in the FIM instruction queue FIMIQ are executed at time points T5 to T10.

[0160] At time point T11, the FIM channel control circuit 110 may activate the bank disable signal bnk_dis based on the active command ACT, the bank address bank0, and the row address row0. As described above, when the bank disable signal bnk_dis is activated, the row decoder circuit 460 may ignore the received command.

[0161] At time T12, the FIM channel control circuit 110 may receive and store configuration information CONF transmitted from the host device based on a write command WR, a bank address bank0, and a column address col32. Here, the configuration information CONF may include information for activating a reset signal rst. The FIM channel control circuit 110 may activate the reset signal rst and, in response to the activated reset signal rst, initialize the values stored in the FIM control register FCREG and the register file REGFL.

[0162] At time point T13 , based on the precharge command PRE and the bank address bank0 , the FIM channel control circuit 110 may deactivate the bank disable signal bnk_dis, and the bank control circuit 430 may perform a precharge operation for all memory banks corresponding to each channel.

[0163] The stacked memory device may perform normal operations after completing the FIM exit operations at time points T11 to T13.

[0164] Figure 17A shows an example FIM instruction sequence sequentially including MOV, MAC, and STORE instructions stored in the FIM instruction queues at indices 0-2, Figure 17B is a diagram showing the implementation of a stacked memory device Figure 17A Timing diagram of the operation of the FIM instruction sequence.

[0165] Reference Figure 17A and Figure 17B The stacked memory device may perform a FIM entry operation at time points T1 to T4 and a FIM exit operation at time points T12 to T14. The stacked memory device may perform a FIM operation in a multi-bank FIM mode and a sequential execution mode at time points T5 to T11.

[0166] Reference Figure 17A The MOV instruction of index 0 indicates a FIM operation in which the same data transferred from the host device is stored in the register files of all memory banks corresponding to each channel. The MAC instruction of index 1 indicates a FIM operation in which the operation circuits corresponding to multiple memory banks perform a MAC operation simultaneously or in the same clock cycle based on the read data from the multiple memory banks and the data stored in the register files corresponding to the multiple memory banks. The STORE instruction of index 2 indicates a FIM operation in which the data of the register files corresponding to all memory banks is stored in all memory banks.

[0167] Figure 17B The operations at time points T1 to T7 and T11 to T14 are the same as Figure 16B The operations at time points T1 to T7 and T10 to T13 are substantially the same, and repeated descriptions are omitted.

[0168] Reference Figure 8 、 Figure 9 、 Figure 10 、 Figure 17A and Figure 17B At time point T8, the bank control circuit 430 may perform a precharge operation based on the precharge command PRE and the bank address bank0.

[0169] At time point T9, based on the active command ACT, the bank address bank0, the row address row2, and the activated multi-bank enable signal mb_en, the bank control circuit 430 may activate the word lines corresponding to the row address row2 for all memory banks. The row address row2 at time point T9 may be different from the row address row1 at time point T5. In other words, the row address row1 of the source data for the MAC operation may be different from the row address row2 of the processed result data to be stored.

[0170] At time point T10, based on the write command, the bank address bank0, and the column address col2, the STORE instruction stored in the FIM instruction queue FIMIQ at index 2 may be executed. The column address col2 corresponds to index 2 of the FIM instruction queue FIMIQ. The register output data reg_out corresponding to the processing result data may be provided to all write drivers 492a-492h to be written to the column address col2 of all memory banks.

[0171] Figure 18A An example FIM instruction sequence is shown that sequentially includes MOV, MAC, and MOV instructions stored in FIM instruction queues at indices 0-2. Figure 18B is a diagram showing the implementation of a stacked memory device Figure 18A Timing diagram of the operation of the FIM instruction sequence.

[0172] Reference Figure 18A and Figure 18B The stacked memory device can perform a FIM entry operation at time points T1 to T4 and a FIM operation at time points T5 to T14 in the single-bank FIM mode and the sequential execution mode. Figure 16B Same as described and Figure 18B Omitted in .

[0173] Reference Figure 18A The MOV instruction with index 0 indicates a FIM operation in which data transmitted from the host device is stored in the register file of one memory bank. The MAC instruction with index 1 indicates a FIM operation in which the operation circuit corresponding to one memory bank performs a MAC operation based on the read data from the one memory bank and the data stored in the register file corresponding to the one memory bank. The MOV instruction with index 2 indicates a FIM operation in which the data of the register file corresponding to the one memory bank is output to the data bus DBUS. In this single-bank FIM mode, the mask value can be ignored.

[0174] Reference Figure 8 、 Figure 9 、 Figure 10 、 Figure 18A and Figure 18B At time point T1, the FIM channel control circuit 110 may activate the bank disable signal bnk_dis based on the valid command ACT, the bank address bank0, and the row address row0. When the bank disable signal bnk_dis is activated, the row decoder circuit 460 may ignore the received command. The row address row0 may correspond to the bank address as shown in FIG. Figure 13 Describes the FIM control address.

[0175] At time point T2, based on the write command WR, the bank address bank0 and the column address col0, the FIM channel control circuit 110 can receive and store multiple FIM instructions INSTR through the data signal DQ transmitted from the host device. The column address col0 corresponds to the address of the FIM instruction queue FIMIQ.

[0176] At time T3, based on a write command WR, bank address bank0, and column address col32, the FIM channel control circuit 110 may receive and store configuration information CONF via a data signal DQ transmitted from the host device. The column address col32 corresponds to the address of the FIM control register FCREG. Based on the stored configuration information CONF, the FIM channel control circuit 110 may activate the operation circuit enable signal alu_en. Here, the configuration information CONF indicates a single-bank FIM mode, and the FIM channel control circuit 110 may maintain the multi-bank enable signal mb_en in a deactivated state.

[0177] At time point T4 , based on the precharge command PRE and the bank address bank0 , the FIM channel control circuit 110 may deactivate the bank disable signal bnk_dis, and the bank control circuit 430 may perform a precharge operation for all memory banks corresponding to each channel.

[0178] The FIM operation may be performed after the FIM entry operations at time points T1 to T4 are completed.

[0179] At a time point T5 , based on the active command ACT, the bank address bank0 , and the row address row1 , the bank control circuit 430 may activate a word line corresponding to the row address row1 for the memory bank corresponding to the bank address bank0 .

[0180] At time point T6, based on the write command WR, the memory bank address bank0, and the column address col0, the MOV instruction stored in the FIM instruction queue FIMIQ at index 0 may be executed. Column address col0 corresponds to index 0 of the FIM instruction queue FIMIQ. Here, the operation controller 210 may activate the memory bank write disable signal bnk_wr_dis to prevent data from being written to the memory bank, and activate the data bus multiplexer control signal dbmux_ctrl to electrically connect the data bus DBUS and the input multiplexer INMUX. Therefore, the register input data reg_in of the data signal DQ transmitted from the host device may be stored in the data register REG0 corresponding to the memory bank address bank0 of the register file REGFL.

[0181] At time point T7, based on the read command RD, the bank address bank0, and the column address col1, the MAC instruction stored in the FIM instruction queue FIMIQ at index 1 can be executed. The column address col1 corresponds to index 1 of the FIM instruction queue FIMIQ. Here, the operation controller 210 can activate the data bus disable signal dbus_dis, so that the data read from the memory bank can be prevented from being output to the data bus DBUS. Therefore, the operation circuit ALU corresponding to the bank address bank0 can perform a MAC operation based on the data read from the row address row1 of the memory bank and the data stored in the registers REG0 and REG32, and the processing result data can be stored in the register REG32.

[0182] At time point T8, based on the read command RD, the memory address bank0 and the column address col2, the MOV instruction stored in the FIM instruction queue FIMIQ of index 2 can be executed. The column address col2 corresponds to the index 2 of the FIM instruction queue FIMIQ. Here, the operation controller 210 can activate the memory read disable signal bnk_rd_dis to prevent data from being read out of the memory bank. Only one per-operation circuit enable signal corresponding to the memory address bank0 can be activated. Therefore, only one memory bank FIM circuit corresponding to the memory address bank0 can be activated among the multiple memory bank FIM circuits 212a~212h, and the register output data reg_out can be output from the data register REG32 of the activated memory bank FIM circuit to the data bus DBUS.

[0183] At time point T9 , based on the precharge command PRE and the bank address bank0 , the bank control circuit 430 may perform a precharge operation on the memory bank corresponding to the bank address bank0 .

[0184] Thus, all FIM instructions stored in the FIM instruction queue FIMIQ may be executed at time points T5 to T9. The value of the program counter PCNT[bank0] corresponding to the bank address bank0 may be sequentially increased by 1, such as 0x0, 0x1, and 0x2.

[0185] At time points T10 to T14, operations substantially the same as those at time points T5 to T9 may be performed for the memory address bank 1. Here, only one per-operation circuit enable signal corresponding to the memory address bank 1 is activated, and the value of the program counter PCNT[bank0] corresponding to the memory address bank 1 may be sequentially increased by 1, such as 0x0, 0x1, and 0x2.

[0186] Figure 19 is a diagram illustrating a stacked memory device according to example embodiments. Figure 19 The configuration shown in Figure 8 The configurations shown in are basically the same, and duplicate descriptions are omitted and only different points are described.

[0187] Reference Figure 19 , Figure 19 The stacked memory device is shown to be capable of selectively executing a sequential execution mode or a batch execution mode. Figures 8 to 18B The sequential execution mode described is the same and will refer to Figures 19 to 24B Describes batch execution mode.

[0188] Figure 19 The FIM channel control circuit (FCCC) 110a in the FIM front-end circuit may receive configuration information indicating a sequential execution mode or a batch execution mode. When the configuration information indicates the sequential execution mode, the FIM channel control circuit (FCCC) 110a included in the FIM front-end circuit may execute one FIM instruction from among a plurality of FIM instructions stored in the FIM channel control circuit (FCCC) 110a based on the command-address signal, such that one FIM instruction corresponds to a command and an address included in the command-address signal. Conversely, when the configuration information indicates the batch execution mode, the FIM channel control circuit (FCCC) 110a may sequentially execute the plurality of FIM instructions stored in the FIM channel control circuit (FCCC) 110a regardless of the command-address signal.

[0189] When execution of multiple FIM instructions stored in the FIM front-end circuit is completed in the batch execution mode, the FIM channel control circuit (FCCC) 110a may generate a FIM end signal DONE and transmit the FIM end signal DONE to the host device through the physical layer 310a.

[0190] In addition, the FIM channel control circuit (FCCC) 110a may generate an internal command-address signal CA_IN based on a plurality of FIM instructions stored in the FIM channel control circuit (FCCC) 110a to control a plurality of memory banks.

[0191] Figure 20 It is shown that the Figure 19 A block diagram of an example embodiment of a FIM channel control circuit in a stacked memory device.

[0192] Reference Figure 20 The FIM channel control circuit FCCC corresponding to each channel may include a FIM decoder FIMDEC, a FIM controller FIMCON, a FIM instruction queue FIMIQ, a FIM instruction decoder INSDEC and a command-address generator CAGEN. Figure 20 Components other than the command-address generator CAGEN Figure 9 The components in FIG. 1 are the same or similar, and repeated descriptions are omitted.

[0193] The FIM controller FIMCON may generate a batch enable signal batch_en based on the configuration information conf stored in the FIM control register FCREG. Activation of the batch enable signal batch_en may indicate a batch execution mode, and deactivation of the batch enable signal batch_en may indicate a sequential execution mode.

[0194] When the batch enable signal batch_en is activated, the command-address generator CAGEN may generate the internal command-address signal CA_IN based on the internal instruction signal instr. Figure 20 As shown in FIG, the internal command-address signal CA_IN may be provided to the CA decoder 410 to replace the command-address signal CA provided from the host device.

[0195] Reference Figure 10 The description of the bank FIM circuit BFC can be applied to Figure 19 The configuration shown in .

[0196] Figure 21 is a diagram illustrating example FIM instructions stored in a stacked memory device according to an example embodiment.

[0197] Figure 21 FIG. 4 shows an FIM instruction for executing one of a sequential execution mode and a batch execution mode applied to a stacked memory device. Figure 11 Duplicate description.

[0198] Reference Figure 21In the batch execution mode, the command transmitted from the host device HOST to the stacked memory device MEM may be omitted.

[0199] Compared to sequential execution mode, batch execution mode does not require the use of MOV instructions. In addition, ACT instructions for activating a memory bank and PRE instructions for precharging a memory bank may be used. In the case of the ACT instruction, the bank address and row address to be accessed may be stored in the destination field DST and the first to third source fields SRC1-SRC3. In the case of the PRE instruction, the bank address to be precharged may be stored in the destination field DST. In addition, in some instructions, the value of the mask field MASK may be replaced by the column address.

[0200] Figure 22 is a diagram illustrating example FIM control signals of a stacked memory device according to example embodiments. Figure 22 FIM control signal and reference Figure 12 The control signals described are almost the same, and repeated descriptions are omitted.

[0201] Reference Figure 22 To implement the batch execution mode, the FIM channel control circuit FCCC may also generate a batch enable signal, batch_en, and a FIM end signal, DONE. Activation of the batch enable signal, batch_en, may indicate the batch execution mode, and deactivation of the batch enable signal, batch_en, may indicate the sequential execution mode. Upon completion of execution of multiple FIM instructions stored in the FIM front-end circuit in the batch execution mode, the FIM channel control circuit FCCC may activate the FIM end signal, DONE, and transmit the activated FIM end signal, DONE, to the host device via the physical layer 310a.

[0202] In addition, in order to implement the batch execution mode, as mentioned above Figure 20 As described, the FIM channel control circuit FCCC may further include a command-address generator CAGEN. The command-address generator CAGEN may be disabled in sequential execution mode and enabled in batch execution mode based on a batch enable signal batch_en. The command-address generator CAGEN may generate an internal command-address signal CA_IN based on an internal instruction signal instr in batch execution mode.

[0203] Figures 23A to 24B is a diagram illustrating an example operation of a stacked memory device according to example embodiments.

[0204] Figure 23Ashows an example FIM instruction sequence sequentially including ACT, LOAD, PRE, ACT, MAC, PRE, ACT, STORE, and PRE instructions stored in FIM instruction queues indexed 0 through 8, Figure 23B is a diagram showing the implementation of a stacked memory device Figure 23A Timing diagram of the operation of the FIM instruction sequence.

[0205] Reference Figure 23A and Figure 23B Based on the command signal CMD and the address signal ADDR transmitted from the host device, the stacked memory device can perform a FIM entry operation at time points T1 to T4 to switch the operation mode from a normal mode in which the stacked memory device performs normal operations to a FIM mode in which the FIM operation is performed. The stacked memory device can perform the FIM operation at time points T5 to T13 in the multi-bank FIM mode and the batch execution mode. The FIM exit operation is similar to the reference operation. Figure 16B The exit operation is the same as described in Figure 23B is omitted.

[0206] The stacked memory device can perform FIM operations at time points T5 to T13 in a batch execution mode to sequentially execute multiple FIM instructions stored in the FIM instruction queue FIMIQ in the FIM channel control circuit FCCC, regardless of the command-address signal. As described above, the command-address generator CAGEN can generate an internal command-address signal CA_IN to provide the command and address to the CA decoder 410. Even in Figure 23B The command signal CMD and the address signal ADDR are different from each other, and the host device may also provide the command and address through the command-address signal. Figure 7A and Figure 7B The described commands and addresses are combined. In addition, an internal command-address signal CA_IN in which the command and address are combined may be provided to the CA decoder 410 from the command-address generator CAGEN.

[0207] Reference Figure 19 、 Figure 20 、 Figure 10 、 Figure 23A and Figure 23B At time point T1, the FIM channel control circuit 110a may activate the bank disable signal bnk_dis based on the valid command ACT, the bank address bank0, and the row address row0. When the bank disable signal bnk_dis is activated, the row decoder circuit 460 may ignore the received command. The row address row0 may correspond to the bank address as shown in FIG. Figure 13 Describes the FIM control address.

[0208] At time point T2, based on a write command WR, a bank address bank0, and a column address col0, the FIM channel control circuit 110a receives and stores a plurality of FIM instructions INSTR via a data signal DQ transmitted from the host device. The column address col0 corresponds to the address of the FIM instruction queue FIMIQ.

[0209] At time T3, the FIM channel control circuit 110a receives and stores configuration information CONF via a data signal DQ transmitted from the host device based on a write command WR, a bank address bank0, and a column address col32. The column address col32 corresponds to the address of the FIM control register FCREG. The FIM channel control circuit 110a activates the multi-bank enable signal mb_en and the operation circuit enable signal alu_en based on the stored configuration information CONF.

[0210] At time point T4 , based on the precharge command PRE and the bank address bank0 , the FIM channel control circuit 110 a may deactivate the bank disable signal bnk_dis, and the bank control circuit 430 may perform a precharge operation for all memory banks corresponding to each channel.

[0211] The FIM operation can be performed after the FIM entry operation at time points T1 to T4 is completed. Since the configuration information CONF indicates the batch execution mode, the command-address generator CAGEN can be enabled. At time points T5 to T13, the command-address generator CAGEN can be enabled as shown in FIG. Figure 23A As shown in FIG, commands CMD and addresses ADDR corresponding to FIM instructions of indexes 0 to 8 are sequentially generated.

[0212] At time point T5, based on the activated multi-bank enable signal mb_en and the valid command ACT, bank address bank0, and row address row1 generated by decoding the ACT instruction of index 0, the bank control circuit 430 can activate the word line corresponding to the row address row1 for all memory banks.

[0213] At time point T6, based on the write command WR or read command RD generated by decoding the LOAD instruction of index 1, the bank address bank0 and the column address col0, data can be read from the memory bank. In batch execution mode, the bank write disable signal bnk_wr_en and the bank read disable signal bank_rd_en can be deactivated. All per-operation circuit enable signals per_alu_en[0:15] can be activated (0xFFFF) according to the mask value "000000". Therefore, the data read from the row address row1 and column address col0 of all memory banks can be stored in the register file REGFL of all bank FIM circuits 212.

[0214] At time points T6, T9, and T12, when a read command RD or a write command WR is internally generated by the command-address generator CAGEN in the batch execution mode, the operation controller 210 may activate the data bus enable signal dbus_dis to electrically disconnect the data bus DBUS from the read-write circuits 491 and 492.

[0215] At time point T7 , based on the precharge command PRE and the bank address bank0 generated by decoding the PRE instruction of index 2 , the bank control circuit 430 may perform a precharge operation on all memory banks corresponding to each channel.

[0216] At time point T8 , based on the valid command ACT, the bank address bank0 , and the row address row2 generated by decoding the ACT instruction of index 3 , the bank control circuit 430 may activate word lines corresponding to the row address row2 for all memory banks.

[0217] At time point T9, based on the read command RD, bank address bank0, and column address col0 generated by decoding the MAC instruction of index 4, data can be read from all memory banks. All per-operation circuit enable signals per_alu_en[0:15] can be activated (0xFFFF) according to the mask value "000000". Therefore, the operation circuits ALU corresponding to all memory banks can perform MAC operations based on the data read from the row address row2 and column address col0 of all memory banks and the data stored in registers REG0 and REG32, and the processing result data can be stored in register REG32.

[0218] At a time point T10 , based on a precharge command PRE and a bank address bank0 generated by decoding a PRE instruction of index 5 , the bank control circuit 430 may perform a precharge operation on all memory banks corresponding to each channel.

[0219] At time point T11 , based on the valid command ACT, the bank address bank0 , and the row address row3 generated by decoding the ACT instruction of index 6 , the bank control circuit 430 may activate word lines corresponding to the row address row3 for all memory banks.

[0220] At time point T12, based on the write command WR, storage body address bank0 and column address col0 generated by decoding the STORE instruction of index 7, the register output data corresponding to the processing result data can be provided to the write drivers 492a~492h and written into the row address row3 of all memory storage bodies.

[0221] At a time point T13 , based on a precharge command PRE and a bank address bank0 generated by decoding a PRE instruction of index 8 , the bank control circuit 430 may perform a precharge operation on all memory banks corresponding to each channel.

[0222] When all FIM instructions stored in the FIM instruction queue FIMIQ are completed, the FIM channel control circuit 110a can activate the FIM end signal DONE and provide the FIM end signal DONE to the host device through the physical layer 310a. The host device can perform the FIM exit operation as described above in response to the activated FIM end signal DONE.

[0223] Figure 24A shows an example FIM instruction sequence sequentially including ACT, LOAD, PRE, ACT, MAC, PRE, ACT, STORE, and PRE instructions stored in FIM instruction queues indexed 0-8, Figure 24B is a diagram showing the implementation of a stacked memory device Figure 24A The timing diagram of the operation of the FIM instruction sequence is omitted below. Figure 23A and Figure 23B Duplicate description.

[0224] Figure 24A The FIM instruction sequence is the same as Figure 23A The FIM instruction sequence is the same. Figure 24B shows operation in single-bank FIM mode, while Figure 23B Operation in multi-bank FIM mode is shown.

[0225] Reference Figure 24B , the multi-bank enable signal mb_en is deactivated in the single-bank FIM mode. In addition, the mask value can be ignored, and only one per-operation circuit enable signal (0xFFFE) corresponding to one memory bank can be activated in the single-bank FIM mode. Therefore, a FIM operation can be performed for one activated memory bank.

[0226] Figures 25 to 27 is a diagram illustrating a package structure of a stacked memory device according to example embodiments.

[0227] Reference Figure 25 The memory chip 2001 may include an interposer ITP and a stacked memory device stacked on the interposer ITP. The stacked memory device may include a buffer semiconductor die BSD and a plurality of memory semiconductor dies MSD1-MSD4.

[0228] Reference Figure 26 and 27 Each of the memory chips 2002 and 2003 may include a base substrate BSUB and a stacked memory device stacked on the base substrate BSUB. The stacked memory device may include a buffer semiconductor die BSD and a plurality of memory semiconductor dies MSD1 to MSD4.

[0229] Figure 25 A structure is shown in which the memory semiconductor dies MSD1 to MSD4 except the buffer semiconductor die BSD are vertically stacked and the buffer semiconductor die BSD is electrically connected to the memory semiconductor dies MSD1 to MSD4 through an interposer ITP or a base substrate. Figure 26 and Figure 27 The structure in which the buffer semiconductor die BSD and the memory semiconductor dies MSD1 - MSD4 are vertically stacked is shown.

[0230] like Figures 25 to 27 As shown in FIG, the plurality of FIM back-end circuits FBEC1 ˜ FBEC4 described above may be formed or included in the memory semiconductor dies MSD1 ˜ MSD4 .

[0231] In some example embodiments, Figure 25 and 26 As shown in , the plurality of FIM channel control circuits FCCC1 ˜ FCCC4 of the FIM front-end circuit described above may be included in the buffer semiconductor die BSD. In other example embodiments, the plurality of FIM channel control circuits FCCC1 ˜ FCCC4 may be distributed and included in the memory semiconductor dies MSD1 ˜ MSD4 , respectively.

[0232] Figures 25 to 27An example embodiment in which one memory semiconductor die corresponds to one channel is shown, but example embodiments are not limited thereto. As described above, one memory semiconductor die may correspond to two or more channels, and the number of FIM back-end circuits and the number of FIM channel control circuits included in each memory semiconductor die may be determined according to the channel configuration.

[0233] The base substrate BSUB may be the same as or include the interposer ITP. The base substrate BSUB may be a printed circuit board (PCB). External connection elements such as conductive bumps BMP may be formed on the lower surface of the base substrate BSUB, and internal connection elements such as conductive bumps may be formed on the upper surface of the base substrate BSUB. Figure 25 In an example embodiment, the buffer semiconductor die BSD and the memory semiconductor dies MSD1 to MSD4 may be electrically connected through through-silicon vias. The stacked semiconductor dies BSD and MSD1 to MSD4 may be packaged using a resin RSN.

[0234] Figure 28 is a perspective view of a semiconductor package including a stacked memory device according to example embodiments.

[0235] Reference Figure 28 , the semiconductor package 3000 may include one or more stacked memory devices 3100 , a central processing unit (CPU) 3200 , and a graphics processing unit (GPU) 3250 .

[0236] The stacked memory device 3100, the CPU 3200, and the GPU 3250 may be mounted on the interposer 3300, and the interposer 3300 on which the stacked memory device 3100, the CPU 3200, and the GPU 3250 are mounted may be mounted on the package substrate 3400. The CPU 3200 or the GPU 3250 may be implemented to perform the functions of the above-described host device. The CPU 3200 and the GPU 3250 may correspond to Figure 1 The CPU 2120 and the GPU 2130 in the processor.

[0237] The stacked memory device 3100 may be implemented in various forms, and may be a high-bandwidth memory (HBM) memory device in which multiple layers are stacked. Therefore, the stacked memory device 3100 may include a buffer semiconductor die and a plurality of memory semiconductor dies. The buffer semiconductor die may include a FIM front-end circuit (FFEC) and a plurality of FIM back-end circuits according to example embodiments to efficiently perform FIM operations.

[0238] For example, each of the stacked memory device 3100, the CPU 3200, and the GPU 3250 may include a physical layer (PHY), and communication may be performed through the physical layer among the stacked memory device 3100, the CPU 3200, and the GPU 3250. When the stacked memory device 3100 includes a direct access area, a test signal may be provided to the stacked memory device 3100 through conductive means (e.g., solder balls 3500) mounted below the package substrate 3400 and the direct access area.

[0239] As described above, the stacked memory devices, systems, and methods according to example embodiments can reduce the power consumption and latency of the stacked memory devices and systems by using the FIM back-end circuitry integrated in the stacked memory devices to perform memory-intensive or data-intensive data processing. Furthermore, data processing time can be reduced by using the bank FIM circuitry assigned to the memory banks to perform data processing in parallel. Furthermore, by storing FIM instructions in the FIM front-end circuitry and performing FIM operations based on the stored FIM instructions, complex data processing can be efficiently performed and system performance can be enhanced.

[0240] The inventive concept can be applied to any electronic device and system that includes a memory device. For example, the inventive concept can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash memory (UFS), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, and the like.

[0241] The above is an illustration of example embodiments and should not be construed as limiting thereof. Although several example embodiments have been described, it will be readily apparent to those skilled in the art that many modifications can be made to the example embodiments without substantially departing from the inventive concept.

Claims

1. A stacked memory device, comprising: a buffer semiconductor die configured to communicate with a host device; a plurality of memory semiconductor dies stacked on the buffer semiconductor die, the plurality of memory semiconductor dies comprising a plurality of memory banks; a plurality of through-silicon vias electrically connecting the buffer semiconductor die to the plurality of memory semiconductor dies; a memory function front-end circuit configured to receive a plurality of memory function instructions for memory function operations from a host device and store the plurality of memory function instructions, wherein the memory function operations include data processing based on internal data read from the plurality of memory banks; and and a plurality of memory function back-end circuits located in corresponding memory semiconductor dies among the plurality of memory semiconductor dies, wherein the plurality of memory function back-end circuits are configured to perform memory function operations corresponding to the plurality of memory function instructions stored in the memory function front-end circuit under the control of the memory function front-end circuit.

2. The stacked memory device according to claim 1, wherein: The memory function front-end circuit is configured to switch an operation mode from a normal mode for performing normal operation of the stacked memory device to a memory function mode for performing memory function operation, or to switch from the memory function mode to the normal mode based on a command-address signal transmitted from the host device.

3. The stacked memory device according to claim 2, wherein: The memory function front-end circuit is configured to receive the plurality of memory function instructions through a data signal transmitted from the host device when the memory function front-end circuit switches an operation mode from a normal mode to a memory function mode.

4. The stacked memory device according to claim 2, wherein: The memory function front-end circuit is configured to receive configuration information for controlling the plurality of memory function back-end circuits through a data signal transmitted from a host device when the memory function front-end circuit switches an operation mode from a normal mode to a memory function mode.

5. The stacked memory device according to claim 4, wherein: When the configuration information indicates the sequential execution mode, the memory function front-end circuit is configured to execute one memory function instruction among the plurality of memory function instructions stored in the memory function front-end circuit based on the command-address signal, wherein the one memory function instruction corresponds to a command and an address included in the command-address signal.

6. The stacked memory device according to claim 4, wherein: When the configuration information indicates the batch execution mode, the memory function front-end circuit is configured to sequentially execute the plurality of memory function instructions stored in the memory function front-end circuit regardless of the command-address signal.

7. The stacked memory device according to claim 6, wherein: When execution of the plurality of memory function instructions stored in the memory function front end circuit is completed in the batch execution mode, the memory function front end circuit is configured to generate a memory function end signal and transmit the memory function end signal to the host device.

8. The stacked memory device according to claim 6, wherein: The memory function front-end circuit is configured to generate internal command-address signals for controlling the plurality of memory banks based on the plurality of memory function instructions stored in the memory function front-end circuit in a batch execution mode.

9. The stacked memory device according to claim 1, in, The plurality of memory banks form a plurality of channels that are independently accessed by a host device, and Among them, the memory function front-end circuit includes a plurality of memory function channel control circuits, and the plurality of memory function channel control circuits are configured to control the memory function operation of each memory storage body corresponding to each channel among the plurality of channels.

10. The stacked memory device according to claim 9, wherein The plurality of memory function channel control circuits are all included in the buffer semiconductor die.

11. The stacked memory device according to claim 9, wherein: Each of the plurality of memory function channel control circuits is included in one memory semiconductor die, the one memory semiconductor die including a memory bank corresponding to each of the plurality of channels.

12. The stacked memory device according to claim 9, wherein Each of the plurality of memory function channel control circuits comprises: a memory function decoder configured to decode a command-address signal transmitted from a host device to generate an internal command signal and an internal address signal; a memory function controller configured to generate a queue control signal based on the internal command signal and the internal address signal; a memory function instruction queue configured to store a memory function instruction included in a data signal transmitted from a host device based on a queue control signal and output the stored memory function instruction; and The memory function instruction decoder is configured to decode the memory function instruction output from the memory function instruction queue to generate an internal instruction signal, and transmit the internal instruction signal to the memory function back-end circuit corresponding to each channel.

13. The stacked memory device according to claim 12, wherein: The memory function controller includes: a memory function control register configured to store configuration information included in a data signal from a host device based on an internal command signal and an internal address signal, The memory function controller generates a memory function channel control signal based on configuration information stored in the memory function control register to control the memory function back-end circuit corresponding to each channel.

14. The stacked memory device according to claim 13, in, Memory function channel control signals include multi-bank enable signals, The memory function backend circuit corresponding to each channel is configured to perform memory function operations for the memory banks corresponding to each channel in the same clock cycle when the multi-bank enable signal is activated, and The memory function backend circuit corresponding to each channel is configured to perform a memory function operation on one of the memory banks corresponding to each channel when the multi-bank enable signal is deactivated.

15. The stacked memory device according to claim 13, wherein: The host device is configured to allocate a portion of the system address space to set a memory function control address indicating a memory function instruction queue and a memory function control register, and is configured to control read and write operations of memory function instructions and configuration information using the memory function control address and commands for normal operation of the stacked memory device.

16. The stacked memory device according to claim 9, wherein The memory function backend circuit corresponding to each channel includes: a plurality of bank memory function circuits associated with respective ones of the memory banks, wherein some of the plurality of bank memory function circuits are configured to perform memory function operations on respective ones of the memory banks; and an operation controller configured to generate memory function die control signals for controlling the plurality of memory bank memory function circuits based on an internal instruction signal and memory function channel control signals corresponding to the plurality of memory function instructions, wherein the internal instruction signal and the memory function channel control signals are provided from corresponding memory function channel control circuits among the plurality of memory function channel control circuits.

17. The stacked memory device according to claim 16, wherein: Each of the plurality of memory bank function circuits comprises: an operation circuit configured to perform data processing to generate processing result data; a register file configured to store processing result data provided from the operation circuit; and The data path control circuit is configured to control connections between inputs of the operation circuit, outputs of the register file, memory banks, and a data bus configured to communicate with the buffer semiconductor die.

18. The stacked memory device according to claim 1, wherein The stacked memory device comprises a high bandwidth memory device.

19. An electronic system, comprising: stacked memory devices; and a host device configured to control the stacked memory device, The stacked memory device includes: a buffer semiconductor die configured to communicate with a host device; a plurality of memory semiconductor dies stacked on the buffer semiconductor die, the plurality of memory semiconductor dies comprising a plurality of memory banks; a plurality of through-silicon vias electrically connecting the buffer semiconductor die to the plurality of memory semiconductor dies; a memory function front-end circuit configured to receive a plurality of memory function instructions for memory function operations from a host device and store the plurality of memory function instructions, wherein the memory function operations include data processing based on internal data read from the plurality of memory banks; and and a plurality of memory function back-end circuits located in corresponding memory semiconductor dies among the plurality of memory semiconductor dies, wherein the plurality of memory function back-end circuits are configured to perform memory function operations corresponding to the plurality of memory function instructions stored in the memory function front-end circuit under the control of the memory function front-end circuit.

20. A method of operating a stacked memory device comprising a buffer semiconductor die configured to communicate with a host device and a plurality of memory semiconductor die comprising a plurality of memory banks, wherein: The buffer semiconductor die and the plurality of memory semiconductor dies are stacked, the method comprising: transmitting a plurality of memory function instructions for memory function operations from a host device to the stacked memory device, wherein the memory function operations include data processing based on internal data read from a plurality of memory banks; storing the plurality of memory function instructions in a memory function front-end circuit located in a buffer semiconductor die or located in the plurality of memory semiconductor dies; and Using a plurality of memory function back-end circuits included in corresponding memory semiconductor dies among the plurality of memory semiconductor dies, memory function operations corresponding to memory function instructions stored in the memory function front-end circuits are performed under the control of the memory function front-end circuits.

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