Semiconductor device and method of forming the same

Abstract

A method includes providing a structure having a first fin and a second fin above a substrate and generally longitudinally oriented along a first direction and source / drain (S / D) components above the first fin and the second fin; forming an interlayer dielectric (ILD) layer covering the S / D components; performing a first etching process on at least a region between the S / D components to form trenches in the ILD layer; depositing a dielectric material in the trenches; performing a second etching process to selectively recess the dielectric material; and then performing a third etching process to selectively recess the ILD layer to form contact holes exposing the S / D components. According to other embodiments of the present application, semiconductor devices are also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple IC eras, each having smaller and more complex circuits than the previous era. During the evolution of ICs, the functional density (i.e., the number of interconnected devices per chip area) generally increases while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. This scaling process typically provides benefits by increasing production efficiency and reducing associated costs. This scaling also increases the complexity of processing and manufacturing ICs.

[0003] For example, when forming n-type and p-type epitaxial source / drain (S / D) components for small-scale transistors, such as field-effect transistors (FETs) with fin channels (so-called "FinFETs"), sometimes the fins in the S / D region first recess. A patterned resist (or photoresist) is used to expose regions of one type of FinFET (e.g., p-type FinFETs) while covering other regions of the other type of FinFET (e.g., n-type FinFETs). However, implementing such an IC manufacturing process presents challenges, especially when scaling IC components at advanced process nodes. For example, as scaling continues, the distance between adjacent gate structures above the fins decreases. Along with the decrease in gate distance, it becomes difficult to remove the resist material stacked between the gate structures during resist material patterning, resulting in resist residues remaining. In particular, along the boundary line between different regions for n-type and p-type FinFETs, the resist material can form curved sidewalls. The curved sidewalls can extend into the regions that should be exposed and cover the fins near the boundary line, which may cause uniformity issues in fin height after fin recess, thus deteriorating device performance. The purpose of the present disclosure is to solve this problem, etc. Summary of the Invention

[0004] According to an embodiment of the present application, a method of forming a semiconductor device is provided, including: providing a structure including a substrate, fins protruding from the substrate, an isolation component surrounding the fins, and a gate structure joined to the fins; depositing a resist layer covering the fins, the isolation component, and the gate structure; performing a first etching process to recess the resist layer below the top surface of the gate structure; performing a second etching process to further recess the resist layer, wherein the second etching process has a higher etching rate than the first etching process; performing a third etching process to remove the resist layer, wherein the third etching process has a lower etching rate than the second etching process; recessing the fins; and forming an epitaxial source / drain (S / D) component over the fins.

[0005] According to another embodiment of the present application, a method of forming a semiconductor device is provided, including: providing a structure including a substrate having a first region and a second region, an isolation component above the substrate, a first fin extending from the first region of the substrate and passing through the isolation component, a second fin extending from the second region of the substrate and passing through the isolation component, and a gate structure joined to the first fin and the second fin; recessing the first fin and a first portion of the isolation component surrounding the first fin; epitaxially growing a first source / drain (S / D) component on the first fin; recessing the second fin and a second portion of the isolation component surrounding the second fin, thereby forming a protruding portion of the isolation component between the first portion and the second portion; and epitaxially growing a second S / D component on the second fin.

[0006] According to yet another embodiment of the present application, a semiconductor device is provided, including: a substrate having a p-type region and an n-type region; an isolation component above the substrate; a first fin protruding from the substrate and passing through the isolation component in the p-type region; a p-type epitaxial component above the source / drain (S / D) region of the first fin; a second fin protruding from the substrate and passing through the isolation component in the n-type region; and an n-type epitaxial component above the S / D region of the second fin, wherein a portion of the isolation component spanning the p-type region and the n-type region is higher than other portions of the isolation component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure can be better understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of various components can be arbitrarily increased or decreased.

[0008] Figure 1A 、 Figure 1B and Figure 1C show flowcharts of methods for forming semiconductor devices according to aspects of the present disclosure.

[0009] Figure 2 Shows a perspective view of a semiconductor structure during a manufacturing process in accordance with a method according to some embodiments. Figures 1A - 1C

[0010] Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A, Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A ,Figure 24B , Figure 24C and Figure 25 show cross-sectional views of semiconductor structures during a manufacturing process in accordance with a method according to Figures 1A - 1C . DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for simplicity and clarity purposes and does not in itself dictate a relationship between the various embodiments and / or structures discussed.

[0012] Furthermore, spatial relative terms, such as "beneath", "below", "lower", "above", "upper", etc., may be used herein for ease of description to describe the relationship of one element or component shown in the figures to another element or component. In addition to the orientation depicted in the figures, the spatial relative terms are also intended to encompass different orientations of the device in use or operation. The device may be positioned otherwise (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Additionally, when a numerical value or range of numerical values is described using "about", "approximate", etc., the term is intended to encompass numerical values within + / - 10% of the described numerical value, unless otherwise specified. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0013] The present disclosure generally relates to semiconductor devices and manufacturing methods, and more particularly to manufacturing FinFET semiconductor devices having multiple etching steps, the multiple etching steps including removing a resist (or photoresist) material in source / drain (S / D) regions stacked between gate structures, which advantageously increases the uniformity of fin height in a subsequent fin recess process. The manufacturing method also includes recessing an isolation component surrounding the fin, which creates a protruding isolation component above a boundary line between regions for different types of FinFETs (e.g., n-type FinFETs and p-type FinFETs). The protruding isolation component increases the isolation between different regions and improves the leakage performance of the device.

[0014] Figure 1A , Figure 1B and Figure 1CFIG. 0 shows a flowchart of a method 100 for forming a semiconductor device 200 (or device 200) according to some embodiments. Method 100 is merely an example and is not intended to limit the present disclosure beyond the scope explicitly recited in the claims. Additional operations may be provided before, during, and after method 100, and for additional embodiments of the method, some of the described operations may be replaced, eliminated, or moved. The following describes method 100 in conjunction with Figure 2 and Figures 3A - 24C and FIG. 8 shows various cross-sectional views of device 200 during manufacturing steps according to method 100. In particular, Figure 2 and Figures 3A - 24C FIGS. 1, Figure 3A , Figure 4A , Figure 5A , Figure 6A , FIG. 7, Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25 are cross-sectional views of portions of device 200 along the Figure 2 line A-A shown in FIG. 5 (cut between adjacent gate structures in the Y-Z plane). Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B and Figure 24B are cross-sectional views of portions of device 200 along the Figure 2 line B-B shown in FIG. 6 (cut along the longitudinal direction of the fins in the PFET region in the X-Z plane). Figure 3C ,Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 22C , Figure 23C and Figure 24C are cross-sectional views of a portion of device 200 along the Figure 2 C-C line shown in (cut along the longitudinal direction of the fins in the NFET region in the X-Z plane).

[0015] Device 200 is for illustrative purposes and does not necessarily limit the embodiments of the present disclosure to any number of devices, any number of regions, or any configuration of structures or regions. Additionally, as Figure 2 and Figures 3A - 25 shown, device 200 may be an intermediate device fabricated during the processing of an IC or a portion of an IC, which may include static random access memory (SRAM) and / or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs (such as FinFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof.

[0016] Refer to Figure 1A , Figure 2 and Figures 3A - 3C, at operation 102, method 100 provides or is equipped with device 200, which has substrate 202, fins 204 (including fins 104a, 104b, 104c, and 104d) protruding from substrate 202, and isolation component 206 above substrate 202 and between fins 204. Each fin 204 includes two S / D regions and a channel region sandwiched between the two S / D regions. The device also includes gate structures 212 (including gate structure 212a and gate structure 212b) joined to the channel regions of fins 204. In an alternative gate process, gate structure 212 is sometimes referred to as a dummy gate structure or a dummy gate stack. The device also includes gate spacers 214 on the sidewalls of gate structure 212. Various components (or elements) of device 200 are further described below.

[0017] In this embodiment, substrate 202 is a silicon (Si) substrate. In alternative embodiments, substrate 202 includes other elemental semiconductors, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); or alloy semiconductors, such as silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), and gallium indium phosphide (GaInP). In an embodiment, substrate 202 may include a silicon-on-insulator (SOI) substrate, strained and / or stressed to improve performance, including epitaxial regions, doped regions, and / or including other suitable components and layers.

[0018] Device 200 includes two regions 220a and 220b (with boundary line 210 represented by a dashed line in Figure 3A ). In this embodiment, region 220a is for forming one or more p-type FinFET devices, and region 220b is for forming one or more n-type FinFET devices. Thus, region 220a is also referred to as PFET region 220a, and region 220b is also referred to as NFET region 220b. Each of PFET region 220a and NFET region 220b includes one or more fins 204 separated by isolation component 206, such as fins 204a / 204b in PFET region 220a and fins 204c / 204d in NFET region 220b. It should be understood that the present disclosure is not limited to any specific number of fins and regions, or to any specific device structure. For example, although the illustrated device 200 is a FinFET device, the present disclosure may also provide embodiments for manufacturing planar FET devices or gate-all-around (GAA) FET devices. It should also be understood that device 200 may alternatively have n-type FinFETs formed in region 220a and p-type FinFETs formed in region 220b.

[0019] The fins 204 are longitudinally oriented along the X direction and are spaced apart from each other along the Y direction perpendicular to the X direction. Each of the fins 204 can be designed to form an n-type FinFET or a p-type FinFET according to its respective region. The fins 204 can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the fins 204, including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer or mandrel can be used as a mask element for patterning the fins 204. For example, the mask element can be used to etch into the substrate 202, leaving the fins 204 on the substrate 202. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0020] The isolation component 206 can include silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. The isolation component 206 can be a shallow trench isolation (STI) component. In one embodiment, the isolation component 206 is formed by etching trenches in the substrate 202 (e.g., as part of the process of forming the fins 204), filling the trenches with an insulating material, and performing a chemical mechanical planarization (CMP) process on the substrate 202 including the insulating material. Other types of isolation components may also be applicable, such as field oxidation and local oxidation of silicon (LOCOS).

[0021] The gate structures 212 are longitudinally oriented along the Y direction and are spaced apart from each other along the X direction. The gate structures 212 engage the fins 204a, 204b, 204c, and 204d in their respective channel regions, thereby forming FinFETs. Each of the gate structures 212a and 212b is a multi-layer structure. In one embodiment, the gate stacks 106A and 106B are placeholders for high-k metal gates (so-called "dummy gates" or "temporary gates"), where one or more layers in the gate structures 212a and 212b are replaced in a subsequent process. For example, each of the gate structures 212a and 212b can include an interface layer (not shown), an electrode layer 224 over the interface layer, and two hard mask layers 226 and 228.

[0022] The interface layer can include, for example, a silicon oxide layer (e.g., SiO 2) or a dielectric material such as silicon oxynitride (e.g., SiON), and can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, and / or other suitable methods. The gate electrode 224 can include polysilicon (poly-Si) and can be formed by suitable deposition processes such as low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD). Each of the hard mask layer 226 and the hard mask layer 228 can include one or more layers of dielectric material such as silicon oxide and / or silicon nitride, and can be formed by CVD or other suitable methods. The respective layers in the gate structure 212 can be patterned by lithography and etching processes. The gate spacer 214 can include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other dielectric materials, or a combination thereof, and can include one or more layers of material. The gate spacer 214 can be formed by depositing a spacer material as a covering layer over the isolation component 206, the fin 204, and the gate structure 212. Then, the spacer material is etched by an anisotropic etching process to expose the isolation component 206, the hard mask layer 228, and the fin 204. The portion of the spacer material on the sidewalls of the gate structure 212 becomes the gate spacer 214. Adjacent gate spacers 214 provide trenches 230 that expose the fins 204 in the S / D regions.

[0023] Subsequently, method 100 proceeds to an operation of covering the NFET region 220b with a resist (or photoresist) layer and exposing the fins 204a and 204b in the PFET region 220a for fin recess and epitaxial S / D component growth.

[0024] Reference Figure 1A and Figures 4A - 4C, at operation 104, method 100 deposits a resist layer 232 over device 200 covering both region 220a and region 220b and filling trench 230 between adjacent gate structures 212a and gate structure 212b. In the illustrated embodiment, resist layer 232 is a trilayer resist that includes a bottom layer 234, an intermediate layer 236, and a relatively thin top photoresist layer 238. Since the limits of the lithography process have been reached through advanced semiconductor manufacturing processes, a thinner top photoresist layer is required to achieve a smaller process window. However, a single photoresist layer may not be sufficient to support the etching of the target layer. The trilayer resist provides a relatively thin top photoresist layer 238. The trilayer resist 232 also includes an intermediate layer 236 that may include a silicon-containing photoresist material to increase the selectivity of the bottom layer 234. The trilayer resist 232 also includes bottom layer 234, which may include a spin-on photoresist material. Thus, the trilayer resist 232 allows for robust patterning of the underlying layer while still providing a relatively thin top photoresist layer 238. In some embodiments, bottom layer 234 may include a carbon-rich polymer material (e.g., C x H y O z ), intermediate layer 236 may include a silicon-rich polymer material (e.g., SiC x H y O z ), and top photoresist layer 238 may include a carbon-rich polymer material with a photosensitive component (e.g., C x H y O z ) that undergoes a change in properties when exposed to radiation. It should be understood that in other embodiments, one or more of the layers of the trilayer resist may be omitted (e.g., no intermediate layer 236), and additional layers may be provided as part of the trilayer resist. In the illustrated embodiment, bottom layer 234 is higher than gate structure 212.

[0025] Reference Figure 1A and Figures 5A - 5C, at operation 106, method 100 patterns the top photoresist layer 238 to form an opening over the PFET region 220a. The patterning of the top photoresist layer 238 can be achieved, for example, by exposing portions of the top photoresist layer 238 using an immersion lithography system and developing either the exposed or unexposed portions depending on whether a positive or negative photoresist is used. Method 100 also etches the intermediate layer 236 through the opening in the top photoresist layer 238 at operation 106. In this way, the top photoresist layer 238 serves as an etch mask that confines the etch process in the PFET region 220a. Operation 106 can include any suitable etch process, including wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques. The top photoresist layer 238 can be stripped from the NFET region 220b after patterning of the intermediate layer 236, as Figures 6A - 6C shown.

[0026] Referring Figure 1A to Figures 7A - 7C and Figure 7A , at operation 110, method 100 etches the top portion of the bottom layer 234 through the opening in the intermediate layer 236. In this way, the intermediate layer 236 serves as an etch mask that confines the etch process in the PFET region 220a. Conventionally, in one etch step such as wet etching or dry etching, the bottom layer 234 is removed from the PFET region 220a to expose the fin thereunder. However, with scaled-down IC components at advanced process nodes, the distance between adjacent gate structures 212a and 212b decreases, resulting in trenches 230 having a high aspect ratio. It becomes difficult to completely remove the resist material of the bottom layer 238 from the high-aspect-ratio trenches. In particular, the sidewalls of the bottom layer 234 along the boundary line 210 (represented by the dashed line 240 in

[0027] Still referring to Figures 7A - 7C , operation 110 recesses the underlying layer 234 in the PFET region 220a. Operation 110 can include wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques. In one embodiment, operation 110 includes a wet etching process using a suitable etching solution, such as a hydrofluoric acid (HF)-based solution, a sulfuric acid (H 2 SO 4 )-based solution, a hydrochloric acid (HCl)-based solution, an ammonium hydroxide (NH 4 OH)-based solution, other suitable etching solutions, or combinations thereof. In another embodiment, operation 110 includes a dry etching process. In a further refinement of this embodiment, operation 110 includes a plasma etching process 242a. The etchant can be a plasma containing a sulfur-containing compound, such as sulfur dioxide (SO 2 ) mixed with an inert gas selected from He, Ar, Xe, Kr, Ne, and combinations thereof. In a specific example, at a gas pressure between 0 and about 60 mtorr, a bias voltage between 0 and about 200 V, a frequency between about 12 MHz and about 14 MHz, a temperature between about 50 °C and about 60 °C, for a duration between about 50 seconds and about 80 seconds, with a SO 2 / He flow rate between 0 and about 500 sccm, the plasma etching process is applied.

[0028] In some embodiments, as Figure 8B shown, the underlying layer 234 is recessed a distance represented as H2 below the gate structure 212. In various embodiments, the ratio of the distance H2 to the depth of the trench 230 (measured from the fin top to the gate structure top) represented as H1 is in the range of about 1:4 to about 1:2. If H2:H1 is less than 1:4, this means that the underlying layer 234 remaining in the trench 230 is still high, which requires a subsequent stronger etching process for a longer duration. As described above, a stronger etching process with a longer duration may damage the gate structure and the gate spacers that have been exposed to the etchant. If H2:H1 is greater than 1:2, due to the relatively weak etching process used in operation 110, resist material residues may start to accumulate on the top portion of the sidewalls of the trench 230.

[0029] Referring to Figure 1A and Figures 8A - 8C, at operation 112, method 100 etches an intermediate portion of underlying layer 234 through an opening in intermediate layer 236. Compared with operation 110, the etching process in operation 112 is relatively stronger, such as having a greater etching rate and a greater etching directionality (e.g., at least 2 times greater). In some embodiments, operation 112 includes a dry etching process. In a further refinement of the embodiment, operation 112 includes plasma etching process 242b. Various etching parameters can be adjusted to enhance plasma etching process 242b, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, power supply power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. In a specific example, plasma etching process 242b has the same etchant, flow rate, gas pressure, and temperature as plasma etching process 242a, but has a higher bias voltage between about 300V and about 800V, at a lower frequency such as between about 1MHz and about 2MHz, and a shorter duration such as between about 10 seconds and about 20 seconds. In some embodiments, plasma etching process 242b uses a different etchant from plasma etching process 242a, such as a plasma containing a mixture of CF 4 and Cl 2 (i.e., a CF 4 / Cl 2 plasma).

[0030] In some embodiments, after operation 112, a portion of underlying layer 234 remains above the fin top at a height designated as H3, as Figure 8B shown. In various embodiments, the ratio of height H3 to trench depth H1 (measured from the fin top to the top of the gate structure) is in the range of about 1:4 to about 1:2. If H3:H1 is less than 1:4, the underlying layer 234 above the remaining fin top may be too thin to protect the fin from strong plasma bombardment. If H3:H1 is greater than 1:2, due to the relatively weak etching process after operation 112, resist material residues may remain on the bottom portion of the sidewall of trench 230. In some alternative embodiments, underlying layer 234 is recessed below fins 204a and 204b, as Figures 9A - 9C shown.

[0031] Refer to Figure 1A and Figures 10A - 10C, at operation 114, method 100 etches the bottom portion of the underlying layer 234 and completely removes the underlying layer 234 from the PFET region 220a, thereby exposing the isolation member 206 and the fins 204a and 204b in the S / D regions. Compared with operation 112, the etching process in operation 114 is relatively weak, such as having a smaller etching rate and a smaller etching directionality (e.g., substantially the same as operation 110). In some embodiments, the etching process in operation 114 is weaker than the etching process in operation 110, such as having a smaller etching rate and a smaller etching directionality. In some other embodiments, the etching process in operation 114 is weaker than the etching process in operation 112, but stronger than the etching process in operation 110. In one embodiment, operation 114 includes using a suitable etching solution (such as, a hydrofluoric acid (HF)-based solution, a sulfuric acid (H 2 SO 4 )-based solution, a hydrochloric acid (HCl)-based solution, an ammonium hydroxide (NH 4 OH)-based solution, other suitable etching solutions, or a combination thereof) for a wet etching process. In some embodiments, operation 114 includes a dry etching process. In a further refinement of the embodiment, operation 114 includes a plasma etching process 242c. Various etching parameters can be adjusted to weaken the plasma etching process 242c, such as the etchant composition, the etching temperature, the etching solution concentration, the etching time, the etching pressure, the power supply power, the RF bias voltage, the RF bias power, the etchant flow rate, other suitable etching parameters, or a combination thereof. In a specific example, the plasma etching process 242c has the same etchant, flow rate, gas pressure, bias voltage, frequency, and temperature as the plasma etching process 242a. The plasma etching process 242c has a smaller bias voltage and a higher frequency than the plasma etching process 242b, but the duration of the plasma etching process 242c is longer than the duration of the plasma etching process 242b but shorter than the duration of the plasma etching process 242a, such as between about 15 seconds and about 30 seconds.

[0032] Compared with Figure 8A the dashed curve 240 therein, the sidewall 246 of the underlying layer 234 is straight and substantially perpendicular to the top surface of the isolation member 206 (or the top surface of the substrate 202). Here, the term "substantially perpendicular" means that the included angle θ1 formed between the sidewall 246 and the top surface of the isolation member 206 (or the top surface of the substrate 202) is in the range of about 88 degrees to about 95 degrees, and in some examples, such as from about 90 degrees to about 93 degrees.

[0033] Referring to Figure 1B and Figures 11A - 11C, at operation 116, method 100 recesses fins 204a and 204b in the S / D regions in an etching process 250. In the illustrated embodiment, method 100 at operation 116 also recesses isolation component 206 in PFET region 220a, thereby forming a stepped profile. The sidewall of the stepped profile facing PFET region 220a is substantially perpendicular to the top surface of isolation component 206 such that the angle θ2 formed between the sidewall and the top surface of isolation component 206 is in the range of about 88 degrees to about 95 degrees, such as from about 90 degrees to about 93 degrees in some examples. Etching process 250 may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 and / or C 2 F 6 ), a chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), a bromine-containing gas (e.g., HBr and / or CHBR 3 ), an iodine-containing gas, other suitable gases, and / or plasmas and / or combinations thereof. For example, a wet etching process may include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO 3 ), and / or acetic acid (CH 3 COOH); or other suitable wet etchants. Many other embodiments of the method of recessing fins 204a and 204b and isolation component 206 may be suitable. In the illustrated embodiment, the top surface of isolation component 206 in PFET region 220a remains flush with the top surfaces of fins 204a and 204b.

[0034] Reference Figure 1B and Figures 12A - 12C, at operation 118, method 100 forms epitaxial S / D components 252a and epitaxial S / D component 252b (collectively referred to as epitaxial S / D component 252) above fins 204a and 204b respectively. The semiconductor material of the epitaxial S / D component 252 rises above the top surface of the fin 204. The epitaxial S / D component 252 in the PFET region 220a may include epitaxially grown silicon germanium (SiGe). The epitaxial S / D component 252 in the PFET region 220a may be further doped with a suitable dopant suitable for p-type devices. For example, the epitaxial S / D component 252a and the epitaxial S / D component 252b may be doped with a p-type dopant such as boron (B) or indium (In). In some embodiments such as Figure 12A as shown, the adjacent epitaxial S / D components 252a and 252b may be separated from each other (not shown) or may be combined together.

[0035] Referring Figure 1B and Figures 13A - 13C , at operation 120, method 100 removes the resist layer 232 (e.g., the bottom layer 234, the intermediate layer 236, and / or the top photoresist layer 238 (if any)) from the device 200. Operation 120 may include any suitable etching process including wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques. After operation 120, the device 200 in the NFET region 220b is also exposed.

[0036] Subsequently, method 100 proceeds to the following operations: covering the PFET region 220a with a resist (or photoresist) layer and exposing the fins 204c and 204d in the NFET region 220b for fin recess and epitaxial S / D component growth.

[0037] Referring Figure 1B and Figures 14A - 14C , at operation 122, method 100 deposits a resist layer 232' above the device 200, and the resist layer 232' covers both the region 220a and the region 220b and fills the trench 230 between the adjacent gate structures 212a and 212b. In the illustrated embodiment, the resist layer 232 is a three-layer resist, which includes a bottom layer 234', an intermediate layer 122', and a relatively thin top photoresist layer 238'. In some embodiments, the resist layer 232' is substantially similar to the discussion related to the resist layer 232 above.

[0038] Referring Figure 1B and Figures 15A - 15C, at operation 124, method 100 patterns the top photoresist layer 238' to form an opening over the NFET region 220b. The patterning of the top photoresist layer 238' can be achieved, for example, by using an immersion lithography system to expose portions of the top photoresist layer 238' and developing the exposed or unexposed portions depending on whether a positive or negative photoresist is used. Method 100 also etches the intermediate layer 236' through the opening in the top photoresist layer 238' at operation 124. In this way, the top photoresist layer 238' serves as an etch mask that confines the etching process in the NFET region 220b. Operation 124 can include any suitable etching process, including wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques. The top photoresist layer 238' can be stripped from the PFET region 220a after patterning the intermediate layer 236', as Figures 16A - 16C shown.

[0039] Refer Figure 1A and Figures 17A - 17C , at operation 128, method 100 etches the top portion of the bottom layer 234' through the opening in the intermediate layer 236'. In this way, the intermediate layer 236' serves as an etch mask that confines the etching process in the NFET region 220b. As explained in more detail below, method 100 includes multiple etching steps to remove the bottom layer 234' from the NFET region 220b, rather than a single etching step. The multiple etching steps employ a combination of a weaker etching process and a stronger etching process to shrink the stronger etching process to an appropriate duration, thereby protecting other semiconductor structures thereunder. In some embodiments, the multiple etching steps are in-situ.

[0040] Still referring Figures 17A - 17C , operation 128 recesses the bottom layer 234' in the NFET region 220b. Operation 128 can include wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques. In one embodiment, operation 128 includes a wet etching process using a suitable etching solution, such as a hydrofluoric acid (HF)-based solution, a sulfuric acid (H 2 SO 4 )-based solution, a hydrochloric acid (HCl)-based solution, an ammonium hydroxide (NH 4 OH)-based solution, other suitable etching solutions, or combinations thereof. In another embodiment, operation 128 includes a dry etching process. In a further refinement of the embodiment, operation 128 includes a plasma etching process 242'a. The etchant can be a plasma containing a sulfur-containing compound, such as sulfur dioxide (SO 2)Mix with an inert gas selected from He, Ar, Xe, Kr, Ne, and combinations thereof. In certain examples, at a gas pressure between 0 and about 60 mtorr, at a bias voltage between 0 and about 200 V, at a frequency between about 12 MHz and about 14 MHz, at a temperature between about 50 °C and about 60 °C, for a duration between about 50 seconds and about 80 seconds, with a SO 2 / He flow rate, apply a plasma etching process.

[0041] In some embodiments, as Figure 17C shown, the underlying layer 234' is recessed a distance represented as H2' below the gate structure 212. In various embodiments, the ratio of the distance H2' to the depth of the trench 230 (measured from the fin top to the gate structure top) represented as H1' is in the range of about 1:4 to about 1:2. If H2':H1' is less than 1:4, this means that the underlying layer 234' left in the trench 230 is still high, which requires a subsequent stronger etching process for a longer time. As described above, a stronger etching process with a longer duration may damage the gate structure that has been exposed to the etchant. If H2':H1' is greater than 1:2, due to the relatively weak etching process used in operation 128, resist material residues may start to accumulate on the top portion of the sidewalls of the trench 230.

[0042] Refer to Figure 1C and Figures 18A - 18C , at operation 130, method 100 etches an intermediate portion of the underlying layer 234' through an opening in the intermediate layer 236'. Compared to operation 128, the etching process in operation 130 is relatively stronger, such as having a greater etching rate and a greater etching directionality (e.g., at least 2 times greater). In some embodiments, operation 130 includes a dry etching process. In a further refinement of the embodiment, operation 130 includes a plasma etching process 242b'. Various etching parameters can be adjusted to enhance the plasma etching process 242b', such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, power supply power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. In a specific example, the plasma etching process 242b' has the same etchant, flow rate, gas pressure, and temperature as the plasma etching process 242a', but has a higher bias voltage between about 300 V and about 800 V, at a lower frequency such as between about 1 MHz and about 2 MHz, and a shorter duration such as between about 10 seconds and about 20 seconds. In some embodiments, the plasma etching process 242b' uses a different etchant from the plasma etching process 242a', such as including CF 4 and Cl 2plasma of the mixture (i.e., CF 4 / Cl 2 plasma).

[0043] In some embodiments, after operation 130, a portion of the underlying layer 234'remains above the fin top, denoted as height H3', as shown in Figure 18C . In various embodiments, the ratio of the height H3' to the trench depth H1' (measured from the fin top to the top of the gate structure) is in the range of about 1:4 to about 1:2. If H3':H1' is less than 1:4, the underlying layer 234' above the remaining fin top may be too thin to protect the fin from strong plasma bombardment. If H3':H1' is greater than 1:2, due to the relatively weak etching process after operation 130, resist material residues may remain on the bottom portion of the sidewalls of the trench 230. In some alternative embodiments, the underlying layer 234' is recessed below the fins 204c and 204d, as shown in Figures 19A - 19C .

[0044] Referring to Figure 1C and Figures 20A - 20C , at operation 132, method 100 etches the bottom portion of the underlying layer 234' and completely removes the underlying layer 234' from the NFET region 220b, thereby exposing the isolation component 206 and the fins 204c and 204d in the S / D regions. Compared to operation 130, the etching process in operation 132 is relatively weak, such as having a smaller etching rate and a greater etching directionality (e.g., substantially the same as operation 128). In some embodiments, the etching process in operation 132 is weaker than the etching process in operation 128, such as having a smaller etching rate and a smaller etching directionality. In some other embodiments, the etching process in operation 132 is weaker than the etching process in operation 130, but stronger than the etching process in operation 128. In one embodiment, operation 132 includes using a suitable etching solution (such as an HF-based solution, an H 2 SO 4 -based solution, an HCl-based solution, an NH 4A wet etching process using a solution of OH), other suitable etching solutions, or a combination thereof. In some embodiments, operation 132 includes a dry etching process. In a further refinement of the embodiment, operation 132 includes a plasma etching process 242c'. Various etching parameters can be adjusted to weaken the plasma etching process 242c', such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, power supply power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or a combination thereof. In a specific example, the plasma etching process 242c' has the same etchant, flow rate, gas pressure, bias voltage, frequency, and temperature as the plasma etching process 242a', the plasma etching process 242c' has a smaller bias voltage and a higher frequency than the plasma etching process 242b', but the duration of the plasma etching process 242c' is longer than the duration of the plasma etching process 242b' but shorter than the duration of the plasma etching process 242a', such as between about 15 seconds and about 30 seconds.

[0045] After operation 132, the sidewalls 246' of the underlying layer 234' are straight and substantially perpendicular to the top surface of the isolation member 206 (or the top surface of the substrate 202). Here, the term "substantially perpendicular" means that the included angle θ1' formed between the sidewalls 246' and the top surface of the isolation member 206 (or the top surface of the substrate 202) is in the range of about 88 degrees to about 95 degrees, and in some examples, such as from about 90 degrees to about 93 degrees.

[0046] Refer to Figure 1C and Figures 21A - 21C , at operation 134, method 100 recesses fins 204c and 204d in the S / D regions in an etching process 250'. In the illustrated embodiment, method 100 at operation 134 also recesses the isolation member 206 in the NFET region 220b, thereby forming a protrusion 256 above (or across) the boundary line 210 between the PFET region 220a and the NFET region 220b. The boundary line 210 can be the interface between the n-well in the substrate 202 in the PFET region 220a and the p-well in the substrate 202 in the NFET region 220b. The sidewalls of the protrusion 256 facing the NFET region 220b are substantially perpendicular to the top surface of the isolation member 206, such that the included angle θ2' formed between the sidewalls and the top surface of the isolation member 206 is in the range of about 88 degrees to about 95 degrees, such as from about 90 degrees to about 93 degrees in some examples. The etching process 250' can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, the dry etching process can implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 、SF 6 、CH2 F 2 、 CHF 3 and / or C 2 F 6 )、 chlorine-containing gas (e.g., Cl 2 、 CHCl 3 、 CCl 4 and / or BCl 3 )、 bromine-containing gas (e.g., HBr and / or CHBR 3 )、 iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. For example, the wet etching process may include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO 3 ) and / or acetic acid (CH 3 COOH); or other suitable wet etchants. Many other embodiments of the method of recessing fin 204c and fin 204d and isolation component 206 may be suitable. In the illustrated embodiment, the top surface of isolation component 206 in NFET region 220b remains flush with the top surfaces of fin 204c and fin 204d.

[0047] Protrusion 256 protrudes a certain distance from other parts of isolation component 206, denoted as H4. The other parts of isolation component 206 have a thickness denoted as H5. Protrusion 256 helps to improve the isolation between PFET region 220a and NFET region 220b. In some embodiments, H4:H5 is in the range from about 2:5 to about 3:4. If H4:H5 is less than about 2:5, the protrusion is too low to bring about a substantial improvement in isolation. If H4:H5 is greater than about 3:4, the isolation feature 206 is recessed too thinly around other parts of fin 204 to provide sufficient isolation for the bottom part of fin 204.

[0048] Refer to Figure 1C and Figures 22A - 22C , at operation 136, method 100 forms epitaxial S / D components 252c and epitaxial S / D component 252d above fin 204c and fin 204d, respectively. The semiconductor material of epitaxial S / D component 252 rises above the top surface of fin 204. The epitaxial S / D component 252 in NFET region 220b may include epitaxially grown silicon (Si) or silicon carbide (SiC). The epitaxial S / D component 252 in NFET region 220b may be further doped with a suitable dopant suitable for n-type devices. For example, epitaxial S / D component 252c and epitaxial S / D component 252d may be doped with an n-type dopant such as phosphorus (P) or arsenic (As). In such as Figure 22AIn some of the illustrated embodiments, adjacent epitaxial S / D components 252c and epitaxial S / D components 252d may be separated from each other.

[0049] Refer to Figure 1C and Figures 23A - 23C , at operation 138, method 100 removes the resist layer 232 (e.g., bottom layer 234, intermediate layer 236, and / or top photoresist layer 238 (if any)) from device 200. Operation 138 may include any suitable etching process including wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques. After operation 138, device 200 in the PFET region 220a is also exposed.

[0050] Refer to Figure 1C and Figures 24A - 24C , at operation 140, method 100 performs further steps to form various components of device 200. Operation 140 includes various processes. In some embodiments, operation 140 forms a contact etch stop layer (not shown) over the epitaxial S / D components 252 and forms an interlayer dielectric layer (ILD) 260 over the contact etch stop layer. The ILD layer 260 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as boron phosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 260 may be formed by PECVD, FCVD, or other suitable methods. In some embodiments, operation 140 replaces the gate structures 212a and gate structures 212b with high-k metal gate stacks 262a and high-k metal gate stacks 262b (collectively high-k metal gate stacks 262). The high-k metal gate stacks 262 include a high-k dielectric layer 264 and a conductive layer 266. The high-k metal gate stacks 262 may further include an interface layer 268 (e.g., silicon dioxide or silicon oxynitride) between the high-k dielectric layer 264 and the fin 204. The interface layer 268 may be formed using chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. The high-k dielectric layer 264 may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials), such as hafnium silicate (HfSiO), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), strontium titanate (SrTiO3 ) or a combination thereof. A high-k dielectric layer 264 can be deposited using CVD, ALD, and / or other suitable methods. The conductive layer 266 includes one or more metal layers, such as a work function metal layer, a conductive barrier layer, and a metal fill layer. Depending on the type of device (PFET or NFET), the work function metal layer can be a p-type or an n-type work function layer. The p-type work function layer includes a metal having an effective work function large enough, which is selected from but not limited to titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or a combination thereof. The n-type work function layer includes a metal having an effective work function low enough, which is selected from but not limited to titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), or a combination thereof. The metal fill layer can include aluminum (Al), tungsten (W), cobalt (Co), and / or other suitable materials.

[0051] Method 100 can further perform a CMP process to remove excess material and form metal interconnects that electrically connect the source, drain, and gate terminals of various transistors to complete the fabrication of device 200.

[0052] Now refer to Figure 25 . An alternative embodiment of device 200 at the end of operation 140 in method 100 is shown along line A-A (cut between adjacent gate stacks in the Y-Z plane). In the alternative embodiment, the vertical portion of the gate spacer 214 remains on the sidewalls of the epitaxial S / D component 252. The remaining vertical portion of the gate spacer 214 may be due to an anisotropic etching process in the formation of the gate spacer, which mainly etches away the horizontal portion of the gate spacer 214. During the recessing of the fin 204 at operations 116 and / or 134, the vertical portion of the gate spacer 214 may also suffer some etching loss due to the etching contrast between the materials of the fin 204 and the gate spacer 214. In some embodiments, the remaining vertical portion of the gate spacer 214 has a height H6, and H6 ranges from about 5 nm to about 10 nm. The vertical portion of the gate spacer 214 protects the portion of the isolation component 206 directly below it from the recessing process at operations 116 and / or operation 134. Thus, similar to the protruding portion 256, these portions of the isolation component 206 directly below the gate spacer 214 also protrude from the recessed top surface of the isolation component 206 by substantially the same distance H4. As described above, in some embodiments, the range of H4:H5 is from about 2:5 to about 3:4. Compared with Figure 24A In Figure 24A , the top surfaces of the fin 204 and the isolation component 206 are shown to be substantially coplanar. In Figure 25In some embodiments, the recessed fin 204 has a top surface that is a distance H7 higher than the recessed top surface of the isolation member 206, and the distance H7 ranges from about 10 nm to about 15 nm. This is mainly because the etchant targeting the fin 204 must pass through a relatively narrow opening formed between the vertical portions of the gate spacer 214 to reach the fin 204, which slows down the etching rate of the fin 204 when the fin 204 is below the vertical portions of the recessed gate spacer 214.

[0053] Still referring to Figure 25 , according to the circuit layout, one of the PFET region 220a and the NFET region 220b may have a larger process window, thereby allowing the method 100 to skip the triple-etch process in that region and use a conventional one-step etching process to remove the bottom portion of the resist layer 234 or the resist layer 234'. This simplifies the etching process and thus increases the production yield. For example, in a static random access memory (SRAM) bit cell layout, n-wells and p-wells are often staggered, but the fins above each well and well boundary (also serving as a region boundary) 210 have different widths and / or different distances. In the illustrated embodiment, the PFET region 220a has a larger process window and a larger fin-to-region boundary distance, and the method 100 can skip operations 110-114 and etch the bottom portion of the resist layer 234 using a conventional one-step etching process. As a result, the resulting protrusion 256 has a curved sidewall 240 facing the PFET region 220a and a substantially vertical sidewall 240' facing the NFET region 220b. An angle θ2 is formed between the curved sidewall 240 and the top surface of the isolation member 206, and the angle θ2 ranges from about 100 degrees to about 130 degrees. An angle θ2' is formed between the vertical sidewall 240' and the top surface of the isolation member 206, and the angle θ2' ranges from about 88 degrees to about 95 degrees, and θ2' is less than θ2. The larger process window on the side of the PFET region 220a allows for the exchange of sidewall profiles to achieve higher production yields. In some alternative embodiments, if the NFET region 220b has a larger process window, the method 100 can skip operations 128-132, and the curved sidewall will instead face the NFET region 220b. Additionally, the lateral position of the protrusion 256 does not have to be directly above the boundary line 210, but in some embodiments, it can be moved to the region with a larger process window to leave a greater distance for other regions between the fin and the protrusion 256. In the illustrated embodiment, the protrusion 256 (vertical sidewall 240') is entirely within the PFET region 220a. Alternatively, if the NFET region 220b provides a larger process window, the protrusion 256 can be entirely within the NFET region 220b.

[0054] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits for semiconductor devices and their formation. For example, embodiments of the present disclosure provide multiple etching steps to remove resist material from high aspect ratio trenches between adjacent gate structures, which advantageously increases the uniformity of fin height in a fin recess process. The manufacturing method also creates prominent isolation components across the boundary lines between regions of different types of FinFETs (e.g., n-type FinFETs and p-type FinFETs). The prominent isolation components increase the isolation between different regions and improve the leakage performance of the device. Additionally, the manufacturing method can be easily integrated into existing semiconductor manufacturing processes.

[0055] In one exemplary aspect, the present disclosure is directed to a method for manufacturing a semiconductor device. The method includes forming a semiconductor device. The method includes providing a structure that includes: a substrate, fins protruding from the substrate, an isolation component surrounding the fins, and gate structures in contact with the fins; depositing a resist layer covering the fins, the isolation component, and the gate structures; performing a first etching process to recess the resist layer below the top surface of the gate structures; performing a second etching process to further recess the resist layer, wherein the etching rate of the second etching process is higher than that of the first etching process; performing a third etching process to remove the resist layer, wherein the etching rate of the third etching process is lower than that of the second etching process; recessing the fins; and forming epitaxial source / drain (S / D) components over the fins. In some embodiments, the recessing of the fins also includes recessing the isolation component. In some embodiments, after the isolation component is recessed, the top surface of the isolation component has a stepped profile. In some embodiments, each of the first, second, and third etching processes includes a plasma etching process for a period of time under a bias voltage. In some embodiments, the bias voltage of the second etching process is higher than that of the first etching process or the third etching process. In some embodiments, the duration of the second etching process is shorter than that of the first etching process or the third etching process. In some embodiments, each of the first, second, and third etching processes uses the same etchant. In some embodiments, the etchant includes a sulfur-containing compound. In some embodiments, after performing the second etching process, the top surface of the resist layer is above the top surface of the fins. In some embodiments, after performing the second etching process, the top surface of the resist layer is below the top surface of the fins.

[0056] In another exemplary aspect, the present disclosure is directed to a method for manufacturing a semiconductor device. The method includes forming a semiconductor device. The method includes providing a structure that includes a substrate having a first region and a second region, an isolation component over the substrate, a first fin extending from the first region of the substrate and through the isolation component, a second fin extending from the second region of the substrate and through the isolation component, and a gate structure coupled to the first fin and the second fin; recessing the first fin and a first portion of the isolation component surrounding the first fin; epitaxially growing a first source / drain (S / D) component on the first fin; recessing the second fin and a second portion of the isolation component surrounding the second fin to form a protruding portion of the isolation component between the first portion and the second portion; and epitaxially growing a second S / D component on the second fin. In some embodiments, the method further includes depositing a first resist layer covering the first region and the second region; and removing the first resist layer from the first region before recessing the first fin and the first portion of the isolation component; removing the first resist layer from the second region; depositing a second resist layer covering the first and second regions; removing the second resist layer from the second region before recessing the second fin and the second portion of the isolation component; and removing the second resist layer from the first region. In some embodiments, each of removing the first resist layer from the first region and removing the second resist layer from the second region includes etching an upper portion of the first resist layer or the second resist layer in a first etching direction; and etching a lower portion of the first resist layer or the second resist layer in a second etching direction that is lower than the first etching direction. In some embodiments, sidewalls of the protruding portion of the isolation component are substantially perpendicular to a top surface of the isolation component. In some embodiments, the protruding portion of the isolation component straddles a boundary line between the first region and the second region. In some embodiments, the first and second S / D components are of opposite types.

[0057] In yet another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a semiconductor device. The semiconductor device includes a substrate having a p-type region and an n-type region; an isolation component over the substrate; a first fin protruding from the substrate and through the isolation component in the p-type region; a p-type epitaxial component over a source / drain (S / D) region of the first fin; a second fin protruding from the substrate and through the isolation component in the n-type region; an n-type epitaxial component over an S / D region of the second fin, wherein a portion of the isolation component spanning the p-type region and the n-type region is higher than other portions of the isolation component. In some embodiments, sidewalls of the portion of the isolation component are substantially perpendicular to a top surface of the substrate. In some embodiments, the portion of the isolation component is higher than the first fin and the second fin in corresponding S / D regions. In some embodiments, the semiconductor device further includes a gate stack coupled to a channel region of the first fin and a channel region of the second fin.

[0058] According to one embodiment of the present application, a method of forming a semiconductor device is provided, including: providing a structure including a substrate, fins protruding from the substrate, isolation components surrounding the fins, and gate structures joined to the fins; depositing a resist layer covering the fins, the isolation components, and the gate structures; performing a first etching process to recess the resist layer below the top surface of the gate structures; performing a second etching process to further recess the resist layer, wherein the second etching process has a higher etching rate than the first etching process; performing a third etching process to remove the resist layer, wherein the third etching process has a lower etching rate than the second etching process; recessing the fins; and forming epitaxial source / drain (S / D) components over the fins. In some embodiments, recessing the fins further includes recessing the isolation components. In some embodiments, after recessing the isolation components, the top surface of the isolation components has a stepped profile. In some embodiments, each of the first etching process, the second etching process, and the third etching process includes a plasma etching process for a period of time under a bias voltage. In some embodiments, the bias voltage of the second etching process is higher than the bias voltage of the first etching process or the bias voltage of the third etching process. In some embodiments, the duration of the second etching process is shorter than the duration of the first etching process or the duration of the third etching process. In some embodiments, each of the first etching process, the second etching process, and the third etching process uses the same etchant. In some embodiments, the etchant includes a sulfur-containing compound. In some embodiments, after performing the second etching process, the top surface of the resist layer is above the top surface of the fins. In some embodiments, after performing the second etching process, the top surface of the resist layer is below the top surface of the fins.

[0059] According to another embodiment of the present application, a method of forming a semiconductor device is provided, including: providing a structure including a substrate having a first region and a second region, an isolation component above the substrate, a first fin extending from the first region of the substrate and passing through the isolation component, a second fin extending from the second region of the substrate and passing through the isolation component, and a gate structure joined to the first fin and the second fin; recessing the first fin and a first portion of the isolation component surrounding the first fin; epitaxially growing a first source / drain (S / D) component on the first fin; recessing the second fin and a second portion of the isolation component surrounding the second fin, thereby forming a protruding portion of the isolation component between the first portion and the second portion; and epitaxially growing a second S / D component on the second fin. In some embodiments, the method of forming a semiconductor device further includes: depositing a first resist layer covering the first region and the second region; removing the first resist layer from the first region before recessing the first fin and the first portion of the isolation component; removing the first resist layer from the second region; depositing a second resist layer covering the first region and the second region; removing the second resist layer from the second region before recessing the second fin and the second portion of the isolation component; and removing the second resist layer from the first region. In some embodiments, each of removing the first resist layer from the first region and removing the second resist layer from the second region includes: etching an upper portion of the first resist layer or the second resist layer in a first etching direction; and etching a lower portion of the first resist layer or the second resist layer in a second etching direction lower than the first etching direction. In some embodiments, a sidewall of the protruding portion of the isolation component is substantially perpendicular to a top surface of the isolation component. In some embodiments, the protruding portion of the isolation component straddles a boundary line between the first region and the second region. In some embodiments, the first S / D component and the second S / D component are of opposite types.

[0060] According to yet another embodiment of the present application, a semiconductor device is provided, including: a substrate having a p-type region and an n-type region; an isolation component above the substrate; a first fin protruding from the substrate and passing through the isolation component in the p-type region; a p-type epitaxial component above a source / drain (S / D) region of the first fin; a second fin protruding from the substrate and passing through the isolation component in the n-type region; and an n-type epitaxial component above an S / D region of the second fin, wherein a portion of the isolation component straddling the p-type region and the n-type region is higher than other portions of the isolation component. In some embodiments, a sidewall of the portion of the isolation component is substantially perpendicular to a top surface of the substrate. In some embodiments, the portion of the isolation component is higher than the first fin and the second fin in the corresponding S / D regions. In some embodiments, the semiconductor device further includes: a gate stack joined to a channel region of the first fin and a channel region of the second fin.

[0061] The foregoing has outlined the components of several embodiments such that those of ordinary skill in the art can better understand various aspects of the present disclosure. Those of ordinary skill in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those of ordinary skill in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor device, comprising: providing a structure including a substrate, fins protruding from the substrate, isolation components surrounding the fins, and a gate structure joined to the fins; depositing a resist layer covering the fins, the isolation components, and the gate structure; performing a first etching process to recess the resist layer below a top surface of the gate structure, wherein, after performing the first etching process, a height difference between a top surface of the resist layer and the top surface of the gate structure ranges from 1:4 to 1:2 relative to a height difference between the top surface of the gate structure and a top surface of the fins; performing a second etching process to further recess the resist layer, wherein the second etching process has a higher etching rate than the first etching process; performing a third etching process to remove the resist layer, wherein the third etching process has a lower etching rate than the second etching process; recessing the fins; and forming epitaxial source / drain components over the fins.

2. The method according to claim 1, wherein recessing the fins further includes recessing the isolation components.

3. The method according to claim 2, wherein, after recessing the isolation components, a top surface of the isolation components has a stepped profile.

4. The method according to claim 1, wherein each of the first etching process, the second etching process, and the third etching process includes a plasma etching process for a period of time under a bias voltage.

5. The method according to claim 4, wherein the bias voltage of the second etching process is higher than the bias voltage of the first etching process or the bias voltage of the third etching process.

6. The method according to claim 4, wherein a duration of the second etching process is shorter than a duration of the first etching process or a duration of the third etching process.

7. The method according to claim 1, wherein each of the first etching process, the second etching process, and the third etching process uses the same etchant.

8. The method according to claim 7, wherein the etchant includes a sulfur-containing compound.

9. The method according to claim 1, wherein after performing the second etching process, a top surface of the resist layer is above a top surface of the fins.

10. The method according to claim 1, wherein after performing the second etching process, a top surface of the resist layer is below a top surface of the fins.

11. A method of forming a semiconductor device, comprising: providing a structure including a substrate having a first region, a second region, and a third region between the first region and the second region, an isolation component above the substrate, a first fin extending from the first region of the substrate and passing through the isolation component, a second fin extending from the second region of the substrate and passing through the isolation component, and a gate structure joined to the first fin and the second fin; Deposit a first resist layer to cover the first region, the second region, and the third region; Remove the first resist layer from the first region, with the third region still covered by the first resist layer; In the region exposed after removing the first resist layer from the first region, recess the first fin and a first portion of the isolation member surrounding the first fin; Epitaxially grow a first source / drain member on the first fin; Remove the first resist layer from the second region and the third region; Deposit a second resist layer to cover the first region, the second region, and the third region; Remove the second resist layer from the second region, with the third region still covered by the second resist layer; In the region exposed after removing the second resist layer from the second region, recess the second fin and a second portion of the isolation member surrounding the second fin, thereby forming a protruding portion of the isolation member between the first portion and the second portion, wherein the protruding portion is in the third region; Epitaxially grow a second source / drain member on the second fin; and Remove the second resist layer from the first region and the third region.

12. The method according to claim 11, wherein: The conductivity type of the first region is P-type, and the conductivity type of the second region is N-type.

13. The method according to claim 12, wherein, Each of removing the first resist layer from the first region and removing the second resist layer from the second region includes: Etching an upper portion of the first resist layer or the second resist layer in a first etching direction; and Etching a lower portion of the first resist layer or the second resist layer in a second etching direction lower than the first etching direction.

14. The method according to claim 11, wherein a sidewall of the protruding portion of the isolation member is substantially perpendicular to a top surface of the isolation member.

15. The method according to claim 11, wherein, The protruding portion of the isolation member is higher than the first fin and the second fin in a corresponding source / drain region.

16. The method according to claim 11, wherein the first source / drain member and the second source / drain member are of opposite types.

17. A semiconductor device, comprising: A substrate having a first region, a second region, and a third region between the first region and the second region; An isolation member above the substrate; A first fin protruding from the substrate and passing through the isolation member in the first region; A p-type epitaxial member above a source / drain region of the first fin; A second fin protruding from the substrate and passing through the isolation member in the second region; and An n-type epitaxial member above a source / drain region of the second fin, wherein a portion of the isolation member in the third region is higher than other portions of the isolation member, Wherein, the portion of the isolation component in the third region has a curved sidewall facing the first region and a vertical sidewall facing the second region.

18. The semiconductor device according to claim 17, wherein, a first angle formed by the curved sidewall and the top surface of the other portion of the isolation component is greater than a second angle formed by the vertical sidewall and the top surface of the other portion of the isolation component.

19. The semiconductor device according to claim 17, wherein the portion of the isolation component in the third region is higher than the first fin and the second fin in the corresponding source / drain region.

20. The semiconductor device according to claim 17, further comprising: a gate stack, which is joined to the channel regions of the first fin and the second fin.

Images