Method of preventing copper contamination in metal-insulator-metal (MIM) capacitors

Abstract

This invention relates to a composite capacitor (MIM) comprising a composite capacitor top metal (CTM) electrode and a composite capacitor bottom metal (CBM) electrode. The composite CBM electrode includes a first diffusion barrier layer covering a first metal layer, and the composite CTM electrode includes a second diffusion barrier layer covering a second metal layer. A dielectric layer is disposed above the composite CBM electrode and below the composite CTM electrode. The first and second diffusion barrier layers protect the first and second metal layers from metals that diffuse or migrate from metal lines beneath the MIM capacitor to the composite CTM and CBM electrodes during manufacturing. The invention also provides a method for manufacturing the MIM capacitor.

Description

[0001] This application is a divisional application of application number 201510736539.8, filed on November 2, 2015, entitled "Method for preventing copper contamination in metal-insulator-metal (MIM) capacitors". Technical Field

[0002] This invention relates generally to capacitors, and more specifically to metal-insulator-metal (MIM) capacitors. Background Technology

[0003] A capacitor is a passive two-terminal electronic device used to store energy within an electric field, and it comprises at least two electrodes separated by a dielectric region. The capacitance of a capacitor is directly proportional to the surface area of ​​the electrodes and inversely proportional to the thickness of the dielectric region. Some examples of capacitors include deep trench (DT) capacitors and metal-insulator-metal (MIM) capacitors. DT capacitors are formed directly within a substrate, while MIM capacitors are formed within a back-end processing (BEOL) metallization stack. Summary of the Invention

[0004] According to one aspect of the present invention, a semiconductor structure including a metal-insulator-metal (MIM) capacitor is provided, the MIM capacitor comprising: a composite capacitor bottom metal (CBM) electrode including a first diffusion barrier layer covering a first metal layer; a dielectric layer disposed above the composite CBM electrode; and a composite capacitor top metal (CTM) electrode disposed above the dielectric layer, wherein the CTM electrode includes a second diffusion barrier layer covering a second metal layer.

[0005] Preferably, the semiconductor structure further includes a via extending into the first or second diffusion barrier layer and reaching a location within the first or second diffusion barrier layer, the location being spaced apart from the first and second metal layers.

[0006] Preferably, the via extends into the first diffusion barrier layer, and the MIM capacitor further includes: a second via extending into the second diffusion barrier layer and reaching a location within the second diffusion barrier layer, the location being spaced apart from the first and second metal layers.

[0007] Preferably, the semiconductor structure further includes: a back-end process (BEOL) stack, including a first metallization layer and a second metallization layer stacked on opposite sides of the MIM capacitor; and a second via, laterally spaced from the MIM capacitor, and extending between the first metallization layer and the second metallization layer; wherein the second via extends from the second metallization layer into the first or second diffusion barrier layer.

[0008] Preferably, the first and second metal layers comprise titanium (Ti) or titanium nitride (TiN), while the first and second diffusion barrier layers comprise tantalum nitride (TaN) or niobium nitride (NbN).

[0009] Preferably, the first and second diffusion barrier layers are amorphous metals.

[0010] Preferably, the thickness of the first and second diffusion barrier layers is about 50 to 200 angstroms.

[0011] Preferably, the MIM capacitor further includes: a top electrode hard mask disposed above the composite CTM electrode; and a bottom electrode hard mask disposed above the dielectric layer, and pads the top electrode hard mask and the composite CTM electrode.

[0012] Preferably, the semiconductor structure further includes: an interlayer dielectric (ILD) layer surrounding the MIM capacitor; a via opening extending through the ILD layer into the first or second diffusion barrier layer and reaching a location within the first or second diffusion barrier layer, the location being spaced apart from the first and second metal layers; and a third diffusion barrier layer lining the via opening; wherein the via filler of the via opening is above the third diffusion barrier layer.

[0013] According to another aspect of the present invention, a method for forming a semiconductor structure is provided, the method comprising: forming a MIM capacitor with a first metallization layer covering a back-end process (BEOL) stack, the MIM capacitor including a composite capacitor top metal (CTM) electrode covering a composite capacitor bottom metal (CBM) electrode, and both the composite CBM and CTM electrodes including corresponding metal layers and corresponding diffusion barrier layers covering the corresponding metal layers; forming a second metallization layer of the BEOL stack above the MIM capacitor; forming a first via extending from the second metallization layer into a diffusion barrier layer and reaching a location within the diffusion barrier layer, the location being spaced apart from the metal layer; and forming a second via laterally spaced from the MIM capacitor and extending between the first and second metallization layers.

[0014] Preferably, the method further includes: forming a second via extending from the second metallization layer into another diffusion barrier layer of the diffusion barrier layer and reaching a location within the other diffusion barrier layer of the diffusion barrier layer, the location being spaced apart from the metal layer.

[0015] Preferably, the method further includes: forming an interlayer dielectric (ILD) layer over a MIM capacitor; etching the ILD layer to form via openings and trenches, the via openings extending to the MIM capacitor and the first metallization layer, respectively, while the trenches define a pattern of a second metallization layer; forming a conductive layer over the ILD layer and filling the trenches and via openings to form vias; and planarizing the conductive layer to form a second metallization layer.

[0016] Preferably, the method further includes forming an additional diffusion barrier layer of pad trenches and via openings before forming the conductive layer.

[0017] Preferably, the method further includes forming a MIM capacitor by at least the following operations: forming a composite CBM layer; forming a dielectric layer over the composite CBM layer; forming a composite CTM layer over the dielectric layer; forming a top electrode hard mask over the composite CTM layer to mask the CTM electrode region of the composite CTM layer; performing a first etching on the region of the composite CTM layer not masked by the top electrode hard mask to form a composite CTM electrode; forming a bottom electrode hard mask over the dielectric layer and padding the composite CTM electrode and the top electrode hard mask to mask the CBM electrode region of the composite CBM layer; and performing a second etching on the region of the composite CBM layer not masked by the bottom electrode hard mask to form a composite CBM electrode.

[0018] Preferably, the method further includes forming a composite CBM layer by at least the following operations: forming a first metal layer; and forming a first diffusion barrier layer over the first metal layer; and forming a composite CTM layer by at least the following operations: forming a second metal layer over the dielectric layer; and forming a second diffusion barrier layer over the second metal layer.

[0019] Preferably, the method further includes forming a diffusion barrier layer having tantalum nitride (TaN) or niobium nitride (NbN).

[0020] Preferably, the method further includes forming a diffusion barrier layer with a thickness of about 50 to 200 angstroms.

[0021] Preferably, the method further includes: forming a composite CTM electrode, wherein the package of the composite CTM electrode is smaller than that of the composite CBM electrode.

[0022] According to another aspect of the present invention, an integrated circuit (IC) is provided, comprising: a metal-insulator-metal (MIM) capacitor including a bottom electrode, a top electrode, and a dielectric layer disposed between the top electrode and the bottom electrode, wherein the top electrode and the bottom electrode include corresponding metal layers and corresponding diffusion barrier layers covering the corresponding metal layers; a back-end process (BEOL) stack including a first metallization layer and a second metallization layer stacked on opposite sides of the MIM capacitor; a first via and a second via extending from the second metallization layer into the diffusion barrier layer and reaching locations within the diffusion barrier layer, the locations being spaced apart from the metal layers; and a third via laterally spaced from the MIM capacitor and extending between the first and second metallization layers.

[0023] Preferably, the diffusion barrier layer comprises tantalum (Ta) or niobium (Nb). Attached Figure Description

[0024] The various aspects of the invention can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various parts are not drawn to scale. In fact, the dimensions of the various parts can be arbitrarily increased or decreased for clarity of discussion.

[0025] Figure 1 Cross-sectional views of some embodiments of a semiconductor structure including a metal-insulator-metal (MIM) capacitor with composite top and bottom electrodes are shown.

[0026] Figure 2 Cross-sectional views of some embodiments of back-end process (BEOL) metallization stacks including MIM capacitors with composite top and bottom electrodes are shown.

[0027] Figure 3 Flowcharts are shown of some embodiments of a method for manufacturing a semiconductor structure including a MIM capacitor with composite top and bottom electrodes.

[0028] Figures 4 to 12 A series of cross-sectional views of some embodiments of a semiconductor structure at various stages of manufacturing are shown, the semiconductor structure including a MIM capacitor with composite top and bottom electrodes. Detailed Implementation

[0029] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or above a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0030] Furthermore, for ease of description, spatial relation terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to encompass various different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and can be interpreted accordingly using the spatial relation descriptors used herein.

[0031] Furthermore, for ease of description, the terms "first," "second," "third," etc., may be used herein to distinguish different elements in the accompanying drawings or a series of drawings. The terms "first," "second," "third," etc., are not intended to describe corresponding elements. Therefore, the "first dielectric layer" described in conjunction with the first drawing does not necessarily correspond to the "first dielectric layer" described in conjunction with another drawing.

[0032] MIM capacitors have top and bottom metal electrodes separated by the capacitor's dielectric layer. One type of MIM capacitor is the high-density decoupling MIM capacitor (HD decap MIM). High-density decoupling MIM capacitors typically have a dielectric strength exceeding 10 femtofarads per square micrometer (fF / μm). 2 High-density decoupling MIM capacitors are typically used to filter out or reduce noise from the power supply of integrated circuits. Furthermore, high-density decoupling MIM capacitors are often formed within the back-end process (BEOL) metallization stack of integrated circuits.

[0033] According to some methods, a MIM capacitor is formed in or on a BEOL metallization stack, the BEOL metallization stack including a first metallization layer in electrical communication with a logic region of an integrated circuit. A first interlayer dielectric (ILD) layer is disposed above the first metallization layer, and the MIM capacitor is formed above the first ILD layer. Specifically, the MIM capacitor includes: a capacitor bottom metal (CBM) electrode; a capacitor dielectric layer located above the CBM electrode; and a capacitor top metal (CTM) electrode located above the capacitor dielectric layer. A second ILD layer is formed above the CTM electrode. To form vias to the CBM electrode, the CTM electrode, and the underlying first metallization layer, etching can be used to form vertical openings extending through the second ILD layer to simultaneously expose the CBM electrode, the CTM electrode, and the upper portion of the first metallization layer. These vertical openings are then padded with a barrier layer and simultaneously filled with a conductive material to form vias that electrically contact the CBM electrode, the CTM electrode, and the first metallization layer.

[0034] Because these openings are simultaneously open, the challenge in forming the aforementioned MIM capacitor lies in the fact that, in some cases, the etching used to form the via openings can cause metallic material (e.g., copper) to be ejected from the first metallization layer and deposited on the CBM and / or CTM electrodes. If this metallic material is deposited on the CBM and / or CTM electrodes (and / or diffuses into the CBM and / or CTM electrodes and / or the capacitor dielectric layer), it can potentially increase the leakage current of the MIM capacitor and reduce its breakdown voltage. This adversely affects the performance of the MIM capacitor and may lead to premature failure.

[0035] In view of the foregoing, this application relates to a MIM capacitor comprising composite CTM and CBM electrodes with a diffusion barrier layer that protects the underlying metal layer from the influence of metal from a first metallization layer. Vias corresponding to the CTM and CBM electrodes extend into the diffusion barrier layer at locations spaced apart from the underlying metal layer. Therefore, if metal from the first metallization layer is ejected while the vias of the CBM and CTM electrodes are open, the diffusion barrier layer prevents the metal from reaching the underlying metal layer. Advantageously, by preventing metal from the first metallization layer from reaching the metal layers of the underlying CBM and CTM electrodes, the influence of metal on the leakage current and breakdown voltage of the MIM capacitor is reduced.

[0036] Figure 1A cross-sectional view 100 illustrates some embodiments of a semiconductor structure of a BEOL metallized stack. The semiconductor structure includes a metal-insulator-metal (MIM) capacitor 102. The MIM capacitor 102 includes a composite capacitor bottom metal (CBM) electrode 104 and a composite capacitor top metal (CTM) electrode 106. The composite CBM electrode 104 is disposed below the composite CTM electrode 106, and the composite CBM electrode 104 has a larger package than the composite CTM electrode 106. The composite CBM electrode 104 includes a first diffusion barrier layer 108 disposed over the bottom metal layer 110. Similarly, the composite CTM electrode 106 includes a second diffusion barrier layer 112 disposed over the top metal layer 114. For example, the first diffusion barrier layer 108 and the second diffusion barrier layer 112 may be amorphous metals, such as tantalum nitride, niobium nitride, etc. For example, the top metal layer 114 and the bottom metal layer 110 may be titanium or titanium nitride.

[0037] The capacitor dielectric layer 116 of the MIM capacitor 102 is disposed between the composite CTM electrode 106 and the composite CBM electrode 104, and the capacitor dielectric layer 116 typically shares the package of the composite CBM electrode 104. The capacitor dielectric layer 116 is configured to electrically isolate the composite CBM electrode 104 from the composite CTM electrode 106. By electrically isolating the composite CBM electrode 104 from the composite CTM electrode 106, the MIM capacitor 102 is able to store energy in the electric field generated between the composite CBM electrode 104 and the composite CTM electrode 106. In some embodiments, the capacitor dielectric layer 116 may comprise a high-k dielectric material (i.e., a dielectric material with a dielectric constant k larger than that of silicon dioxide). Advantageously, this allows for high capacitance density (e.g., exceeding 10 fF / μm). 2 (capacitance density).

[0038] A top electrode hard mask 118 of the MIM capacitor 102 is disposed over the composite CTM electrode 106, and a bottom electrode hard mask 120 of the MIM capacitor 102 is disposed over the capacitor dielectric layer 116 and the top electrode hard mask 118. In some embodiments, the top electrode hard mask 118 typically shares the package of the composite CTM electrode 106, and the top electrode hard mask 118 has a thickness of approximately 250 angstroms to 500 angstroms. For example, the top electrode hard mask 118 may be silicon oxynitride. The bottom electrode hard mask 120 pads the top electrode hard mask 118 and the composite CTM electrode 106. Furthermore, in some embodiments, the bottom electrode hard mask 120 typically shares the package of the composite CBM electrode 104, and the bottom electrode hard mask 120 has a thickness of approximately 600 angstroms to 1200 angstroms. The bottom electrode hard mask 120 includes a cover layer 122 beneath a first etch stop layer 124. The capping layer 122 may be, for example, silicon dioxide, while the first etch stop layer 124 may be, for example, silicon nitride.

[0039] MIM capacitor 102 is disposed within a first ILD layer 126 between a first metallization layer 128 and a second metallization layer 130. The first metallization layer 128 is disposed within a second ILD layer 132 and is located below a second etch stop layer 134 disposed between the first ILD layer 126 and the second ILD layer 132. The first metallization layer 128 includes a first metal line 136 electrically coupled to a logic region of an underlying device layer (not shown). The second metallization layer 130 is disposed within a third ILD layer 138 and covers a third etch stop layer 140 disposed between the first ILD layer 126 and the third ILD layer 138. The second metallization layer 130 includes second metal lines 142, 144, and 146, corresponding to the composite CTM electrode 106, the composite CBM electrode 104, and the first metal line 136, respectively. The second metal lines 142, 144, corresponding to the composite CTM electrode 106 and the composite CBM electrode 104, respectively, typically have different dimensions (e.g., height and / or width) than the second metal line 146 corresponding to the first metal line 136. Furthermore, the second metal lines 142, 144, 146 typically have larger dimensions (e.g., height and / or width) than the first metal line 136 and the other metal lines below it. For example, the first, second, and third ILD layers 126, 132, 138 can be low-k dielectrics (i.e., dielectrics with a dielectric constant less than 3.9), such as undoped silicate glass. For example, the first and second metallization layers 128, 130 can be metals such as copper or tungsten.

[0040] A first via 148, a second via 150, and a third via 152 extend from second metal lines 142, 144, and 146 to a second diffusion barrier layer 112, a first diffusion barrier layer 108, and a first metal line 136, respectively. The first via 148 extends into the second diffusion barrier layer 112 at a location spaced apart from the top metal layer 114, and the second via 150 extends into the first diffusion barrier layer 108 at a location spaced apart from the bottom metal layer 110. The first and second vias 148 and 150 are configured to electrically couple the second metallization layer 130 to the composite CTM and CBM electrodes 106 and 104, respectively. The third metal via 152 extends to the top surface of the first metal line 136 and is configured to electrically couple the second metallization layer 130 to the first metallization layer 128. For example, the first, second, and third vias 148, 150, and 152 can be metals such as copper or tungsten.

[0041] A third diffusion barrier layer 154 liner the first, second, and third vias 148, 150, and 152 and the second metallization layer 130. The third diffusion barrier layer 154 acts as a barrier to prevent material from diffusing into the MIM capacitor 102 and the first metallization layer 128 during the formation of the first, second, and third vias 148, 150, and 152 and the second metallization layer 130. For example, the third diffusion barrier layer 154 may be tantalum nitride or other group V nitrides.

[0042] As will be appreciated in more detail below, the first diffusion barrier layer 108 and the second diffusion barrier layer 112 prevent metals such as copper from moving or diffusing from the first metallization layer 128 to the top and bottom metal layers 114, 110 during the formation of the MIM capacitor 102. This advantageously prevents the adverse effects typically associated with metal movement or diffusing to the top and bottom metal layers 114, 110, such as increased leakage current and reduced breakdown voltage.

[0043] Figure 2 A cross-sectional view 200 shows some embodiments of a BEOL metallization stack for an integrated circuit. The BEOL metallization stack includes a MIM capacitor 102 having composite CTM and CBM electrodes. Furthermore, the BEOL metallization stack includes multiple ILD layers 126, 132, 138, 202 and multiple metallization layers 128, 130, 204 stacked above and within the ILD layers 126, 132, 138, 202. For example, the ILD layers 126, 132, 138, 202 may be a low-k dielectric such as undoped silicate glass. For example, the metallization layers 128, 130, 204 may be copper or aluminum.

[0044] Metallization layers 128, 130, 204 include a redistributed metallization layer 204 and a plurality of layers 128, 130 located beneath the redistributed metallization layer 204. The redistributed metallization layer 204 and the underlying metallization layers 128, 130 include metal components 136, 142, 144, 146, 206 (also labeled M1 to M8 and M7'). For the redistributed metallization layer 204, metal component 206 corresponds to a bonding pad 206, and for the underlying metallization layers 128, 130, 146, 146 correspond to metal lines. In some embodiments, the metal components 136, 142, 144, 146, 206 within and / or between the metallization layers 128, 130, 204 have different dimensions (e.g., width and / or height). For example, the metallization layer 130 below the adjacent redistributed metallization layer 204 typically has a larger metal component size than the other metallization layers 128 below it, thereby withstanding thermal stresses generated during manufacturing. As another example, the metallization layer 130 below the adjacent redistributed metallization layer 204 typically has different component sizes between the metal components 142, 144 corresponding to the MIM capacitor 102 and the metal component 146 unrelated to the MIM capacitor.

[0045] Vias 148, 150, 152, 208 extend between adjacent metallization layers 128, 130, 204 and between metallization layers 128, 130, 204 and a device layer (not shown) beneath the BEOL metallization stack. Vias 148, 150, 152, 208 extend through etch stop layers 134, 140, 210 and isolation layer 212 disposed between ILD layers 126, 132, 138, 202 and metallization layers 128, 130, 204. In some embodiments, etch stop layers 134, 140, 210 and isolation layer 212 covering etch stop layer 210 are disposed between each pair of adjacent metallization layers 128, 130, 204 beneath MIM capacitor 102. For example, etch stop layers 134, 140, 210 may be silicon nitride, and isolation layer 212 may be a dielectric such as silicon dioxide. For example, through holes 148, 150, 152, and 208 can be made of metals such as copper or tungsten.

[0046] A low-k dielectric layer 214 is disposed above the redistribution metallization layer 204 and ILD layers 126, 132, 138, 202, and a passivation layer 216 is disposed above the low-k dielectric layer 214. Typically, the low-k dielectric layer 214 and the passivation layer 216 are conformally oriented. The low-k dielectric layer 214 and the passivation layer 216 protect the redistribution metallization layer 204 and the integrated circuit from environmental influences including dust and electrostatic discharge. For example, the low-k dielectric layer 214 may be undoped silicate glass, and the passivation layer 216 may be silicon nitride, for example.

[0047] Figure 3 A flowchart 300 illustrates some embodiments of a method for fabricating a semiconductor structure including a MIM capacitor with composite top and bottom electrodes. Hereinafter, although the disclosed methods are shown and described as a series of operations or events, it will be understood that the order in which these operations or events are shown should not be construed as limiting. For example, some operations may be performed in a different order and / or concurrently with other operations or events besides those shown and / or described herein. Furthermore, it is not required that all shown operations are used to implement one or more aspects or embodiments described herein. Additionally, one or more of the operations described herein may be performed in one or more separate operations and / or stages.

[0048] In 302, a MIM stack is formed over a first metallization layer. The MIM stack includes a composite CBM layer, a capacitor dielectric layer, and a composite CTM layer stacked in a certain order. The composite CBM and CTM layers include first and second diffusion barrier layers covering the bottom and top metal layers.

[0049] In 304, a top electrode hard mask is formed over the MIM stack to mask the composite CTM electrode region of the composite CTM layer.

[0050] In step 306, a first etch is performed on the capacitor dielectric layer through the region of the composite CTM layer that is not masked by the top electrode hard mask to form the composite CTM electrode.

[0051] In 308, a bottom electrode hard mask is formed above the capacitor dielectric layer, and the bottom electrode hard mask pads the composite CTM electrode and the top electrode hard mask to mask the composite CBM electrode region of the composite CBM layer.

[0052] In step 310, a second etching is performed on the regions in the capacitor dielectric layer and the composite CBM layer that are not masked by the bottom electrode hard mask to form the composite CBM electrode.

[0053] In 312, the ILD layer is formed above the bottom electrode hard mask.

[0054] In step 314, a third etching is performed on the ILD layer to form via openings extending to the first metallization layer and the composite CTM or CBM electrode, respectively.

[0055] In step 316, a fourth etch is performed on the remaining ILD layer to form a trench above the via opening, wherein the trench defines the pattern of the second metallization layer.

[0056] In 318, a third diffusion barrier layer is formed, consisting of liner grooves and through-hole openings.

[0057] In 320, a conductive layer is formed over the remaining ILD layer and the third diffusion barrier layer, and fills the trenches and via openings to form vias.

[0058] In step 322, planarization is performed on the conductive layer to align it with the remaining ILD layer, thereby forming a second metallization layer.

[0059] Advantageously, the first and second diffusion barrier layers of the composite CTM and CBM electrodes protect the composite CTM and CBM electrodes during intermediate operation steps 316 and 318. As described above, during this period, metal can diffuse or migrate from the first metallization layer to the composite CTM and CBM electrodes. In this case, the first and second diffusion barrier layers of the composite CTM and CBM electrodes protect the underlying top and bottom metal layers from metal diffusion. Without this protection, the resulting MIM capacitor may have increased leakage current and / or decreased breakdown voltage.

[0060] Reference Figures 4 to 12 Cross-sectional views of several embodiments of semiconductor structures at different stages of manufacturing are provided to illustrate... Figure 3 The method. Although a description of the method is provided. Figures 4 to 12 However, one will realize that Figures 4 to 12 The structure disclosed herein is not limited to this method; on the contrary, Figures 4 to 12 The structure disclosed herein can exist independently of this method. Similarly, although regarding Figures 4 to 12 The method has been described, but it will be apparent that it is not limited to... Figures 4 to 12 Contrary to the structure disclosed herein, this method can be independent of Figures 4 to 12 It exists independently of the structure disclosed in the document.

[0061] Figure 4 It shows the corresponding Figure 3 Cross-sectional view 400 of some embodiments of the semiconductor structure of operation 302.

[0062] like Figure 4As shown, a first ILD layer 132 and a second ILD layer 402 are provided. The first ILD layer 132 includes a first metallization layer 128 disposed within the first ILD layer 132, and the first ILD layer 132 is located below the second ILD layer 402. The first metallization layer 128 includes a first metal line 136, which is typically electrically coupled to a logic region. The first and second ILD layers 132 and 402 are separated by a first etch stop layer 134' disposed between them. In some embodiments, the thickness of the first etch stop layer 134' is in the range of approximately 450 angstroms to approximately 900 angstroms. For example, the first and second ILD layers 132 and 402 may be silicon dioxide, and for example, the first etch stop layer 134' may be silicon carbide.

[0063] Still Figure 4 As shown, a MIM stack 404 is formed over the first and second ILD layers 132, 402. The MIM stack 404 includes a composite CBM layer 104', a capacitor dielectric layer 116', and a composite CTM layer 106' stacked in some order. In some embodiments, the composite CBM layer 104' and the composite CTM layer 106' are formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable layer growth processes.

[0064] The composite CBM layer 104' includes a first diffusion barrier layer 108' covering the bottom metal layer 110', and the composite CBM layer 106' includes a second diffusion barrier layer 112' covering the top metal layer 114'. For example, the thicknesses of the top and bottom metal layers 114', 110' can range from approximately 400 angstroms to approximately 800 angstroms. Furthermore, for example, the bottom metal layer 110' and the top metal layer 114' can be formed of a material having a metallic composition (e.g., aluminum, copper, tantalum, titanium, and / or tungsten) such as titanium nitride. For example, the thicknesses of the first and second diffusion barrier layers 108', 112' can range from approximately 50 angstroms to approximately 200 angstroms. Furthermore, for example, the first and second diffusion barrier layers 108', 112' can be tantalum and / or niobium.

[0065] For example, the capacitor dielectric layer 116' includes a high-k dielectric, such as alumina, hafnium oxide, silicon dioxide, silicon carbide, silicon nitride (SiN or Si3N4), tantalum pentoxide (Ta2O5), tantalum oxynitride (TaON), tantalum dioxide (TaO2), zirconium dioxide (ZrO2), tetraethyl orthosilicate (TEOS), spin-coated glass (SOG), halosilicon oxide, fluorinated silicate glass (FSG), etc. In some embodiments, for example, the thickness of the capacitor dielectric layer 116' is in the range of about 50 angstroms to about 150 angstroms.

[0066] Figure 5 It shows the corresponding Figure 3 A cross-sectional view 500 of the semiconductor structure of operation 304 is shown. As shown, a top electrode hard mask 118' is formed over the MIM stack 404 to mask the composite CTM electrode region 502 of the MIM stack 404. For example, the top electrode hard mask 118' may be a protective silicon oxynitride (PE-SiON) layer deposited by plasma-enhanced CVD technology. In some embodiments, the process of forming the top electrode hard mask 118' includes: forming a hard mask layer over the MIM stack 404; and performing etching on the MIM stack 404 through a region of the hard mask layer surrounding the composite CTM electrode region 502.

[0067] Figure 6 It shows the corresponding Figure 3 A cross-sectional view 600 of the semiconductor structure of operation 306 is shown. As shown, a first etch is performed on the capacitor dielectric layer 116' by exposing the unmasked area of ​​the composite CTM layer 106' to the etchant 602 to etch through the unmasked area. In some embodiments, the etchant 602 may include a dry etchant (e.g., a plasma etchant, a RIE etchant, etc.) or a wet etchant (e.g., hydrofluoric acid). The first etch defines the composite CTM electrode 106' by removing the unmasked area in the composite CTM layer 106'. The composite CTM electrode 106' includes the remaining top metal layer 114 and the remaining second diffusion barrier layer 112.

[0068] Figure 7 It shows the corresponding Figure 3A cross-sectional view 700 of the semiconductor structure of operation 308 is shown. As shown, a bottom electrode hard mask 120' is formed over the composite CBM electrode region 702 of the remaining MIM stack 404'. The bottom electrode hard mask 120' includes a capping layer 122' and a second etch stop layer 124' covering the capping layer 122'. The capping layer 122' is formed over the capacitor dielectric layer 116' and pads the composite CTM electrode 106" and the top electrode hard mask 118'. The second etch stop layer 124' conformally covers the capping layer 122' and is configured to prevent damage to the composite CTM electrode 106" during subsequent processes. The capping layer 122' and the second etch stop layer 124' can be deposited by a vapor deposition process (e.g., PVD or CVD). For example, the capping layer 122' can be an oxide, and the second etch stop layer 124' can be silicon nitride, for example. In some embodiments, the process for forming the bottom electrode hard mask 120' includes: forming a hard mask layer over the capacitor dielectric layer 116'; padding the composite CTM electrode 106" and the top electrode hard mask 118'; and performing etching on the capacitor dielectric layer 116' to penetrate the region of the hard mask layer surrounding the composite CTM electrode region 702.

[0069] Figure 8 It shows the corresponding Figure 3 A cross-sectional view 800 of the semiconductor structure of operation 310 is shown. As shown, a second etch is performed on the second ILD layer 402 by exposing regions of the capacitor dielectric layer 116' and the composite CBM layer 104' that are not masked by the bottom electrode hard mask 120' to the etchant 802 to penetrate the unmasked regions. In some embodiments, the etchant 802 may include a dry etchant (e.g., a plasma etchant, a RIE etchant, etc.) or a wet etchant (e.g., hydrofluoric acid). The second etch defines the composite CBM electrode 104" by removing the unmasked regions in the capacitor dielectric layer 116' and the composite CBM layer 104'. The composite CBM electrode 104" includes the remaining bottom metal layer 110 and the remaining first diffusion barrier layer 108.

[0070] Figure 9 It shows the corresponding Figure 3A cross-sectional view 900 of the semiconductor structure of operation 312 is shown. As shown, a third ILD layer 902 is formed over a bottom electrode hard mask 120', a top electrode hard mask 118', the remaining first diffusion barrier layer 108', the remaining second diffusion barrier layer 112', a top metal layer 114, a bottom metal layer 110, a capacitor dielectric layer 116', and a second ILD layer 402. Still as shown, a third etch stop layer 140' and a fourth ILD layer 138' are sequentially formed over the third ILD layer 902. For example, the third ILD layer 902 and the fourth ILD layer 138' may be silicon dioxide, and for example, the third etch stop layer 140' may be silicon carbide.

[0071] Figure 10 It shows the corresponding Figure 3 Cross-sectional view 1000 of the semiconductor structures of 314 and 316.

[0072] exist Figure 10 In the process, third and fourth etching are performed. The third etching defines via openings 1002, while the fourth etching defines trenches 1004, and the third and fourth etchings can be performed in any order. Each via opening 1002 extends toward the first metallization layer 128, the remaining composite CBM electrode 104, and the remaining composite CTM electrode 106, respectively. Specifically, the third etching forms CTM via openings extending through the fourth ILD layer 138 / 138', the third etch stop layer 140', the third ILD layer 902, the bottom electrode hard mask 120', and the top mask 118' and stopping in the second diffusion barrier layer 112. The third etching also forms CBM via openings extending through the fourth ILD layer 138 / 138', the third etch stop layer 140', the third ILD layer 902, the bottom electrode hard mask 120', the capacitor dielectric layer 116 and stopping in the first diffusion barrier layer 108. The third etching also forms a first metallized via opening extending through the fourth ILD layer 138 / 138', the third etch stop layer 140', the third ILD layer 902, the second ILD layer 402, and the first etch stop layer 134, and stopping on the upper surface region of the first metal line 136. The trench 1004 defines the pattern of the second metallization layer. The third and fourth etchings may include dry etching (e.g., plasma etchant, RIE etchant, etc.) or wet etching (e.g., hydrofluoric acid as an etchant).

[0073] In some embodiments, the via opening 1002 and the trench 1004 are formed by one or more photolithography processes. For example, the process of forming the trench 1004 may include: coating a fourth ILD layer 138' with a photoresist layer; exposing the photoresist layer to radiation; and developing the photoresist layer to form a pattern in the photoresist layer. The pattern is then etched through the exposed portion of the photoresist layer to form the trench 1004 in the fourth ILD layer 138'. In some embodiments, the pattern is anisotropically etched using known etching techniques such as sputtering etching, particle beam etching, plasma etching, etc. Other techniques may also be employed. After etching, the photoresist layer is removed using common techniques such as stripping or ashing.

[0074] Figure 11 It shows the corresponding Figure 3 A cross-sectional view 1100 of the semiconductor structure of operation 318 is shown. As shown, a third diffusion barrier layer 154 is formed to line the trench 1004 and the via opening 1002 to prevent diffusion to the remaining composite CTM and CBM electrodes 106, 104. For example, the third diffusion barrier layer 154 may be tantalum nitride.

[0075] Figure 12 It shows the corresponding Figure 3 A cross-sectional view 1200 of the semiconductor structures of operations 320 and 322 is shown. As shown, a conductive layer 1202 is formed to fill trench 1004 and via opening 1002. The conductive layer 1202 defines a second metallization layer 130 and vias 148, 150, and 152. The second metallization layer 130 includes second metal lines 144, 142, and 146, corresponding to the remaining composite CBM electrode 104, the remaining composite CTM electrode 106, and the first metal line 136, respectively. The conductive layer 1202 may include a metal such as copper, tungsten, or aluminum. In some embodiments, the process for forming the conductive layer 1202 includes: forming an initial conductive layer over the remaining fourth ILD layer 138 and the third diffusion barrier layer 154, and filling trench 1004 and via opening 1002; and performing planarization of the initial conductive layer to the remaining fourth ILD layer 138.

[0076] It should be noted that the present invention presents embodiments in the form of MIM capacitors, which can be included in the BEOL metallization stack of fabricated integrated circuits (such as microprocessors, memory devices, and / or other integrated circuits). Integrated circuits can also include a variety of passive and active microelectronic devices. For example, integrated circuits can include one or more of the following devices: resistors, capacitors (e.g., deep trench capacitors), inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-power metal-oxide-semiconductor transistors (such as laterally diffused metal-oxide-semiconductor (LDMOS) transistors), and other types of transistors.

[0077] The integrated circuit is disposed on a substrate. For example, the substrate may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Optionally, the substrate may include: 1) for example, other elemental semiconductors, such as germanium; 2) for example, compound semiconductors, including one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; 3) for example, alloy semiconductors, including one or more of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium arsenide phosphide; or 4) for example, a combination of the above.

[0078] Therefore, it can be understood from the above that the present invention provides a semiconductor structure including a MIM capacitor. The MIM capacitor includes a composite CBM electrode having a first diffusion barrier layer covering a first metal layer. Furthermore, the MIM capacitor includes: a dielectric layer disposed above the composite CBM electrode; and a composite CTM electrode disposed above the dielectric layer. The composite CTM electrode includes a second diffusion barrier layer covering a second metal layer.

[0079] In other embodiments, the present invention provides a method for forming a semiconductor structure. A MIM capacitor is formed as a first metallization layer covering a BEOL stack. The MIM capacitor includes a composite CTM electrode covering a composite CBM electrode. The composite CBM and CTM electrodes include: corresponding metal layers; and corresponding diffusion barrier layers covering the corresponding metal layers. A second metallization layer of the BEOL stack is formed above the MIM capacitor. A first via extends from the second metallization layer into a diffusion barrier layer and extends to a location within that diffusion barrier layer, which is spaced apart from the metal layer. A second via is laterally spaced from the MIM capacitor and extends between the first and second metallization layers.

[0080] In other embodiments, the present invention provides an integrated circuit including a MIM capacitor. The MIM capacitor includes: a bottom electrode; a top electrode; and a dielectric layer disposed between the top and bottom electrodes. The top and bottom electrodes include: corresponding metal layers; and corresponding diffusion barrier layers covering the corresponding metal layers. A BEOL stack includes a first metallization layer and a second metallization layer stacked on opposite sides of the MIM capacitor. A first via and a second via extend from the second metallization layer into the diffusion barrier layer and extend to a location within the diffusion barrier layer, spaced apart from the metal layers. A third via, laterally spaced from the MIM capacitor, extends between the first and second metallization layers.

[0081] The foregoing description of several embodiments provides features that enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure including a MIM (metal-insulator-metal) capacitor, comprising: A first metallization layer is laterally spaced from the MIM capacitor and has a surface lower than the top surface of the MIM capacitor; The MIM capacitor includes: a bottom metal electrode of the composite capacitor, including a first metal layer and a first diffusion barrier layer covering the first metal layer; a dielectric layer disposed above the bottom metal electrode of the composite capacitor; and a top metal electrode of the composite capacitor disposed above the dielectric layer, wherein the top metal electrode of the composite capacitor includes a second metal layer and a second diffusion barrier layer covering the second metal layer. A first interlayer dielectric layer surrounds the MIM capacitor; The first etch stop layer is located on the first interlayer dielectric layer; The second metallization layer, located on the first etch stop layer, includes a plurality of metal lines and a second interlayer dielectric layer surrounding the metal lines; The second etch stop layer is located above the first metallization layer and below the first interlayer dielectric layer, and perpendicularly separates the MIM capacitor from the first metallization layer from the first interlayer dielectric layer. The first via extends from the corresponding metal line of the second metallization layer through the first etch stop layer and the first interlayer dielectric layer into the first diffusion barrier layer and is separated from the first metal layer. The second via extends from the corresponding metal line of the second metallization layer through the first etch stop layer, the first interlayer dielectric layer and the second etch stop layer to the top surface of the first metallization layer, wherein the lateral dimensions of the first via and the second via are smaller than the corresponding metal line.

2. The semiconductor structure according to claim 1, wherein, The first via reaches a location within the first diffusion barrier layer, the location being separated from the first metal layer and the second metal layer.

3. The semiconductor structure according to claim 2, further comprising: A third through-hole extends into the second diffusion barrier layer and reaches a position within the second diffusion barrier, the position being spaced apart from the second metal layer.

4. The semiconductor structure according to claim 2, further comprising: The back-end process stack includes a first metallization layer and a second metallization layer stacked on opposite sides of the MIM capacitor.

5. The semiconductor structure according to claim 1, wherein, The first metal layer and the second metal layer comprise titanium (Ti) or titanium nitride (TiN), while the first diffusion barrier layer and the second diffusion barrier layer comprise tantalum nitride (TaN) or niobium nitride (NbN).

6. The semiconductor structure according to claim 1, wherein, The first diffusion barrier layer and the second diffusion barrier layer are amorphous metals.

7. The semiconductor structure according to claim 1, wherein, The thickness of the first diffusion barrier layer and the second diffusion barrier layer is 50 angstroms to 200 angstroms.

8. The semiconductor structure according to claim 1, wherein, The MIM capacitor also includes: A top electrode hard mask is disposed above the top metal electrode of the composite capacitor; and A bottom electrode hard mask is disposed above the dielectric layer and serves as a backing for the top electrode hard mask and the top metal electrode of the composite capacitor.

9. The semiconductor structure according to claim 1, further comprising: A third diffusion barrier layer is used to line the first through-hole opening and the second through-hole opening; The through-hole filling material of the first through-hole opening and the second through-hole opening is above the third diffusion barrier layer.

10. A method for forming a semiconductor structure, the method comprising: A first metallization layer covering the back-end process stack is formed and surrounded by a first interlayer dielectric layer. The first metallization layer is laterally spaced from the MIM capacitor and has a surface lower than the top surface of the MIM capacitor. The MIM capacitor includes a composite capacitor bottom metal electrode and a composite capacitor top metal electrode covering the composite capacitor bottom metal electrode. Both the composite capacitor bottom metal electrode and the composite capacitor top metal electrode include corresponding metal layers and corresponding diffusion barrier layers covering the corresponding metal layers. A second interlayer dielectric layer is formed above the MIM capacitor and above the first interlayer dielectric layer. A first etch stop layer is provided between the first interlayer dielectric layer and the second interlayer dielectric layer. A second etch stop layer is provided between the first metallization layer and the first interlayer dielectric layer. The second etch stop layer and the first interlayer dielectric layer vertically separate the MIM capacitor from the first metallization layer. A first opening is formed through the first etch stop layer, the first interlayer dielectric layer, and the second interlayer dielectric layer, simultaneously reaching one of the diffusion barrier layers; a first trench is formed on the first opening and the first etch stop layer; a second opening is formed reaching the first metallization layer; and a second trench is formed on the second opening and the first etch stop layer. The first trench and the second trench are surrounded by the second interlayer dielectric layer, and the first trench and the second trench are respectively wider than the first opening and the second opening. A second metallization layer is formed over the MIM capacitor and the first etch stop layer of the back-end process stack; A first via is formed within the first opening. The first via extends from the second metallization layer through the first etch stop layer and the first interlayer dielectric layer into one of the diffusion barrier layers and reaches a location within the diffusion barrier layer, the location being spaced apart from the metal layer. A second via is formed within the second opening, laterally spaced from the MIM capacitor and extending between the first metallization layer and the second metallization layer. The second via extends from the second metallization layer through the first etch stop layer, the first interlayer dielectric layer, and the second etch stop layer to the top surface of the first metallization layer.

11. The method of claim 10, further comprising: A third via is formed, the third via extending from the second metallization layer into another diffusion barrier layer of the diffusion barrier layer and reaching a location within the other diffusion barrier layer of the diffusion barrier layer, the location being spaced apart from the metal layer.

12. The method of claim 10, further comprising: Metal lines are formed in the first trench and the second trench respectively to form the second metallization layer.

13. The method of claim 12, further comprising: Before forming the first through-hole and the second through-hole, an additional diffusion barrier layer is formed to line the first trench, the second trench, the first opening, and the second opening.

14. The method of claim 10, further comprising forming the MIM capacitor by at least the following operations: Forming a bottom metal layer for the composite capacitor; A dielectric layer is formed above the bottom metal layer of the composite capacitor; A top metal layer for the composite capacitor is formed above the dielectric layer; A top electrode hard mask is formed above the top metal layer of the composite capacitor to mask the capacitor top metal electrode region of the top metal layer of the composite capacitor; A first etching is performed on the area in the top metal layer of the composite capacitor that is not masked by the hard mask of the top electrode to form the top metal electrode of the composite capacitor; A bottom electrode hard mask is formed above the dielectric layer, and the top metal electrode of the composite capacitor and the top electrode hard mask are padded to mask the capacitor bottom metal electrode region of the bottom metal layer of the composite capacitor; as well as A second etching is performed on the area in the bottom metal layer of the composite capacitor that is not masked by the bottom electrode hard mask to form the bottom metal electrode of the composite capacitor.

15. The method of claim 14, further comprising: The bottom metal layer of the composite capacitor is formed by at least the following operations: forming a first metal layer; And a first diffusion barrier layer is formed above the first metal layer; as well as The top metal layer of the composite capacitor is formed by at least the following operations: forming a second metal layer over the dielectric layer; and forming a second diffusion barrier layer over the second metal layer.

16. The method of claim 10, further comprising: The diffusion barrier layer is formed, wherein the diffusion barrier layer has tantalum nitride (TaN) or niobium nitride (NbN).

17. The method of claim 10, further comprising: The diffusion barrier layer is formed, and the thickness of the diffusion barrier layer is 50 angstroms to 200 angstroms.

18. The method of claim 10, further comprising: A top metal electrode is formed in the composite capacitor, and the package of the top metal electrode is smaller than that of the bottom metal electrode.

19. An integrated circuit, comprising: A MIM (metal-insulator-metal) capacitor includes a bottom electrode, a top electrode, and a dielectric layer disposed between the top electrode and the bottom electrode, wherein the top electrode and the bottom electrode include corresponding metal layers and corresponding diffusion barrier layers covering the corresponding metal layers; The back-end process stack includes a first metallization layer and a second metallization layer stacked on opposite sides of the MIM capacitor, wherein the first metallization layer is laterally spaced from the MIM capacitor and has a lower surface than the top surface of the MIM capacitor, and the second metallization layer is located above the MIM capacitor. A first interlayer dielectric layer surrounds the MIM capacitor and is located between the first metallization layer and the second metallization layer, wherein the second metallization layer includes a second interlayer dielectric layer located above the first interlayer dielectric layer and a plurality of metal lines surrounded by the second interlayer dielectric layer; A first etch stop layer is located between the plurality of metal lines of the second metallization layer and the first interlayer dielectric layer; The second etch stop layer is vertically located between the first metallization layer and the first interlayer dielectric layer, and together with the first interlayer dielectric layer, vertically separates the MIM capacitor from the first metallization layer. The first via and the second via extend from the corresponding metal lines of the second metallization layer through the first etch stop layer and the first interlayer dielectric layer into the diffusion barrier layer, respectively, and reach positions within the diffusion barrier layer, these positions being spaced apart from the metal layer; and The third via is laterally separated from the MIM capacitor, and the third via extends from the corresponding metal line of the second metallization layer through the first etch stop layer, the first interlayer dielectric layer and the second etch stop layer to the top surface of the first metallization layer, wherein the lateral dimensions of the first via, the second via and the third via are smaller than the corresponding metal lines.

20. The integrated circuit according to claim 19, wherein, The diffusion barrier layer comprises tantalum (Ta) or niobium (Nb).

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