Metal-insulator-metal capacitor structure and method of forming a capacitor structure

Abstract

In some embodiments, the disclosure relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and expose portions of the capacitor dielectric layer. A spacer structure is formed on a horizontally-extending surface of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally-extending surface of the upper electrode layer and the capacitor dielectric layer and define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric layer and a lower electrode. The disclosure also relates to a capacitor structure.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the semiconductor field, and more specifically, to metal-insulator-metal capacitor structures and methods for forming capacitor structures. Background Technology

[0002] Integrated circuits are formed on semiconductor dies containing millions or billions of transistors. These transistors are configured to act as switches and / or generate power gain to enable logic functions on the integrated circuit (e.g., forming a processor configured to perform logic functions). Integrated circuits also include passive components such as capacitors, resistors, inductors, varactor diodes, etc. Passive components are widely used to control characteristics of the integrated circuit, such as gain, time constant, etc. Summary of the Invention

[0003] According to one aspect of the present invention, a method for forming a capacitor structure is provided, comprising: forming a capacitor dielectric layer over a lower electrode layer; forming an upper electrode layer over the capacitor dielectric layer; etching the upper electrode layer to define an upper electrode and expose a portion of the capacitor dielectric layer; forming a spacer structure over a horizontally extending surface of the upper electrode layer and the capacitor dielectric layer and along a sidewall of the upper electrode; etching the spacer structure to remove the spacer structure from the horizontally extending surface of the upper electrode layer and the capacitor dielectric layer and define a spacer; and etching the capacitor dielectric layer and the lower electrode layer according to the spacer to define a capacitor dielectric and a lower electrode.

[0004] According to another aspect of the present invention, a method of forming a capacitor structure is provided, comprising: forming one or more lower interconnects within a lower dielectric structure above a substrate; forming a first dielectric layer above the lower dielectric structure; forming a plurality of openings extending through the first dielectric layer to expose the one or more lower interconnects; forming a capacitor stack above the first dielectric layer and within the plurality of openings, the capacitor stack including a capacitor dielectric layer located between a lower electrode layer and an upper electrode layer; forming one or more capping layers above the upper electrode layer; etching the one or more capping layers and the upper electrode layer to define a capping structure above the upper electrode; forming spacers along the sidewalls of the capping structure and the upper electrode, wherein the spacers have an outermost surface extending from the capacitor dielectric layer to the top of the spacers; and etching the capacitor dielectric layer and the lower electrode layer according to the spacers to define a capacitor dielectric above the lower electrode.

[0005] According to another aspect of the invention, a metal-insulator-metal capacitor structure is provided, comprising: one or more lower interconnects disposed within a lower dielectric structure above a substrate; a first dielectric layer located above the lower dielectric structure, wherein the first dielectric layer includes sidewalls defining a plurality of openings extending through the first dielectric layer; a lower electrode disposed along the sidewalls of the first dielectric layer and above an upper surface of the first dielectric layer; a capacitor dielectric disposed along the sidewalls of the lower electrode and the upper surface of the lower electrode; an upper electrode disposed along the sidewalls of the capacitor dielectric and the upper surface of the capacitor dielectric; and a spacer disposed along a relatively outermost sidewall of the upper electrode, wherein the spacer has an outermost surface extending from the lowermost surface of the spacer to the top of the spacer, the outermost surface being aligned with the outermost sidewall of the lower electrode. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated chip with a high-density MIM capacitor structure are shown.

[0008] Figure 2 Cross-sectional views of some additional embodiments of an integrated chip with a high-density MIM capacitor structure are shown.

[0009] Figures 3A to 3D Some additional embodiments of an integrated chip with a high-density MIM capacitor structure are shown.

[0010] Figure 4 Cross-sectional views of some additional embodiments of an integrated chip with a high-density MIM capacitor structure are shown.

[0011] Figures 5A to 5C Cross-sectional views of some additional embodiments of an integrated chip with a high-density MIM capacitor structure are shown.

[0012] Figure 6 Cross-sectional views of some additional embodiments of an integrated chip with a high-density MIM capacitor structure are shown.

[0013] Figures 7 to 17 Cross-sectional views of some embodiments of a method for forming an integrated chip with a high-density MIM capacitor structure are shown.

[0014] Figure 18Flowcharts of some embodiments of a method for forming an integrated chip with a high-density MIM capacitor structure are shown.

[0015] Figures 19 to 29 Cross-sectional views of some alternative embodiments of a method for forming an integrated chip with a high-density MIM capacitor structure are shown.

[0016] Figure 30 Flowcharts of some alternative embodiments of a method for forming an integrated chip with a high-density MIM capacitor structure are shown. Detailed Implementation

[0017] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0019] A MIM (metal-insulator-metal) capacitor is a passive device typically disposed within a back-end stack (BEOL) of integrated chips. An MIM capacitor can be formed by depositing a capacitor dielectric layer on a lower electrode layer and subsequently depositing an upper electrode layer on the capacitor dielectric layer. One or more patterning processes are performed to remove portions of the upper electrode layer, portions of the capacitor dielectric layer, and portions of the lower electrode layer to define an MIM capacitor having a capacitor dielectric disposed between the upper and lower electrodes.

[0020] It has been recognized that using a single patterning process to remove portions of the upper and lower electrode layers can lead to the redeposition and / or accumulation of metal from the upper and / or lower electrode layers along the sides of the upper electrode, lower electrode, and capacitor dielectric during manufacturing, thereby short-circuiting the upper and lower electrodes. To prevent the redepositioned metal from short-circuiting the upper and lower electrodes, discrete patterning processes can be used to etch the upper and lower electrode layers. For example, the upper electrode layer can be patterned using a first patterning process with a first photomask, and then the capacitor dielectric layer and lower electrode layer can be patterned using a second patterning process with a second photomask.

[0021] However, alignment tolerances between the different photomasks used to form the MIM capacitor result in the lower electrode of the capacitor having a significantly larger footprint than the upper electrode. For example, the upper electrode may have 50% to 70% of the footprint of the lower electrode. Since the capacitance of a MIM capacitor is proportional to the area of ​​the upper and lower conductive electrodes, this alignment tolerance causes the MIM capacitor to consume a relatively large integrated chip footprint (e.g., surface area) to achieve the capacitance required for integrated chip applications. For example, a MIM capacitor may have a footprint of approximately 10 square micrometers. Furthermore, while the minimum feature size of integrated chips (e.g., gate size, metal interconnect size, etc.) continues to decrease, MIM capacitors cannot scale their size similarly without reducing their capacitance. Therefore, as the minimum feature size of integrated chips decreases, MIM capacitors are proportionally occupying a larger substrate area to achieve the same capacitance, thus becoming increasingly expensive.

[0022] This disclosure relates to a method of forming a MIM device including an upper electrode and a lower electrode with similar package areas (e.g., package areas differing from each other by less than about 10%). In some embodiments, the method can be performed by forming a capacitor dielectric layer over the lower electrode layer and forming an upper electrode layer over the capacitor dielectric layer. A first etching process is performed to pattern the upper electrode layer and define the upper electrode. A spacer layer is then formed over the horizontally extending surface of the upper electrode and the capacitor dielectric layer and along the sidewalls of the upper electrode. The spacer layer is etched using a second etching process that removes the spacer layer from the horizontally extending surface of the upper electrode and the capacitor dielectric layer and defines self-aligned spacers along the sidewalls of the upper electrode. A third etching process is then performed to pattern the capacitor dielectric layer and the lower electrode layer according to the self-aligned spacers. Patterning the lower electrode layer using self-aligned spacers allows the formation of upper and lower electrodes with similar package areas. By forming upper and lower electrodes with similar package areas, the capacitance of the resulting MIM device can be increased without increasing the overall package area of ​​the MIM device.

[0023] Figure 1 Cross-sectional views of some embodiments of an integrated chip 100 having a high-density MIM (metal-insulator-metal) capacitor structure are shown.

[0024] The integrated chip 100 includes one or more lower interconnects 104 disposed within a lower dielectric structure 106 above a substrate 102. A first etch stop layer 108 is disposed above the lower dielectric structure 106, and a first dielectric layer 110 is disposed above the first etch stop layer 108. The first dielectric layer 110 includes one or more sidewalls 110s defining openings extending through the first dielectric layer 110.

[0025] MIM capacitor structure 111 is disposed over one or more lower interconnects 104. MIM capacitor structure 111 includes a capacitor dielectric 114 vertically disposed between a lower electrode 112 and an upper electrode 116. In some embodiments, MIM capacitor structure 111 extends through an opening in a first dielectric layer 110 to electrically contact one or more lower interconnects 104. In some such embodiments, capacitor dielectric layer 114 may be disposed vertically and laterally between the lower electrode 112 and the upper electrode 116. In such embodiments, the lower electrode 112 is disposed along the upper surface and one or more sidewalls 110s of the first dielectric layer 110, capacitor dielectric layer 114 is disposed along the upper surface and one or more sidewalls of the lower electrode 112, and upper electrode 116 is disposed along the upper surface and one or more sidewalls of the capacitor dielectric 114. In some embodiments, a cover structure 118 is disposed over the upper electrode 116. In some such embodiments, an upper interconnect structure 122 (e.g., an interconnect via) extends through the cover structure 118 to contact the upper electrode 116.

[0026] Spacer 120 (e.g., a self-aligning spacer) is arranged along the opposite outermost walls of the upper electrode 116 and the cover structure 118. Spacer 120 has a lowermost surface 120L disposed on the upper surface of the capacitor dielectric 114. In some embodiments, the lowermost surface 120L of spacer 120 directly contacts the upper surface of the capacitor dielectric 114. In some other embodiments, the entire spacer 120 is completely confined above the upper surface of the capacitor dielectric 114. Spacer 120 has an outermost surface 120s extending continuously between the uppermost surface and the lowermost surface 120L of spacer 120. The outermost surface 120s of spacer 120 is substantially aligned with the outermost walls of the capacitor dielectric 114 and the lower electrode 112. In some embodiments, the outermost surface 120s of spacer 120 and the outermost walls of the capacitor dielectric 114 and the lower electrode 112 form substantially smooth surfaces.

[0027] The spacer 120 has a relatively small width 124. For example, the spacer 120 may have a width 124 in the range of approximately 50 angstroms (Å) to approximately 1000 Å, approximately 250 Å to approximately 750 Å, approximately 400 Å to approximately 600 Å, approximately 500 Å, or other similar values. During manufacturing, the spacer 120 serves as a mask in the etching process defining the capacitor dielectric 114 and the lower electrode 112. Due to the relatively small width 124 of the spacer 120, the lower electrode 112 can be formed with a package area similar to that of the upper electrode 116. For example, in some embodiments, the upper electrode 116 may have a first package area 126 covering between approximately 90% and approximately 95% of the second package area 128 of the lower electrode 112. In other embodiments, the first package area 126 of the upper electrode 116 may cover between approximately 85% and approximately 99% of the second package area 128. By making the first package area 126 of the upper electrode 116 have similar dimensions to the second package area 128 of the lower electrode 112, the capacitance of the MIM capacitor structure 111 can be increased without increasing the overall package area of ​​the MIM capacitor structure 111. For example, the capacitance of a MIM capacitor structure formed using separate photomasks to define the upper and lower electrodes can be between 50% and 75% of the capacitance of the disclosed MIM capacitor structure, which has the same package area and uses self-aligned spacers to define the lower electrode (e.g., a capacitor formed using a separate patterning process can have a capacitance of approximately 175 femtofarads (fF) to approximately 225 fF, while a disclosed MIM capacitor structure with the same package area can have a capacitance of approximately 345 fF to approximately 400 fF).

[0028] Figure 2 Cross-sectional views of some additional embodiments of an integrated chip 200 with a high-density MIM capacitor structure are shown.

[0029] The integrated chip 200 includes one or more lower interconnects 104 disposed within a lower dielectric structure 106 above a substrate 102. In some embodiments, the one or more lower interconnects 104 may be connected to a transistor device 202 disposed within the substrate 102. The lower dielectric structure 106 may include a plurality of stacked interlayer dielectric (ILD) layers 106a to 106b disposed above the substrate 102. In some embodiments, the plurality of stacked ILD layers 106a to 106b may include one or more of silicon dioxide, silicon nitride, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), silicon phosphosilicate glass (PSG), borosilicate phosphorus glass (BPSG), fluorosilicone glass (FSG), undoped silicon glass (USG), porous dielectric materials, etc. In some embodiments, the one or more lower interconnects 104 may include one or more of mid-process (MOL) interconnects, conductive contacts, interconnects, interconnect vias, etc. In some embodiments, the one or more lower interconnects 104 may include one or more of copper, tungsten, ruthenium, aluminum, etc.

[0030] A first etch stop layer 108 is disposed above the lower dielectric structure 106, and a first dielectric layer 110 is disposed above the first etch stop layer 108. A MIM capacitor structure 111 is disposed above the first dielectric layer 110. The MIM capacitor structure 111 extends through the first dielectric layer 110 and the first etch stop layer 108 to electrically contact one or more lower interconnects 104. In some embodiments, the MIM capacitor structure 111 includes a lower electrode 112 arranged along the upper surface and one or more sidewalls of the first dielectric layer 110, a capacitor dielectric 114 arranged along the upper surface and one or more sidewalls of the lower electrode 112, and an upper electrode arranged along the upper surface and one or more sidewalls of the capacitor dielectric 114.

[0031] In some embodiments, the lower electrode 112 and the upper electrode 116 may each comprise a metal such as aluminum, copper, tantalum, titanium, tantalum nitride, titanium nitride, tungsten, etc. In some embodiments, the lower electrode 112 comprises the same metal as the upper electrode 116, while in other embodiments, the lower electrode 112 and the upper electrode 116 may comprise different metals. The lower electrode 112 and the upper electrode 116 each have a thickness in the range of approximately 10 angstroms (Å) and approximately 200 angstroms, approximately 50 angstroms and approximately 100 angstroms, or other similar values. In some embodiments, the capacitor dielectric 114 may comprise a high-k dielectric material. In some embodiments, the capacitor dielectric 114 may comprise one or more of the following: aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), silicon dioxide (SiO₂), silicon carbide (SiC), silicon nitride mononitride (SiN), silicon nitride (Si₃N₄), tantalum nitride (Ta₂O₅), tantalum oxynitride (TaON), titanium oxide (TiO₂), zirconium oxide (ZrO₂), etc.

[0032] In some embodiments, dielectric 204 covers the upper surface of upper electrode 116 and extends between the inner sidewalls of upper electrode 116. In some embodiments, dielectric 204 extends continuously from above upper electrode 116 between the inner sidewalls of upper electrode 116. In some embodiments, dielectric 204 may include oxides (e.g., silicon oxide, silicon dioxide), nitrides (e.g., silicon nitride), etc.

[0033] A cover structure 118 is disposed above the upper electrode 116. In some embodiments, the cover structure 118 is perpendicularly separated from the upper electrode 116 by a dielectric 204. In some embodiments, the cover structure 118 is configured to prevent interactions between adjacent layers (e.g., to prevent diffusion from a capacitor metal layer to adjacent dielectric materials) and / or to protect underlying layers during manufacturing. In some embodiments, the cover structure 118 may include a dielectric material such as silicon oxynitride or silicon carbide. The cover structure 118 and the masking layer 206 have substantially equal widths. In some embodiments, the masking layer 206 is disposed above the cover structure 118. In some embodiments, the masking layer may include an anti-reflective layer. In various embodiments, the masking layer 206 may include a dielectric material such as silicon nitride or silicon carbide.

[0034] Spacer 120 is arranged along opposite sides of upper electrode 116, cover structure, and / or masking layer 206. Spacer 120 has an outermost surface that faces away from upper electrode 116 and extends continuously between the lowermost surface of spacer 120 and the top and / or uppermost surface of spacer 120. In some embodiments, the outermost surface of spacer 120 may include a curved surface. For example, the outermost surface of spacer 120 may include a vertically extending segment and a curved segment above the vertically extending segment. In some such embodiments, the vertically extending segment is substantially aligned with the outermost outer wall of capacitor dielectric 114 and lower electrode 112. In some embodiments, first dielectric layer 110 may include sidewalls 110s that are also substantially aligned with the vertically extending segment of spacer 120. In some embodiments, spacer 120 includes an outermost wall that is completely confined between the outermost outer wall of upper electrode 116 facing a first direction and the outermost outer wall of lower electrode 112 facing the same first direction.

[0035] In some embodiments, spacer 120 includes a first dielectric 208 and a second dielectric 210 above the first dielectric 208. The first dielectric 208 extends along the lower surface and sidewalls of the second dielectric 210. The first dielectric 208 includes a horizontal extension separating the second dielectric 210 from the capacitor dielectric 114 and a vertical extension separating the second dielectric 210 from the upper electrode 116 and the cover structure 118. In some embodiments, the first dielectric 208 may include a first dielectric material and the second dielectric 210 may include a second dielectric material different from the first dielectric material. In some embodiments, the first dielectric 208 may include an oxide (e.g., silicon dioxide, silicon-rich oxide, etc.), while the second dielectric 210 may include a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), etc.

[0036] A second dielectric layer 212 is disposed above the MIM capacitor structure 111 and the first dielectric layer 110. In some embodiments, the second dielectric layer 212 is disposed along the upper surface and sidewalls 110s of the first dielectric layer 110. In some embodiments, the second dielectric layer 212 may have a single sidewall extending along the outer surface of the spacer 120, the outermost sidewall of the capacitor dielectric layer 114 and the lower electrode 112, and along the sidewalls 110s of the first dielectric layer 110. In some embodiments, the second dielectric layer 212 may include one or more of silicon dioxide, silicon nitride, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, USG, porous dielectric materials, etc. In some embodiments, an upper interconnect structure 122 (e.g., an interconnect via) extends through the second dielectric layer 212, the masking layer 206, the cover structure 118, and the dielectric 204 to contact the upper electrode 116.

[0037] Figure 3A Cross-sectional views of some additional embodiments of an integrated chip 300 with a high-density MIM capacitor structure are shown, the structure including a plurality of protrusions extending outward from the lower surface of the MIM capacitor structure.

[0038] The integrated chip 300 includes a first dielectric layer 110 disposed above a substrate 102. The first dielectric layer 110 includes sidewalls defining a plurality of openings extending through the first dielectric layer 110. A MIM capacitor structure 111 is disposed above the first dielectric layer 110 and includes a plurality of protrusions 302a to 302c extending outward from the lower surface of the MIM capacitor structure 111 into the plurality of openings. The plurality of protrusions 302a to 302c respectively include a lower electrode 112, a capacitor dielectric 114, and an upper electrode 116. In some embodiments, the plurality of protrusions 302a to 302c further include a dielectric 204. One or more of the plurality of protrusions 302a to 302c contact one or more lower interconnects 104 within a lower dielectric structure 106 between the first dielectric layer 110 and the substrate 102.

[0039] The capacitance of the MIM capacitor structure 111 can be further increased by having a plurality of protrusions 302a to 302c extending outward from the lower surface of the MIM capacitor structure 111, because the protrusions increase the surface area of ​​the upper electrode 116 and the lower electrode 112. For example, a MIM capacitor structure 111 with three protrusions can have a capacitance that is approximately 50% to approximately 70% larger than that of a MIM capacitor structure with two protrusions. In some embodiments, the plurality of protrusions 302a to 302c may include three protrusions. In other embodiments (not shown), the plurality of protrusions 302a to 302c may include more than three protrusions (e.g., four protrusions, five protrusions, etc.).

[0040] Figure 3B It shows Figure 3A Top view of the integrated chip 304. Figure 3A The cross-sectional view is taken along the section line A-A' of the top view 304.

[0041] As shown in top view 304, the multiple protrusions 302a to 302c of the MIM capacitor structure 111 each have a generally rectangular shape, the rectangular shape extending a first distance along a first direction 306 and a second distance along a second direction 308, the second direction 308 being perpendicular to the first direction 306. The second distance is greater than the first distance.

[0042] Within each of the plurality of protrusions 302a to 302c, the lower electrode 112 completely surrounds the capacitor dielectric 114, the capacitor dielectric 114 completely surrounds the upper electrode 116, and the upper electrode 116 completely surrounds the dielectric 204. The upper electrode 116 extends continuously through the plurality of protrusions 302a to 302c along a first direction 306 and along a second direction 308 perpendicular to the first direction 306. The spacer 120 extends around the periphery of the upper electrode 116 in a closed path. The lower electrode 112 and the capacitor dielectric 114 have an outermost periphery substantially the same as the outermost periphery of the spacer 120. In such an embodiment, the total package area of ​​both the upper electrode 116 and / or the spacer 120 is substantially equal to the package area of ​​the lower electrode 112.

[0043] It should be understood that, in various embodiments, the disclosed MIM capacitor structure may have multiple protrusions defined by different shapes (e.g., Figure 3A (302a to 302c). For example... Figures 3C to 3D Some embodiments of alternative shapes for the plurality of protrusions within the disclosed MIM capacitor structure are shown. Different shapes of the plurality of protrusions affect the electric field characteristics within the disclosed MIM capacitor structure, thereby affecting the performance of the MIM capacitor structure. Figures 3C to 3D The shapes of the multiple protrusions shown are not limited examples of possible protrusion shapes, and protrusions with other shapes are also considered to fall within the scope of this disclosure.

[0044] Figure 3C A top view 310 shows some alternative embodiments of an integrated chip having a high-density MIM capacitor structure including multiple protrusions.

[0045] As shown in top view 310, the MIM capacitor structure 111 includes a plurality of protrusions 312. The plurality of protrusions 312 have a generally circular shape. In some embodiments, the plurality of protrusions 312 may be arranged in an array. In some such embodiments, the plurality of protrusions 312 may be aligned in rows (extending in a first direction 306) and columns (extending in a second direction 308).

[0046] Figure 3D A top view 314 shows some alternative embodiments of an integrated chip having a high-density MIM capacitor structure including multiple protrusions.

[0047] As shown in top view 314, the MIM capacitor structure 111 includes a plurality of protrusions 316. The plurality of protrusions 316 have a generally square shape. In some embodiments, the plurality of protrusions 316 may be arranged in an array. In some such embodiments, the plurality of protrusions 316 may be aligned in rows (extending in a first direction 306) and columns (extending in a second direction 308).

[0048] Figure 4 Cross-sectional views of some additional embodiments of an integrated chip 400 with a high-density MIM capacitor structure are shown.

[0049] The integrated chip 400 includes one or more lower interconnects 104 disposed within a lower dielectric structure 106 above a substrate 102. A first etch stop layer 108 is disposed above the lower dielectric structure 106, and a first dielectric layer 110 is disposed above the first etch stop layer 108. A MIM capacitor structure including a lower electrode 112, a capacitor dielectric 114, and an upper electrode 116 is disposed above the first dielectric layer 110. A spacer 120 is disposed along the opposite side of the upper electrode 116. In some embodiments, the spacer 120 may have a curved upper surface. In some embodiments, a cover structure 118 is disposed above the upper electrode 116, and a masking layer 206 is disposed above the cover structure 118. A second dielectric layer 212 is disposed above the MIM capacitor structure. In some embodiments, the second dielectric layer 212 may extend above the upper surface of the spacer 120 and above the top surface of the masking layer 206.

[0050] In some embodiments, the first dielectric layer 110 has sidewalls inclined at a first angle θ1. The first angle θ1 is an acute angle measured through the first dielectric layer 110 and relative to the lower surface of the first dielectric layer 110 facing the substrate 102. The lower electrode 112 has a lower sidewall 112 extending through the first dielectric layer 110. L and the upper sidewall 112 covering the first dielectric layer 110 U Lower sidewall 112 L The upper sidewall 112U is inclined at a second angle θ2, while the lower sidewall 112U is inclined at a third angle θ3. The second angle θ2 is an obtuse angle measured through the lower electrode 112 and relative to the lower surface of the lower electrode 112 facing the substrate 102. The third angle θ3 is an acute angle measured through the lower electrode 112 and relative to the lower surface of the lower electrode 112 facing the substrate 102. In some embodiments, the capacitor dielectric 114, the upper electrode 116, and the cover structure 118 may also have inclined sidewalls, such as... Figure 4 As shown.

[0051] In some embodiments, an upper dielectric structure 402 is disposed above the first dielectric layer 110 and the second dielectric layer 212. In some embodiments, the upper dielectric structure 402 may include an upper etch stop layer 404 and an upper interlayer dielectric (ILD) layer 406. In some embodiments, an upper interconnect structure 122 extends through the upper dielectric structure 402, the masking layer 206, the cover structure 118, and the dielectric 204 to contact the upper electrode 116. In some embodiments, the upper interconnect structure 122 may include an upper interconnect via 122v and an upper interconnect wiring 122w above the upper interconnect via 122v. In some embodiments, the upper interconnect structure 122 may extend a non-zero distance 408 below the top surface of the upper electrode 116.

[0052] In some embodiments, one or more conductive byproducts 410 (e.g., metallic byproducts) may be arranged along the sidewalls of the lower electrode 112, the capacitor dielectric 114, and / or the spacer 120. The one or more conductive byproducts 410 are generated by the redeposition of material etched from the lower electrode layer during the formation of the lower electrode 112. Because the one or more conductive byproducts 410 are spaced from the upper electrode 116 by the spacer 120, conductive byproducts cannot form a conductive path between the lower electrode 112 and the upper electrode 116, thereby preventing an electrical short circuit between the lower electrode 112 and the upper electrode 116. In some additional embodiments (not shown), one or more additional conductive byproducts may be disposed along the sidewalls of the upper electrode 116. The one or more additional conductive byproducts may be generated by etching the upper electrode layer to define the upper electrode 116 and may be covered by the spacer 120, thereby separating the one or more additional conductive byproducts from the one or more conductive byproducts 410 by the spacer 120.

[0053] Figure 5A Cross-sectional views of some additional embodiments of an integrated chip 500 with a high-density MIM capacitor structure are shown.

[0054] The integrated chip 500 includes a MIM capacitor structure 111 disposed over one or more lower interconnects 104 disposed within a lower dielectric structure 106 over a substrate 102. A cover structure 118 is disposed over the MIM capacitor structure 111. The cover structure 118 may be separated from the upper electrode 116 by a dielectric 204. A spacer 120 is disposed over the cover structure 118 and the capacitor dielectric 114. In some embodiments, the spacer 120 may extend laterally across the opposing outermost walls of the upper electrode 116 and the cover structure 118 from directly above the upper electrode 116 and the cover structure 118. In some embodiments, the spacer 120 may extend a non-zero distance 506 across one or more of the opposing outermost walls of the upper electrode 116 and the cover structure 118. In some embodiments, the non-zero distance 506 may be in the range of approximately 50 angstroms to approximately 750 angstroms.

[0055] In some embodiments, the spacer 120 extends from directly above the cover structure 118 along the sidewalls of the cover structure 118. In such embodiments, the spacer 120 includes a protrusion 120p extending outward from the lower surface of the spacer 120 that directly covers the cover structure 118. In some embodiments, the spacer 120 may include an outermost surface 120s substantially aligned with the outermost sidewalls of the capacitor dielectric 114 and the lower electrode 112. In some embodiments, the outermost surface 120s may also be aligned with the sidewalls of the first dielectric layer 110. The outermost surface 120s extends continuously from the bottom of the spacer 120 to the top and / or the topmost surface of the spacer 120. In some embodiments, the outermost surface 120s of the spacer 120 is substantially flat.

[0056] In some embodiments, spacer 120 may include a first dielectric 502 and a second dielectric 504, the second dielectric 504 being a dielectric material different from the first dielectric 502. In some embodiments, the first dielectric 502 pads over the sidewalls of structure 118 and upper electrode 116, as well as over the horizontally extending surface of structure 118 and capacitor dielectric 114. In some embodiments, the second dielectric 504 pads over the sidewalls and horizontally extending surface of the first dielectric 502. In some embodiments, the first dielectric 502 and the second dielectric 504 may completely cover the uppermost surface of overstructure 118 and capacitor dielectric 114. In some such embodiments, the second dielectric 504 may extend continuously from a first outermost wall aligned with a first outermost wall of capacitor dielectric 114 to a second outermost wall aligned with a opposite second outermost wall of capacitor dielectric 114.

[0057] Figure 5B Cross-sectional views of some additional embodiments of the integrated chip 508 with a high-density MIM capacitor structure are shown.

[0058] The integrated chip 508 includes a MIM capacitor structure 111 disposed above a substrate 102. A cover structure 118 is disposed above the MIM capacitor structure 111. A spacer 120 is disposed above the capacitor dielectric 114 of the cover structure 118 and the MIM capacitor structure 111. In some embodiments, the spacer 120 may extend through the upper electrode 116 and the outermost wall of the cover structure 118.

[0059] The spacer 120 includes a surface defining one or more cavities 510a to 510b disposed along one or more outer sidewalls of the spacer 120. The one or more cavities 510a to 510b may extend vertically from the top of the spacer 120 over the bottom of the cover structure 118. In some embodiments, the one or more cavities 510a to 510b may include a first cavity 510a and a second cavity 510b disposed along opposite sides of the spacer 120. In some embodiments, the first cavity 510a may be laterally recessed from the first outer sidewall of the spacer 120 by a first distance 512, and the second cavity 510b may be laterally recessed from the second outer sidewall of the spacer 120 by a second distance 514. In some embodiments, the first distance 512 may be approximately equal to the second distance 514. In other embodiments, the first distance 512 may be less than the second distance 514.

[0060] Figure 5C Cross-sectional views of some additional embodiments of the integrated chip 516 with a high-density MIM capacitor structure are shown.

[0061] The integrated chip 516 includes a spacer 120 having a surface defining one or more cavities 510a to 510b disposed along one or more outer sidewalls of the spacer 120. In some embodiments, the one or more cavities 510a to 510b may include a first cavity 510a and a second cavity 510b disposed along opposite sides of the spacer 120. In some embodiments, the first cavity 510a may be vertically recessed from the top of the spacer 120 by a first distance, and the second cavity may be vertically recessed from the top of the spacer 120 by a second distance. In some embodiments, the first distance may be different from the second distance. In such an embodiment, a first lower surface 518L1 defining the first cavity 510a is vertically offset by a non-zero distance 520 from a second lower surface 518L2 defining the second cavity 510b.

[0062] Figure 6 Cross-sectional views of some additional embodiments of an integrated chip 600 with a high-density MIM capacitor structure are shown.

[0063] The integrated chip 600 includes a first region 602 and a second region 604 laterally offset from the first region 602. Within the first region 602, one or more lower interconnects 104 are disposed within a lower dielectric structure 106 above the substrate 102. A MIM capacitor structure 111 is disposed over both a first etch stop layer 108 and a first dielectric layer 110 located above the lower dielectric structure 106. The MIM capacitor structure 111 includes one or more protrusions 302 extending through the first dielectric layer 110 to contact one or more lower interconnects 104.

[0064] A second dielectric layer 212 is disposed along the sidewalls of the first dielectric layer 110 and above the upper surface of the first dielectric layer 110 and the first etch stop layer 108. In some embodiments, the spacer 120 may have a flat upper surface that is substantially coplanar with the upper surface of the second dielectric layer 212 and / or the masking layer 206 (e.g., flat within the tolerances of a chemical mechanical planarization (CMP) process). An upper dielectric structure 402 is disposed above the first dielectric layer 110 and the second dielectric layer 212. An upper interconnect structure 122 is disposed within the upper dielectric structure 402 and extends vertically through the masking layer 206 to be electrically connected to the MIM capacitor structure 111.

[0065] Within the second region 604, one or more additional lower interconnects 612 are disposed within the lower dielectric structure 106. The one or more additional lower interconnects 612 are connected to additional interconnect vias 614 disposed within the second dielectric layer 212. The additional interconnect vias 614 are laterally separated from the MIM capacitor structure 111 through the first dielectric layer 110 and / or the second dielectric layer 212. An additional upper interconnect structure 616 is disposed within the upper dielectric structure 402 and connected to the additional interconnect vias 614.

[0066] In some embodiments, the upper interconnect structure 122 and the additional upper interconnect structure 616 may be disposed within the topmost interlayer dielectric (ILD) layer and / or the topmost interconnect layer. In such embodiments, the upper interconnect structure 122 and / or the additional upper interconnect structure 616 are connected to bonding pads 606 disposed within the passivation layer 608. In some embodiments, the bonding pads 606 may be further connected to external bonding structures 610 (e.g., solder bumps, microbumps, etc.). Placing the MIM capacitor structure 111 on an interconnect layer directly below the topmost ILD layer and / or the topmost interconnect layer provides a relatively large height for the MIM capacitor structure 111 (e.g., since the height of the ILD layer and / or interconnect layer typically increases with distance from the substrate 102). The relatively large height of the MIM capacitor structure 111 further increases the capacitance of the MIM capacitor structure 111 without increasing the area occupied by the MIM capacitor structure 111.

[0067] Figures 7 to 18Cross-sectional views of some embodiments of a method for forming an integrated chip with a high-density MIM capacitor structure are shown. Although Figures 7 to 18 It describes a method, but it should be understood that... Figures 7 to 18 The structure disclosed in the method may not be limited to this method, but may exist independently of this method.

[0068] like Figure 7 As shown in cross-sectional view 700, one or more lower interconnects 104 are formed within a lower dielectric structure 106 formed above a substrate 102. In various embodiments, the substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, and any other type of semiconductor and / or epitaxial layer associated therewith. In some embodiments, one or more lower interconnects 104 may include one or more of mid-process (MOL) interconnects, conductive contacts, interconnects, and / or interconnect vias.

[0069] In some embodiments, one or more lower interconnects 104 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). In such embodiments, one or more lower interconnects 104 may be formed by the following steps: forming an interlayer dielectric (ILD) layer over a substrate 102; selectively etching the ILD layer to define vias and / or trenches within the ILD layer; forming a conductive material (e.g., copper, aluminum, etc.) within the vias and / or trenches; and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) to remove excess conductive material from over the ILD layer.

[0070] like Figure 8 As shown in cross-sectional view 800, a first etch stop layer 108 is formed over the lower dielectric structure 106, and a first dielectric layer 110 is formed over the first etch stop layer 108. In some embodiments, the first etch stop layer 108 may include a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), etc. In some embodiments, the first dielectric layer 110 may include an oxide, a low-k dielectric material, etc. In various embodiments, the first etch stop layer 108 and / or the first dielectric layer 110 may be formed by one or more deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), atomic layer deposition (ALD), etc.).

[0071] like Figure 9A Cross-sectional view 900 (taken along the first direction) and Figure 9BAs shown in cross-sectional view 908 (taken along a second direction perpendicular to the first direction), a first etching process is performed to pattern the first dielectric layer 110. The first etching process forms one or more sidewalls 110s of the first dielectric layer 110, which define a plurality of openings 902 extending through the first dielectric layer 110. In some embodiments, the plurality of openings 902 may each have a substantially rectangular shape when viewed from top to bottom. In other embodiments, the plurality of openings 902 may each have a generally circular, generally square, or other shape when viewed from top to bottom. In some embodiments, the first etching process may be performed by exposing the first dielectric layer 110 to a first etchant 904 according to a first mask 906. In some embodiments, the first etchant 904 may include a dry etchant (e.g., a reactive ion etchant (RIE) etchant, a plasma etchant, etc.). In some embodiments, the first etchant 904 may have one or more etching chemicals including fluorine (F), tetrafluoromethane (CF4), ozone (O2), and octafluorocyclobutane (C4F8). In some embodiments, the first mask 906 may include a photosensitive material (e.g., photoresist), a hard mask, etc.

[0072] like Figure 10 As shown in cross-sectional view 1000, a capacitor stack 1001 is formed above a first dielectric layer 110 and within a plurality of openings 902. In some embodiments, the capacitor stack 1001 may be formed by the following steps: forming a lower electrode layer 1002 along one or more sidewalls 110s and the upper surface of the first dielectric layer 110; forming a capacitor dielectric layer 1004 along the sidewalls and the upper surface of the lower electrode layer 1002; forming an upper electrode layer 1006 along the sidewalls and the upper surface of the capacitor dielectric layer 1004; and forming a dielectric layer 1008 along the sidewalls and the upper surface of the upper electrode layer 1006. In some embodiments, the lower electrode layer 1002, the capacitor dielectric layer 1004, the upper electrode layer 1006, and the dielectric layer 1008 may be formed by various deposition processes (e.g., PVD, CVD, PE-CVD, ALD, etc.).

[0073] like Figure 11As shown in cross-sectional view 1100, one or more capping layers 1102 are formed over a capacitor stack 1001. In some embodiments, the one or more capping layers 1102 may include an anti-reflective layer. In some embodiments, a masking layer 1104 is formed over the one or more capping layers 1102. A second mask 1106 is then formed over the one or more capping layers 1102 and / or the masking layer 1104. The second mask 1106 may be formed to directly cover a plurality of openings 902 within the first dielectric layer 110. In some embodiments, the masking layer 1104 and the one or more capping layers 1102 may each comprise a dielectric. For example, in some embodiments, the one or more capping layers 1102 may comprise silicon oxynitride, while the masking layer 1104 may comprise silicon nitride. In some embodiments, the second mask 1106 may comprise a photosensitive material (e.g., photoresist), a hard mask, etc.

[0074] like Figure 12 As shown in the cross-sectional view 1200, a second etching process is performed based on the second mask 1106. The second etching process removes the mask layer (e.g., Figure 11 Part of 1104), one or more overlays (e.g., Figure 11 Part of 1102), dielectric layer (e.g., Figure 11 The portion of 1008) and the upper electrode layer (e.g., Figure 11 A portion of the second etch layer 1006 defines a masking layer 206, a cover structure 118, a dielectric layer 204, and an upper electrode 116. The second etch process also exposes the upper surface of the capacitor dielectric layer 1004. In some embodiments, according to the second mask 1106, the second etch process uses a second etchant 1202 to etch the masking layer, one or more cover layers, the dielectric layer, and the upper electrode layer. In some embodiments, the second etchant 1202 may include a dry etchant (e.g., a reactive ion etching (RIE) etchant, a plasma etchant, etc.). In some embodiments, the second etchant 1202 may have an etch chemical comprising one or more of tetrafluoromethane (CF4), fluoroform (CHF3), chlorine (Cl2), nitrogen (N2), argon (Ar), boron trichloride (BCl3), and boron trichloride (BCl3).

[0075] like Figure 13As shown in cross-sectional view 1300, spacer structure 1302 is formed along the horizontally extending surfaces of cover structure 118 and capacitor dielectric layer 1004, and also along the sidewalls of cover structure 118 and upper electrode 116. In some embodiments, spacer structure 1302 includes a first dielectric layer 1304 and a second dielectric layer 1306 above the first dielectric layer 1304. The first dielectric layer 1304 and the second dielectric layer 1306 extend continuously between the outermost sidewalls of spacer structure 1302. In some embodiments, spacer structure 1302 can be formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CV process, etc.). In various embodiments, spacer structure 1302 can include silicon nitride, silicon dioxide, silicon oxynitride, etc. In some embodiments, the thickness of spacer structure 1302 is between approximately 100 angstroms and approximately 1500 angstroms, between approximately 50 angstroms and approximately 1000 angstroms, between approximately 250 angstroms and approximately 7500 angstroms, and approximately 500 angstroms or other similar values.

[0076] like Figure 14 As shown in cross-sectional view 1400, during the third etching process, the spacer structure (e.g., Figure 13 1302) is exposed to the third etchant 1402. The third etchant removes the spacer structure (e.g., from the horizontally extending surface) Figure 13 1302). Remove the spacer structure from the horizontally extending surface (e.g., Figure 13 (1302) Leaves a portion of the spacer structure along the opposite sidewalls of the covering structure 118 and the upper electrode 116 (e.g., Figure 13 The third etchant 1402 may be used as spacer 120 (e.g., a self-aligning pad spacer). In some embodiments, the third etchant 1402 may include a dry etchant (e.g., a reactive ion etching (RIE) etchant, a plasma etchant, etc.). In some embodiments, the third etchant 1402 may have one or more etching chemicals including tetrafluoromethane (CF4), chloroform (CHF3), chlorine (Cl2), nitrogen (N2), argon (Ar), boron trichloride (BCl3), and boron trichloride (BCl3).

[0077] In some embodiments, the lower electrode layer (e.g., Figure 13 1002) and capacitor dielectric layer (e.g., Figure 13A portion of (1004) is then exposed to a fourth etchant according to spacer 120 to define the lower electrode 112 and capacitor dielectric 114 of MIM capacitor structure 111. In some embodiments, the fourth etchant may be the same etchant as the third etchant 1402 (e.g., as part of a continuous etching process defining spacer 120), while in other embodiments, the fourth etchant may include an etchant independent of and different from the third etchant 1402. Since the lower electrode layer and capacitor dielectric layer are etched according to spacer 120, spacer 120 has an outermost wall that is substantially aligned with the outermost wall of the lower electrode 112 and capacitor dielectric 114.

[0078] By using spacer 120 to define the lower electrode 112 and the capacitor dielectric 114, the lower electrode 112 can be formed to have a package area with similar dimensions to the upper electrode 116. Furthermore, using spacer 120 to define the lower electrode 112 allows both the upper electrode 116 and the lower electrode 112 to be formed using a single photomask, thereby providing a relatively low-cost process for forming the MIM capacitor structure 111 (e.g., compared to processes using different photomasks to define the upper and lower electrodes). Additionally, positioning spacer 120 during the third etching process allows spacer 120 to cover the sidewalls of the upper electrode 116 and prevents conductive byproducts (e.g., from the etched lower electrode layer) from redepositing along the sidewalls of the upper electrode 116. By preventing the redeposition of conductive byproducts along the sidewalls of the upper electrode 116, conductive byproducts cannot form conductive paths between the lower electrode 112 and the upper electrode 116, thereby preventing electrical short circuits between the lower electrode 112 and the upper electrode 116.

[0079] like Figure 15 As shown in cross-sectional view 1500, a second dielectric layer 212 is formed over the MIM capacitor structure 111 and the first dielectric layer 110. In some embodiments, the second dielectric layer 212 may include oxides, low-k dielectric materials, etc. The second dielectric layer 212 may be formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, ALD process, etc.).

[0080] like Figure 16As shown in cross-sectional view 1600, a fifth etching process is then performed to form one or more upper interconnect openings 1602 within the second dielectric layer 212. The one or more upper interconnect openings 1602 extend through the second dielectric layer 212, masking layer 206, overlay structure 118, and dielectric 204, exposing the upper surface of the upper electrode 116. In some embodiments, the fifth etching process may be performed by exposing the second dielectric layer 212 to a fifth etchant 1604, according to a third mask 1606. In some embodiments, the fifth etchant 1604 may comprise a plasma etchant having an etching chemical substance, including one or more of fluorine (F), tetrafluoromethane (CF4), ozone (O2), and octafluorocyclobutane (C4F8). In some embodiments, the third mask 1606 may comprise a photosensitive material (e.g., photoresist), a hard mask, etc.

[0081] like Figure 17 As shown in cross-sectional view 1700, an upper interconnect structure 122 is formed within a second dielectric layer 212. In some embodiments, the upper interconnect structure 122 can be formed by forming a conductive material in one or more upper interconnect openings 1602 etched into the second dielectric layer 212. In some embodiments, the conductive material can be formed by a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the conductive material may include copper, aluminum, etc. After the conductive material is formed within the upper interconnect openings 1602, a planarization process may be performed to remove excess conductive material over the second dielectric layer 212 and define the upper interconnect structure 122. In some embodiments, the upper interconnect structure 122 may include an upper interconnect via 122v and an upper interconnect wiring 122w.

[0082] Figure 18 Flowcharts of some embodiments of a method 1800 for forming an integrated chip with a high-density MIM capacitor structure are shown.

[0083] Although the methods (e.g., methods 1800 and 3000) are illustrated and described herein as a series of actions or events, it should be understood that the order of these actions or events shown should not be interpreted as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all illustrated actions may be required to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0084] At action 1802, one or more lower interconnects are formed within the lower dielectric structure above the substrate. Figure 7 A cross-sectional view 700 is shown, corresponding to some embodiments of action 1802.

[0085] At action 1804, a first dielectric layer is formed above the lower dielectric structure. Figure 8 A cross-sectional view 800 is shown, corresponding to some embodiments of action 1804.

[0086] At action 1806, the first dielectric layer is patterned to form multiple openings. Figures 9A to 9B Cross-sectional views 900 and 908 are shown for some embodiments corresponding to action 1806.

[0087] At action 1808, a lower electrode layer is formed above the first dielectric layer and within a plurality of openings. Figure 10 A cross-sectional view 1000 is shown, corresponding to some embodiments of action 1808.

[0088] At operation 1810, a capacitor dielectric layer is formed on the lower electrode layer. Figure 10 A cross-sectional view 1000 is shown, corresponding to some embodiments of action 1810.

[0089] At action 1812, an upper electrode layer is formed on the dielectric layer of the capacitor. Figure 10 A cross-sectional view 1000 is shown, corresponding to some embodiments of action 1812.

[0090] At action 1814, one or more covering layers are formed above the upper electrode layer. Figure 11 A cross-sectional view 1100 is shown, corresponding to some embodiments of action 1814.

[0091] At action 1816, one or more cover layers and upper electrode layers are patterned outside the mask to define the cover structure and upper electrode. Figures 11 to 12 Cross-sectional views 1100 to 1200 are shown for some embodiments corresponding to action 1816.

[0092] At action 1818, spacers (e.g., self-aligning spacers) are formed along the opposite sides of the upper electrode and the cover structure. Figures 13 to 14 Cross-sectional views 1300 to 1400 are shown for some embodiments corresponding to action 1818.

[0093] At action 1820, the lower electrode layer and capacitor dielectric layer are patterned according to the spacer to define the lower electrode and capacitor dielectric of the MIM capacitor structure. Figure 14 A cross-sectional view 1400 is shown, corresponding to some embodiments of action 1820.

[0094] At action 1822, a second dielectric layer is formed above the MIM capacitor structure. Figure 15 A cross-sectional view 1500 is shown, corresponding to some embodiments of action 1822.

[0095] At action 1824, an upper interconnect structure is formed to extend through the cover structure to contact the upper electrode. Figures 16 to 17 Cross-sectional views 1600 to 1700 are shown for some embodiments corresponding to action 1824.

[0096] Figures 19 to 29 Cross-sectional views 1900 to 2900 show some alternative embodiments of a method for forming an integrated chip with a high-density MIM capacitor structure. Although Figures 19 to 29 It describes a method, but it should be understood that... Figures 19 to 29 The structure disclosed in the method may not be limited to this method, but may exist independently of this method.

[0097] like Figure 19 As shown in cross-sectional view 1900, one or more lower interconnects 104 are formed within a lower dielectric structure 106, which is formed on a substrate 102.

[0098] like Figure 20 As shown in the cross-sectional view 2000, a first etch stop layer 108 is formed above the lower dielectric structure 106 and a first dielectric layer 110 is formed above the first etch stop layer 108.

[0099] like Figure 21A Cross-sectional view 2100 (taken along the first direction) and Figure 21B As shown in cross-sectional view 2102 (taken along a second direction perpendicular to the first direction), a first etching process is performed to pattern the first dielectric layer 110. The first etching process forms one or more sidewalls 110s of the first dielectric layer 110, the one or more sidewalls 110s defining a plurality of openings 902 extending through the first dielectric layer 110.

[0100] like Figure 22 As shown in cross-sectional view 2200, a capacitor stack 1001 is formed above a first dielectric layer 110 and within a plurality of openings 902. In some embodiments, the capacitor stack 1001 may be formed by the following steps: forming a lower electrode layer 1002 along one or more sidewalls 110s and the upper surface of the first dielectric layer 110; forming a capacitor dielectric layer 1004 along the sidewalls and the upper surface of the lower electrode layer 1002; forming an upper electrode layer 1006 along the sidewalls and the upper surface of the capacitor dielectric layer 1004; and forming a dielectric layer 1008 along the sidewalls and the upper surface of the upper electrode layer 1006.

[0101] like Figure 23As shown in cross-sectional view 2300, one or more capping layers 1102 are formed over the capacitor stack 1001. A second mask 2302 is then formed over the capping layers 1102. The second mask 2302 may be formed to directly cover a plurality of openings 902 within the first dielectric layer 110. In some embodiments, the second mask 2302 may include a photosensitive material (e.g., photoresist), a hard mask, etc.

[0102] like Figure 24 As shown in the cross-sectional view 2400, a second etching process is performed according to the second mask 2302. The second etching process removes one or more overlay layers (e.g., Figure 11 Part of 1102), dielectric layer (e.g., Figure 11 The portion of 1008) and the upper electrode layer (e.g., Figure 11 The second etching process defines a portion of the capacitor dielectric layer 1004 (1006) to cover the structure 118, dielectric 204, and upper electrode 116. The second etching process also exposes the upper surface of the capacitor dielectric layer 1004. In some embodiments, the second etchant 2402 may include a dry etchant (e.g., a reactive ion etching (RIE) etchant, a plasma etchant, etc.). In some embodiments, the second etchant 2402 may have one or more etching chemicals including tetrafluoromethane (CF4), fluoroform (CHF3), chlorine (Cl2), nitrogen (N2), argon (Ar), boron trichloride (BCl3), etc.

[0103] like Figure 25 As shown in cross-sectional view 2500, spacer structure 2502 is formed along the horizontally extending surfaces of cover structure 118 and capacitor dielectric layer 1004, and along the sidewalls of cover structure 118 and upper electrode 116. In some embodiments, spacer structure 2502 includes a first dielectric layer 2504 and a second dielectric layer 2506 above the first dielectric layer 2504. The first dielectric layer 2504 and the second dielectric layer 2506 extend continuously between the outermost sidewalls of spacer structure 2502. In some embodiments, the thickness of spacer structure 2502 is in the range of approximately 100 angstroms to approximately 1500 angstroms, approximately 50 angstroms to approximately 1000 angstroms, or other similar values.

[0104] like Figure 26 As shown in cross-sectional view 2600, a third mask 2602 is formed above the spacer structure 2502. In some embodiments, the third mask 2602 may extend beyond the outermost wall of the upper electrode 116 and the cover structure 118. In some embodiments, the third mask 2602 may extend beyond a non-zero distance 506 between the outermost wall of the upper electrode 116 and the cover structure 118. In some embodiments, the non-zero distance 506 may be between about 50 Å and about 750 Å. In some embodiments, the third mask 2602 may be completely confined within the spacer structure (e.g., Figure 26 Above the top surface of the third mask 2502. In such an embodiment, the third mask 2602 may have a spacer structure (e.g., Figure 26 The bottom surface above the top surface of the third mask 2502. In some embodiments, the third mask 2602 may include a photosensitive material (e.g., photoresist), a hard mask, etc.

[0105] like Figure 27 As shown in the cross-sectional view 2700, a third etching process is performed according to the third mask 2602 to remove the spacer structure (e.g., Figure 26 The 2502 portion of the spacer structure is exposed to the third etchant 2702. The third etchant 2702 removes the unmasked portions of the spacer structure (e.g., Figure 26 (2502) to define spacer 120. In some embodiments, the lower electrode layer (e.g., according to spacer 120) is then... Figure 26 1002) and capacitor dielectric layer (e.g. Figure 26 A portion of the 1004 layer is exposed to the fourth etchant to define the lower electrode 112 and capacitor dielectric 114 of the MIM capacitor structure 111. Since the lower electrode layer and capacitor dielectric layer are etched according to the spacer 120, the spacer 120 has an outermost wall substantially aligned with the outermost walls of the lower electrode 112 and capacitor dielectric 114. In some embodiments, the fourth etchant may be the same etchant as the third etchant 2702 (e.g., as part of a continuous etching process defining the spacer 120), while in other embodiments, the fourth etchant may include an etchant separate from and different from the third etchant 2702.

[0106] like Figure 28 As shown in cross-sectional view 2800, a second dielectric layer 212 is formed above the MIM capacitor structure 111 and the first dielectric layer 110.

[0107] like Figure 29 As shown in cross-sectional view 2900, an upper interconnect structure 122 is subsequently formed within one or more upper interconnect openings 1602 in the second dielectric layer 212. In some embodiments, the upper interconnect structure 122 may include upper interconnect vias 122v and upper interconnect wiring 122w.

[0108] Figure 30 Flowcharts of some alternative embodiments of a method 3000 for forming an integrated chip with a high-density MIM capacitor structure are shown.

[0109] At action 3002, one or more lower interconnects are formed within the lower dielectric structure above the substrate. Figure 19 A cross-sectional view 1900 is shown, corresponding to some embodiments of action 3002.

[0110] At action 3004, a first dielectric layer is formed above the lower dielectric structure. Figure 20 Cross-sectional view 2000 is shown for some embodiments corresponding to action 3004.

[0111] In action 3006, the first dielectric layer is patterned to form multiple openings. Figures 21A to 21B Cross-sectional views 2100 to 2102 are shown for some embodiments corresponding to action 3006.

[0112] At action 3008, a lower electrode layer is formed above the first dielectric layer and within a plurality of openings. Figure 22 Cross-sectional view 2200 is shown for some embodiments corresponding to action 3008.

[0113] At action 3010, a capacitor dielectric layer is formed on the lower electrode layer. Figure 22 A cross-sectional view 2200 is shown, corresponding to some embodiments of action 3010.

[0114] At action 3012, an upper electrode layer is formed on the capacitor dielectric layer. Figure 22 A cross-sectional view 2200 is shown, corresponding to some embodiments of action 3012.

[0115] At action 3014, one or more covering layers are formed above the upper electrode layer. Figure 23 A cross-sectional view 2300 is shown, corresponding to some embodiments of action 3014.

[0116] At action 3016, one or more cover layers and upper electrode layers are patterned outside the first mask to define the cover structure and the upper electrode. Figures 23 to 24 Cross-sectional views 2300 to 2400 are shown for some embodiments corresponding to action 3016.

[0117] At action 3018, a spacer structure is formed above the upper electrode and the covering structure and along the opposite sides of the upper electrode and the covering structure. Figure 25 A cross-sectional view 2500 is shown, corresponding to some embodiments of action 3018.

[0118] At action 3020, a second mask is formed above the spacer structure. Figure 26 A cross-sectional view 2600 is shown, corresponding to some embodiments of action 3020.

[0119] At action 3022, according to the second mask, the spacing structure, the lower electrode layer and the capacitor dielectric layer are patterned to define the lower electrode and capacitor dielectric of the MIM capacitor structure. Figure 27 Cross-sectional view 2700 is shown for some embodiments corresponding to action 3022.

[0120] At action 3024, a second dielectric layer is formed above the MIM capacitor structure. Figure 28 Cross-sectional view 2800 is shown for some embodiments corresponding to action 3024.

[0121] In action 3026, an upper interconnect structure is formed to extend through the cover structure to contact the upper electrode. Figure 29 A cross-sectional view 2900 is shown, corresponding to some embodiments of action 3026.

[0122] Therefore, in some embodiments, this disclosure relates to a method of forming a MIM device having an upper electrode and a lower electrode having a package area having similar dimensions (e.g., differing from each other by about 10%).

[0123] In some embodiments, this disclosure relates to a method of forming a capacitor structure, the method comprising forming a capacitor dielectric layer over a lower electrode layer; forming an upper electrode layer over the capacitor dielectric layer; etching the upper electrode layer to define an upper electrode and expose a portion of the capacitor dielectric layer; forming a spacer structure on a horizontally extending surface of the upper electrode layer and the capacitor dielectric layer and along the sidewalls of the upper electrode; etching the spacer structure to remove the spacer structure from above the horizontally extending surface of the upper electrode layer and the capacitor dielectric layer and define a spacer; and etching the capacitor dielectric layer and the lower electrode layer according to the spacer to define the capacitor dielectric layer and the lower electrode. In some embodiments, the method may further comprise forming one or more capping layers over the upper electrode layer; etching one or more capping layers to define a capping structure; and forming a spacer structure above the horizontally extending surface of the capping structure and along the sidewalls of the capping structure. In some embodiments, the method may further comprise forming a dielectric layer between the upper electrode layer and the sidewalls of the upper electrode layer prior to forming one or more capping layers, wherein a first etching process for etching the upper electrode layer to define the upper electrode layer further removes a portion of the dielectric layer. In some embodiments, during etching of the lower electrode layer, material from the lower electrode layer is redeposited onto the spacer and the sidewalls of the capacitor dielectric layer. In some embodiments, the spacer structure includes a first dielectric and a second dielectric disposed along the sidewalls and lower surface of a first dielectric. In some embodiments, the outermost sidewall of the lower electrode is aligned with the outermost surface of the spacer. In some embodiments, the method further includes forming one or more lower interconnects within the lower dielectric structure above a substrate; forming a first dielectric layer above the lower dielectric structure; patterning the first dielectric layer to define a plurality of openings extending through the first dielectric layer to expose one or more lower interconnects, a lower electrode layer, an upper electrode layer, and a capacitor dielectric layer formed within the plurality of openings and above the first dielectric layer. In some embodiments, the patterning process of etching the lower electrode layer also removes portions of the first dielectric layer. In some embodiments, the plurality of openings, viewed from a top view of the first dielectric layer, each has a generally rectangular shape. In some embodiments, the plurality of openings are arranged in an array, the array including a first plurality of openings arranged in a first column extending along a first direction perpendicular to the first direction. In some embodiments, the upper electrode covers between approximately 90% and approximately 95% of the lower electrode.

[0124] In other embodiments, this disclosure relates to a method of forming a capacitor structure, the method comprising forming one or more lower interconnects within a lower dielectric structure above a substrate; forming a first dielectric layer above the lower dielectric structure; forming a plurality of openings extending through the first dielectric layer to expose the one or more lower interconnects; forming a capacitor stack having a capacitor dielectric layer between a lower electrode layer and an upper electrode layer above the first dielectric layer and within the plurality of openings; forming one or more capping layers on the upper electrode layer; etching the one or more capping layers and the upper electrode layer to define a capping structure above the upper electrode; forming spacers along the sidewalls of the capping structure and the upper electrode, the spacers having an outermost surface extending from the capacitor dielectric layer to the top of the spacers; and etching the capacitor dielectric layer and the lower electrode layer according to the spacers to define a capacitor dielectric layer above the lower electrode. In some embodiments, the method further comprises forming a second dielectric layer on the first dielectric layer and along the sidewalls of the first dielectric layer; forming one or more additional interconnects within the second dielectric layer, the one or more additional interconnects being laterally separated from the lower electrode through the first dielectric layer and the second dielectric layer. In some embodiments, the method further includes patterning a second dielectric layer and a capping structure to form an upper interconnect opening exposing the upper electrode; and forming a conductive material within the upper interconnect opening. In some embodiments, the lower electrode is completely confined below the spacer and the upper electrode. In some embodiments, the spacer extends continuously along a closed path surrounding the outermost wall of the upper electrode.

[0125] In other embodiments, this disclosure relates to a metal-insulator-metal (MIM) capacitor structure, comprising: one or more lower interconnects disposed within a lower dielectric structure above a substrate; a first dielectric layer above the lower dielectric structure, the first dielectric layer having sidewalls defining a plurality of openings extending through the first dielectric layer; a lower electrode disposed along the sidewalls of the first dielectric layer and above a upper surface; a capacitor dielectric disposed along the sidewalls of the lower electrode and the upper surface; an upper electrode disposed along the sidewalls of the capacitor dielectric and the upper surface; and a spacer along the opposite outermost wall of the upper electrode, the spacer having an outermost surface extending from the lowermost surface of the spacer to the top of the spacer, the outermost surface being substantially aligned with the outermost wall of the lower electrode. In some embodiments, the outermost wall of the lower electrode is substantially aligned with the sidewall of the first dielectric layer. In some embodiments, the MIM capacitor structure further includes a cover structure located above the upper electrode, spacers covering the sidewalls of the upper electrode and the cover structure; and the spacers having a first dielectric and a second dielectric; the first dielectric having a horizontal extension separating the second dielectric from the capacitor dielectric and a vertical extension separating the second dielectric from the upper electrode and the cover structure. In some embodiments, the total package area of ​​the upper electrode and the spacers is substantially equal to the package area of ​​the lower electrode.

[0126] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a capacitor structure, comprising: One or more lower interconnects are formed within the lower dielectric structure above the substrate; A first dielectric layer is formed above the lower dielectric structure; The first dielectric layer is patterned to define a plurality of openings that extend through the first dielectric layer to expose the one or more underlying interconnects; A capacitor dielectric layer is formed above the lower electrode layer; An upper electrode layer is formed above the capacitor dielectric layer, wherein the lower electrode layer, the upper electrode layer, and the capacitor dielectric layer are formed within the plurality of openings and above the first dielectric layer; Etch the upper electrode layer to define the upper electrode and expose a portion of the capacitor dielectric layer; A spacer structure is formed above the horizontally extending surface of the upper electrode layer and the capacitor dielectric layer, and along the sidewall of the upper electrode; Etching the spacer structure to remove the spacer structure from above the horizontally extending surface of the upper electrode layer and the capacitor dielectric layer and defining the spacer; and The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define the capacitor dielectric and the lower electrode.

2. The method according to claim 1, further comprising: One or more cover layers are formed above the upper electrode layer; Etch the one or more cover layers to define the cover structure; as well as The spacer structure is formed above the horizontally extending surface of the covering structure and along the sidewalls of the covering structure.

3. The method according to claim 2, further comprising: Prior to forming the one or more cover layers, a dielectric layer is formed above the upper electrode layer and between the sidewalls of the upper electrode layer, wherein a first etching process, which etches the upper electrode layer to define the upper electrode, also removes a portion of the dielectric layer.

4. The method according to claim 1, wherein, During the etching of the lower electrode layer, material from the lower electrode layer is redeposited onto the sidewalls of the spacer and the capacitor dielectric layer.

5. The method according to claim 1, wherein, The spacer structure includes a first dielectric and a second dielectric disposed along the sidewalls and lower surface of the first dielectric.

6. The method according to claim 1, wherein, The outermost wall of the lower electrode is aligned with the outermost surface of the spacer.

7. The method according to claim 1, wherein, The top surface of the spacer extends laterally to different distances beyond the opposite sides of the upper electrode.

8. The method according to claim 1, wherein, The patterning process of etching the lower electrode layer also removes a portion of the first dielectric layer.

9. The method according to claim 1, wherein, From a top view of the first dielectric layer, the plurality of openings each have a rectangular shape.

10. The method according to claim 1, wherein, The plurality of openings are arranged in an array, the array including a first plurality of openings arranged in a first column extending along a first direction, and a second plurality of openings arranged in a first row extending along a second direction perpendicular to the first direction.

11. The method according to claim 1, wherein, The upper electrode covers between 90% and 95% of the lower electrode.

12. A method for forming a capacitor structure, comprising: One or more lower interconnects are formed within the lower dielectric structure above the substrate; A first dielectric layer is formed above the lower dielectric structure; Forming a plurality of openings extending through the first dielectric layer to expose the one or more lower interconnects; A capacitor stack is formed above the first dielectric layer and within the plurality of openings, the capacitor stack including a capacitor dielectric layer located between a lower electrode layer and an upper electrode layer; One or more cover layers are formed above the upper electrode layer; Etch the one or more cover layers and the upper electrode layer to define a cover structure above the upper electrode; A spacer is formed along the sidewall of the cover structure and the upper electrode, wherein the spacer has an outermost surface extending from the capacitor dielectric layer to the top of the spacer; as well as The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define the capacitor dielectric above the lower electrode.

13. The method of claim 12, further comprising: A second dielectric layer is formed on the first dielectric layer and along the sidewall of the first dielectric layer; as well as One or more additional interconnects are formed within the second dielectric layer, and the one or more additional interconnects are laterally separated from the lower electrode through the first dielectric layer and the second dielectric layer.

14. The method of claim 13, further comprising: The second dielectric layer and the overlay structure are patterned to form an upper interconnect opening that exposes the upper electrode; as well as Conductive material is formed within the upper interconnect opening.

15. The method according to claim 12, wherein, The lower electrode is completely confined below the spacer and the upper electrode.

16. The method according to claim 12, wherein, The spacer extends continuously along a closed path surrounding the outermost wall of the upper electrode.

17. A metal-insulator-metal capacitor structure, comprising: One or more lower interconnects are disposed within a lower dielectric structure above the substrate; A first dielectric layer is located above the lower dielectric structure, wherein the first dielectric layer includes sidewalls defining a plurality of openings extending through the first dielectric layer; The lower electrode is arranged along the sidewall of the first dielectric layer and above the upper surface of the first dielectric layer, and directly contacts the upper surface of the one or more lower interconnects; The capacitor dielectric is arranged along the sidewall of the lower electrode and the upper surface of the lower electrode; The upper electrode is arranged along the sidewalls of the capacitor dielectric and the upper surface of the capacitor dielectric; and A spacer along the outermost wall of the upper electrode, wherein the spacer has an outermost surface extending from the lowermost surface of the spacer to the top of the spacer, the outermost surface being aligned with the outermost wall of the lower electrode.

18. The metal-insulator-metal capacitor structure according to claim 17, wherein, The outermost wall of the lower electrode is aligned with the sidewall of the first dielectric layer.

19. The metal-insulator-metal capacitor structure according to claim 17, further comprising: A covering structure, located above the upper electrode, wherein the spacer covers the upper electrode and the sidewalls of the covering structure; and The spacer includes a first dielectric and a second dielectric, wherein the first dielectric has a horizontal extension separating the second dielectric from the capacitor dielectric and a vertical extension separating the second dielectric from the upper electrode and the cover structure.

20. The metal-insulator-metal capacitor structure according to claim 17, wherein, The total encapsulation area of ​​the upper electrode and the spacer is equal to the encapsulation area of ​​the lower electrode.

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