Metal-insulator-metal capacitor and method of forming the same

Abstract

The present disclosure relates to metal-insulator-metal capacitors and methods of forming the same. An integrated circuit (IC) device includes a metal-insulator-metal (MIM) capacitor having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate. A plurality of dielectric layers can separate each electrode plate of the MIM capacitor from an adjacent plate of the MIM capacitor. A thickness of each intermediate electrode plate can be greater than a thickness of the top electrode plate and the bottom electrode plate. By providing a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate of the MIM capacitor, and allocating a maximum plate thickness to the intermediate plates, a capacitance density can be provided in a given area of the IC device, which can provide higher IC device performance.

Description

Technical Field

[0001] This disclosure generally relates to metal-insulator-metal capacitors and methods for forming the same. Background Technology

[0002] Typically, a capacitor comprises two conductive electrodes located on opposite sides of a dielectric or other dielectric layer, and can be classified based on the materials used to form the capacitor. For example, in a metal-insulator-metal (MIM) capacitor, as the name suggests, the electrodes are essentially made of metallic material and the insulator may comprise a dielectric layer. The advantage of MIM capacitors is that they have a relatively constant capacitance value over a relatively wide range of voltages applied to them. MIM capacitors also exhibit relatively low parasitic resistance.

[0003] In integrated circuit design, on-chip capacitors are used in a variety of applications, including dynamic random access memory (DRAM), voltage-controlled oscillators (VCOs), phase-locked loops, operational amplifiers, and other circuit designs. On-chip capacitors can also be used as decoupling capacitors, configured to mitigate switching noise that may be caused by the switching of logic devices on the integrated circuit. Summary of the Invention

[0004] According to one aspect of this disclosure, an integrated circuit (IC) device having a metal-insulator-metal (MIM) capacitor is provided, the MIM capacitor comprising: a top electrode plate; a bottom electrode plate; a plurality of intermediate electrode plates stacked between the top electrode plate and the bottom electrode plate; and a plurality of dielectric layers separating each of the top electrode plate, the bottom electrode plate, and each of the plurality of intermediate electrode plates from adjacent electrode plates of the MIM capacitor, wherein the thickness of each of the plurality of intermediate electrode plates is greater than the thickness of the top electrode plate and the bottom electrode plate.

[0005] According to another aspect of this disclosure, a method is provided for manufacturing a metal-insulator-metal (MIM) capacitor between a first conductive via and a second conductive via on an integrated circuit (IC) device, comprising: determining whether a package resonant frequency of the IC device is greater than a threshold frequency; determining the capacitance of the MIM capacitor based on a default plate count of the electrode plates of the MIM capacitor and a default distance between the first conductive via and the second conductive via; increasing the plate count of the electrode plates of the MIM capacitor when the package resonant frequency of the IC device is not greater than the threshold frequency and the capacitance of the MIM capacitor does not meet a predetermined performance standard; and decreasing the distance between the first conductive via and the second conductive via when the package resonant frequency of the IC device is greater than the threshold frequency and the capacitance of the MIM capacitor does not meet the design requirements of the MIM capacitor.

[0006] According to another aspect of this disclosure, a method for manufacturing an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor is provided, comprising: forming a bottom electrode plate on an insulating material layer; forming a first dielectric material layer on the bottom electrode plate; forming a plurality of intermediate electrode plates on the first dielectric material layer, wherein the thickness of each of the intermediate electrode plates is greater than the thickness of the bottom electrode plate; forming a second dielectric material layer on the plurality of intermediate electrode plates; forming a top electrode plate on the second dielectric material layer, wherein the thickness of the top electrode plate is less than the thickness of each of the intermediate electrode plates; and forming a pair of conductive vias laterally adjacent to the electrode plates of the MIM capacitor, wherein each of the pair of conductive vias is conductively coupled to at least two electrode plates of the MIM capacitor. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1A This is a vertical cross-sectional view of an exemplary structure of a part of an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor located between two conductive vias.

[0009] Figure 1B This is a schematic representation of the total capacitance of the MIM capacitor. Figure 1A A vertical cross-sectional view of an exemplary structure.

[0010] Figure 1C yes Figure 1A and Figure 1B The image shows an enlarged vertical cross-sectional view of the central region of the MIM capacitor.

[0011] Figure 2 This is a graph showing the normalized capacitance of a MIM capacitor as a function of the thickness of the intermediate electrode plate at a package resonant frequency of 200 MHz.

[0012] Figure 3 This is a graph showing the effective capacitance as a function of the package resonant frequency for three MIM capacitors with different intermediate electrode plate thicknesses.

[0013] Figure 4 This is a horizontal cross-sectional view of an exemplary structure that includes a MIM capacitor and multiple conductive vias as part of an integrated circuit (IC) device.

[0014] Figure 5 This is a horizontal cross-sectional view illustrating an exemplary structure of an array of conductive vias arranged according to an embodiment of the present disclosure.

[0015] Figure 6 This is a horizontal cross-sectional view illustrating an exemplary structure of another arrangement of an array of conductive vias according to an embodiment of the present disclosure.

[0016] Figure 7 This is a horizontal cross-sectional view illustrating an exemplary structure of yet another arrangement of an array of conductive vias according to an embodiment of the present disclosure.

[0017] Figure 8 This is a horizontal cross-sectional view illustrating an exemplary structure of yet another arrangement of an array of conductive vias according to an embodiment of the present disclosure.

[0018] Figure 9A and Figure 9B yes Figure 8 An exemplary structure is shown in a vertical cross-sectional view along line A-A', illustrating different configurations of MIM capacitors between conductive vias according to various embodiments of the present disclosure.

[0019] Figure 10 This is a graph showing the admittance of a MIM capacitor as a function of via-to-via distance for IC device packages with resonant frequencies of 40MHz and 200MHz.

[0020] Figure 11A This is a flowchart illustrating a method for designing a MIM capacitor coupled between a first via and a second via in an IC device according to an embodiment of the present disclosure.

[0021] Figure 11B It is a schematic illustration of what can be used to perform Figure 11A A block diagram of the processing device for the method.

[0022] Figure 12 This is a graph showing the admittance of MIM capacitors with different board thicknesses as a function of via-to-via distance for an IC device package having a resonant frequency of 200MHz according to an embodiment of the present disclosure.

[0023] Figure 13 This is a graph showing the admittance of MIM capacitors with different board opening sizes as a function of via-to-via distance for an IC device package having a resonant frequency of 200MHz according to an embodiment of the present disclosure.

[0024] Figure 14 This illustrates the minimum Vi as a function of via-to-via distance for IC devices with different MIM capacitors according to embodiments of the present disclosure. dd The curve graph.

[0025] Figure 15 This is a graph showing the percentage gain of the operating speed of an IC device as a function of via-to-via distance for different MIM capacitor configurations.

[0026] Figure 16 This is a graph showing the minimum ring frequency of an IC device as a function of via-to-via distance for different MIM capacitor configurations.

[0027] Figures 17A-17Q This is a sequential vertical cross-sectional view illustrating exemplary structures during the formation of a MIM capacitor according to various embodiments of the present disclosure.

[0028] Figure 18 This is a flowchart illustrating the general processing steps of the method of this disclosure. Detailed Implementation

[0029] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0030] In addition, this document may use spatially relevant terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) to facilitate the description of the relationship between one element or feature as shown in the figure and another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein can be interpreted similarly.

[0031] This disclosure relates to semiconductor devices, and more specifically, to semiconductor devices having metal-insulator-metal (MIM) capacitors. An MIM capacitor is a capacitor comprising a top metal plate and a bottom metal plate separated by a thin layer of dielectric material. The advantage of MIM capacitors is that they have a relatively constant capacitance value over a relatively wide voltage range applied to them. MIM capacitors also exhibit relatively low parasitic resistance. In integrated circuit design, on-chip capacitors such as MIM capacitors can be used in a variety of applications, including dynamic random access memory (DRAM), voltage-controlled oscillators (VCOs), phase-locked loops, operational amplifiers, and other circuit designs. On-chip capacitors can also be used as decoupling capacitors, which can reduce noise on power lines that may be caused by the switching of logic devices within an integrated chip. For example, on-chip capacitors can be used to reduce switching noise caused by voltage drops on power lines due to simultaneous switching of input / output (I / O) and core circuitry within the integrated circuit (i.e., the chip). Without decoupling capacitors, this switching noise can increase signal delay, thereby reducing the operating frequency of the integrated circuit, and may also lead to unintended state transitions in the logic circuitry within the integrated circuit.

[0032] The capacitance of the capacitor needs to be increased because this increase improves performance. Capacitance can be expressed in farads. Where ε is the dielectric constant of the dielectric material (absolute, not relative), A is the area of ​​the overlapping plates (in square meters), and d is the distance between the plates (in meters). Therefore, as the area of ​​the overlapping plates increases, the capacitance also increases directly. Thus, one solution to increase capacitance is to increase the area of ​​the metal plates. However, in the context of semiconductor device manufacturing, increasing the plate area reduces the area density of the device that can ultimately be fabricated on the substrate, because the increased MIM footprint will consume the available space for other devices.

[0033] Various embodiments of this disclosure relate to integrated circuit (IC) devices including metal-insulator-metal (MIM) capacitors having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates located between the top and bottom electrode plates. Multiple dielectric layers separate each electrode plate of the MIM capacitor from its adjacent plates. The thickness of each intermediate electrode plate can be greater than the thickness of the top and bottom electrode plates. By providing a plurality of intermediate electrode plates between the top and bottom electrode plates of the MIM capacitor and allocating the largest plate thickness to the intermediate plates, capacitance density can be increased in a given region of the IC device, which can provide a higher-performance IC device without increasing the overall footprint of the MIM capacitor. Therefore, additional space can be provided for other devices.

[0034] Figure 1A This is a vertical cross-sectional view of an exemplary structure of a portion of an integrated circuit (IC) device 100, including a metal-insulator-metal (MIM) capacitor 105 located between two conductive vias 101 and 103. Reference Figure 1A In various embodiments, the MIM capacitor 105 may be located within the interconnect structure of the IC device 100. The interconnect structure may include multiple metal interconnect features, such as metal lines 107, 108, 109, and 110, and vias 101 and 103, which may be partially or completely embedded in one or more dielectric materials 118, 119, 120, and 121. The metal interconnect features of the interconnect structure may be electrically connected to the device structure of the IC device 100. The device structure may be a semiconductor device structure, such as a logic transistor, memory cell, diode, photoelectric sensor, etc. In some embodiments, a front-end process (FEOL) may be used on a semiconductor substrate (… Figure 1A Device structures are formed on and / or within (not shown). In various embodiments, interconnect structures including metal features 101, 103, 107, 108, 109, 110 and one or more MIM capacitors 105 may be formed on a semiconductor material substrate and the device structures thereon may be formed using a back-end process (BEOL) process.

[0035] Refer again Figure 1AThe interconnect structure of IC device 100 may include multiple metal layers M1, M2 (each metal layer comprising metal features 107, 108, 109, and 110), and dielectric material layers 119 and 120 between the respective metal layers M1, M2. Dielectric material layers 118, 119, 120, and 121 may be composed of suitable dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN, Si3N4), silicon carbide (SiC), undoped silicate glass (USG), doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Other dielectric materials are within the scope of this disclosure. Dielectric material layer 120 may be composed of a different dielectric material than dielectric material layers 118 and 119. In various embodiments, dielectric material layer 120 may be an etch stop layer having different etch characteristics (e.g., higher etch resistance) than one or more materials of adjacent dielectric material layers 118 and 119. In a non-limiting embodiment, dielectric material layer 119 may include silicon oxide, and dielectric material layer 120 may include silicon nitride. Dielectric material layer 119 may have a thickness T. height This thickness is greater than the thickness of the dielectric material layer 120.

[0036] Multiple conductive vias 101, 103 may extend through dielectric material layers 119, 120 to electrically couple metallic features 107, 108, 109, and 110 of different metal layers M1, M2. In various embodiments, conductive vias 101, 103 may include a barrier layer 104 along the sidewalls and bottom surface of each conductive via, and a metallic filler material 106 within the barrier layer 104. The barrier layer 104 may include a layer of TiN, TaN, WN, TiC, TaC, and WC, or combinations thereof. Other suitable materials for the barrier layer 104 are within the scope of this disclosure. The metallic filler material 106 may include suitable conductive materials, such as copper (Cu), tungsten (W), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tantalum (Ta), titanium (Ti), alloys thereof, combinations thereof, etc. Other conductive materials are within the scope of this disclosure.

[0037] Metal features 107, 108, 109, and 110 may be made of the same (one or more) conductive materials as conductive vias 101 and 103, or may be made of different (one or more) conductive materials. Furthermore, metal features 107, 108, and 109 may optionally include a barrier layer on one or more outer surfaces of metal features 107, 108, 109, and 110. Figure 1A (not shown in the image) and the metal filling material inside the barrier layer.

[0038] although Figure 1A An exemplary portion of the interconnect structure shown includes two metal layers M1 and M2; however, it should be understood that the interconnect structure according to various embodiments may include more than two metal layers.

[0039] In various embodiments, the MIM capacitor 105 may be located between two metal layers M1 and M2 of the interconnect structure of the IC device 100. Figure 1A In the exemplary embodiment shown, the MIM capacitor 105 may be located between the lower metal layer M1 and the overlying metal layer M2. In some embodiments, the metal layer M2 overlying the MIM capacitor 105 may be a redistribution layer. The redistribution layer may be a metal layer on an IC device (i.e., a chip) that redistributes the input-output pads of the integrated circuit, allowing electrical connections to be made at another location on the IC device 100. In this way, the redistribution layer can provide more convenient access to the input-output pads. Another example of using a redistribution layer may be to distribute (i.e., distribute) contact points around the IC device 100, allowing solder balls to be applied and the thermal stresses of the mounting to be distributed (i.e., distributed) throughout the die. In various embodiments, the metal layer M2 forming the redistribution layer may include a plurality of metal features 107, 108, and a dielectric material layer 121 located above the upper and side surfaces of the metal features 107, 108 and above the upper surface of the dielectric material layer 119. In various embodiments, dielectric material layer 121 may be composed of a different dielectric material than dielectric material layer 119. In a non-limiting embodiment, dielectric material layer 119 may include silicon oxide, and dielectric material layer 121 may include silicon nitride. Although Figure 1A The exemplary embodiments illustrate a MIM capacitor between a redistribution layer (M2) and an underlying metal layer (M1), but it should be understood that the MIM capacitor 105 according to various embodiments may be located between any metal layers of the interconnect structure of the IC device 100.

[0040] MIM capacitor 105 may include multiple vertically stacked metal layers, which may also be referred to as electrode plates. (Reference) Figure 1A The MIM capacitor 105 may include a pair of external electrode plates 125a and 125b, respectively, closest to the metal layers M1 and M2. The uppermost external electrode plate 125b may also be referred to as the top electrode plate, and the lowermost external electrode plate 125a may also be referred to as the bottom electrode plate. The MIM capacitor 105 also includes a plurality of intermediate electrode plates 127a, 127b, and 127c, which may be located between the top electrode plate 125b and the bottom electrode plate 125a. Although Figure 1AThe exemplary embodiment illustrates three intermediate electrode plates 127a, 127b, and 127c located between the top electrode plate 125b and the bottom electrode plate 125a. However, it should be understood that the MIM capacitor 105 according to various embodiments may include more or fewer than three intermediate electrode plates between the top electrode plate 125b and the bottom electrode plate 125a. In some embodiments, the MIM capacitor 105 according to various embodiments may include at least two intermediate electrode plates 127 between the top electrode plate 125b and the bottom electrode plate 125a.

[0041] Each of the electrode plates 125 (125a, 125b) and 127 (127a, 127b, 127c) of the MIM capacitor 105 can be separated from the adjacent electrode plates 125, 127 of the MIM capacitor 105 by a dielectric material layer 129. The dielectric material layer 129 between the electrode plates 125, 127 can be made of a different dielectric material than dielectric material layer 119. In some embodiments, the dielectric material layer 129 can be made of a high-k dielectric material. Examples of high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfO2-Al2O3), tantalum oxide (Ta2O5), and SiO2. x / SiN y / SiO x Or ferroelectric materials. Other suitable dielectric materials are within the scope of this disclosure.

[0042] As described above, the MIM capacitor 105 can be located between two conductive vias 101 and 103. In various embodiments, each of the electrode plates 125 and 127 of the MIM capacitor 105 can be electrically coupled to one of the adjacent conductive vias 101 and 103. Figure 1A In the exemplary embodiment shown, a first set of electrode plates, including intermediate electrode plates 127a and 127c, is electrically coupled to the conductive via 101, and a second set of electrode plates, including outer electrode plates 125a, 127b, and 125b, is electrically coupled to the conductive via 103. In various embodiments, adjacent electrode plates of the MIM capacitor 105 may be alternately coupled to the first via 101 and the second via 103, respectively.

[0043] exist Figure 1AIn the illustrated embodiment, the MIM capacitor 105 includes an odd number of intermediate electrode plates 127, such that the outer electrode plates 125a and 125b are both coupled to the same conductive via 103, and the number of intermediate plates 127a and 127c coupled to another conductive via 101 is greater than the number of intermediate plates 127b coupled to the conductive via 103 in the same way as the outer electrode plates 125a and 125b. In an alternative embodiment, the total number of intermediate plates may be even. In such an embodiment, the outer electrode plates 125a and 125b may each be coupled to different conductive vias 101 and 103, and the number of intermediate electrode plates 127 coupled to each of the conductive vias 101 and 103 may be equal.

[0044] Electrode plates 125 and 127 may be made of a suitable conductive material, which may be the same as or a different material than the conductive vias 101 and 103. Suitable conductive materials for electrode plates 125 and 127 may include, but are not limited to, copper (Cu), tungsten (W), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tantalum (Ta), titanium (Ti), alloys thereof, combinations thereof, etc. Other conductive materials are within the scope of this disclosure. Furthermore, at least some conductive electrode plates 125 and / or 127 may further include a barrier layer located on one or more outer surfaces of the conductive electrode plates 125, 127, which may be made of a suitable metal nitride and / or metal carbide material.

[0045] In various embodiments, during operation of the IC device 100, different voltages can be applied to the conductive vias 101 and 103 on opposite sides of the MIM capacitor 105. In a non-limiting example, one of the conductive vias 101 / 103 can be electrically coupled to ground, and the other conductive via 101 / 103 can be electrically coupled to a different non-zero voltage, which can be a power supply voltage. In some embodiments, one of the conductive vias 101 / 103 can be connected to a positive power supply voltage (e.g., V). DD And another conductive via 101 / 103 can be connected to ground voltage (e.g., V). SS One of the conductive vias 101 / 103 can be used to transmit a positive power supply voltage (e.g., V). DD One or more source terminals of one or more field-effect transistors (FETs) of IC device 100 are coupled to each other, and another conductive via 101 / 103 can be used to couple one or more drain terminals of one or more field-effect transistors of IC device 100 to ground voltage (e.g., V). SS ).

[0046] Figure 1BThis schematically shows the total capacitance (C) of the MIM capacitor 105. MIM The following is a vertical cross-sectional view of an exemplary structure of the MIM capacitor 105. The MIM capacitor 105 may include a central region 130 in which all electrode plates 125, 127 overlap in the vertical (z-axis) direction. The MIM capacitor 105 may have a first capacitance C1 between the outer electrode plate 125a and the intermediate electrode plate 127a, a second capacitance C2 between the intermediate electrode plates 127a and 127b, a third capacitance C3 between the intermediate electrode plates 127b and 127c, and a fourth capacitance C4 between the intermediate electrode plate 127c and the outer electrode plate 125b. The total capacitance C between the first via 101 and the second via 103 is also shown. MIM It could be the sum of these capacitors, or C MIM =C1+C2+C3+C4.

[0047] For the maximum capacitance C MIM There are several limitations, such as its use Figure 1A and Figure 1B The MIM capacitor 105 shown is implemented between the first via 101 and the second via 103. As described above, the total capacitance of the MIM capacitor 105 can be increased by increasing the area of ​​the overlapping electrode plates. However, increasing the area of ​​the overlapping electrode plates may also require increasing the lateral spacing between the conductive vias 101, 103 (i.e., along the...). Figure 1B (x-axis direction). This can have many adverse effects on the design and performance of IC device 100, such as reducing the density of IC device 100 and / or requiring a larger chip area. Furthermore, increasing via spacing may cause the circuit to experience a larger voltage drop and / or a lower operating frequency. Another technique that can be used to increase the total capacitance is to increase the total number of electrode plates in the vertical stack. However, adding additional electrode plates requires additional processing steps, which may increase manufacturing time and cost. Furthermore, the available space along the vertical (z-axis) direction is limited by the thickness T of the dielectric layer 119. height Due to limitations, the number of electrode plates that can be stacked between conductive vias 101 and 103 is limited.

[0048] According to various embodiments of this disclosure, the MIM capacitor 105 with increased capacitance may include an intermediate electrode plate 127 having a thickness greater than that of the outer electrode plate 125. By allocating a larger share of the total plate thickness of the MIM capacitor 105 to the intermediate electrode plate 127, the total capacitance C of the MIM capacitor 105 can be increased without increasing the overall size of the MIM capacitor 105. MIM Increasing the thickness of the intermediate electrode plate 127 reduces the resistance in the intermediate electrode plate and increases the total capacitance C of the MIM capacitor 105.MIM This is in Figure 1C The diagram illustrates that, Figure 1C yes Figure 1A and Figure 1B An enlarged cross-sectional view of the central region 130 of the MIM capacitor 105 shown. Figure 1C As illustrated schematically, as the resistance of the intermediate electrode plate 127 decreases, the current increases, thereby increasing the charge accumulation on each plate. This increase in charge accumulation on the intermediate electrode plate 127 occurs on both sides of the plate, each side being adjacent to the other electrode plate of the MIM capacitor 105. This increased charge accumulation can increase the capacitance on both sides of the intermediate electrode plate 127. In contrast, each outer electrode plate 125 is adjacent to only one other electrode plate. Therefore, an increase in charge accumulation on the outer electrode plate 125 may only increase the capacitance on one side of the outer electrode plate 125. Therefore, by providing the intermediate electrode plate 127 with the maximum plate thickness, the total capacitance C of the MIM capacitor 105 can be increased. MIM .

[0049] In various embodiments, the thickness (T) of each intermediate electrode plate 127a, 127b, 127c is... int.plate The thickness (T) can be greater than the thickness of the external electrode plates 125a and 125b of the MIM capacitor 105. out.plate In the embodiment, the thickness (T) of the intermediate electrode plates 127a, 127b, and 127c int.plate The thickness can be at least 50 nm, for example, between 50 nm and 100 nm, and the thickness (T) of the external electrode plates 125a and 125b is... out.plate The thickness (T) of the dielectric material layer 129 can be less than 50 nm, for example, between 10 nm and 45 nm. insulator The thickness of the conductive vias 125a, 125b, 127a, 127b, and 127c can be less than that of the electrode plates 125a, 125b, 127a, 127b, and 127c. In various embodiments, the width 102 of the conductive vias 101 and 103 can be in the range of about 1 μm to about 10 μm, but thicker or thinner conductive vias can be used.

[0050] Refer again Figure 1A Each of the intermediate electrode plates 127a, 127b, and 127c may include a first horizontal extension 131 that contacts the conductive vias 101 and 103 and extends to the central region 130 of the MIM capacitor 105 (see [link]). Figure 1B The second horizontal extension 133 and the vertical extension 132 extending between the first horizontal extension 131 and the second horizontal extension 133. The upper surface of the second horizontal extension 133 may be higher than the upper surface of the first horizontal extension 131. In an embodiment, at least one of the external electrode plates (e.g., as shown in the figure) Figure 1AThe bottom electrode plate 125a shown can extend continuously in the horizontal direction between the conductive vias 101, 103 and the central region 130 of the MIM capacitor 105. In some embodiments, at least one of the outer electrode plates (e.g., as shown) Figure 1A The top electrode plate 125b shown may include a first horizontal extension contacting the conductive vias 101, 103, a second horizontal extension extending into the central region 130 of the MIM capacitor 105, and a vertical extension extending between the first and second horizontal extensions. A gap 134 may exist between the peripheral edge of each electrode plate 125a, 125b, 127a, 127b, 127c and the conductive vias 101, 103 to which the respective electrode plates 125a, 125b, 127a, 127b, 127c are not electrically coupled.

[0051] Figure 2 This is a graph showing the normalized capacitance of a MIM capacitor as a function of the thickness of the intermediate electrode plate at a package resonant frequency of 200MHz. (Example:) Figure 2 As shown, increasing the thickness of the intermediate electrode plate can increase the capacitance by about 20%. Figure 3 This is a graph showing the effective capacitance as a function of the package resonant frequency for three MIM capacitors with different intermediate electrode plate thicknesses. (Reference) Figure 3 At a package resonant frequency of 200MHz, the highest effective capacitance is the MIM capacitor with the thickest intermediate electrode plate (curve 301), followed by the MIM capacitor with a medium-thickness intermediate electrode plate (curve 303), and the MIM capacitor with the thinnest intermediate electrode plate (curve 305).

[0052] Figure 4 This is a horizontal cross-sectional view of an exemplary structure of an integrated circuit (IC) device 100, including a MIM capacitor 105 and a plurality of conductive vias 101 and 103. Reference Figure 4 ,For example Figures 1A-1CThe MIM capacitor 105 shown is illustrated in a horizontal cross-sectional view (i.e., in the xy plane). The MIM capacitor 105 extends among a plurality of conductive vias, including a central conductive via 101 and four peripheral conductive vias 103a, 103b, 103c, and 103d surrounding the central conductive via 101. The central via 101 can be connected to a first voltage, and the peripheral conductive vias 103a, 103b, 103c, and 103d can be connected to a second voltage different from the first voltage. The MIM capacitor 105 can be a single-cell capacitor comprising a first plurality of electrode plates conductively coupled to the central conductive via 101 and a second plurality of electrode plates conductively coupled to the peripheral conductive vias 103a, 103b, 103c, and 103d. In some embodiments, the central conductive via 101 can be connected to a positive power supply voltage (e.g., V). DD Furthermore, the peripheral conductive vias 103a, 103b, 103c, and 103d can be connected to ground voltage (e.g., V). SS ). Figure 4 The width 401 of the via opening and the width 403 of the vias 101 and 103 are also shown in a horizontal (xy) plane. Figure 4 Additionally, a gap 134 is shown between the outer edge of the electrode plate and one or more conductive vias 101, 103a, 103b, 103c to which the corresponding electrode plate is non-conductively coupled. Figure 4 In the illustrated embodiment, the via-to-via spacing 405 between the central conductive via 101 connected to the first voltage and the peripheral conductive vias 103a, 103b, 103c, 103d connected to the second voltage is uniform.

[0053] Figure 5 This is a horizontal cross-sectional view illustrating an exemplary structure of an array arrangement of conductive vias 101, 103 according to an embodiment of the present disclosure. Reference Figure 5 Vias 101 and 103 can be arranged in a rectangular array pattern. Alternating rows of vias 101 and 103 can be connected to different voltages. For example... Figure 5 As shown, for example, vias 101-1 to 101-8 can be connected to a first voltage, and vias 103-1 to 103-8 can be connected to a second voltage different from the first voltage. In some embodiments, vias 101-1 to 101-8 can be connected to a positive power supply voltage (e.g., V). DD And vias 103-1 to 103-8 can be connected to ground voltage (e.g., V). SS Multiple MIM capacitors ( Figure 5 (Not shown) can be located between adjacent vias 101 and 103 connected to different voltages. Figure 5In the via array, the via-to-via spacing between adjacent vias 101 and 103 connected to different voltages is non-uniform. Specifically, adjacent vias spaced apart along the y-axis (e.g., vias 101-2 and 103-2) have a first via-to-via spacing D1, while adjacent vias spaced apart diagonally (e.g., vias 101-2 and 103-1) have a second via-to-via spacing D2 greater than D1.

[0054] Figure 6 This is a horizontal cross-sectional view illustrating an exemplary structure of another arrangement of the array of conductive vias 101, 103 according to an embodiment of the present disclosure. Reference Figure 6 Vias 101 and 103 can be arranged in a rectangular array pattern. Figure 6 The layout and Figure 5 The arrangement shown differs in that the alternating vias 101, 103 in both the x-axis and y-axis directions can be connected to different voltages. In some embodiments, vias 101-1 to 101-8 can be connected to a positive power supply voltage (e.g., V). DD And vias 103-1 to 103-8 can be connected to ground voltage (e.g., V). SS Multiple MIM capacitors ( Figure 6 (Not shown) can be located between adjacent vias 101 and 103 connected to different voltages. By alternating vias 101 and 103 in the x and y directions, the via-to-via spacing D1 between adjacent vias connected to different voltages can be uniform.

[0055] Figure 7 This is a horizontal cross-sectional view illustrating an exemplary structure of yet another arrangement of the array of conductive vias 101, 103 according to an embodiment of the present disclosure. Reference Figure 7 Vias 101, 103 can be arranged in a rectangular array pattern, including alternating rows of vias 101, 103 connected to different voltages. Vias 101, 103 in each row can be offset from vias 101, 103 in adjacent rows(s). Specifically, vias 101 connected to a first voltage can be offset in the x-axis direction such that they are located between vias 103 connected to a second voltage. In some embodiments, vias 101-1 to 101-16 can be connected to a positive power supply voltage (e.g., V). DD And vias 103-1 to 103-9 can be connected to ground voltage (e.g., V). SS Multiple MIM capacitors ( Figure 7(Not shown) can be located between adjacent vias 101, 103 connected to different voltages. By providing alternating rows of vias 101, 103 connected to different voltages and offsetting the vias in each row from those in adjacent rows, the via-to-via spacing D3 between adjacent vias connected to different voltages can be uniform. Furthermore, Figure 7 The via-to-via spacing D3 in the arrangement can be less than Figure 5 and Figure 6 In the embodiments, the via-to-via spacings D1 and D2 are provided, and a greater number of vias 101, 103 can be provided in the same area of ​​the IC device 100.

[0056] Figure 8 This is a horizontal cross-sectional view illustrating an exemplary structure of yet another arrangement of the array of conductive vias 101, 103 according to an embodiment of the present disclosure. Reference Figure 8 Vias 101 and 103 can be arranged in a rectangular array pattern, wherein vias 101 and 103 in each row are offset from vias 101 and 103 in adjacent rows(s). Furthermore, alternating vias 101 and 103 within each row can be connected to different voltages. In some embodiments, vias 101-1 to 101-13 can be connected to a positive power supply voltage (e.g., V). DD And vias 103-1 to 103-12 can be connected to ground voltage (e.g., V). SS Multiple MIM capacitors ( Figure 8 (Not shown) can be located between adjacent vias 101, 103 connected to different voltages. In this arrangement, there may be two different via-to-via spacings D1 and D3 between vias connected to different voltages. Specifically, adjacent vias spaced along the x-axis or y-axis (e.g., vias 103-1 and 101-2) have a first via-to-via spacing D1, while adjacent vias spaced diagonally (e.g., vias 103-1 and 101-3) have a second via-to-via spacing D3 that is smaller than D1.

[0057] Figure 9A and Figure 9B yes Figure 8 An exemplary structure is shown in a vertical cross-sectional view along line A-A', illustrating different configurations of the MIM capacitor 105 between conductive vias 101-10, 103-10, and 101-11. (Reference) Figure 9AThe MIM capacitor 105a between conductive vias 101-10 and 103-10 can have the same configuration as the MIM capacitor 105b between conductive vias 103-10 and 101-11. Specifically, in the MIM capacitor 105a, intermediate electrode plates 127a and 127c can extend from conductive vias 101-10 to the central region 130 of the MIM capacitor 105a, while outer electrode plates 125a and 125b and intermediate electrode plate 127b can extend from adjacent conductive vias 103-10 to the central region 130 of the MIM capacitor 105a. MIM capacitor 105b may have a similar configuration, wherein intermediate electrode plates 127a and 127c may extend from conductive vias 103-10 to the central region 130 of MIM capacitor 105b, while outer electrode plates 125a and 125b and intermediate electrode plate 127b may extend from adjacent conductive vias 101-11 to the central region 130 of MIM capacitor 105a.

[0058] Figure 9B An alternative embodiment in which MIM capacitors 105a and 105b have a symmetrical configuration is shown. Specifically, Figure 9B The MIM capacitor 105a located between conductive vias 101-10 and 103-10 includes intermediate electrode plates 127a and 127c extending from the conductive vias 101-10 to a central region 130 of the MIM capacitor 105a, and outer electrode plates 125a and 125b and intermediate electrode plate 127b extending from adjacent conductive vias 103-10 to the central region 130 of the MIM capacitor 105a. The MIM capacitor 105b located between conductive vias 103-10 and 101-11 may have a symmetrical configuration relative to the MIM capacitor 105a, wherein the outer electrode plates 125a and 125b and the intermediate electrode plate 127b extend from the conductive vias 103-10 to the central region 130 of the MIM capacitor 105b, and the intermediate electrode plates 127a and 127c extend from the conductive vias 101-11 to the central region 130 of the MIM capacitor 105b. Typically, in a configuration having identical (i.e., asymmetrical) MIM capacitors 105a, one or more electrode plates electrically contacting the conductive vias 101 and 103 on the first side of the conductive vias 101 and 103 may be different from one or more electrode plates electrically contacting the conductive vias 101 and 103 on the second side of the conductive vias 101 and 103 opposite to the first side. In a symmetrical configuration, one or more identical electrode plates may be electrically contacting both the first and second sides of the conductive vias 101 and 103. In various embodiments, Figures 4-8The MIM capacitors 105 in any of the via layouts shown can have the same configuration, a symmetrical configuration, or a combination of the same and symmetrical configurations.

[0059] like Figures 4-8 As schematically illustrated, different via layouts can provide different via-to-via distances (e.g., D1, D2, and D3) between conductive vias 101 and 103 connected to different voltages. For a MIM capacitor 105 located between vias 101 and 103, the via-to-via distance can affect the capacitor's performance. A shorter via-to-via distance can reduce the effective capacitor area of ​​the MIM capacitor 105. However, this may be partially offset by a reduction in the total capacitor resistance due to the shorter via-to-via distance. In various embodiments, when using a MIM capacitor structure throughout the chip design, there may be an optimal via-to-via distance to achieve maximum capacitance. In some embodiments, the via-to-via distance can be between about 2 μm and about 15 μm, for example, between about 5 μm and about 10 μm.

[0060] The effect of via-to-via distance on the performance of MIM capacitors can also be a function of the resonant frequency of the package in which IC device 100 (i.e., die) is integrated. Figure 10 This is a graph showing the admittance of a MIM capacitor 105 as a function of via-to-via distance for an IC device package with resonant frequencies of 40MHz (curve 1001) and 200MHz (curve 1003). Figure 10 As shown, the maximum effective capacitance of the MIM capacitor in the package with a higher resonant frequency (curve 1003) is at a lower via-to-via distance (e.g., about 5 μm) than the maximum effective capacitance of the MIM capacitor in the package with a lower resonant frequency (curve 1001), which is at a via-to-via distance of about 8 μm.

[0061] Figure 11A This is a flowchart illustrating a method 1100 for designing a MIM capacitor 105 coupled between a first via 101 and a second via 103 in an IC device 100 according to embodiments of the present disclosure. In various embodiments, Figure 11A Methods such as Figure 11B The block diagram schematically illustrates a processing device such as a processing device 200 (e.g., a computer) for implementation. Reference Figure 11BThe processing device 200 according to various embodiments may include an input device 202 (e.g., a keyboard, mouse, touchscreen device, etc.) and an output device 204 (e.g., a display device, printer, etc.) coupled to the processing unit 206 (e.g., a central processing unit). The processing unit 206 may include a control unit 208 and an arithmetic and logic unit (ALU) 210, and may be coupled to a memory device 212 (e.g., random access memory (RAM)) configured with processor-executable instructions for performing the operations of method 1100. Reference Figure 11A Method 1100 may begin at block 201. In determining block 203, it may be determined whether the package resonant frequency of IC device 100 is greater than a threshold resonant frequency. In various embodiments, the threshold resonant frequency may be between approximately 50 MHz and approximately 100 MHz. In a non-limiting example, the threshold resonant frequency may be approximately 50 MHz.

[0062] Refer again Figure 11A In response to determining that the package resonant frequency is not greater than a threshold frequency (i.e., determining block 203 = "No"), method 1100 may proceed to block 205. In block 205, method 1100 may include determining the capacitance (C) of the MIM capacitor based on the total plate count i of the MIM capacitor. MIM ), where i≥2. In various embodiments, the plate count can be a default plate count. In some embodiments, the default plate count can be equal to two. In various embodiments, the capacitance (C) of the MIM capacitor can also be determined based on the default via-to-via distance between the first via 101 and the second via 103. MIM In various embodiments, the default via-to-via distance can be greater than 5 μm, for example, between about 7 μm and about 30 μm. In a non-limiting example, the default via-to-via distance can be about 10 μm. In some embodiments, the default via-to-via distance can be determined in part based on the allowable design area of ​​the MIM capacitor. In embodiments, the capacitance (C) of the MIM capacitor can be determined by simulation. MIM ).

[0063] Refer again Figure 11A In determining block 207, the capacitance (C) of the MIM capacitor can be determined. MIM Whether the predetermined performance criteria are met. In some embodiments, the performance criteria may be related to the operating speed of the IC device 100. In response to determining the capacitance (C) of the MIM capacitor... MIM If the predetermined performance criteria are met (i.e., block 207 is determined to be "yes"), then method 1100 can proceed to block 221, where the final design of the MIM capacitor 105 can be determined based on the default plate count and via-to-via distance. In response to determining the capacitance (C) of the MIM capacitor...MIM If the predetermined performance criteria are not met (i.e., determination block 207 = "No"), then method 1100 can proceed to block 209. In block 209, the number of plates i in the MIM capacitor design can be increased by 1, and then method 1100 can return to block 205. In block 205, the capacitance of the MIM capacitor can be determined based on the increased plate count i and the default via-to-via distance, and in determination block 207, the capacitance (C) of the MIM capacitor with the increased plate count can be determined. MIM Whether a predetermined performance standard is met. In various embodiments, method 1100 may include repeatedly incrementing the plate count i of the MIM capacitor by one plate in block 209, determining the capacitance of the MIM capacitor in block 205, and determining whether a performance standard is met in determination block 207, until it is determined that the design of the MIM capacitor meets the performance standard (i.e., determination block 207 = "yes"). Method 1100 may then proceed to block 221 and the final design of the MIM capacitor 105 may be determined based on the iterative plate count and the default via-to-via distance.

[0064] Referring again to determination block 203 of method 1100, in response to determining that the package resonant frequency is greater than a threshold frequency (i.e., determination block 203 = "Yes"), method 1100 can proceed to block 211. In block 211, method 1100 may include determining the capacitance (C) of the MIM capacitor based on the plate count i (where i ≥ 2) and the via-to-via distance d. MIM In various embodiments, the plate count can be a default plate count. In some embodiments, the default plate count can be equal to two. In various embodiments, the via-to-via distance d can be a default via-to-via distance. In various embodiments, the default via-to-via distance can be greater than 5 μm, for example, between about 7 μm and about 30 μm, but larger and smaller default via-to-via distances are within the scope of this disclosure. In a non-limiting example, the default via-to-via distance can be about 10 μm. In some embodiments, the default via-to-via distance can be determined in part based on the allowable design area of ​​the MIM capacitor. In embodiments, the capacitance (C) of the MIM capacitor can be determined by simulation. MIM ).

[0065] Refer again Figure 11A In determining block 213, the capacitance (C) of the MIM capacitor can be determined. MIM Whether the predetermined performance criteria are met. In some embodiments, the performance criteria may be related to the operating speed of the IC device 100. In response to determining the capacitance (C) of the MIM capacitor... MIMIf the predetermined performance criteria are met (i.e., block 213 = "Yes"), then method 1100 can proceed to block 221, and in block 221, the final design of the MIM capacitor 105 can be determined based on the default plate count and the default via-to-via distance. In response to determining the capacitance (C) of the MIM capacitor... MIM If the predetermined performance criteria are not met (i.e., determination block 213 = "No"), then method 1100 can proceed to determination block 215.

[0066] In determining block 215, it can be determined whether the via-to-via distance d is less than a threshold distance. In various embodiments, the threshold distance can be less than 10 μm, for example, between about 3 μm and about 9 μm. In a non-limiting example, the threshold via-to-via distance d can be about 5 μm. This is in response to determining the capacitance (C) of the MIM capacitor. MIM If the predetermined performance criterion is not met (i.e., determination block 215 = "No"), then method 1100 can proceed to block 217. In block 217, the via-to-via distance d can be reduced by a predetermined amount (e.g., between 0.1 μm and 3 μm, for example, reduced by 1 μm), and method 1100 can then return to block 211. In block 211, the capacitance of the MIM capacitor can be determined based on the reduced via-to-via distance, and in determination block 213, the capacitance (C) of the MIM capacitor with the reduced via-to-via distance d can be determined. MIM Does it meet the predetermined performance standards? This is in response to determining the capacitance (C) of the MIM capacitor. MIM If the predetermined performance criteria are met (i.e., block 213 is determined to be "yes"), then method 1100 can proceed to block 221, where the final design of the MIM capacitor 105 can be determined based on the default plate count and the reduced via-to-via distance. In response to determining the capacitance (C) of the MIM capacitor... MIM If the predetermined performance criteria are not met (i.e., determination block 213 = "No"), then method 1100 can proceed to determination block 215 to determine whether the reduced via-to-via distance is less than a threshold distance.

[0067] In various embodiments, method 1100 may include repeatedly reducing the via-to-via distance d in block 215 in response to determining that the via-to-via distance d is not less than a threshold distance (i.e., determining block 215 = "No"), determining the capacitance of the MIM capacitor having the reduced via-to-via distance d in block 211, and determining whether a performance criterion is met in determining block 213 until it is determined that the design of the MIM capacitor meets the performance criterion (i.e., determining block 213 = "Yes") or it is determined that the via-to-via distance d is less than a threshold distance (i.e., determining block 215 = "Yes").

[0068] In response to determining that the via-to-via distance d is less than a threshold distance (i.e., determining block 215 = "Yes"), method 1100 can then proceed to block 219. In block 219, the number of plates i in the MIM capacitor design can be increased by 1, and then method 1100 can return to block 211. In block 211, the capacitance of the MIM capacitor can be determined based on the increased plate count i and the via-to-via distance, and in determining block 213, the capacitance (C) of the MIM capacitor with the increased plate count and via-to-via distance can be determined. MIM Whether a predetermined performance standard is met. In various embodiments, method 1100 may include repeatedly incrementing the plate count i of the MIM capacitor by one plate in block 219, determining the capacitance of the MIM capacitor in block 211, and determining whether a performance standard is met in determination block 213, until it is determined that the design of the MIM capacitor meets the performance standard (i.e., determination block 213 = "yes"). Then, method 1100 may proceed to block 221 and may determine the final design of the MIM capacitor 105 based on the iterative plate count and via-to-via distances less than a threshold distance.

[0069] Figure 12 This is a graph showing the admittance of a MIM capacitor 105 as a function of via-to-via distance for an IC device package with a resonant frequency of 200MHz. Curves 1201, 1202, 1203, 1204, 1205, and 1206 show the admittance of the MIM capacitor 105 with an intermediate electrode plate 127 having increased thickness and decreased resistance. Figure 12 As shown, the thicker intermediate plate 127 provides lower resistance and increased admittance. As mentioned above, the lower resistance in the MIM capacitor can increase the effective capacitance.

[0070] In some embodiments, the capacitance characteristics of the MIM capacitor 105 can also vary as a function of the size of the plate opening (i.e., the size of the through-hole opening through the capacitor electrode plates). Figure 13 This is a graph showing the admittance of a MIM capacitor 105 as a function of via-to-via distance for an IC device package with a resonant frequency of 200MHz. Each curve shows the admittance of a MIM capacitor with different sized plate openings. Curve 1301 shows a MIM capacitor with the largest plate opening (TPC_O = 5.6μm plate opening width), while curve 1310 shows a MIM capacitor with the smallest plate opening (TPC_O = 3.8μm plate opening width). Figure 13 As shown, a smaller plate opening can increase the admittance of the MIM capacitor 105.

[0071] Figure 14This illustrates the minimum V of an IC device 100 with a MIM capacitor 105 according to an embodiment of the present disclosure as a function of via-to-via distance. dd The curve graph. Figure 14 This verifies that the high capacitance density of the MIM capacitor 105 can reduce the level of chip voltage drop. Figure 14 In the curve graph, 1 volt V dd Transistors of IC device 100 with different MIM capacitor configurations were applied, and the voltage drop for each MIM design was measured at different via-to-via distances. Curve 1401 shows the voltage drop of IC device 100 without MIM capacitors, curve 1402 shows the voltage drop of a 2-plate MIM capacitor, curve 1403 shows the voltage drop of a 3-plate MIM capacitor, curve 1404 shows the voltage drop of a 4-plate MIM capacitor, and curve 1405 shows the voltage drop of a 5-plate MIM capacitor. Figure 14 As shown, the 5-plate MIM capacitor achieved the lowest voltage drop.

[0072] Figure 15 This is a graph showing the gain percentage of the operating speed of the IC device 100 as a function of via-to-via distance for different MIM capacitor configurations. Curve 1501 shows the speed gain percentage of the IC device 100 with a 2-plate MIM capacitor, curve 1502 shows the speed gain percentage of the IC device 100 with a 3-plate MIM capacitor, curve 1503 shows the speed gain percentage of the IC device 100 with a 4-plate MIM capacitor, and curve 1504 shows the speed gain percentage of the IC device 100 with a 5-plate MIM capacitor. Figure 15 As shown, the 5-plate MIM capacitor according to various embodiments of this disclosure can provide an approximately 10% performance improvement for the IC device 100. This improvement in operating speed may be partly due to the smaller voltage drop of the 5-plate MIM capacitor (i.e., a higher minimum voltage drop). dd ). Figure 15 It was also shown that a via-to-via distance of approximately 5 μm can achieve the greatest device performance improvement.

[0073] Figure 16 This is a graph showing the minimum loop frequency of IC device 100 as a function of via-to-via distance for different MIM capacitor configurations. The minimum loop frequency can represent the operating frequency of IC device 100. Curve 1601 shows the minimum loop frequency of a 5-plate MIM capacitor 105 with a thick intermediate plate, curve 1602 shows the minimum loop frequency of a 4-plate MIM capacitor 105 with a thick intermediate plate, and curve 1603 shows the minimum loop frequency of a 4-plate MIM capacitor 105 with a thinner intermediate plate than the capacitor shown in curve 1602. Figure 16 As shown, lower electrode plate resistance and higher plate count can provide a faster design frequency.

[0074] Figures 17A-17Q This is a sequential vertical cross-sectional view illustrating exemplary structures during the formation of the MIM capacitor 105 according to various embodiments of the present disclosure. Reference Figure 17A The first dielectric material layer 120, the second dielectric material layer 119a, and the first metal layer 501 can be conformally deposited on the metal layer M1 of the interconnect structure of the IC device 100. The first dielectric material layer 120 and the second dielectric material layer 119a can be composed of suitable dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN, Si3N4), silicon carbide (SiC), undoped silicate glass (USG), doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Other dielectric materials are within the scope of this disclosure. In one embodiment, dielectric material layer 119a may comprise silicon oxide, and dielectric material layer 120 may comprise silicon nitride. In some embodiments, dielectric material layer 119a may comprise silicon oxide deposited via plasma-enhanced CVD (PE-CVD) using a suitable precursor (e.g., TEOS).

[0075] The first metal layer 501 may include suitable conductive materials, such as copper (Cu), tungsten (W), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tantalum (Ta), titanium (Ti), alloys thereof, combinations thereof, etc. Other conductive materials are within the scope of this disclosure.

[0076] Any suitable deposition process can be used to deposit the first dielectric layer 120, the second dielectric layer 119a, and the first metal layer 501. In this document, "suitable deposition process" can include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), low-pressure CVD, metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, etc.

[0077] Refer again Figure 17A A patterned mask 502 can be formed on the upper surface of the first metal layer 501. The patterned mask 502 can be photolithographically patterned to form at least one opening through the mask 502, which exposes the upper surface of the first metal layer 501.

[0078] Figure 17BThis is a vertical cross-sectional view showing an exemplary structure of the bottom electrode plate 125a of a MIM capacitor above the second dielectric layer 119a. (Refer to...) Figure 17B An anisotropic etching process can be performed using a patterned mask 502 to remove portions of the first metal layer 501 and form the bottom electrode plate 125a of the MIM capacitor. After the etching process, the patterned mask 502 can be removed using a suitable process, such as by ashing or solvent dissolution.

[0079] Figure 17C This is a vertical cross-sectional view of an exemplary structure, showing a dielectric material layer 503 above the upper surface of the second dielectric layer 119a and above the side and upper surfaces of the bottom electrode plate 125a, and a second metal layer 504 above the upper surface of the dielectric material layer 503. (See reference...) Figure 17C A dielectric material layer 503 can be conformally deposited on the upper surface of the second dielectric layer 119a, the side surface of the bottom electrode plate 125a, and the upper surface of the bottom electrode plate 125a using a suitable deposition process as described above. In embodiments, the dielectric material layer 503 may be composed of a different dielectric material than the second dielectric material layer 119a. In some embodiments, the dielectric material layer 503 may be composed of a high-k dielectric material. Examples of high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium dioxide-alumina (HfO2-Al2O3), tantalum oxide (Ta2O5), and SiO2. x / SiN y / SiO x Or ferroelectric materials. Other suitable dielectric materials are within the scope of this disclosure.

[0080] Refer again Figure 17C A second metal layer 504 can be conformally deposited on the dielectric material layer 503 using a suitable deposition process as described above. The second metal layer 504 may include a suitable conductive material and may be composed of the same or different materials as the bottom electrode plate 125a. The thickness of the second metal layer 504 may be greater than the thickness of the bottom electrode plate 125a.

[0081] Figure 17D This is a vertical cross-sectional view of an exemplary structure, showing a patterned mask 505 above the upper surface of the second metal layer 504. The patterned mask 505 may be photolithographically patterned to form at least one opening through the mask 505, which exposes the upper surface of the second metal layer 504.

[0082] Figure 17E This is a vertical cross-sectional view of an exemplary structure, showing the first intermediate electrode plate 127a of the MIM capacitor above the dielectric layer 503. (Reference) Figure 17E An anisotropic etching process can be performed using a patterned mask 505 to remove portions of the second metal layer 504 and form the first intermediate electrode plate 127a of the MIM capacitor. The first intermediate electrode plate 127a can be separated from the bottom electrode plate 125a by a dielectric layer 503, and the thickness of the first intermediate electrode plate 127a can be greater than the thickness of the bottom electrode plate 125a. After the etching process, the patterned mask 505 can be removed using a suitable process, such as by ashing or solvent dissolution.

[0083] Figure 17F This is a vertical cross-sectional view of an exemplary structure, showing a dielectric material layer 506 and a third metal layer 507 formed on a first intermediate electrode plate 127a and a bottom electrode plate 125a, and a patterned mask 508 formed on the third metal layer 507. (See reference...) Figure 17F The dielectric material layer 506 can be conformally deposited on the upper and side surfaces of the first intermediate electrode plate 127a and on the exposed upper surface of the dielectric material layer 503 using a suitable deposition process as described above. In an embodiment, the dielectric material layer 506 may be composed of a suitable dielectric material, such as the high-k dielectric material as described above.

[0084] Refer again Figure 17F A third metal layer 507 can be conformally deposited on the dielectric material layer 506 using a suitable deposition process as described above. The third metal layer 507 may include a suitable conductive material and may be composed of the same or different materials as the bottom electrode plate 125a and / or the first intermediate electrode plate 127a. The thickness of the third metal layer 507 may be greater than the thickness of the bottom electrode plate 125a. A patterned mask 508 may be formed on the third metal layer 507 and may be photolithographically patterned to form at least one opening through the mask 508, which exposes the upper surface of the third metal layer 507.

[0085] Figure 17G This is a vertical cross-sectional view of an exemplary structure, showing the second intermediate electrode plate 127b of the MIM capacitor above the dielectric layer 506. Reference Figure 17GAn anisotropic etching process can be performed using a patterned mask 508 to remove portions of the third metal layer 507 and form the second intermediate electrode plate 127b of the MIM capacitor. The second intermediate electrode plate 127b can be separated from the first intermediate electrode plate 127a by a dielectric material layer 506, and from the bottom electrode plate 125a by dielectric material layers 503 and 506. The thickness of the second intermediate electrode plate 127b can be greater than the thickness of the bottom electrode plate 125a. After the etching process, the patterned mask 508 can be removed using a suitable process, such as ashing or solvent dissolution.

[0086] Figure 17H This is a vertical cross-sectional view of an exemplary structure, showing a dielectric material layer 509 formed over the second intermediate electrode plate 127b and the first intermediate electrode plate 127a. (Reference) Figure 17H The dielectric material layer 509 can be conformally deposited on the exposed surface of the dielectric material layer 506 on the first intermediate electrode plate 127a and on the side and top surfaces of the second intermediate electrode plate 127b using a suitable deposition process as described above. In an embodiment, the dielectric material layer 509 can be made of a suitable dielectric material, such as the high-k dielectric material as described above.

[0087] Figure 17I This is a vertical cross-sectional view of an exemplary structure, showing a fourth metal layer 510 over the dielectric material layer 509. The fourth metal layer 510 can be conformally deposited over the dielectric material layer 509 using a suitable deposition process as described above. The fourth metal layer 510 may include a suitable conductive material and may be composed of the same or different materials as the bottom electrode plate 125a, the first intermediate electrode plate 127a, and / or the second intermediate electrode plate 127b.

[0088] Figure 17J This is a vertical cross-sectional view of an exemplary structure after a planarization process for removing portions of the fourth metal layer 510 from the upper surface of the dielectric material layer 509. (See reference) Figure 17J Planarization processes such as chemical mechanical planarization (CMP) can be used to remove some portions of the fourth metal layer 510 and expose the upper surface of the dielectric material layer 509.

[0089] Figure 17K This is a vertical cross-sectional view of an exemplary structure, showing a dielectric material layer 511 and a fifth metal layer 512 formed over a fourth metal layer 510 and a dielectric material layer 509, and a patterned mask 513 formed over the fifth metal layer 512. (See reference...) Figure 17KA dielectric material layer 511 can be conformally deposited over the exposed surfaces of the fourth metal layer 510 and the dielectric material layer 509 using a suitable deposition process as described above. In an embodiment, the dielectric material layer 511 may be composed of a suitable dielectric material, such as the high-k dielectric material described above. A fifth metal layer 512 can be conformally deposited over the dielectric material layer 511 using a suitable deposition process as described above. The fifth metal layer 512 may include a suitable conductive material and may be composed of the same or different (one or more) materials as the bottom electrode plate 125a, the first intermediate electrode plate 127a, and / or the second intermediate electrode plate 127b. The thickness of the fifth metal layer 512 may be greater than the thickness of the bottom electrode plate 125a. A patterned mask 513 may be formed over the fifth metal layer 512 and may be photolithographically patterned to form at least one opening through the mask 513 that exposes the upper surface of the fifth metal layer 512.

[0090] Figure 17L This is a vertical cross-sectional view of an exemplary structure, showing the third intermediate electrode plate 127c of the MIM capacitor above the dielectric layer 511. Reference Figure 17L An anisotropic etching process can be performed using a patterned mask 513 to remove portions of the fifth metal layer 512 and form the third intermediate electrode plate 127c of the MIM capacitor. The third intermediate electrode plate 127c can be separated from the second intermediate electrode plate 127b by dielectric material layers 509 and 511. The thickness of the third intermediate electrode plate 127c can be greater than the thickness of the bottom electrode plate 125a. After the etching process, the patterned mask 513 can be removed using a suitable process, such as by ashing or solvent dissolution.

[0091] Figure 17M This is a vertical cross-sectional view of an exemplary structure, showing a dielectric material layer 514 and a sixth metal layer 515 formed on the third intermediate electrode plate 127c, and a patterned mask 516 formed on the sixth metal layer 515. (See reference...) Figure 17M The dielectric material layer 514 can be conformally deposited on the upper and side surfaces of the third intermediate electrode plate 127c and on the exposed upper surface of the dielectric material layer 511 using a suitable deposition process as described above. In an embodiment, the dielectric material layer 514 may be composed of a suitable dielectric material, such as the high-k dielectric material as described above.

[0092] Refer again Figure 17MA sixth metal layer 515 can be conformally deposited on the dielectric material layer 514 using a suitable deposition process as described above. The sixth metal layer 515 may include a suitable conductive material and may be composed of the same or different materials as the bottom electrode plate 125a, the first intermediate electrode plate 127a, the second intermediate electrode plate 127b, and / or the third intermediate electrode plate 127c. The thickness of the sixth metal layer 515 may be less than the thickness of the first intermediate electrode plate 127a, the second intermediate electrode plate 127b, and the third intermediate electrode plate 127c. A patterned mask 516 may be formed on the sixth metal layer 515 and may be photolithographically patterned to form at least one opening through the mask 516, which exposes the upper surface of the third metal layer 515.

[0093] Figure 17N This is a vertical cross-sectional view of an exemplary structure, showing the top electrode plate 125b of the MIM capacitor above the dielectric layer 514. (Reference) Figure 17N An anisotropic etching process can be performed using a patterned mask 516 to remove portions of the sixth metal layer 515 and form the top electrode plate 125b of the MIM capacitor. The top electrode plate 125b can be separated from the third intermediate electrode plate 127c by a dielectric material layer 514. The thickness of the top electrode plate 125b can be less than the thicknesses of the first intermediate electrode plate 127a, the second intermediate electrode plate 127b, and the third intermediate electrode plate 127c. After the etching process, the patterned mask 516 can be removed using a suitable process, such as by ashing or solvent dissolution.

[0094] Figure 17O This is a vertical cross-sectional view of an exemplary structure, showing a dielectric layer 119b above the top electrode plate 125b and a patterned mask 517 above the dielectric layer 119b. (See reference...) Figure 17O The dielectric layer 119b may be deposited over the exposed upper surfaces of the sixth metal layer 515, the dielectric material layer 514, and the top electrode plate 125b. The dielectric layer 119b may optionally undergo a planarization process to provide a planarized upper surface. The dielectric layer 119b may be deposited using a suitable deposition process as described above. In embodiments, the dielectric layer 119b may be composed of the same material as the dielectric layer 119a. In some embodiments, the dielectric layer 119b may comprise silicon oxide. Other suitable dielectric materials are within the scope of this disclosure.

[0095] Refer again Figure 17OA patterned mask 517 can be formed on the dielectric layer 119b and can be photolithographically patterned to form at least one opening through the mask 517, which exposes the upper surface of the dielectric material layer 119b.

[0096] Figure 17P This is a vertical cross-sectional view of an exemplary structure, showing via openings 518 formed through the dielectric material layers 119b, 119a, 120 and the electrode plates 125b, 127c, 127b, 127a, 125a of the MIM capacitor structure to expose the metallic features 109, 110 of the underlying metal layer M1. Reference Figure 17P An anisotropic etching process can be performed using a patterned mask 517 to remove portions of the dielectric material layers 119b, 119a, 120 and electrode plates 125b, 127c, 127b, 127a, 125a, forming via openings 518b and 518b. Via opening 518a can expose portions of the intermediate electrode plates 127c and 127a on its sidewalls, and via opening 518b can expose portions of the top electrode plate 125b, intermediate electrode plate 127b, and bottom electrode plate 125a on its sidewalls. After the etching process, the patterned mask 517 can be removed using a suitable process, such as ashing or solvent dissolution.

[0097] Figure 17Q This is a vertical cross-sectional view of an exemplary structure, showing conductive vias 101 and 103 formed in via openings 518a and 518b, and an upper metal layer M2 formed over conductive vias 101, 103 and dielectric layer 119b to form an IC device 100 including a MIM capacitor structure 105, as shown in the reference above. Figures 1A-1C As described.

[0098] Figure 18 A general method 600 for manufacturing an IC device 100 including a MIM capacitor structure 105 according to various embodiments of the present disclosure is shown. Reference Figure 17A , Figure 17B and Figure 18 In step 601 of method 600, a bottom electrode plate 125a may be formed on the insulating material layer 119a. (See reference) Figure 17C and Figure 18 In step 603 of method 600, a first dielectric material layer 503 may be formed on the bottom electrode plate 125a. (See reference) Figures 17C-17L and Figure 18In step 605 of method 600, a plurality of intermediate electrode plates 127a, 127b, and 127c may be formed on the dielectric material layer 503, wherein the thickness of each of the intermediate electrode plates 127a, 127b, and 127c is greater than the thickness of the bottom electrode plate 125a. (See reference) Figure 17M and Figure 18 In step 607 of method 600, a second dielectric material layer 514 may be formed over the plurality of intermediate electrode plates 127a, 127b, and 127c. (See reference) Figure 17M , Figure 17N and Figure 18 In step 609 of method 600, a top electrode plate 125b may be formed on the second dielectric material layer 514, wherein the thickness of the top electrode plate 125b is less than the thickness of each of the intermediate electrode plates 127a, 127b, and 127c. (See reference) Figure 17O , Figure 17P and Figure 17Q In step 611 of method 600, a pair of conductive vias 101 and 103 may be formed laterally adjacent to the electrode plates 125a, 127a, 127b, 127c and 125b, wherein each of the conductive vias 101 and 103 may be conductively coupled to at least two electrode plates 125a, 127a, 127b, 127c and 125b.

[0099] Referring to all the accompanying drawings and various embodiments of the present disclosure, an integrated circuit (IC) device 100 having a metal-insulator-metal (MIM) capacitor 105 includes a top electrode plate 125b, a bottom electrode plate 125a, a plurality of intermediate electrode plates 127a, 127b, 127c stacked between the top and bottom electrode plates 125b, 125a, and a plurality of dielectric layers 129 separating each of the top electrode plate 125b, the bottom electrode plate 125a, and the intermediate electrode plates 127a, 127b, 127c from the adjacent electrode plates of the MIM capacitor 105, wherein the thickness of each of the intermediate electrode plates 127a, 127b, 127c is greater than the thickness of the top electrode plate 125b and the bottom electrode plate 125a.

[0100] In one embodiment, the IC device 100 further includes a first conductive via 101 and a second conductive via 103, wherein the MIM capacitor 105 is located between the first conductive via 101 and the second conductive via 103.

[0101] In another embodiment, the first conductive via 101 and the second conductive via 103 are connected to different voltages.

[0102] In another embodiment, the first conductive via 101 is connected to the power supply voltage and the second conductive via is connected to the ground voltage.

[0103] In another embodiment, the total number of intermediate electrode plates 127 of the MIM capacitor 105 is odd, the top electrode plate 125b and the bottom electrode plate 125a are electrically coupled to the first conductive via 101, and the number of intermediate electrode plates 127 electrically coupled to the second conductive via 103 is greater than the number of intermediate electrode plates 127 electrically coupled to the first conductive via 101.

[0104] In another embodiment, the total number of intermediate electrode plates 127 of the MIM capacitor 105 is even, the top electrode plate 125b is conductively coupled to the first conductive via 101, the bottom electrode plate 125a is conductively coupled to the second conductive via 103, and the number of intermediate electrode plates 127 conductively coupled to the first conductive via 101 is equal to the number of intermediate electrode plates 127 conductively coupled to the second via 103.

[0105] In another embodiment, the first conductive via 101 and the second conductive via 103 have the same opening size, and the opening size of the first and second conductive vias is between 1 μm and 10 μm.

[0106] In another embodiment, the MIM capacitor 105 includes a first MIM capacitor 105a, and the IC device 100 further includes a third conductive via 101 and a second MIM capacitor 105b located between the second conductive via 103 and the third conductive via 101. The second MIM capacitor 105b includes a top electrode plate 125b, a bottom electrode plate 125a, a plurality of intermediate electrode plates 127 stacked between the top and bottom electrode plates 125b and 125a, and a plurality of dielectric layers 129 separating each of the top electrode plate 125b, the bottom electrode plate 125a, and the intermediate electrode plates 127 from the adjacent electrode plates of the second MIM capacitor 105b. The thickness of each of the intermediate electrode plates 127 is greater than the thickness of the top electrode plate 125b and the bottom electrode plate 125a.

[0107] In another embodiment, the second MIM capacitor 105b has the same structure as the first MIM capacitor 105a.

[0108] In another embodiment, the second MIM capacitor 105b has a structure that is symmetrical with respect to the first MIM capacitor 105a.

[0109] In another embodiment, the via-to-via distance between the first conductive via 101 and the second conductive via 103 is different from the via-to-via distance between the second conductive via 103 and the third conductive via 101.

[0110] In another embodiment, the thickness of each of the intermediate electrode plates 127 of the MIM capacitor 105 is between 50 nm and 100 nm, and the thickness of the top electrode plate 125b and the bottom electrode plate 125a is between 10 nm and 45 nm.

[0111] In another embodiment, the MIM capacitor 105 includes a central region 130 in which a top electrode plate 125b, a plurality of intermediate electrode plates 127 and a bottom electrode plate 125a overlap in a vertical direction, and wherein each of the intermediate electrode plates 127 includes a first horizontal extension 131 contacting one of a first conductive via 101 and a second conductive via 103, a second horizontal extension 133 extending into the central region 130 of the MIM capacitor 105, and a vertical extension 132 extending between the first horizontal extension 131 and the second horizontal extension 133.

[0112] An additional embodiment relates to a method for manufacturing a metal-insulator-metal (MIM) capacitor 105 between a first conductive via 101 and a second conductive via 103 on an integrated circuit (IC) device 100. The method includes determining whether the package resonant frequency of the IC device 100 is greater than a threshold frequency; determining the capacitance of the MIM capacitor 105 based on a default plate count of the electrode plates of the MIM capacitor 105 and a default distance between the first conductive via 101 and the second conductive via 103; increasing the plate count of the electrode plates 125 and 127 of the MIM capacitor 105 when the package resonant frequency of the IC device 100 is not greater than the threshold frequency and the capacitance of the MIM capacitor 105 does not meet a predetermined performance standard; and decreasing the distance between the first via 101 and the second via 103 when the package resonant frequency of the IC device 100 is greater than the threshold frequency and the capacitance of the MIM capacitor 105 does not meet the design requirements of the MIM capacitor 105.

[0113] In one embodiment, the threshold frequency is between 50MHz and 100MHz.

[0114] In another embodiment, the method further includes: increasing the plate count of the MIM capacitor 105 when the reduced distance between the first via 101 and the second via 103 is less than a predetermined threshold distance between the first via 101 and the second via 103, and the capacitance of the MIM capacitor 105 does not meet a predetermined performance standard.

[0115] In another embodiment, the threshold distance between the first via and the second via is between 3 μm and 9 μm.

[0116] Additional embodiments relate to a method of manufacturing an integrated circuit (IC) device 100 including a metal-insulator-metal (MIM) capacitor 105, the method comprising forming a bottom electrode plate 125a over an insulating material layer 119a, forming a first dielectric material layer 503 over the bottom electrode plate 125a, and forming a plurality of intermediate electrode plates 127a, 127b, 127c over the first dielectric material layer 503, wherein the thickness of each of the intermediate electrode plates 127a, 127b, 127c is greater than the thickness of the bottom electrode plate 125a. A second dielectric material layer 514 is formed on a plurality of intermediate electrode plates 127a, 127b, and 127c, and a top electrode plate 125b is formed on the second dielectric material layer 514, wherein the thickness of the top electrode plate 125b is less than the thickness of each of the intermediate electrode plates 127a, 127b, and 127c, and a pair of conductive vias 101 and 103 are formed on the electrode plates laterally adjacent to the MIM capacitor, wherein each of the conductive vias is conductively coupled to at least two electrode plates 125 and 127 of the MIM capacitor 105.

[0117] In one embodiment, each of the conductive vias 101 and 103 contacts a metal feature 109 or 110 of the lower first metal layer M1 of the interconnect structure of the IC device 100. The method further includes forming a second metal layer M2 of the interconnect structure over the MIM capacitor 105, wherein each of the conductive vias 101 and 103 extends between metal features 107, 108, 109, and 110 of the first metal layer M1 and the second metal layer M2 of the interconnect structure.

[0118] In another embodiment, the second metal layer M2 is a redistribution layer.

[0119] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0120] Example 1. An integrated circuit (IC) device having a metal-insulator-metal (MIM) capacitor, the MIM capacitor comprising: a top electrode plate; a bottom electrode plate; a plurality of intermediate electrode plates stacked between the top electrode plate and the bottom electrode plate; and a plurality of dielectric layers separating each of the top electrode plate, the bottom electrode plate, and each of the plurality of intermediate electrode plates from adjacent electrode plates of the MIM capacitor, wherein the thickness of each of the plurality of intermediate electrode plates is greater than the thickness of the top electrode plate and the bottom electrode plate.

[0121] Example 2. The IC device according to Example 1 further includes: a first conductive via; and a second conductive via, wherein the MIM capacitor is located between the first conductive via and the second conductive via.

[0122] Example 3. The IC device according to Example 2, wherein the first conductive via and the second conductive via are connected to different voltages.

[0123] Example 4. The IC device according to Example 3, wherein the first conductive via is connected to a power supply voltage, and the second conductive via is connected to a ground voltage.

[0124] Example 5. The IC device according to Example 2, wherein the total number of intermediate electrode plates of the MIM capacitor is odd, the top electrode plate and the bottom electrode plate are conductively coupled to the first conductive via, and the number of intermediate electrode plates conductively coupled to the second conductive via is greater than the number of intermediate electrode plates conductively coupled to the first conductive via.

[0125] Example 6. The IC device according to Example 2, wherein the total number of intermediate electrode plates of the MIM capacitor is even, the top electrode plate is conductively coupled to the first conductive via, the bottom electrode plate is conductively coupled to the second conductive via, and the number of intermediate electrode plates conductively coupled to the first conductive via is equal to the number of intermediate electrode plates conductively coupled to the second conductive via.

[0126] Example 7. The IC device according to Example 2, wherein the first conductive via and the second conductive via have the same opening size, and the opening size of the first conductive via and the second conductive via is between 1 μm and 10 μm.

[0127] Example 8. An IC device according to Example 1, wherein the MIM capacitor includes a first MIM capacitor, the IC device further includes: a third conductive via; and a second MIM capacitor located between the second conductive via and the third conductive via, wherein the second MIM capacitor includes: a top electrode plate; a bottom electrode plate; a plurality of intermediate electrode plates stacked between the top electrode plate and the bottom electrode plate; and a plurality of dielectric layers separating each of the top electrode plate, the bottom electrode plate, and each of the plurality of intermediate electrode plates from the adjacent electrode plates of the second MIM capacitor, wherein the thickness of each of the plurality of intermediate electrode plates is greater than the thickness of the top electrode plate and the bottom electrode plate.

[0128] Example 9. The IC device according to Example 8, wherein the second MIM capacitor has the same structure as the first MIM capacitor.

[0129] Example 10. The IC device according to Example 8, wherein the second MIM capacitor has a structure symmetrical with respect to the first MIM capacitor.

[0130] Example 11. The IC device according to Example 8, wherein the via-to-via distance between the first conductive via and the second conductive via is different from the via-to-via distance between the second conductive via and the third conductive via.

[0131] Example 12. The IC device according to Example 1, wherein the thickness of each of the plurality of intermediate electrode plates of the MIM capacitor is between 50 nm and 100 nm, and the thickness of the top electrode plate and the bottom electrode plate is between 10 nm and 45 nm.

[0132] Example 13. The IC device according to Example 1, wherein the MIM capacitor includes a central region in which the top electrode plate, the plurality of intermediate electrode plates and the bottom electrode plate overlap in a vertical direction, and wherein each of the plurality of intermediate electrode plates includes a first horizontal extension contacting one of the first conductive via and the second conductive via, a second horizontal extension extending into the central region of the MIM capacitor, and a vertical extension extending between the first horizontal extension and the second horizontal extension.

[0133] Example 14. A method for manufacturing a metal-insulator-metal (MIM) capacitor between a first conductive via and a second conductive via on an integrated circuit (IC) device, comprising: determining whether a package resonant frequency of the IC device is greater than a threshold frequency; determining the capacitance of the MIM capacitor based on a default plate count of the electrode plates of the MIM capacitor and a default distance between the first conductive via and the second conductive via; increasing the plate count of the electrode plates of the MIM capacitor when the package resonant frequency of the IC device is not greater than the threshold frequency and the capacitance of the MIM capacitor does not meet a predetermined performance standard; and decreasing the distance between the first conductive via and the second conductive via when the package resonant frequency of the IC device is greater than the threshold frequency and the capacitance of the MIM capacitor does not meet the design requirements of the MIM capacitor.

[0134] Example 15. The method according to Example 14, wherein the threshold frequency is between 50 MHz and 100 MHz.

[0135] Example 16. The method according to Example 14 further includes: increasing the plate count of the MIM capacitor when the reduced distance between the first conductive via and the second conductive via is less than a predetermined threshold distance between the first conductive via and the second conductive via, and the capacitance of the MIM capacitor does not meet a predetermined performance standard.

[0136] Example 17. The method according to Example 15, wherein the threshold distance between the first conductive via and the second conductive via is between 3 μm and 9 μm.

[0137] Example 18. A method of manufacturing an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor, comprising: forming a bottom electrode plate over an insulating material layer; forming a first dielectric material layer over the bottom electrode plate; forming a plurality of intermediate electrode plates over the first dielectric material layer, wherein the thickness of each of the intermediate electrode plates is greater than the thickness of the bottom electrode plate; forming a second dielectric material layer over the plurality of intermediate electrode plates; forming a top electrode plate over the second dielectric material layer, wherein the thickness of the top electrode plate is less than the thickness of each of the intermediate electrode plates; and forming a pair of conductive vias laterally adjacent to the electrode plates of the MIM capacitor, wherein each of the pair of conductive vias is conductively coupled to at least two electrode plates of the MIM capacitor.

[0138] Example 19. The method according to Example 18, wherein each of the pair of conductive vias contacts a metal feature of a lower first metal layer of the interconnect structure of the IC device, the method further comprising: forming a second metal layer of the interconnect structure over the MIM capacitor, wherein each of the pair of conductive vias extends between the metal features of the lower first metal layer and the second metal layer of the interconnect structure.

[0139] Example 20. The method according to Example 19, wherein the second metal layer includes a redistribution layer.

Claims

1. An integrated circuit (IC) device having a metal-insulator-metal (MIM) capacitor, wherein the MIM capacitor comprises: Top electrode plate; Bottom electrode plate; Multiple intermediate electrode plates are stacked between the top electrode plate and the bottom electrode plate; as well as Multiple dielectric layers separate each of the top electrode plate, the bottom electrode plate, and each of the multiple intermediate electrode plates from the adjacent electrode plates of the MIM capacitor. The thickness of each of the plurality of intermediate electrode plates is greater than the thickness of the top electrode plate and the bottom electrode plate.

2. The IC device according to claim 1, further comprising: First conductive via; as well as The second conductive via, wherein the MIM capacitor is located between the first conductive via and the second conductive via.

3. The IC device of claim 2, wherein, The first conductive via and the second conductive via are connected to different voltages.

4. The IC device of claim 3, wherein, The first conductive via is connected to the power supply voltage, and the second conductive via is connected to the ground voltage.

5. The IC device of claim 2, wherein, The total number of intermediate electrode plates of the MIM capacitor is odd. The top electrode plate and the bottom electrode plate are electrically coupled to the first conductive via. The number of intermediate electrode plates electrically coupled to the second conductive via is greater than the number of intermediate electrode plates electrically coupled to the first conductive via.

6. The IC device of claim 2, wherein, The total number of intermediate electrode plates of the MIM capacitor is even. The top electrode plate is conductively coupled to the first conductive via, and the bottom electrode plate is conductively coupled to the second conductive via. The number of intermediate electrode plates conductively coupled to the first conductive via is equal to the number of intermediate electrode plates conductively coupled to the second conductive via.

7. The IC device of claim 2, wherein, The first conductive via and the second conductive via have the same opening size, and the opening size of the first conductive via and the second conductive via is between 1 μm and 10 μm.

8. The IC device of claim 2, wherein, The MIM capacitor includes a first MIM capacitor, and the IC device further includes: The third conductive via; and A second MIM capacitor is located between the second conductive via and the third conductive via, wherein the second MIM capacitor includes: Top electrode plate; Bottom electrode plate; Multiple intermediate electrode plates are stacked between the top electrode plate and the bottom electrode plate; and Multiple dielectric layers separate each of the top electrode plate, the bottom electrode plate, and each of the multiple intermediate electrode plates from the adjacent electrode plates of the second MIM capacitor. The thickness of each of the plurality of intermediate electrode plates is greater than the thickness of the top electrode plate and the bottom electrode plate.

9. The IC device of claim 8, wherein, The second MIM capacitor has the same structure as the first MIM capacitor.

10. The IC device of claim 8, wherein, The second MIM capacitor has a structure that is symmetrical with respect to the first MIM capacitor.

11. The IC device according to claim 8, wherein, The via-to-via distance between the first conductive via and the second conductive via is different from the via-to-via distance between the second conductive via and the third conductive via.

12. The IC device according to claim 1, wherein, The thickness of each of the plurality of intermediate electrode plates of the MIM capacitor is between 50 nm and 100 nm, and the thickness of the top electrode plate and the bottom electrode plate is between 10 nm and 45 nm.

13. The IC device according to claim 2, wherein, The MIM capacitor includes a central region in which the top electrode plate, the plurality of intermediate electrode plates, and the bottom electrode plate overlap in a vertical direction, and wherein each of the plurality of intermediate electrode plates includes a first horizontal extension contacting one of the first conductive via and the second conductive via, a second horizontal extension extending into the central region of the MIM capacitor, and a vertical extension extending between the first horizontal extension and the second horizontal extension.

14. A method for fabricating a metal-insulator-metal (MIM) capacitor between a first conductive via and a second conductive via on an integrated circuit (IC) device, comprising: Determine whether the package resonant frequency of the IC device is greater than the threshold frequency; The capacitance of the MIM capacitor is determined based on the default plate count of the electrode plates of the MIM capacitor and the default distance between the first conductive via and the second conductive via. When the package resonant frequency of the IC device is not greater than the threshold frequency and the capacitance of the MIM capacitor does not meet the predetermined performance standard, the plate count of the electrode plates of the MIM capacitor is increased. as well as When the package resonant frequency of the IC device is greater than the threshold frequency and the capacitance of the MIM capacitor does not meet the design requirements of the MIM capacitor, the distance between the first conductive via and the second conductive via is reduced.

15. The method according to claim 14, wherein, The threshold frequency is between 50MHz and 100MHz.

16. The method of claim 14, further comprising: When the reduced distance between the first conductive via and the second conductive via is less than a predetermined threshold distance between the first conductive via and the second conductive via, and the capacitance of the MIM capacitor does not meet a predetermined performance standard, the plate count of the MIM capacitor is increased.

17. The method according to claim 16, wherein, The threshold distance between the first conductive via and the second conductive via is between 3 μm and 9 μm.

18. A method for manufacturing an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor, comprising: A bottom electrode plate is formed on top of an insulating material layer; A first dielectric material layer is formed on the bottom electrode plate; A plurality of intermediate electrode plates are formed on the first dielectric material layer, wherein the thickness of each of the intermediate electrode plates is greater than the thickness of the bottom electrode plate. A second dielectric material layer is formed on the plurality of intermediate electrode plates; A top electrode plate is formed on the second dielectric material layer, wherein the thickness of the top electrode plate is less than the thickness of each of the intermediate electrode plates; and A pair of conductive vias are formed laterally adjacent to the electrode plates of the MIM capacitor, wherein each of the pair of conductive vias is conductively coupled to at least two electrode plates of the MIM capacitor.

19. The method according to claim 18, wherein, Each of the conductive vias contacts a metal feature of the lower first metal layer of the interconnect structure of the IC device, and the method further includes: A second metal layer of the interconnect structure is formed on the MIM capacitor, wherein each of the pair of conductive vias extends between the metal features of the lower first metal layer and the second metal layer of the interconnect structure.

20. The method according to claim 19, wherein, The second metal layer includes a redistribution layer.

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