A QC-LDPC encoding method and an encoder

Abstract

The present invention discloses a QC-LDPC encoding method and encoder, belonging to the field of QC-LDPC encoding technology. The present invention only stores generators of a circulant matrix, saving storage resources, simplifying the encoding storage and transport volume, reducing hardware implementation complexity, and thus reducing the power consumption of the encoder; adopting a cyclic shift unit and a binary field multiplication-addition unit, using AND operations and XOR operations to implement encoding operations of the generator matrix and information bits, simplifying the operation process; through a high-parallel storage method, the generators of the generator matrix are pre-read and then simultaneously sent to a shift register for calculation, thereby realizing high-parallel encoding operations; and can support efficient LDPC encoding operations with 1 / 2 code rate and 19 code lengths under the IEEE 802.16e communication protocol. The present invention has the characteristics of low hardware complexity and high storage resource utilization, and ultimately can realize high-parallelism and high-throughput encoding operations.

Description

Technical Field

[0001] The present invention relates to the field of QC-LDPC coding technology, and more particularly to a QC-LDPC coding method and encoder. Background Art

[0002] Low-density parity-check (LDPC) codes are sparse parity-check matrix linear block codes first proposed by Robert Gallager in the 1960s. Their performance approaches the Shannon limit and they are widely used in communication and navigation algorithms. Therefore, designing an LDPC coding method with high parallelism, low computational complexity, and easy hardware implementation, as well as its hardware implementation, are currently hot research topics.

[0003] If the length of the LDPC code check bit is m, the length of the encoded codeword is n, and the check matrix is H m×n It means that the length of the information sequence s is k=nm, and the code rate is r=k / n. After transforming the check matrix, the corresponding generator matrix G is obtained, and then the information sequence s and G are multiplied to complete the encoding, that is, c=s*G. This encoding method based on the generator matrix mainly includes three types: direct encoding algorithm, lower triangle-based encoding algorithm, and QC-LDPC (quasi-cyclic LDPC) encoding algorithm. Because the check matrix H is a sparse matrix, but the generator matrix transformed from the check matrix is not sparse, its encoding complexity is often proportional to the code length. The larger the code length, the more storage registers are required, the more hardware resources are consumed, and the encoding efficiency is also lower. Therefore, direct encoding has large computational and storage requirements, and the coding based on the lower triangle has a large delay, and neither is the best choice for hardware implementation.

[0004] The performance of QC-LDPC codes in short and medium code segments is close to that of the optimal randomly constructed LDPC codes, and they have strong error correction capabilities. Due to their quasi-cyclic nature, the generator matrix can be represented by the generator of the cyclic matrix, reducing hardware logic and storage resources. The LDPC code in the IEEE802.16e standard is a quasi-cyclic LDPC code, which includes four code rates. Each code rate has a corresponding matrix, called the base check matrix, denoted by H. b , the size of the check matrix is m b ×n b , which can be written as H b =[H b1 H b2 ], where H b1 The size is m b ×k b , (k b =n b -m b ), H b2 The size is m b ×m bBy transforming the base check matrix according to a certain rule, the check matrix can be obtained. The check matrix can be transformed into a generating matrix with a quasi-cyclic structure.

[0005] The quasi-cyclic nature greatly reduces the storage resources required for encoding, but the traditional QC-LDPC encoding process still involves a large number of multiplication calculations between information blocks and the generator matrix, which is computationally intensive. Therefore, the traditional encoding method needs to be optimized to increase parallelism and reduce hardware implementation complexity in order to achieve high-throughput encoding.

[0006] Chinese patent application, application number CN201811158252.1, published on March 1, 2019, discloses a QC_LDPC code encoding method based on a generator matrix, characterized by comprising the following steps: converting the encoded information sequence S into information bits S i ; Get submatrix G from generator matrix G i,j ; Using each sub-matrix G i,j The addresses of all non-zero elements "1" in the first row correspond to the information bits S i Perform circular shift operations to obtain intermediate product results respectively; accumulate all intermediate product results to obtain vector matrix product results sg i,j ; The result of vector matrix product sg i,j The middle check bit P is obtained by operation i,j Generate the check bit P. This encoding method converts the input information sequence and then uses the quasi-cyclic characteristics of the generator matrix to encode it, reducing hardware resource consumption, reducing chip area, and achieving code rate compatibility. However, this method still involves a large amount of calculation and has high hardware implementation complexity. Summary of the Invention

[0007] 1. Technical problems to be solved

[0008] To address the problems of large computational complexity and high hardware implementation complexity in conventional QC-LDPC coding in the prior art, the present invention provides a QC-LDPC coding method and encoder that saves storage resources, simplifies the computational process, and can implement highly parallel coding operations. Ultimately, it can support LDPC coding operations with a 1 / 2 code rate and 19 code lengths under the IEEE 802.16e communication protocol.

[0009] 2. Technical solution

[0010] The purpose of the present invention is achieved through the following technical solutions.

[0011] The present invention realizes high-parallel coding operations through parallel storage and generator pre-reading, and can ultimately support LDPC coding operations with 1 / 2 code rate and 19 code lengths under the IEEE 802.16e communication protocol.

[0012] A QC-LDPC encoding method performs a cyclic shift on the generator elements of an input generator matrix, inputs the cyclic shift result and information bits into a multiplier module for binary domain multiplication calculation, accumulates the multiplication results in sequence through a first adder, and then accumulates the calculation results of the first adder through a second adder to obtain a check bit.

[0013] Furthermore, the cyclic shift is controlled by an enable signal. When the enable signal is valid, the input generator is cyclically shifted right by one bit in each clock cycle, and the cyclic shift result is outputted at the same time.

[0014] Furthermore, the information bits are divided into k equal length b parts, each part s i It consists of z consecutive information bits, k b , i, z are all positive integers, z represents the test matrix H b Extended to the extended parameters of the check matrix H, the basis check matrix H b The size is m b ×n b , the size of the check matrix H is recorded as m×n, m=m b z,n=n b z, m b 、n b All are positive integers.

[0015] The following is an explanation of the 1 / 2 code rate LDPC coding for the IEEE 802.16e standard. b All are 24, 1 / 2 bit rate m b =12. Before expansion, select a parameter z and set H b Expanded to m b ·z×n b z’s check matrix H; let m = m b z,n=n b z, the size of the check matrix H is denoted as m × n. According to the IEEE 802.16e standard, the extended parameter z can be one of a series of 19 values, with a minimum of 24 and a maximum of 96, with intervals of 4. At a code rate of 1 / 2, the 19 code lengths supported by QC-LDPC range from 576 to 2304, with intervals of 96, which are medium-short codes.

[0016] The information bit s=(s1,s2,…,s 12×z ), divide it into k equal length b Part (k b =12), then s=(s1,s2,…,s 12 ), where the i-th part s iIt consists of z consecutive information bits, 1≤i≤12. The information bits are multiplied by the generator matrix to obtain the encoded codeword C, C=s×G=(s,p1,p2,…,p 12 ), where the jth (1≤j≤12) check part contains z check bits, which can be expressed as p j =(p j,1 ,p j,2 ,…,p j,z )=s1G 1,j +s2G 2,j +…+s 12 G 12,j .

[0017] The generator matrix has the following quasi-cyclic form:

[0018]

[0019] Where I is the z×z identity matrix, 0 is the z×z zero matrix, G i,j Is a z×z circulant matrix, generating matrix G qc The left part is k b ×z×k b ×z unit matrix, and the right side is the P matrix that generates the check bit. Let g i,j is the cyclic matrix G i,j The generator of G i,j The first line, g i,j Can represent G qc All loops G i,j , enter g i,j The generator matrix G can be constructed qc When 0≤l≤x, let is the generator g i,j The result of a circular right shift of 1 bit, and Then we have:

[0020] The generation method of the cyclic generator is as follows: let u = (1, 0, ..., 0), 0 = (0, 0, ..., 0), the length of each is z, for 1≤i≤12, then the matrix G is generated qc Line i: g i =(0,…,u,0…0,g i,1 ,g i,2 ,…,g i,12 ), where u is in g i The i-th part. Because the check matrix and the generator matrix satisfy so From this, all generators g can be obtained according to the check matrix i,j , thus constructing the generator matrix G qc.

[0021] The present invention utilizes the characteristics of parallel storage and adopts the generator pre-reading method to first use 12 clock cycles to read g 1,j (0) , g 2,j (0) ,……g 12,j (0) After being taken out, it is stored in 12 circular shift registers, and then encoded with the information bits at the same time, which can greatly improve the parallelism.

[0022] Furthermore, the information bit data is read by reading the address of the information bit storage unit, and the address of the information bit storage unit is controlled to increase by one bit per clock cycle, and each part of the information bit s is read out in turn. i .

[0023] The present invention saves storage resources by storing generators of circulant matrices; adopts a cyclic shift unit and a binary field multiplication-addition unit, uses AND operations and XOR operations to realize encoding operations of generator matrices and information bits, and simplifies the operation process; and through a high-parallel storage method, pre-reads the generators of the generator matrix and then simultaneously sends them to the shift register for calculation, thereby realizing high-parallel encoding operations.

[0024] A QC-LDPC encoder, using the QC-LDPC encoding method, the encoder comprising a calculation module, the calculation module being used to solve the encoded check bit;

[0025] The operation module includes a cyclic shift unit, a binary domain multiplication and addition unit and a check bit solution unit. The cyclic shift unit is used to cyclically shift the generator and send the result of the cyclic right shift to the binary domain multiplication and addition unit. The binary domain multiplication and addition unit is used to perform binary domain multiplication and addition calculations on the cyclic shift result and the information bit. The check bit solution unit is used to implement the binary domain accumulation operation and calculate the check bit.

[0026] Furthermore, the cyclic shift unit includes z levels of cyclic shift subunits connected in series, each cyclic shift subunit includes a selector and a D flip-flop, the output end of the selector is connected to the input end of the D flip-flop, the output end of the D flip-flop is connected to the input end of the selector in the next level subunit, the selector is also connected to the cyclic shift enable signal, and the D flip-flop is connected to the clock signal.

[0027] Furthermore, the binary domain multiplication and addition unit includes z-stage parallel binary domain multiplication and addition sub-units, each binary domain multiplication and addition sub-unit includes an AND gate, an XOR gate and a D flip-flop, the input end of the AND gate is connected to the cyclic shift result and the information bit value, the output end of the AND gate is connected to the input end of the XOR gate, the other input end of the XOR gate is connected to the output end of the D flip-flop, the output end of the XOR gate is connected to the input end of the D flip-flop, and the input end of the D flip-flop is also connected to the clock signal.

[0028] Furthermore, the check bit solution unit includes N levels of XOR gates, the input signal of the first-level XOR gate is the output signal of the binary domain multiplication and addition unit, and the input signal of the first-level XOR gate is the input signal of the next-level XOR gate, thereby realizing the cumulative calculation of the output signal of the binary domain multiplication and addition unit.

[0029] Furthermore, the system also includes a control module and a storage module, the control module is used to control the encoder to perform parallel encoding, and the storage module is used to store the generation matrix, information bits and operation results; the storage module includes a generation matrix storage unit, an information bit storage unit and an operation settlement storage unit, each storage unit includes several storage bodies, and the storage bodies are independent of each other.

[0030] Furthermore, the control module includes a computing enablement control module, an address generation module and a data distribution module.

[0031] The encoding process of the QC-LDPC high-efficiency encoder described in the present invention mainly involves binary domain multiplication and accumulation operations. Multiplication and addition correspond to the "exclusive or" and "and" operations in hardware implementation, respectively. A circular shift register is designed in the algorithm to complete the circular shift operation on the generator. The circular shift module determines the bit width of the circular shift according to the input extension parameter z. The circular shift enable signal is used as a valid signal. When the circular shift enable signal value is 1, the input generator g is shifted. i,j Perform a circular shift, right shift 1 bit in each clock cycle, and output the corresponding circular shift result data; in the binary field multiplication and accumulation operation, the circular shift result of each clock cycle and the information bit s are sent to the multiplier for binary field multiplication calculation, and the calculation result is sent to the adder for binary field accumulation operation, and finally the check bit can be calculated.

[0032] 3. Beneficial effects

[0033] Compared with the existing technology, the LDPC encoder disclosed in the present invention can effectively improve performance, throughput and flexibility, reduce encoder computational complexity, and simplify encoder hardware implementation, as shown in the following aspects:

[0034] (1) The present invention can adapt to different parallel computing paths according to different standards and support different QC-LDPC coding standards. Taking the coding calculation for the IEEE802.16e communication protocol, 1 / 2 code rate, and 19 code lengths as an example, the implementation method of the present invention has good compatibility. The 19 supported code lengths range from 576 to 2304, with an interval of 96 values, which are medium-short codes. Within this range, QC-LDPC codes have better performance and a wide range of adaptability.

[0035] (2) The present invention only stores the generator matrix generators, which simplifies the coding storage and data transmission volume, reduces the hardware implementation complexity, and reduces the power consumption of the encoder; a cyclic shift unit and a binary domain multiplication and addition module are used to implement the coding operation of the generator matrix and the information bit. For the binary domain, multiplication is an AND operation and addition is an XOR operation, so the hardware implementation structure is simple;

[0036] (3) The present invention can realize high parallelism and high throughput coding operation by generating the element g i,j The information sequence s is stored in parallel, fully exploiting the parallelism of the algorithm. On the basis of the parallel generation of twelve check bits, by reading the generators of different rows in advance, the generation of each check bit can also achieve twelve-way parallelism, and a maximum of 144-way parallel operations can be achieved. At the same time, by pre-reading the generators of the generator matrix and storing them in 12 circular shift registers, the encoding parallelism is greatly improved. Taking the code length of 2304 bits and the information bits of 1152 bits as an example, the present invention only needs 12+96=108 cycles to complete the encoding operation, and the throughput rate is 8.5Gbps. Compared with the traditional encoding operation requiring 96×12=1152 cycles, the throughput rate of the present invention is increased by nearly 10 times; BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 1 is a hardware structure diagram of the QC-LDPC encoder in the present invention;

[0038] Figure 2 Schematic diagram of the cyclic shift unit structure of the QC-LDPC encoder in the present invention;

[0039] Figure 3 Schematic diagram of the binary domain multiplication-addition unit structure of the QC-LDPC encoder in the present invention;

[0040] Figure 4 Schematic diagram of the structure of the check bit solving unit of the QC-LDPC encoder in the present invention;

[0041] Figure 5 is a control flow chart of the QC-LDPC encoder in the present invention;

[0042] Figure 6 is the generator g in the present invention i,j Schematic diagram of storage method in SRAM;

[0043] Figure 7 Schematic diagram of the storage method of the information sequence s in the SRAM in the present invention;

[0044] Figure 8 Schematic diagram of the storage method of the result check bit p in SRAM in the present invention. DETAILED DESCRIPTION

[0045] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present invention.

[0046] Example

[0047] The encoder described in this embodiment takes the 1 / 2 code rate LDPC coding under the IEEE 802.16e standard as an example to illustrate the encoder and encoding method. In actual applications, different parallel computing paths can be adapted according to different standards to support different QC-LDPC coding standards.

[0048] In the solution described in this embodiment, the base check matrix H b The number of rows and columns is expressed as m b and n b For different bit rates, n b All are 24, 1 / 2 bit rate m b =12. Before expanding the base check matrix, select an expansion parameter z and set H b Expanded to m b ·z×n b z’s check matrix H; let m = m b z,n=n b z, the size of the check matrix H is denoted as m×n. According to the IEEE 802.16e standard, the extended parameter z can be one of a series of 19 values, with a minimum of 24 and a maximum of 96, with intervals of 4. At a code rate of 1 / 2, the 19 code lengths supported by QC-LDPC range from 576 to 2304, with intervals of 96, making them medium-short codes.

[0049] The encoding method of this embodiment encodes the information sequence to obtain a check sequence. Under the IEEE802.16e communication protocol and 1 / 2 code rate, n b =24, check digit m b =12, the length of the information bit sequence k b =12; the information bit s=(s1,s2,…,s 12×z ), check digit p j =(p j,1 ,p j,2 ,…,p j,z ), 1≤j≤12, z is the above-mentioned extended parameter.

[0050] Divide the information sequence into k equal length b parts, k b=12, then the information bit s=(s1,s2,…,s 12 ), where the i-th part s i It is composed of z consecutive information bits. The information bit s is multiplied by the generator matrix G to obtain the encoded codeword C, that is, C=s×G=(s,p1,p2,…,p 12 ), where the jth check part contains z check bits and can be expressed as p j =(p j,1 ,p j,2 ,…,p j,z )=s1G 1,j +s2G 2,j +…+s 12 G 12,j .

[0051] The generator matrix has the following quasi-cyclic form:

[0052]

[0053] Where I is the z×z identity matrix, 0 is the z×z zero matrix, G i,j Is a z×z circulant matrix, generating matrix G qc The left part is k b ×z×k b ×z unit matrix, generating matrix G qc The right side is the P matrix that generates the check bit. Let g i,j is the cyclic matrix G i,j The generator of G i,j The first line, g i,j Can represent G qc All loops G i,j , enter g i,j The generator matrix G can be constructed qc When 0≤l≤x, let is the generator g i,j The result of a circular right shift of 1 bit, and Then we have:

[0054] The generation method of the cyclic generator is as follows: let u = (1, 0, ..., 0), 0 = (0, 0, ..., 0), the length of each is z, for 1≤i≤12, then the matrix G is generated qc , the i-th line is: g i =(0,…,u,0…0,g i,1 ,g i,2 ,…,g i,12 ), where u is in g i The i-th part. Because the check matrix and the generator matrix satisfy so Figure 5 The control flow chart shown in FIG. j The process of finding s i G i,j The process of all generators g can be obtained according to the check matrix i,j , thus constructing the generator matrix G qc .

[0055] The hardware structure of the encoder in this embodiment is as follows Figure 1 As shown, it includes a control module, a storage module and an operation module. The control module is connected to the storage module and the operation module. The control module reads the data of the storage module and then sends the data to the operation module for calculation, and stores the calculation result data of the operation module in the storage module. In this embodiment, the control module is an LDPC coding controller and the storage module is an SRAM storage unit.

[0056] The LDPC encoding controller is the key to implementing the LDPC encoding method of this embodiment. The LDPC encoding controller includes a calculation enable control module, an address generation module, and a data distribution module. The LDPC encoding controller is used to control the entire encoder to perform parallel encoding, realizing the reading, distribution, calculation, and storage of the source data required for the LDPC encoding operation.

[0057] The SRAM storage unit includes several storage areas for storing the generator G representing the generator matrix. qc , information bit s, and operation result data. In this embodiment, the SRAM storage unit includes a generator matrix storage unit, an information bit storage unit, and an operation settlement storage unit, including 25 storage banks BANK0 to BANK24, of which BANK0 to BANK11 are generator matrix storage units for storing generators of the generator matrix, BANK12 is an information bit storage unit for storing information bits, and BANK13 to BANK24 are operation settlement storage units for storing result data; each storage bank is an independent storage device that can read and write data simultaneously. Through parallel storage, this embodiment takes the LDPC coding for 1 / 2 code rate under the IEEE 802.16e standard as an example, and can achieve a maximum of 12 times 12 parallel coding, a total of 144 channels.

[0058] The operation module includes a cyclic shift unit, a binary field multiplication and addition unit and a check bit solving unit. The structure diagram of the operation module is shown in the figure. Figures 2 to 4 As shown, Figure 2 The schematic diagram of the cyclic shift unit structure is as follows. The cyclic shift unit includes z subunits connected in series. Each subunit includes a selector and a D flip-flop. The output of each subunit selector is connected to the input of the D flip-flop, and the output of the D flip-flop is connected to the input of the selector in the next subunit. Figure 2As shown, the initial input signal of the cyclic shift unit is the generator of the generator matrix, and the enable signal is used as a valid signal. When the enable value is 1, the input generator g i,j Perform circular shift, shifting right by 1 bit in each clock cycle, and at the same time, the result of the circular right shift is sent to the binary field multiplication and addition unit.

[0059] Figure 3 The figure shows the structure of the binary domain multiplication and addition unit, which is the basic subunit in the parallel binary domain multiplication and addition operation. In each clock cycle, the cyclic shift result and the information bit s are sent to the multiplier for binary domain multiplication calculation. The calculation results are accumulated in sequence. In this embodiment, the binary domain multiplier is realized by AND gate, and the binary domain adder is realized by XOR gate. Figure 3 As shown, the binary domain multiplication and addition unit includes z-level parallel binary domain multiplication and addition sub-units, each of which includes an AND gate, an XOR gate, and a D flip-flop. The input of the AND gate is connected to the cyclic shift result and the information bit value, the output of the AND gate is connected to the input of the XOR gate, the other input of the XOR gate is connected to the output of the D flip-flop, the output of the XOR gate is connected to the input of the D flip-flop, and the input of the D flip-flop is also connected to the clock signal. In this embodiment, by pre-reading the generator of the generator matrix, 12 cyclic shift units are called simultaneously to calculate s1G at the same time. 1,j ,s2G 2,j ,…,s 12 G 12,j .

[0060] Figure 4 The figure shows the structure of the check bit solving unit. The check bit solving unit consists of four levels of eleven XOR gates. The input signal of the first level XOR gate is s1G. 1,j ,s2G 2,j ,…,s 12 G 12,j The output of the first-stage XOR gate is connected to the input of the second-stage XOR gate, the output of the second-stage XOR gate is connected to the input of the third-stage XOR gate, and the output of the third-stage XOR gate is connected to the input of the fourth-stage XOR gate; the check bit solving unit is connected to s1G 1,j ,s2G 2,j ,…,s 12 G 12,j Perform binary domain accumulation operation and finally get the jth check bit: p j =s1G 1,j +s2G 2,j +…+s 12 G 12,j This embodiment uses a 12-way parallel method to calculate p1, p2, ... p 12 The overall calculation process of the operation module is as follows: Figure 5 shown.

[0061] The operation data is stored in the SRAM storage module in a sequential manner according to the parallelism of the algorithm. qc The left half is the identity matrix. Any value multiplied by the identity matrix remains itself; the generated matrix G qc The right half is composed of circulant matrices, so the generators of each circulant matrix are stored in the SRAM storage module, and then the encoding can be achieved by continuously shifting the generators for calculation.

[0062] Generator g i,j The storage method in the SRAM storage module is as follows Figure 6 As shown, the bank port width is 128 bits, each address stores a zbit generator, and the memory banks BANK0, 1, ... 11 store g i,1 ,g i,2 ,…,g i,12 , 12-way parallel storage can realize the simultaneous calculation of 12 check bits.

[0063] The information sequence of information bits s is also stored in parallel in a specific way, such as Figure 7 As shown, under the IEEE802.16e protocol, the information sequence has 19 different lengths and is stored in a memory bank BANK12. The 0 address in BANK12 stores s in order from low bit to high bit. 1,1 ,s 2,1 …s 12,1 ; BANK12 stores 1 address from low bit to high bit in sequence 1,2 ,s 2,2 …s 12,2 , and so on for the rest of the addresses.

[0064] The check bit storage method is as follows Figure 8 As shown, they are obtained through 12-way parallel calculations.

[0065] The hardware design of the QC-LDPC encoder is carried out using Verilog HDL language, and basic test verification is completed using VCS and FPGA. Figure 5 The encoding method of this embodiment includes the following steps.

[0066] First, using the characteristics of parallel storage, the generators are read in using the generator pre-reading method.

[0067] In the generator matrix address generation module, according to the storage scheme of the generator, the memory banks BANK0 to BANK11 store the first column of G (G 1,1 , G 2,1 , ... G 12,1 ), the generator of the 2nd column, ..., the 12th column, the generator is represented by gi,j , the bit width is zbit, parallel storage can read data from 12 storage banks independently at the same time, support 12-way parallel calculation of verification results, each calculation is processed in the same way, and p1, p2, ..., p are calculated respectively. 12 .

[0068] Taking the calculation of the first check bit as an example, to calculate p1, it is necessary to calculate s1G separately 1,1 ,s2G 2,1 ,…,s 12 G 12,1 ; G i,1 Stored in BANK0, read out in the first clock cycle 1,1 In the second clock cycle, the address is incremented by 1 and g is read out. 2,1 ...., read out g in the 12th clock cycle 12,1 , the read generators are sent to the cyclic shift module of the operation module respectively, and a cyclic shift start signal is given at the same time.

[0069] At the same time, the information sequence of the information bit s is read and input into the parallel multiplication and addition module.

[0070] The address generation module of the LDPC coding controller controls the reading of the information sequence of the information bit s. According to the storage method of the information sequence, the address 0 in the memory bank BANK12 stores s in sequence from low bit to high bit. 1,1 ,s 2,1 …s 12,1 ; 1 address is stored from low bit to high bit, s 1,2 ,s 2,2 …s 12,2 The check bits can be obtained by 12-way parallel calculations. Taking the calculation of the first check bit as an example, to calculate p1, it is necessary to calculate s1G separately. 1,1 ,s2G 2,1 ,…,s 12 G 12,1 ,in The address of the control memory bank BANK12 is incremented by 1 in each clock cycle, and the s can be read out in sequence. 1,1 , s 1,2 …s 1,12 Perform calculations, and so on.

[0071] The operation module includes a circular shift unit, a binary field multiplication and addition unit, and a check bit solving unit. It determines the width of the circular shift according to the input expansion parameter z. The initial value of each circular shift register is g i,1 0 , g i,2 0 ,……,g i,12 0, the cyclic shift enable signal is used as a valid signal. When the cyclic shift enable signal parameter value is 1, the input G matrix generates the element g i,j Perform circular shift, right shift 1 bit in each clock cycle, and output the corresponding circular shift result data. The circular shift result of each clock cycle and the information bit s are sent to the multiplier of the binary domain multiplication and addition unit for binary domain multiplication calculation, and the result of the calculation is sent to the first adder for binary domain accumulation operation; first, s1G can be obtained. 1,1 , and then sent to the second adder of the check bit solution unit, and then s2G is obtained in one clock cycle. 2,1 , and s1G 1,1 Accumulate, and so on, and then get s after eleven clock cycles 12 G 12,1 , and the previous eleven results are accumulated to get p1, which is s1G 1,1 +s2G 2,1 +…+s 12 G 12,1 , and finally the check digit can be calculated.

[0072] Finally, the address generation module of the encoding controller generates the address of the result check bit and stores the calculation result data in the SRAM storage module.

[0073] Taking z = 96 and LDPC code length = 2304 as an example, the specific encoding step for the j-th segment test sequence is to encode the segmented information sequence s = [s1, s2, s3, ...s 12 ] is input to the parallel multiplication and accumulation module in a parallel manner, and multiplication of the GF(2) domain is performed to realize the AND operation and accumulation to realize the XOR operation.

[0074] Need to calculate According to the storage method of information bits and generator matrix, the information bit sequence s i The bit width is z, and 1 bit is taken out of s in each clock cycle. After 1 clock cycle After cyclic shift, we get conduct It is equivalent to performing multiplication in each clock cycle, producing a result, and adding the result to the previous sum to complete the pipeline multiplication and accumulation operation.

[0075] The multiplication and addition here are both binary domain calculations, addition is equivalent to XOR, and multiplication is equivalent to bitwise AND, so there is no need to use the PE's computing resources. i G i,j After the calculation is completed, according to p j =s1G 1,j +s2G 2,j +…+s 12 G12,j , and get p j , all twelve paths are calculated in the same way, and finally p check bits are obtained, and the encoding is completed.

[0076] In this embodiment, in the first 12 clock cycles of the calculation, g 1,j (0) , g 2,j (0) ,……g 12,j (0) Read it from the storage unit and store it in 12 circular shift registers. Taking z=96 as an example, the pre-stored value in the circular shift register is circularly shifted 96 times to obtain s1G 1,j (1≤i≤12), the encoding operation requires a total of 12+96=108 clock cycles. If the encoder operating frequency is set to 1 GHz and a fixed delay is added, the throughput can reach 8.5 Gbps.

[0077] In the traditional column-by-column calculation method, the matrix G is generated i,j The lth column can be written as v i,j (l-1) , the column data can be accessed through v i,j Shift down by l bits to get, p j,1 =s1v 1,j (0) +s2v 2,j (0) +…+s 12 v 12,j (0) , where s1v 1,j (0) ,s2v 2,j (0) ,……,s 12 v 12,j (0) Multiplication operations can be completed in parallel. At this time, parallel operations require special storage methods to access and calculate at the same time. Otherwise, they will still be operated in serial mode. Here is vector multiplication s1v 1,j (0) , requires z cycles, and since the results need to be accumulated, it takes 12 + 96 = 108 clock cycles to complete p j,1 Calculation. Loop 96 times and get p j A total of 96×108=10368 clock cycles are required. The calculation cycle is proportional to the square of the expansion parameter z. The calculation time is very long and is not suitable for application. The encoder throughput of the present invention is improved by nearly 100 times.

[0078] In summary, the present invention supports coding calculations with 1 / 2 code rate and 19 code lengths under the 802.16e communication protocol and has good compatibility. During operation, the present invention only stores the generators of the generator matrix, which simplifies the coding storage and transportation volume, reduces the hardware implementation complexity, and thus reduces the power consumption of the encoder. By i,j The information sequence s is stored in parallel, the parallelism of the algorithm is fully exploited, and by pre-reading the generator, the coding operation with high parallelism, high throughput and low hardware complexity can be finally achieved.

[0079] The above schematically describes the invention and its implementation methods. This description is non-restrictive. Although the invention has been represented and described with reference to specific preferred embodiments, it should not be interpreted as limiting the invention itself. Without departing from the spirit or basic characteristics of the invention, various changes can be made to it in form and detail. Without departing from the purpose of the invention, structural methods and embodiments similar to the technical solution are designed without creativity, which should all fall within the scope of protection of this application. The multiple elements stated in this application can also be implemented by one element through software or hardware. Words such as first and second are used to represent names and do not represent any specific order.

Claims

1. A QC-LDPC encoding method, characterized in that: Performing a circular shift on the input generator matrix generator, inputting the circular shift result and the information bit into the multiplier module for binary field multiplication calculation, accumulating the multiplication results in sequence through the first adder, and then accumulating the calculation results of the first adder through the second adder to obtain the check bit; The cyclic shift is controlled by an enable signal. When the enable signal is valid, the input generator is cyclically shifted, and the cyclic shift result is outputted at the same time. The information bit is divided into k equal-length bits. b parts, each part s i It consists of z consecutive information bits, k b , i, z are all positive integers, z represents the test matrix H b Extended to the extended parameters of the check matrix H, the basis check matrix H b The size is m b ×n b , the size of the check matrix H is recorded as m×n, m=m b z,n=n b z, m b 、n b are all positive integers; the information bit data is read by reading the address of the information bit storage unit, and the address of the information bit storage unit is controlled to increase by one bit per clock cycle, and each part of the information bit s is read out in turn. i ; The encoding method is specifically to encode the information sequence to obtain the check sequence. In the IEEE802.16e communication protocol, at a 1 / 2 code rate, n b =24, check digit m b =12, the length of the information bit sequence k b =12; the information bit s=(s1,s2,…,s 12×z ), check digit p j =(p j,1 ,p j,2 ,…,p j,z ), 1≤j≤12, z is the above-mentioned extended parameter; Divide the information sequence into k equal length b parts, k b =12, then the information bit s=(s1,s2,…,s 12 ), where the i-th part s i It is composed of z consecutive information bits. The information bit s is multiplied by the generator matrix G to obtain the encoded codeword C, that is, C=s×G=(s,p1,p2,…,p 12 ), where the jth check part contains z check bits, denoted as p j =(p j,1 ,p j,2 ,…,p j,z )=s1G 1,j +s2G 2,j +…+s 12 G 12,j ; The generator matrix has the following quasi-cyclic form: Where I is the z×z identity matrix, 0 is the z×z zero matrix, G i,j Is a z×z circulant matrix, generating matrix G qc The left part is k b ×z×k b ×z unit matrix, generating matrix G qc The right side is the P matrix that generates the check bit; let g i,j is the cyclic matrix G i,j The generator of G i,j The first line, g i,j Can represent G qc All loops G i,j , enter g i,j The generator matrix G can be constructed qc , when 0≤l≤x, let is the generator g i,j The result of a circular right shift of 1 bit, and Then we have: The generation method of the cyclic generator is as follows: let u = (1, 0, ..., 0), 0 = (0, 0, ..., 0), the length of each is z, for 1≤i≤12, then the matrix G is generated qc , the i-th line is: g i =(0,…,u,0…0,g i,1 ,g i,2 ,…,g i,12 ), where u is in g i The i-th part, the check matrix and the generator matrix satisfy so Find the check digit p j The process is to find s i G i,j The process of obtaining all the generators g according to the check matrix i,j , thus constructing the generator matrix G qc .

2. A QC-LDPC encoder, characterized in that Using the QC-LDPC encoding method according to claim 1, the encoder includes a calculation module, the calculation module is used to solve the encoded check bit; The operation module includes a cyclic shift unit, a binary domain multiplication and addition unit and a check bit solution unit. The cyclic shift unit is used to cyclically shift the generator and send the result of the cyclic right shift to the binary domain multiplication and addition unit. The binary domain multiplication and addition unit is used to perform binary domain multiplication and addition calculations on the cyclic shift result and the information bit. The check bit solution unit is used to implement the binary domain accumulation operation and calculate the check bit.

3. A QC-LDPC encoder according to claim 2, characterized in that The cyclic shift unit includes z-level cyclic shift subunits connected in series, each cyclic shift subunit includes a selector and a D flip-flop, the output end of the selector is connected to the input end of the D flip-flop, the output end of the D flip-flop is connected to the input end of the selector in the next-level subunit, the selector is also connected to the cyclic shift enable signal, and the D flip-flop is connected to the clock signal.

4. A QC-LDPC encoder according to claim 2, characterized in that The binary domain multiplication and addition unit includes z-stage parallel binary domain multiplication and addition sub-units, each of which includes an AND gate, an XOR gate, and a D flip-flop. The input end of the AND gate is connected to the cyclic shift result and the information bit value, the output end of the AND gate is connected to the input end of the XOR gate, the other input end of the XOR gate is connected to the output end of the D flip-flop, the output end of the XOR gate is connected to the input end of the D flip-flop, and the input end of the D flip-flop is also connected to a clock signal.

5. A QC-LDPC encoder according to claim 2, characterized in that: The check bit solution unit includes N levels of XOR gates. The input signal of the first-level XOR gate is the output signal of the binary domain multiplication and addition unit. The input signal of the first-level XOR gate is the input signal of the next-level XOR gate, realizing the accumulation calculation of the output signal of the binary domain multiplication and addition unit.

6. A QC-LDPC encoder according to claim 3, 4 or 5, characterized in that: It also includes a control module and a storage module. The control module is used to control the encoder to perform parallel encoding, and the storage module is used to store the generation matrix, information bits and operation results; the storage module includes a generation matrix storage unit, an information bit storage unit and an operation settlement storage unit, each storage unit includes several storage bodies, and the storage bodies are independent of each other.

7. A QC-LDPC encoder according to claim 6, characterized in that: The control module includes a computing enablement control module, an address generation module and a data distribution module.

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