Display device and method of driving the same

Abstract

The present invention relates to a display device and a method for driving the same. The display device includes a display panel, a drive circuit, and a power supply. The drive circuit is connected to a plurality of pixels of the display panel via a plurality of scan line groups and a plurality of data lines, provides a plurality of scan signals to the display panel, and provides data voltages to the plurality of data lines. The power supply applies one or more power supply voltages to the plurality of pixels. The drive circuit enables at least two of the plurality of scan signals during a non-emission interval so that the at least two scan signals partially overlap during at least two consecutive horizontal periods.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to a display device, and more particularly, to an organic light emitting diode (OLED) display device and a method of driving the OLED display device. Background Art

[0002] Various flat panel display devices with reduced weight and volume have been developed. OLED displays have advantages over other flat panel display devices due to their fast response speed and low power consumption. OLED displays use organic light-emitting diodes (OLEDs), which emit light based on the recombination of electrons and holes, to display images.

[0003] An OLED display device may include a display panel including a plurality of pixels arranged in a matrix format, and each of the pixels may include one or more transistors and an OLED element that emits light corresponding to an applied voltage.

[0004] Recently, OLED display devices are driven at a high frequency, which results in a reduction in scan-on time. The reduction in scan-on time may generate crosstalk and low-grayscale coloring, and may increase the occupied area of ​​the driving circuit. Summary of the Invention

[0005] Some example embodiments of the present disclosure provide a display device (eg, an OLED display device) capable of increasing a scan-on time and reducing an occupied area of ​​a driving circuit.

[0006] Some example embodiments of the present disclosure provide a method of operating a display device (eg, an OLED display device) capable of increasing a scan-on time and reducing an occupied area of ​​a driving circuit.

[0007] According to one exemplary embodiment, a display device includes a display panel, a drive circuit, and a power supply. The drive circuit is connected to a plurality of pixels of the display panel via a plurality of scan line groups and a plurality of data lines, and is configured to provide a plurality of scan signals to the display panel and to provide data voltages to the plurality of data lines. The power supply is configured to apply one or more power supply voltages to the plurality of pixels. The drive circuit is configured to enable at least two of the plurality of scan signals during a non-emission interval so that the at least two scan signals partially overlap during at least two consecutive horizontal periods. The horizontal period corresponds to a period during which the drive circuit provides a data voltage to a pixel row of the plurality of pixels.

[0008] In an example embodiment, the driving circuit may include a scan driver, a data driver, an emission driver, and a timing controller. The scan driver may provide a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to each of a plurality of pixel rows. The data driver may provide a data voltage corresponding to the data signal to a plurality of data lines connected to the plurality of pixels. The emission driver may provide a plurality of emission control signals to a plurality of emission control lines connected to the plurality of pixels. The timing controller may control the scan driver, the data driver, the emission driver, and the power supply. The timing controller may generate the data signal based on input image data.

[0009] In an example embodiment, the one or more power supply voltages may include a low power supply voltage, a high power supply voltage, a first initialization voltage, a second initialization voltage, and a bias voltage. Each scan line group in the plurality of scan line groups may include a first scan line, a second scan line, a third scan line, and a fourth scan line. Each pixel in the plurality of pixels may include: a switching transistor having a first electrode coupled to a data line in the plurality of data lines, a gate coupled to the second scan line, and a second electrode coupled to a first node; a storage capacitor having a first terminal receiving the high power supply voltage and a second terminal coupled to a second node; a driving transistor having a first electrode coupled to the first node, a gate coupled to the second node, and a second electrode coupled to a third node; a compensation transistor having a first electrode coupled to the second node, a gate coupled to the third scan line, and a second electrode coupled to the third node; a first initialization transistor having a first electrode coupled to the second node, a gate coupled to the first scan line, and a second electrode receiving the first initialization voltage; A first emission transistor has a first electrode receiving a high power supply voltage, a gate receiving an emission control signal from among a plurality of emission control signals, and a second electrode coupled to the first node; a second emission transistor has a first electrode coupled to a third node, a gate receiving an emission control signal from among a plurality of emission control signals, and a second electrode coupled to a fourth node; a second initialization transistor has a first electrode coupled to the fourth node, a gate coupled to a fourth scan line, and a second electrode receiving a second initialization voltage; a bias transistor has a first electrode coupled to the third node, a gate coupled to the fourth scan line, and a second electrode receiving a bias voltage; and a light-emitting element has an anode coupled to the fourth node and a cathode receiving a low power supply voltage.

[0010] In one embodiment, the emission driver may disable the emission control signal at a logic high level during a non-emission interval. The non-emission interval may include consecutive horizontal periods, the consecutive horizontal periods including the first horizontal period to the sixth horizontal period. The scan driver may include a first scan driver that generates a first scan signal, a second scan signal, and a third scan signal, and a second scan driver that generates a fourth scan signal. For the kth pixel row in the pixel rows, the scan driver may enable the fourth scan signal during the second horizontal period, enable the first scan signal during the third horizontal period, enable the second scan signal during the fourth horizontal period and the fifth horizontal period, and enable the third scan signal during the fifth horizontal period and the sixth horizontal period. Here, k may be a natural number.

[0011] The scan driver may use the third scan signal for the k-th pixel row as the second scan signal for the (k+1)-th pixel row among the pixel rows.

[0012] The second initialization transistor can transmit a second initialization voltage to the anode of the light emitting element in response to a fourth scan signal received through the fourth scan line. The bias transistor can transmit a bias voltage to the second electrode of the driving transistor in response to a fourth scan signal received through the fourth scan line.

[0013] In one embodiment, the emission driver may disable the emission control signal at a logic high level during a non-emission interval. The non-emission interval may include consecutive horizontal periods, the consecutive horizontal periods including the first horizontal period to the sixth horizontal period. The scan driver may include a first scan driver that generates a first scan signal, a second scan signal, and a third scan signal, and a second scan driver that generates a fourth scan signal. For the kth pixel row in the pixel rows, the scan driver may enable the first scan signal during the second horizontal period, the second scan signal during the third and fourth horizontal periods, the third scan signal during the fourth and fifth horizontal periods, and the fourth scan signal during the sixth horizontal period. Here, k may be a natural number.

[0014] The scan driver may use the third scan signal for the k-th pixel row as the second scan signal for the (k+1)-th pixel row among the pixel rows.

[0015] In one embodiment, the emission driver may disable the emission control signal at a logic high level during a non-emission interval. The non-emission interval may include consecutive horizontal periods, the consecutive horizontal periods including the first horizontal period to the sixth horizontal period. The scan driver may include a first scan driver that generates a first scan signal, a second scan signal, and a third scan signal, and a second scan driver that generates a fourth scan signal. For the kth pixel row in the pixel rows, the scan driver may enable the first scan signal during the second horizontal period and the third horizontal period, the second scan signal during the third horizontal period and the fourth horizontal period, the third scan signal during the fourth horizontal period and the fifth horizontal period, and the fourth scan signal during the sixth horizontal period. Here, k may be a natural number.

[0016] In one embodiment, the emission driver may disable the emission control signal at a logic high level during a non-emission interval. The non-emission interval may include consecutive horizontal periods, the consecutive horizontal periods including the first horizontal period to the seventh horizontal period. The scan driver may generate a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal. For the kth pixel row in the pixel rows, the scan driver may enable the first scan signal during the second horizontal period, the second scan signal during the third and fourth horizontal periods, the third scan signal during the fourth and fifth horizontal periods, and the fourth scan signal during the sixth and seventh horizontal periods. Here, k may be a natural number.

[0017] The scan driver may use the third scan signal for the k-th pixel row as the second scan signal for the (k+1)-th pixel row among the pixel rows.

[0018] In one embodiment, the emission driver may disable the emission control signal at a logic high level during a non-emission interval. The non-emission interval may include consecutive horizontal periods, the consecutive horizontal periods including the first horizontal period to the seventh horizontal period. The scan driver may generate a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal. For the kth pixel row in the pixel rows, the scan driver may enable the fourth scan signal during the second horizontal period and the third horizontal period, may enable the first scan signal during the fourth horizontal period, may enable the second scan signal during the fifth horizontal period and the sixth horizontal period, and may enable the third scan signal during the sixth horizontal period and the seventh horizontal period. Here, k may be a natural number.

[0019] The scan driver may use the third scan signal for the k-th pixel row as the second scan signal for the (k+1)-th pixel row among the pixel rows.

[0020] In an example embodiment, the one or more power supply voltages may include a low power supply voltage, a high power supply voltage, a first initialization voltage, a second initialization voltage, and a bias voltage. Each scan line group in the plurality of scan line groups may include a first scan line, a second scan line, a third scan line, and a fourth scan line. Each pixel in the plurality of pixels may include: a switching transistor having a first electrode coupled to a data line in the plurality of data lines, a gate coupled to the second scan line, and a second electrode coupled to a first node; a storage capacitor having a first terminal receiving the high power supply voltage and a second terminal coupled to a second node; a driving transistor having a first electrode coupled to the first node, a gate coupled to the second node, and a second electrode coupled to a third node; a compensation transistor having a first electrode coupled to the second node, a gate coupled to the third scan line, and a second electrode coupled to the third node; a first initialization transistor having a first electrode coupled to the second node, a gate coupled to the first scan line, and a second electrode receiving the first initialization voltage; A first emission transistor has a first electrode receiving a high power supply voltage, a gate receiving an emission control signal from among a plurality of emission control signals, and a second electrode coupled to the first node; a second emission transistor has a first electrode coupled to the third node, a gate receiving an emission control signal from among a plurality of emission control signals, and a second electrode coupled to the fourth node; a second initialization transistor has a first electrode coupled to the fourth node, a gate coupled to the fourth scan line, and a second electrode receiving a second initialization voltage; a bias transistor has a first electrode coupled to the first node, a gate coupled to the fourth scan line, and a second electrode receiving a bias voltage; and a light-emitting element has an anode coupled to the fourth node and a cathode receiving a low power supply voltage.

[0021] The second initialization transistor can transmit a second initialization voltage to the anode of the light emitting element in response to a fourth scan signal received through the fourth scan line. The bias transistor can transmit a bias voltage to the first electrode of the driving transistor in response to a fourth scan signal received through the fourth scan line.

[0022] In example embodiments, a level of the first initialization voltage may be greater than a level of the second initialization voltage.

[0023] In example embodiments, the power supply may change the level of the second initialization voltage and the level of the bias voltage based on a frame rate of an image displayed in the display panel.

[0024] According to one exemplary embodiment, a method for driving a display device includes: outputting data voltages to a plurality of pixels of a display panel via a data driver connected to the display panel via a plurality of data lines; and sequentially outputting a plurality of scan signals to the plurality of pixels via a scan driver connected to the display panel via a plurality of scan line groups. The scan driver enables at least two of the plurality of scan signals during a non-emission interval so that the at least two scan signals partially overlap during at least two consecutive horizontal periods. A horizontal period corresponds to a period during which a driving circuit supplies data voltages to a pixel row of the plurality of pixels.

[0025] In an example embodiment, each of the plurality of scan line groups may include a first scan line, a second scan line, a third scan line, and a fourth scan line. Each of the plurality of pixels may include: a switching transistor having a first electrode coupled to a data line of the plurality of data lines, a gate coupled to the second scan line, and a second electrode coupled to the first node; a storage capacitor having a first terminal receiving a high power supply voltage and a second terminal coupled to the second node; a driving transistor having a first electrode coupled to the first node, a gate coupled to the second node, and a second electrode coupled to the third node; a compensation transistor having a first electrode coupled to the second node, a gate coupled to the third scan line, and a second electrode coupled to the third node; a first initialization transistor having a first electrode coupled to the second node, a gate coupled to the first scan line, and a second electrode receiving the first initialization voltage; a second electrode receiving an initialization voltage; a first emission transistor having a first electrode receiving a high power supply voltage, a gate receiving an emission control signal, and a second electrode coupled to the first node; a second emission transistor having a first electrode coupled to the third node, a gate receiving the emission control signal, and a second electrode coupled to the fourth node; a second initialization transistor having a first electrode coupled to the fourth node, a gate coupled to the fourth scan line, and a second electrode receiving a second initialization voltage; a bias transistor having a first electrode coupled to the third node, a gate coupled to the fourth scan line, and a second electrode receiving a bias voltage; and a light-emitting element having an anode coupled to the fourth node and a cathode receiving a low power supply voltage.

[0026] In one embodiment, the emission control signal can be disabled at a logic high level during a non-emission interval. The non-emission interval can include a continuous horizontal period, the continuous horizontal period including a first horizontal period to a sixth horizontal period. The scan driver can include a first scan driver that generates a first scan signal, a second scan signal, and a third scan signal, and a second scan driver that generates a fourth scan signal. For the kth pixel row in the pixel rows, the scan driver can enable the fourth scan signal during the second horizontal period, enable the first scan signal during the third horizontal period, enable the second scan signal during the fourth horizontal period and the fifth horizontal period, and enable the third scan signal during the fifth horizontal period and the sixth horizontal period. Here, k can be a natural number.

[0027] Therefore, a scan driver of a display device (e.g., an OLED display device) can enable at least two scan signals among a plurality of scan signals during a non-luminous interval in which a pixel does not emit light, so that the at least two scan signals partially overlap during at least two consecutive horizontal periods, thereby increasing the scan-on time. Therefore, when the display device is driven at a high frequency, the scan driver can reduce crosstalk and low grayscale staining. In addition, a circuit for generating a scan signal can be manufactured by merging some of the circuits for generating the scan signal, and thus the area occupied by the scan driver can be reduced, thereby reducing the dead space of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative and non-limiting example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a block diagram illustrating an organic light emitting diode (OLED) display device according to example embodiments.

[0030] Figure 2 According to an example embodiment Figure 1 A plan view of an OLED display device.

[0031] Figure 3 The diagram includes Figure 1 A diagram illustrating the electrical connections of pixels in an OLED display device.

[0032] Figure 4 According to an example embodiment Figure 3 A circuit diagram of an example of a pixel.

[0033] Figure 5 is a diagram illustrating a method according to an example embodiment Figure 3 A circuit diagram of another example of a pixel.

[0034] Figure 6 It is an icon Figure 1 Block diagram of a timing controller in an OLED display device.

[0035] Figure 7 is a diagram illustrating a method according to an example embodiment Figure 1 FIG. 1 is a block diagram of an example of a scan driver in an OLED display device.

[0036] Figure 8 It is an icon Figure 7 Scan driver and Figure 1 Block diagram of the transmit driver in .

[0037] Figure 9 、 Figure 10 and Figure 11 According to an example embodiment Figure 7 Timing diagram of the scan driver in .

[0038] Figure 12 is a diagram illustrating a method according to an example embodiment Figure 1 FIG. 1 is a block diagram of an example of a scan driver in an OLED display device.

[0039] Figure 13 It is an icon Figure 12 Scan driver and Figure 1 Block diagram of the transmit driver in .

[0040] Figure 14 and Figure 15 Diagrams Figure 12 The scan driver in drives the scan lines.

[0041] Figure 16 is a diagram illustrating a method according to an example embodiment Figure 1 A block diagram of an emission driver for an OLED display device is shown in FIG.

[0042] Figure 17 is a flowchart illustrating a method of driving an OLED display device according to example embodiments.

[0043] Figure 18 is a block diagram illustrating a display system according to example embodiments.

[0044] Figure 19 is a block diagram illustrating an electronic device including an OLED display device according to example embodiments. DETAILED DESCRIPTION

[0045] Example embodiments of the present disclosure are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concepts of the present disclosure may be embodied in many different forms and configurations and should not be construed as limited to the example embodiments set forth herein.

[0046] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intermediate elements or layers may be present between the element or layer and the other element or layer. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there may be no intermediate elements or layers between the element and the other element or layer. Identical or similar reference numerals refer to identical or similar elements throughout this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0047] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, patterns and / or sections, these elements, components, regions, layers, patterns and / or sections should not be limited by these terms.

[0048] The terms used herein are for the purpose of describing specific example embodiments only and are not intended to limit the present disclosure. As used herein, singular forms such as "a," "an," and "the" are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used in the present disclosure, the terms "include" and / or "comprise" specify the presence of stated features, wholes, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or combinations thereof.

[0049] Example embodiments are described herein with reference to schematic illustrations of idealized example embodiments (and intermediate structures) of the present inventive concepts. Thus, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances can be anticipated. Therefore, the example embodiments should not be construed as limited to the specific shapes of the regions illustrated herein, but rather should include deviations in shape that are anticipated, for example, as a result of manufacturing. The regions illustrated in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present inventive concepts.

[0050] Unless otherwise defined or explicitly stated, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0051] Hereinafter, example embodiments of the present disclosure will be described more fully with reference to the accompanying drawings.The same or similar reference numerals refer to the same or similar elements throughout this disclosure.

[0052] Figure 1 is a block diagram illustrating an organic light emitting diode (OLED) display device according to an example embodiment. Although an OLED display device is described herein, it should be understood that the present disclosure is not limited thereto. For example, various other display devices such as, but not limited to, quantum dot display devices, liquid crystal display (LCD) devices, and micro light emitting diode (LED) display devices may be included.

[0053] refer to Figure 1 , the OLED display device 100 may include a driving circuit 105 , a display panel 110 and a power supply 180 .

[0054] The driving circuit 105 may include a timing controller 130, a data driver 150, a scan driver 200, and an emission driver 300. The timing controller 130, the data driver 150, the scan driver 200, and the emission driver 300 may be coupled to the display panel 110 in the form of a chip-on-flex (COF) printed circuit, a chip-on-glass (COG), a flexible printed circuit board (FPC), or the like.

[0055] The display panel 110 may be coupled to the scan driver 200 of the driving circuit 105 via a plurality of scan line groups SLS1 to SLSn (n is an integer), may be coupled to the data driver 150 via a plurality of data lines DL1 to DLm (m is an integer), and may be coupled to the emission driver 300 of the driving circuit 105 via a plurality of emission control lines EL1 to ELn. The display panel 110 may include a plurality of pixels (PX) 111, and each pixel 111 is provided at an intersection of each scan line group of the scan line groups SLS1 to SLSn, each data line of the data lines DL1 to DLm, and each emission control line of the emission control lines EL1 to ELn.

[0056] The power supply 180 may provide a high power voltage ELVDD, a low power voltage ELVSS, a first initialization voltage VINT, a second initialization voltage AINT, and a bias voltage Vb to the display panel 110. The power supply 180 may provide a first voltage VGH and a second voltage VGL to the emission driver 300 and the scan driver 200.

[0057] The scan driver 200 may apply a plurality of scan signals to each of the pixels 111 through the first and second scan lines based on the second drive control signal DCTL2. The scan driver 200 may enable at least two of the plurality of scan signals during a non-emission interval in which the pixel 111 does not emit light, such that the at least two scan signals partially overlap during two consecutive horizontal periods. A horizontal period corresponds to a period in which the drive circuit 105 supplies a data voltage to one pixel row of the pixels 111.

[0058] The data driver 150 may apply a data voltage to each of the pixels 111 through the plurality of data lines DL1 to DLm based on the first driving control signal DCTL1 .

[0059] The emission driver 300 may apply an emission control signal to each of the pixels 111 through the plurality of emission control lines EL1 to ELn based on the third driving control signal DCTL3. The brightness of the display panel 110 may be adjusted based on the emission control signal.

[0060] The power supply 180 can provide the high power voltage ELVDD, the low power voltage ELVSS, the first initialization voltage VINT, the second initialization voltage AINT and the bias voltage Vb to the display panel 110 in response to the power control signal PCTL, and can further provide the first voltage VGH and the second voltage VGL to the emission driver 300 and the scan driver 200.

[0061] The power supply 180 may change the levels of the second initialization voltage AINT and the bias voltage Vb based on the power control signal PCTL indicating a frame rate of an image displayed by the display panel 110 .

[0062] The timing controller 130 may receive input image data RGB and a control signal CTL, and may generate a first drive control signal DCTL1, a second drive control signal DCTL2, and a third drive control signal DCTL3, as well as a power control signal PCTL based on the control signal CTL. The timing controller 130 may provide the first drive control signal DCTL1 to the data driver 150, the second drive control signal DCTL2 to the scan driver 200, the third drive control signal DCTL3 to the emission driver 300, and the power control signal PCTL to the power supply 180. The timing controller 130 may receive input image data RGB and arrange the input image data RGB to provide the data signal DTA to the data driver 150.

[0063] Figure 2 According to an example embodiment Figure 11 is a plan view of an OLED display device 100.

[0064] refer to Figure 2 , the OLED display device 100 includes a substrate 10. The substrate 10 may include a display area DA and a peripheral area PA outside the display area DA.

[0065] A plurality of pixels 111 may be arranged in the display area DA of the substrate 10. Various wirings for transmitting electrical signals to the driving circuit 105 and the display area DA may be arranged in the peripheral area PA of the substrate 10.

[0066] Figure 3 The diagram shows the Figure 1 FIG. 1 is an electrical connection diagram illustrating a pixel 111 in the OLED display device 100 .

[0067] Figure 4 According to an example embodiment Figure 3 1 is a circuit diagram of an example of a pixel 111.

[0068] exist Figure 3 , the pixel 111 is coupled to a first scan line group SLS1, a first data line DL1, and a first emission control line EL1. The first scan line group SLS1 includes a first scan line SL11, a second scan line SL21, a third scan line SL31, and a fourth scan line SL41.

[0069] refer to Figure 4 , the pixel 111a may include a pixel circuit 112a and an OLED 112. The pixel circuit 112a may include a switching transistor T1, a driving transistor T2, a compensation transistor T3, a first initialization transistor T4, a second initialization transistor T7, a first emission transistor T5, a second emission transistor T6, a bias transistor T81, and a storage capacitor CST. Each of the switching transistor T1, the driving transistor T2, the compensation transistor T3, the first initialization transistor T4, the second initialization transistor T7, the first emission transistor T5, the second emission transistor T6, and the bias transistor T81 may be a p-type metal oxide semiconductor (PMOS) transistor. However, the present disclosure is not limited thereto. For example, without departing from the scope of the present disclosure, all or some of the transistors T1 to T81 may be n-type metal oxide semiconductor (NMOS) transistors.

[0070] The switching transistor T1 may have a first electrode coupled to the data line DL1 to receive the data voltage SDT, a gate electrode coupled to the second scan line SL21 to receive the second scan signal GW1, and a second electrode coupled to the first node N11. The driving transistor T2 may have a first electrode coupled to the first node N11, a gate electrode coupled to the second node N12, and a second electrode coupled to the third node N13.

[0071] The compensation transistor T3 may have a gate electrode coupled to the third scan line SL31 to receive the third scan signal GC1, a first electrode coupled to the second node N12, and a second electrode coupled to the third node N13. The first initialization transistor T4 may have a gate electrode coupled to the first scan line SL11 to receive the first scan signal GI1, a first electrode coupled to the second node N12, and a second electrode receiving the first initialization voltage VINT.

[0072] The first emission transistor T5 may have a first electrode receiving the high power supply voltage ELVDD, a second electrode coupled to the first node N11, and a gate electrode coupled to the first emission control line EL1 to receive the first emission control signal EC1. The second emission transistor T6 may have a first electrode coupled to the third node N13, a second electrode coupled to the fourth node N14, and a gate electrode coupled to the first emission control line EL1 to receive the first emission control signal EC1.

[0073] The second initialization transistor T7 may have a gate electrode coupled to the fourth scan line SL41 to receive the fourth scan signal GB1, a first electrode coupled to the fourth node N14, and a second electrode receiving the second initialization voltage AINT. The bias transistor T81 may have a first electrode coupled to the third node N13, a second electrode receiving the bias voltage Vb, and a gate electrode coupled to the fourth scan line SL41 to receive the fourth scan signal GB1.

[0074] The storage capacitor CST may have a first terminal receiving the high power voltage ELVDD and a second terminal coupled to the second node N12. The OLED 112 may have an anode coupled to the fourth node N14 and a cathode receiving the low power voltage ELVSS.

[0075] The switching transistor T1 transfers the data voltage SDT to the first node N11 in response to the second scan signal GW1 , and the OLED 112 may emit light in response to the data voltage SDT stored in the storage capacitor CST to display an image.

[0076] The first emission transistor T5 and the second emission transistor T6 are turned on or off in response to the first emission control signal EC1 to supply current to the OLED 112 or intercept current from the OLED 112. When intercepting current from the OLED 112, the OLED 112 does not emit. Therefore, the first emission transistor T5 and the second emission transistor T6 are turned on or off in response to the first emission control signal EC1 to adjust the brightness of the pixel 111a.

[0077] The compensation transistor T3 can connect the second node N12 to the third node N13 in response to the third scan signal GC1. That is, the compensation transistor T3 can compensate for the variation in the threshold voltage of the driving transistor T2 of the pixel 111a by diode-connecting the gate electrode and the second electrode of the driving transistor T2.

[0078] The first initialization transistor T4 may transmit a first initialization voltage VINT to the second node N12 in response to the first scan signal GI1. The first initialization transistor T4 may initialize the data voltage SDT transmitted to the driving transistor T2 during the previous frame by transmitting the first initialization voltage VINT to the gate electrode of the driving transistor T2.

[0079] The second initialization transistor T7 can transmit the second initialization voltage AINT to the fourth node N14 in response to the fourth scan signal GB1 to release the parasitic capacitance between the second emission transistor T6 and the OLED 112. The bias transistor T81 can connect the third node N31 to the bias voltage Vb in response to the fourth scan signal GB1 to apply a conductive bias stress to the second electrode of the driving transistor T2. The bias transistor T81 can compensate for the hysteresis characteristics of the driving transistor T2.

[0080] In some embodiments, the second initialization transistor T7 may connect the fourth node N14 to the first initialization voltage VINT instead of the second initialization voltage AINT in response to the first scan signal GI1 to release the parasitic capacitance between the second emission transistor T6 and the OLED 112. The first scan signal GI1 may be applied to the gate electrode of the second initialization transistor T7 instead of the fourth scan signal GB1.

[0081] Figure 5 is a diagram illustrating a method according to an example embodiment Figure 3 1 is a circuit diagram of another example of the pixel 111.

[0082] refer to Figure 5, the pixel 111b may include a pixel circuit 112b and an OLED 112. The pixel circuit 112b may include a switching transistor T1, a driving transistor T2, a compensation transistor T3, a first initialization transistor T4, a second initialization transistor T7, a first emission transistor T5, a second emission transistor T6, a bias transistor T82, and a storage capacitor CST. The pixel circuit 112b and Figure 4 The pixel circuit 112a of FIG. 1 is different in that a bias transistor T82 (e.g., a PMOS transistor) has a first electrode coupled to the first node N11, a second electrode receiving a bias voltage Vb, and a gate electrode coupled to the fourth scan line SL41 to receive a fourth scan signal GB1. The bias transistor T82 can connect the first node N11 to the bias voltage Vb in response to the fourth scan signal GB1 to apply a conductive bias stress to the first electrode of the drive transistor T2. The bias transistor T82 can compensate for the hysteresis characteristics of the drive transistor T2.

[0083] Figure 6 It is an icon Figure 1 FIG. 1 is a block diagram of a timing controller 130 in an OLED display device 100 .

[0084] refer to Figure 6 , the timing controller 130 may include a data analyzer 132 , a data arranger 133 , and a signal generator 134 .

[0085] The data analyzer 132 generates an arrangement control signal ARC and a scan control signal SCC based on the input image data RGB and the scan driver configuration information SCFI. The data analyzer 132 may provide the arrangement control signal ARC to the data arranger 133 and provide the scan control signal SCC to the signal generator 134. The data analyzer 132 may analyze the grayscale of the input image data RGB of each data line to generate the arrangement control signal ARC, and may generate the scan control signal SCC based on the scan driver configuration information SCFI including the configuration information of the scan driver 200. The scan driver configuration information SCFI may include information about the number of scan drivers (e.g., one, two) included in the scan driver 200. Reference Figure 1 , the scan driver configuration information SCFI may be included in the control signal CTL.

[0086] The data arranger 133 arranges or rearranges the input image data RGB according to the arrangement control signal ARC and outputs a data signal DTA.

[0087] The signal generator 134 can generate a first drive control signal DCTL1 for controlling the data driver 150, a second drive control signal DCTL2 for controlling the scan driver 200, and a third drive control signal DCTL3 for controlling the emission driver 300 based on the control signal CTL and the scan control signal SCC. The signal generator 134 can also generate a power control signal PCTL for controlling the power supply 180 in response to the control signal CTL. The second drive control signal DCTL2 can include a start signal FLM (frame line marker), an initialization signal INT, an output enable signal OE, and a mode signal MS associated with a scan mode. The third drive control signal DCTL3 can include a start signal FLM, a clock signal CLK, and a mode signal MS.

[0088] Figure 7 is a diagram illustrating a method according to an example embodiment Figure 1 FIG. 1 is a block diagram of an example of a scan driver 200 in the OLED display device 100 .

[0089] refer to Figure 7 , the scan driver 200 a may include a first scan driver 210 and a second scan driver 230 .

[0090] The first scan driver 210 may receive an initialization signal INT, a start signal FLM, a first voltage VGH, a second voltage VGL, an output enable signal OE, and a mode signal MS, and may generate a first scan signal GI (e.g., Figure 4 The first scanning signal GI1), the second scanning signal GW (for example, Figure 4 The second scanning signal GW1) and the third scanning signal GC (eg, Figure 4 The first scan signal GI, the second scan signal GW, and the third scan signal GC1 can be generated, and the scan-on time of each of the first scan signal GI, the second scan signal GW, and the third scan signal GC can be determined. The second scan driver 230 can receive the initialization signal INT, the start signal FLM, the first voltage VGH, the second voltage VGL, the output enable signal OE, and the mode signal MS, and can generate the fourth scan signal GB based on the initialization signal INT, the start signal FLM, the first voltage VGH, the second voltage VGL, the output enable signal OE, and the mode signal MS, and can determine the scan-on time of the fourth scan signal GB.

[0091] Figure 8 It is an icon Figure 7 The scan driver 200a and Figure 1 1 is a block diagram of the transmit driver 300 in FIG.

[0092] For ease of explanation, Figure 8 Some of the plurality of stages in the first and second scan drivers 210 and 230 and some of the plurality of stages in the emission driver 300 are shown.

[0093] refer to Figure 8 , the first scan driver 210 may include stages STG1_k, STG1_(k+1), and STG1_(k+2), the second scan driver 230 may include stages STG2_k, STG2_(k+1), and STG2_(k+2), and the emission driver 300 may include stages STG3_k, STG3_(k+1), and STG3_(k+2). Here, k is a natural number and may be one of 1 to n.

[0094] Each of the stages STG2_k, STG2_(k+1), and STG2_(k+2) in the second scan driver 230 may generate the same Figure 1 The fourth scan signals GB(k), GB(k+1), and GB(k+2) associated with the corresponding pixel row of the pixels 111 in the emission driver 300 may be generated by each of the stages STG3_k, STG3_(k+1), and STG3_(k+2). Figure 1 A corresponding one of the emission control signals EM(k), EM(k+1) and EM(k+2) associated with the corresponding pixel row of pixels 111 in FIG.

[0095] The stage STG1_k in the first scan driver 210 can generate a first scan signal GI(k+1) associated with the k+1-th pixel row, a second scan signal GW(k) associated with the k-th pixel row, and a third scan signal GC(k) associated with the k-th pixel row. The stage STG1_(k+1) in the first scan driver 210 can generate a first scan signal GI(k+2) associated with the k+2-th pixel row, a second scan signal GW(k+1) associated with the k+1-th pixel row, and a third scan signal GC(k+1) associated with the k+1-th pixel row. The stage STG1_(k+2) in the first scan driver 210 can generate a first scan signal GI(k+3) associated with the k+3-th pixel row, a second scan signal GW(k+2) associated with the k+2-th pixel row, and a third scan signal GC(k+2) associated with the k+2-th pixel row.

[0096] The first scan driver 210 may combine circuits associated with the second scan signal GW and the third scan signal GC, or may combine circuits associated with the first scan signal GI, the second scan signal GW, and the third scan signal GC. Therefore, the occupied area of ​​the first scan driver 210 may be reduced.

[0097] exist Figure 8 , R, G, and B represent pixels displaying corresponding colors of red, green, and blue, respectively.

[0098] Figures 9 to 11 According to an example embodiment Figure 7 1 is a timing diagram of the scan driver 200a in FIG.

[0099] exist Figures 9 to 11 In FIG, for the convenience of explanation, the emission control signal EM(k) is also shown.

[0100] exist Figures 9 to 11 In the embodiment of the present invention, the emission driver 300 may disable the emission control signal EM(k) at a logic high level during the non-emission interval. The non-emission interval may include the consecutive first to sixth horizontal periods t11 to t16, t21 to t26, and t31 to t36, and each of the consecutive first to sixth horizontal periods t11 to t16, t21 to t26, and t31 to t36 may correspond to one horizontal period 1H. The emission driver 300 may apply the emission control signal EM(k) to the first emission transistor T5 and the second emission transistor T6 in the k-th pixel row. The scan driver 200a may apply the first scan signal GI(k) to the first initialization transistor T4 in the k-th pixel row, the second scan signal GW(k) to the switching transistor T1 in the k-th pixel row, the third scan signal GC(k) to the compensation transistor T3 in the k-th pixel row, and the fourth scan signal GB(k) to the second initialization transistor T7 and the bias transistor T81 or T82 in the k-th pixel row. The scan driver 200 a may enable the first, second, third, and fourth scan signals GI(k), GW(k), GC(k), and GB(k) at a logic low level.

[0101] refer to Figure 9, the scan driver 200a can enable the fourth scan signal GB(k) during the second horizontal period t12, can enable the first scan signal GI(k) during the third horizontal period t13, can enable the second scan signal GW(k) during the fourth horizontal period t14 and the fifth horizontal period t15, and can enable the third scan signal GC(k) during the fifth horizontal period t15 and the sixth horizontal period t16. The activation of the second scan signal GW(k) and the third scan signal GC(k) partially overlaps during the fifth horizontal period t15, and the second scan signal GW(k) and the third scan signal GC(k) are enabled during two consecutive horizontal periods. Therefore, the scan driver 200a can increase the scan-on time of the second scan signal GW(k) and the third scan signal GC(k) to reduce crosstalk and low grayscale staining. In addition, the scan driver 200a can use the third scan signal GC(k) for the k-th pixel row as the second scan signal GW(k+1) for the k+1-th pixel row.

[0102] Because the second scan signal GW(k) and the third scan signal GC(k) are driven during two consecutive horizontal periods, the data voltage SDT can be sufficiently stored in the storage capacitor CST based on the second scan signal GW(k), and the variation in the threshold voltage of the driving transistor T2 can be sufficiently compensated based on the third scan signal GC(k).

[0103] refer to Figure 10 , the scan driver 200a may enable the first scan signal GI(k) during the second horizontal period t22, may enable the second scan signal GW(k) during the third horizontal period t23 and the fourth horizontal period t24, may enable the third scan signal GC(k) during the fourth horizontal period t24 and the fifth horizontal period t25, and may enable the fourth scan signal GB(k) during the sixth horizontal period t26. The activation of the second scan signal GW(k) and the third scan signal GC(k) partially overlaps during the fourth horizontal period t24, and the second scan signal GW(k) and the third scan signal GC(k) are enabled in two consecutive horizontal periods. Therefore, the scan driver 200a can increase the scan-on time of the second scan signal GW(k) and the third scan signal GC(k) to reduce crosstalk and low-grayscale staining.

[0104] refer to Figure 11, the scan driver 200a may enable the first scan signal GI(k) during the second horizontal period t32 and the third horizontal period t33, may enable the second scan signal GW(k) during the third horizontal period t33 and the fourth horizontal period t34, may enable the third scan signal GC(k) during the fourth horizontal period t34 and the fifth horizontal period t35, and may enable the fourth scan signal GB(k) during the sixth horizontal period t36. The activation of the first scan signal GI(k) and the second scan signal GW(k) partially overlaps during the third horizontal period t33, and the first scan signal GI(k) and the second scan signal GW(k) are enabled in two consecutive horizontal periods. The activation of the second scan signal GW(k) and the third scan signal GC(k) partially overlaps during the fourth horizontal period t34, and the second scan signal GW(k) and the third scan signal GC(k) are enabled in two consecutive horizontal periods. Therefore, the scan driver 200a may increase the scan-on time of the first scan signal GI(k), the second scan signal GW(k), and the third scan signal GC(k) to reduce crosstalk and low grayscale staining.

[0105] Figure 12 is a diagram illustrating a method according to an example embodiment Figure 1 FIG. 1 is a block diagram of an example of a scan driver 200 in the OLED display device 100 .

[0106] refer to Figure 12 , the scan driver 200 b may include a scan driver 250 .

[0107] The scan driver 250 can receive an initialization signal INT, a start signal FLM, a first voltage VGH, a second voltage VGL, an output enable signal OE and a mode signal MS, and can generate a first scan signal GI, a second scan signal GW, a third scan signal GC and a fourth scan signal GB based on the initialization signal INT, the start signal FLM, the first voltage VGH, the second voltage VGL, the output enable signal OE and the mode signal MS, and can determine a scan-on time of each of the first scan signal GI, the second scan signal GW, the third scan signal GC and the fourth scan signal GB.

[0108] Figure 13 It is an icon Figure 12 The scan driver 200b and Figure 1 1 is a block diagram of the transmit driver 300 in FIG.

[0109] For ease of explanation, Figure 13 Some of the multiple stages in the scan driver 250 and Figure 1 Some of the multiple stages in the emission driver 300 in FIG. Figure 8The stages STG3_k, STG3_(k+1), and STG3_(k+2) in the emission driver 300 are described, and thus descriptions of the stages STG3_k, STG3_(k+1), and STG3_(k+2) in the emission driver 300 will be omitted.

[0110] refer to Figure 13 , the scan driver 250 may include stages STG4_k, STG4_(k+1), and STG4_(k+2). The stage STG4_k in the scan driver 250 may generate a first scan signal GI(k+1) associated with the k+1-th pixel row, a second scan signal GW(k) associated with the k-th pixel row, a third scan signal GC(k) associated with the k-th pixel row, and a fourth scan signal GB(k) associated with the k-th pixel row. The stage STG4_(k+1) in the scan driver 250 may generate a first scan signal GI(k+2) associated with the k+2-th pixel row, a second scan signal GW(k+1) associated with the k+1-th pixel row, a third scan signal GC(k+1) associated with the k+1-th pixel row, and a fourth scan signal GB(k+1) associated with the k+1-th pixel row. Stage STG4_(k+2) in the scan driver 250 can generate a first scan signal GI(k+3) associated with the k+3th pixel row, a second scan signal GW(k+2) associated with the k+2th pixel row, a third scan signal GC(k+2) associated with the k+2th pixel row, and a fourth scan signal GB(k+2) associated with the k+2th pixel row.

[0111] The scan driver 250 may integrate circuits associated with the first to fourth scan signals GI, GW, GC, and GB. Therefore, the occupied area of ​​the scan driver 250 may be reduced. Figure 13 , R, G, and B represent pixels displaying corresponding colors of red, green, and blue, respectively.

[0112] Figure 14 and Figure 15 The diagrams are respectively Figure 12 The scan driver 200b drives the scan lines.

[0113] exist Figure 14 and Figure 15 In FIG, for the convenience of explanation, the emission control signal EM(k) is also shown.

[0114] exist Figure 14 and Figure 15In the embodiment of the present invention, the emission driver 300 may disable the emission control signal EM(k) at a logic high level during the non-emission interval. The non-emission interval may include the consecutive first to seventh horizontal periods t41 to t47 and t51 to t57, and each of the consecutive first to seventh horizontal periods t41 to t47 and t51 to t57 may correspond to one horizontal period 1H. The emission driver 300 may apply the emission control signal EM(k) to the first emission transistor T5 and the second emission transistor T6 in the k-th pixel row. The scan driver 200b may apply the first scan signal GI(k) to the first initialization transistor T4 in the k-th pixel row, the second scan signal GW(k) to the switching transistor T1 in the k-th pixel row, the third scan signal GC(k) to the compensation transistor T3 in the k-th pixel row, and the fourth scan signal GB(k) to the second initialization transistor T7 and the bias transistor T81 or T82 in the k-th pixel row. The scan driver 200 b may enable the first, second, third, and fourth scan signals GI(k), GW(k), GC(k), and GB(k) at a logic low level.

[0115] refer to Figure 14 , the scan driver 200b can enable the first scan signal GI(k) during the second horizontal period t42, can enable the second scan signal GW(k) during the third horizontal period t43 and the fourth horizontal period t44, can enable the third scan signal GC(k) during the fourth horizontal period t44 and the fifth horizontal period t45, and can enable the fourth scan signal GB(k) during the sixth horizontal period t46 and the seventh horizontal period t47. The activation of the second scan signal GW(k) and the third scan signal GC(k) partially overlaps during the fourth horizontal period t44, and the second scan signal GW(k) and the third scan signal GC(k) are enabled in two consecutive horizontal periods. Therefore, the scan driver 200b can increase the scan-on time of the second scan signal GW(k) and the third scan signal GC(k) to reduce crosstalk and low grayscale staining. In addition, the scan driver 200b can use the third scan signal GC(k) for the k-th pixel row as the second scan signal GW(k+1) for the k+1-th pixel row.

[0116] refer to Figure 15, the scan driver 200b may enable the fourth scan signal GB(k) during the second horizontal period t52 and the third horizontal period t53, may enable the first scan signal GI(k) during the fourth horizontal period t54, may enable the second scan signal GW(k) during the fifth horizontal period t55 and the sixth horizontal period t56, and may enable the third scan signal GC(k) during the sixth horizontal period t56 and the seventh horizontal period t57. The activation of the second scan signal GW(k) and the third scan signal GC(k) partially overlaps during the sixth horizontal period t56, and the second scan signal GW(k) and the third scan signal GC(k) are enabled in two consecutive horizontal periods. Therefore, the scan driver 200b can increase the scan-on time of the second scan signal GW(k) and the third scan signal GC(k) to reduce crosstalk and low-grayscale staining.

[0117] Figure 16 is a diagram illustrating a method according to an example embodiment Figure 1 1 is a block diagram of an emission driver 300 of an OLED display device 100 shown in FIG.

[0118] refer to Figure 16 , the emission driver 300 may include a plurality of stages STG1 to STGn connected one by one to sequentially output emission control signals EC1 to ECn.

[0119] The stages STG1 to STGn are respectively connected to emission control lines EL1 to ELn and sequentially output emission control signals EC1 to ECn. The emission control signals EC1 to ECn may overlap with each other during a predetermined period.

[0120] Each of the stages STG1 to STGn receives a first voltage VGH and a second voltage VGL having a voltage level lower than that of the first voltage VGH. Furthermore, each of the stages STG1 to STGn receives a first clock signal CLK1 and a second clock signal CLK2, and some of the stages STG1 to STGn receive a start signal FLM and / or a mode signal MS. The mode signal MS may determine a non-emission interval and the number of horizontal periods included in a time interval of the non-emission interval.

[0121] Hereinafter, the emission control signals EC1 to ECn output through the emission control lines EL1 to ELn are referred to as first to nth emission control signals.

[0122] Among the stages STG1 to STGn, the first stage STG1 is driven in response to the start signal FLM. Specifically, the first stage STG1 receives a first voltage VGH and a second voltage VGL, and generates a first emission control signal EC1 in response to the start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and a mode signal MS. The first emission control signal EC1 is applied to the pixels 111 in the first pixel row through the first emission control line EL1.

[0123] The stages STG1 to STGn are connected one by one and driven sequentially. For example, except for the first stage STG1, the current stage is connected to the output electrode of the previous stage and receives the emission control signal output from the previous stage. The current stage is driven in response to the emission control signal provided from the previous stage.

[0124] For example, the second stage STG2 can receive the first emission control signal EC1 output from the first stage STG1 and be driven in response to the first emission control signal EC1. The second stage STG2 also receives the first voltage VGH and the second voltage VGL, and generates a second emission control signal EC2 in response to the first emission control signal EC1, the first clock signal CLK1, and the second clock signal CLK2. The second emission control signal EC2 is applied to the pixels 111 in the second pixel row through the second emission control line EL2. The other stages STG3 to STGn are driven in the same manner as the second stage STG2, and therefore their details will not be repeated.

[0125] Figure 17 is a flowchart illustrating a method of driving an OLED display device according to example embodiments.

[0126] Figures 1 to 17 A method of driving an OLED display device 100 including a display panel 110 having a plurality of pixels 111 is provided. The method includes: outputting data voltages to the plurality of pixels 111 through a data driver 150 connected to the display panel 110 via a plurality of data lines DL1 to DLm (operation S110); and sequentially outputting a plurality of scan signals GI, GW, GC, and GB to the plurality of pixels 111 through a scan driver 200 connected to the display panel 110 via a plurality of scan line groups SLS1 to SLSn (operation S130).

[0127] The scan driver 200 may enable at least two scan signals among the plurality of scan signals GI, GW, GC, and GB during a non-emission interval in which the pixel 111 does not emit light such that enabling of the at least two scan signals partially overlaps during two consecutive horizontal periods.

[0128] Figure 18is a block diagram illustrating a display system according to example embodiments.

[0129] refer to Figure 18 , the display system 800 may include an application processor (AP) 810 and an OLED display device 820. The OLED display device 820 may include a driving circuit 830, a display panel (OLED display) 840, and a power supply 850.

[0130] The power supply 850 may provide the power PWR to the display panel 840 in response to the power control signal PCTL received from the driving circuit 830. Figure 1 and Figure 4 As illustrated in FIG, the power PWR may include a high power voltage ELVDD, a low power voltage ELVSS, a first initialization voltage VINT, a second initialization voltage AINT, and a bias voltage Vb. The power supply 850 may provide the first voltage VGH and the second voltage VGL to the driving circuit 830.

[0131] The display system 800 may be a portable device such as a notebook computer, a cellular phone, a smart phone, a personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a navigation system, or the like.

[0132] The application processor 810 provides input image data RGB, a control signal CTL, and a main clock signal MCLK to the OLED display device 820 , and the driving circuit 830 may provide a data signal DTA to the display panel 840 .

[0133] The driving circuit 830, the display panel 840 and the power supply 850 can be connected to Figure 1 The driving circuit 105, display panel 110 and power supply 180 shown are substantially the same.

[0134] Figure 19 is a block diagram illustrating an electronic device including an OLED display device according to example embodiments.

[0135] refer to Figure 19 , the electronic device 1000 includes a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and an OLED display device 1060. The electronic device 1000 may further include a plurality of ports for communicating with a graphics card, a sound card, a memory card, a universal serial bus (USB) device, and other electronic systems, devices, and components.

[0136] The processor 1010 can perform various computing tasks. The processor 1010 can be, for example, a microprocessor, a central processing unit (CPU), etc. The processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 can be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0137] The memory device 1020 may store data used to operate the electronic system 1000. For example, the memory device 1020 may include at least one nonvolatile memory device such as a flash memory device and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0138] The storage device 1030 may be, for example, a solid-state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1040 may be, for example, an input device such as a keyboard, a keypad, a mouse, a touch screen, etc. and / or an output device such as a printer, a speaker, etc. The power supply 1050 may provide power for operating the electronic system 1000. The OLED display device 1060 may communicate with other components via a bus or other communication links.

[0139] The OLED display device 1060 can be used Figure 1 OLED display device 1060. Thus, OLED display device 1060 may include a driving circuit and a display panel, and the driving circuit may include a data driver and a scan driver. The scan driver may enable at least two of a plurality of scan signals during a non-emission interval in which a pixel does not emit light, such that the enabling of the at least two scan signals partially overlaps during two consecutive horizontal periods. Thus, the scan driver may reduce crosstalk and low grayscale coloring for OLED display device 1060 driven at a high frequency.

[0140] The electronic device 1000 may be a mobile electronic device such as a smart phone including an OLED display device 1060 .

[0141] This embodiment can be applied to any electronic device 1000 having an OLED display device 1060. For example, this embodiment can be applied to electronic devices 1000 such as televisions, computer monitors, notebook computers, digital cameras, cellular phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, navigation systems, and the like.

[0142] The inventive concept may be applied to any display device or any electronic device including a display device that displays an image.

[0143] The foregoing is illustrative of example embodiments and should not be construed as limiting the example embodiments. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present invention. Therefore, modifications are intended to be included within the scope of the present invention. Therefore, it should be understood that the foregoing is illustrative of various example embodiments of the present invention and should not be construed as limiting the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the present disclosure, including the appended claims.

Claims

1. A display device, comprising: a display panel comprising a plurality of pixels; a driving circuit connected to the plurality of pixels through a plurality of scan line groups and a plurality of data lines, the driving circuit being configured to provide a plurality of scan signals to the display panel and to provide data voltages to the plurality of data lines; as well as a power supply configured to apply one or more power supply voltages to the plurality of pixels, wherein the driving circuit is configured to enable at least two scan signals of the plurality of scan signals during a non-emission interval so that the at least two scan signals partially overlap during at least two consecutive horizontal periods, and The horizontal period corresponds to a period during which the driving circuit provides the data voltage to one pixel row of the plurality of pixels. Wherein, the driving circuit includes: The scan driver is configured to provide a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to each of the pixel rows of the plurality of pixels.

2. The display device according to claim 1, wherein The driving circuit further comprises: a data driver configured to provide the data voltage corresponding to the data signal to the plurality of data lines connected to the plurality of pixels; an emission driver configured to provide a plurality of emission control signals to a plurality of emission control lines connected to the plurality of pixels; and a timing controller configured to control the scan driver, the data driver, the emission driver, and the power supply, The timing controller is configured to generate the data signal based on input image data.

3. The display device according to claim 2, in, The one or more power supply voltages include a low power supply voltage, a high power supply voltage, a first initialization voltage, a second initialization voltage, and a bias voltage, Each of the plurality of scan line groups includes a first scan line, a second scan line, a third scan line, and a fourth scan line, and Each of the plurality of pixels comprises: a switching transistor having a first electrode coupled to a data line among the plurality of data lines, a gate coupled to the second scan line, and a second electrode coupled to the first node; a storage capacitor having a first terminal receiving the high supply voltage and a second terminal coupled to a second node; a driving transistor having a first electrode coupled to the first node, a gate coupled to the second node, and a second electrode coupled to a third node; a compensation transistor having a first electrode coupled to the second node, a gate coupled to the third scan line, and a second electrode coupled to the third node; a first initialization transistor having a first electrode coupled to the second node, a gate coupled to the first scan line, and a second electrode receiving the first initialization voltage; a first emission transistor having a first electrode receiving the high power supply voltage, a gate receiving an emission control signal from among the plurality of emission control signals, and a second electrode coupled to the first node; a second emission transistor having a first electrode coupled to the third node, a gate receiving the emission control signal among the plurality of emission control signals, and a second electrode coupled to a fourth node; a second initialization transistor having a first electrode coupled to the fourth node, a gate coupled to the fourth scan line, and a second electrode receiving the second initialization voltage; a bias transistor having a first electrode coupled to the third node, a gate coupled to the fourth scan line, and a second electrode receiving the bias voltage; and The light emitting element has an anode coupled to the fourth node and a cathode receiving the low power supply voltage.

4. The display device according to claim 3, in, The transmit driver is configured to disable the transmit control signal at a logic high level during the non-transmitting interval, The non-emission interval includes continuous horizontal periods, and the continuous horizontal periods include a first horizontal period, a second horizontal period, a third horizontal period, a fourth horizontal period, a fifth horizontal period, and a sixth horizontal period. Wherein, the scanning driver comprises: a first scan driver configured to generate the first scan signal, the second scan signal, and the third scan signal; and a second scanning driver configured to generate the fourth scanning signal, and For the k-th pixel row among the pixel rows, k is a natural number, and the scan driver is configured as follows: enabling the fourth scanning signal during the second horizontal period; enabling the first scan signal during the third horizontal period; enabling the second scan signal during the fourth horizontal period and the fifth horizontal period; and The third scan signal is enabled during the fifth horizontal period and the sixth horizontal period.

5. The display device according to claim 3, wherein The second initialization transistor is configured to transmit the second initialization voltage to the anode of the light emitting element in response to the fourth scan signal received through the fourth scan line; and The bias transistor is configured to transmit the bias voltage to the second electrode of the driving transistor in response to the fourth scan signal received through the fourth scan line.

6. The display device according to claim 3, in, The transmit driver is configured to disable the transmit control signal at a logic high level during the non-transmitting interval, The non-emission interval includes continuous horizontal periods, and the continuous horizontal periods include a first horizontal period, a second horizontal period, a third horizontal period, a fourth horizontal period, a fifth horizontal period, and a sixth horizontal period. Wherein, the scanning driver comprises: a first scan driver configured to generate the first scan signal, the second scan signal, and the third scan signal; and a second scanning driver configured to generate the fourth scanning signal, and For the k-th pixel row among the pixel rows, k is a natural number, and the scan driver is configured as follows: enabling the first scan signal during the second horizontal period; enabling the second scan signal during the third horizontal period and the fourth horizontal period; enabling the third scan signal during the fourth horizontal period and the fifth horizontal period; and The fourth scan signal is enabled during the sixth horizontal period.

7. The display device according to claim 3, in, The transmit driver is configured to disable the transmit control signal at a logic high level during the non-transmitting interval, The non-emission interval includes continuous horizontal periods, and the continuous horizontal periods include a first horizontal period, a second horizontal period, a third horizontal period, a fourth horizontal period, a fifth horizontal period, and a sixth horizontal period. Wherein, the scanning driver comprises: a first scan driver configured to generate the first scan signal, the second scan signal, and the third scan signal; and a second scanning driver configured to generate the fourth scanning signal, and For the k-th pixel row among the pixel rows, k is a natural number, and the scan driver is configured as follows: enabling the first scan signal during the second horizontal period and the third horizontal period; enabling the second scan signal during the third horizontal period and the fourth horizontal period; enabling the third scan signal during the fourth horizontal period and the fifth horizontal period; and The fourth scan signal is enabled during the sixth horizontal period.

8. The display device according to claim 3, in, The emission driver is configured to disable the emission control signal at a logic high level during the non-emission interval, The non-emission interval includes continuous horizontal periods, and the continuous horizontal periods include a first horizontal period, a second horizontal period, a third horizontal period, a fourth horizontal period, a fifth horizontal period, a sixth horizontal period, and a seventh horizontal period. The scan driver is configured to generate the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal. For the k-th pixel row among the pixel rows, k is a natural number, and the scan driver is configured as follows: enabling the first scan signal during the second horizontal period; enabling the second scan signal during the third horizontal period and the fourth horizontal period; enabling the third scan signal during the fourth horizontal period and the fifth horizontal period; and The fourth scan signal is enabled during the sixth horizontal period and the seventh horizontal period.

9. The display device according to claim 3, in, The transmit driver is configured to disable the transmit control signal at a logic high level during the non-transmitting interval, The non-emission interval includes continuous horizontal periods, and the continuous horizontal periods include a first horizontal period, a second horizontal period, a third horizontal period, a fourth horizontal period, a fifth horizontal period, a sixth horizontal period, and a seventh horizontal period. The scan driver is configured to generate the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal. For the k-th pixel row among the pixel rows, k is a natural number, and the scan driver is configured as follows: enabling the fourth scan signal during the second horizontal period and the third horizontal period; enabling the first scan signal during the fourth horizontal period; enabling the second scan signal during the fifth horizontal period and the sixth horizontal period; and The third scan signal is enabled during the sixth horizontal period and the seventh horizontal period.

10. A method for driving a display device, comprising: outputting data voltages to a plurality of pixels of the display panel through a data driver connected to the display panel via a plurality of data lines; and sequentially outputting a plurality of scan signals including a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to each of the plurality of pixel rows through a scan driver connected to the display panel via a plurality of scan line groups, wherein the scan driver is configured to enable at least two scan signals among the plurality of scan signals during a non-emission interval so that the at least two scan signals partially overlap during at least two consecutive horizontal periods, and The horizontal period corresponds to a period during which the data driver provides the data voltage to one pixel row of the plurality of pixels.

Images