Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package includes a plurality of semiconductor chips and an interposer structure. The interposer structure has a plurality of tiers for housing the plurality of semiconductor chips. The interposer structure includes at least one conductive via connected to a pad of the plurality of semiconductor chips.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device package and a method of manufacturing the same. More specifically, this disclosure relates to a semiconductor device package including an interposer structure and a method of manufacturing the same. Background Technology

[0002] Semiconductor device packages can contain one or more semiconductor chips. With advancements in the miniaturization of electronic device packaging structures, multiple semiconductor chips can be stacked on a packaging substrate to form a semiconductor device package. This presents challenges in terms of heat dissipation and conductivity, requiring solutions to improve the properties of semiconductor device packages containing stacked semiconductor chips. Summary of the Invention

[0003] In one or more embodiments, a semiconductor device package includes a plurality of semiconductor chips and an interposer structure. The interposer structure has a plurality of tiers for accommodating the plurality of semiconductor chips. The interposer structure includes conductive vias connected to at least one pad of the plurality of semiconductor chips.

[0004] In one or more embodiments, the semiconductor device package includes a ladder interconnect structure and a plurality of semiconductor chips. The ladder interconnect structure has multiple steps at different elevations. The semiconductor chips are disposed on and electrically connected to the multiple steps of the ladder interconnect structure. The ladder interconnect structure includes a silicon substrate.

[0005] In one or more embodiments, a method for manufacturing a semiconductor device package includes: forming a stair-step interconnect structure having multiple steps at different elevations; and placing a plurality of semiconductor chips on the multiple steps of the stair-step interconnect structure. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the features may not be drawn to scale, and the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0008] Figure 2 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0009] Figure 3 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0010] Figure 4 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0011] Figure 5 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0012] Figure 6A , Figure 6B , Figure 6C and Figure 6D Methods for manufacturing semiconductor device packages according to some embodiments of the present disclosure are shown.

[0013] Figure 7A , Figure 7B , Figure 7C and Figure 7D Methods for manufacturing semiconductor device packages according to some embodiments of the present disclosure are shown.

[0014] Common reference numerals are used throughout the accompanying drawings and detailed description to indicate the same or similar elements. This disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0015] Figure 1 This is a cross-sectional view of a semiconductor device package 10 according to some embodiments of the present disclosure. The semiconductor device package 10 includes semiconductor chips 110, 120, and 130 and an interposer structure 200.

[0016] In some embodiments, semiconductor chips 110, 120, and 130 may independently comprise a CPU chip, a GPU chip, a logic chip, and / or a memory chip, but this disclosure is not limited thereto. Various types of semiconductor chips can be implemented as needed. Furthermore, the arrangement of three semiconductor chips 110, 120, and 130 in the semiconductor device package 10 is an example described herein; however, the number of semiconductor chips arranged in the semiconductor device package 10 can vary as needed, and this disclosure is not limited thereto.

[0017] Interposer structure 200 has multiple layers (e.g., layers 210, 220, and 230) for accommodating multiple semiconductor chips (e.g., semiconductor chips 110, 120, and 130). Each layer may have one or more semiconductor chips disposed thereon. In some embodiments, semiconductor chip 110 is located at a first layer 210 of the multiple layers 210, 220, and 230 of interposer structure 200, semiconductor chip 120 is located at a second layer 220 of the multiple layers 210, 220, and 230 of interposer structure 200, and semiconductor chip 130 is located at a third layer 230 of the multiple layers 210, 220, and 230 of interposer structure 200. In some embodiments, semiconductor chip 110 is located at the top layer (e.g., first layer 210) of the interposer structure 200, semiconductor chip 120 is located at the next uppermost layer (e.g., second layer 220) of the interposer structure 200, and semiconductor chip 130 is located at the bottom layer (e.g., third layer 230) of the interposer structure 200. For example, semiconductor chip 130 at the bottom layer may be a base logic chip, and semiconductor chips 110 and 120 may be independent functional chips, such as computer chips, field-effect programmable gate array (FPGA) chips, memory chips, and / or radio frequency (RF) ICs. In some embodiments, the interposer structure 200 may be referred to as a packaging substrate for stacking multiple chips thereon.

[0018] In some embodiments, semiconductor chip 110 is stacked on semiconductor chip 120, and semiconductor chip 120 is stacked on semiconductor chip 130. In some embodiments, a portion of semiconductor chip 110 is located at a first layer 210 and another portion of semiconductor chip 110 is stacked on semiconductor chip 120. In some embodiments, a portion of semiconductor chip 120 is located at a second layer 220 and another portion of semiconductor chip 120 is stacked on semiconductor chip 130.

[0019] In some embodiments, the interposer structure 200 may be referred to as a ladder interconnect structure having multiple steps (e.g., steps 210a, 220a, and 230a) at different elevations. In some embodiments, semiconductor chips 110, 120, and 130 are respectively disposed on and electrically connected to the multiple steps 210a, 220a, and 230a of the ladder interconnect structure.

[0020] In a scenario where multiple chips are stacked on top of each other on a packaging substrate, only one or a few chips at the bottom of the stack can directly contact the packaging substrate and conduct heat and electricity directly through it. Other chips stacked above the bottom chips cannot directly contact the packaging substrate; therefore, heat and electricity conduction of the bottom chips can only occur through the stacked chips, resulting in relatively low heat dissipation efficiency and limited conductive paths. In some embodiments of this disclosure, by using an interposer structure having multiple layers for accommodating multiple semiconductor chips, each of the multiple semiconductor chips can substantially contact the interposer structure and dissipate heat or conduct electricity through the interposer, thereby improving the heat and electricity conduction of the semiconductor chips stacked on the interposer structure and the performance of the semiconductor device package.

[0021] In some embodiments, the interposer structure 200 has a surface 200a (also referred to as the "upper surface") and a surface 200b (also referred to as the "bottom surface") opposite to the surface 200a, and the surface 200a is a tiered surface. In some embodiments, steps 210a, 220a, and 230a are located at the surface 200a of the interposer structure 200. In some embodiments, steps 210a, 220a, and 230a form tiered surfaces of the interposer structure 200 (e.g., surface 200a). In some embodiments, the surface 200b of the interposer structure 200 is substantially planar. In some embodiments, the surface 200b of the interposer structure 200 is an active surface. In some embodiments, the tiers of the interposer structure 200 may be made of the same substrate material. In some embodiments, some or all of the tiers of the interposer structure 200 may be made of different substrate materials. In some embodiments, the substrate material of each tier of the interposer structure 200 may independently comprise silicon, glass, and / or an organic dielectric material. In some embodiments, the substrate material of each tier of the interposer structure 200 is silicon. In some embodiments, the interposer structure 200 includes a silicon substrate 201. The silicon substrate 201 may be located at one or more of the first layer 210, the second layer 220, and the third layer 230, or the silicon substrate 201 may constitute one or more of the first layer 210, the second layer 220, and the third layer 230.

[0022] Interposer structure 200 may include a plurality of conductive vias connected to a semiconductor chip disposed thereon. In some embodiments, interposer structure 200 may include a plurality of conductive vias (e.g., conductive vias 210A, 210B, 210C, and 210E), and the conductive vias pass through silicon substrate 201 and are connected to semiconductor chips 110, 120, and 130. In some embodiments, conductive via 210A or 210B is connected to a pad (e.g., a power pad or a ground pad) of semiconductor chip 110. In some embodiments, pad 111 of semiconductor chip 110 is a power pad, and pad 113 of semiconductor chip 110 is a ground pad. In some embodiments, conductive via 210A is connected to a power pad (e.g., pad 111) of the semiconductor chip 110, and conductive via 210B is connected to a ground pad (e.g., pad 113) of the semiconductor chip 110. Conductive via 210A and conductive via 210B are electrically isolated, preventing short circuits between the power pad and ground pad of the semiconductor chip 110. The conductive vias can pass through the interposer structure 200, thus providing a thermally or electrically conductive path from surface 200a to surface 200b of the interposer structure 200.

[0023] Typically, chips can be stacked on a package structure made of organic dielectric materials such as resin materials and / or molding materials. While organic dielectric materials may be less expensive, they have relatively low thermal conductivity and therefore poor thermal conductivity. By using the interposer structure according to embodiments of this disclosure, the device package can accommodate more semiconductor chips on the one hand, and on the other hand, the heat generated by those semiconductor chips can be quickly removed through conductive vias (which are typically made of metal or alloy and have excellent thermal conductivity), thereby effectively improving heat dissipation in IC stacks. Additionally, as discussed above, in some embodiments according to this disclosure, the interposer structure may comprise silicon or a silicon substrate. Compared to organic dielectric materials, silicon substrate materials exhibit higher thermal conductivity, allowing for further improvement in the thermal conductivity of the semiconductor device.

[0024] Furthermore, a relatively large amount of heat is typically present at the power and ground pads of a semiconductor chip. Without efficient heat dissipation, the temperature will rise sharply, which can negatively impact the overall performance of the device package. According to some embodiments of this disclosure, even when the semiconductor chip is located relatively high in the stack, one or more conductive vias of the interposer structure are connected to the power and / or ground pads of the semiconductor chip to effectively conduct heat from the power and / or ground pads through the interposer structure, thereby improving thermal conductivity efficiency.

[0025] In some embodiments, conductive via 210C is connected to a pad of semiconductor chip 120. In some embodiments, conductive via 210E is connected to a pad of semiconductor chip 130. In some embodiments, conductive vias 210A, 210B, 210C, and / or 210E may be one or more conductive vias. In some embodiments, the extension length L1 of conductive via 210A or 210B is greater than the extension length L2 of conductive via 210C. In some embodiments, the extension length L2 of conductive via 210C is greater than the extension length L3 of conductive via 210E.

[0026] In some embodiments, the interposer structure 200 may further include at least one dummy conductive via (e.g., dummy conductive vias 210D1, 210D2, 210D3, and 210D4) connected to at least one of the plurality of semiconductor chips 110, 120, and 130. In some embodiments, dummy conductive via 210D1 passes through the silicon substrate 201 and is connected to the semiconductor chip 110. In some embodiments, dummy conductive via 210D2 passes through the silicon substrate 201 and is connected to the semiconductor chip 120. In some embodiments, dummy conductive vias 210D3 and 210D4 pass through the silicon substrate 201 and are connected to the semiconductor chip 130. In some embodiments, dummy conductive vias 210D1, 210D2, 210D3, and / or 210D4 may be one or more conductive vias. One or more dummy conductive vias provide one or more additional heat conduction paths, and thus the heat dissipation efficiency of the semiconductor device can be further improved.

[0027] In some embodiments, conductive vias 210A, 210B, 210C, and 210E, as well as dummy conductive vias 210D1, 210D2, 210D3, and 210D4, may independently comprise or be formed of gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), one or more other metals or alloys, or combinations thereof. In some embodiments, conductive vias 210A, 210B, 210C, and 210E, as well as dummy conductive vias 210D1, 210D2, 210D3, and 210D4, are formed of copper (Cu).

[0028] In some embodiments, the semiconductor device package 10 may further include a plurality of conductive elements (e.g., conductive elements 310a, 310b, 310c, 310d, and 310e) disposed on the surface 200b of the interposer structure 200. In some embodiments, a conductive via 210A connects the semiconductor chip 110 to the conductive element 310a. In some embodiments, a conductive via 210B connects the semiconductor chip 110 to the conductive element 310b. In some embodiments, a conductive via 210C connects the semiconductor chip 120 to the conductive element 310c. In some embodiments, a conductive via 210E connects the semiconductor chip 130 to the conductive element 310e. In some embodiments, conductive elements 310a, 310b, 310c, 310d, and 310e may be solder balls or bumps. In some embodiments, conductive elements 310a, 310b, 310c, 310d, and 310e may be controlled-collapse chip-to-chip (C4) bumps, ball grid arrays (BGAs), or planar grid arrays (LGAs).

[0029] In some embodiments, the semiconductor device package 10 may further include electrical contacts (e.g., electrical contacts 240a, 240b, 240c, and 240e). In some embodiments, electrical contact 240a is disposed between a pad 111 of the semiconductor chip 110 and an interposer structure 200 and is in direct contact with the pad and the interposer structure. For example, electrical contact 240a directly contacts a conductive via 210A of the interposer structure 200. In some embodiments, electrical contact 240b is disposed between a pad 113 of the semiconductor chip 110 and an interposer structure 200 and is in direct contact with the pad and the interposer structure. For example, electrical contact 240b directly contacts a conductive via 210B of the interposer structure 200. In some embodiments, electrical contact 240c is disposed between a pad 121 of the semiconductor chip 120 and an interposer structure 200 and is in direct contact with the pad and the interposer structure. For example, electrical contact 240c can directly contact the conductive via 210C of the interposer structure 200. In some embodiments, semiconductor chip 110 and semiconductor chip 120 are electrically connected to each other via electrical contact 240e.

[0030] In some embodiments, the semiconductor device package 10 may further include one or more dummy electrical contacts (e.g., dummy electrical contacts 240d1, 240d2, 240d3, and 240d4). In some embodiments, dummy electrical contact 240d1 directly contacts dummy conductive via 210D1 and semiconductor chip 110. In some embodiments, dummy electrical contact 240d2 directly contacts dummy conductive via 210D2 and semiconductor chip 120. In some embodiments, dummy electrical contact 240d3 directly contacts dummy conductive via 210D3 and semiconductor chip 130. In some embodiments, dummy electrical contact 240d4 directly contacts dummy conductive via 210D4 and semiconductor chip 130.

[0031] The following section presents simulation results for an exemplary semiconductor device package (E1) and a comparative semiconductor device package (C1). The exemplary semiconductor device package (E1) has... Figure 1 The structure shown is different from that of the comparative semiconductor device package (C1), which includes a planar substrate with three semiconductor chips stacked on top of each other. Table 1 shows the simulated temperature results for the exemplary semiconductor device package (E1) and the comparative semiconductor device package (C1). In Table 1, "junction temperature" indicates the temperature of the PN junction within each semiconductor device package, and the junction temperature also indicates the maximum temperature within each semiconductor device package.

[0032] Table 1

[0033] C1 E1 <![CDATA[Junction temperature (T j )(°C)]]> 118 81 <![CDATA[Ambient temperature (T A )(°C)]]> 25 25 <![CDATA[T j With T A The difference (ΔT) 93 56 Improvement in heat dissipation (%) 40((93-56) / 93)

[0034] Table 1 clearly shows that without the interposer structure according to some embodiments of this disclosure, the node temperature is very high, reaching approximately 118°C. However, with the interposer structure, the node temperature drops significantly to approximately 81°C, representing an improvement in heat dissipation of approximately 40%.

[0035] Figure 2 This is a cross-sectional view of a semiconductor device package 20 according to some embodiments of the present disclosure. The semiconductor device package 20 is similar to... Figure 1 The semiconductor device package 10 in the semiconductor device package 20 may further include an electronic circuit structure 260, in addition to the interposer structure 200 of the semiconductor device package 20.

[0036] In some embodiments, the electronic circuit structure 260 is embedded in the silicon substrate 201. In some embodiments, the electronic circuit structure 260 may be referred to as an embedded circuitry. In some embodiments, the electronic circuit structure 260 is adjacent to the bottom surface (e.g., surface 200b) of the interposer structure 200. In some embodiments, the electronic circuit structure 260 is adjacent to the active surface (e.g., surface 200b) of the interposer structure 200. In some embodiments, the electronic circuit structure 260 is embedded in the bottommost layer (e.g., the third layer 230) of the interposer structure 200.

[0037] Figure 3 This is a cross-sectional view of a semiconductor device package 30 according to some embodiments of the present disclosure. The semiconductor device package 30 is similar to... Figure 1 The semiconductor device package 10 in the semiconductor device package 30 may further include conductive components (e.g., conductive components 410 and 420).

[0038] In some embodiments, at least one of the conductive components 410 and 420 is disposed between the interposer structure 200 and at least one of the plurality of semiconductor chips 110, 120, and 130. In some embodiments, at least one of the conductive components 410 and 420 is in direct contact with the interposer structure 200 and at least one of the plurality of semiconductor chips 110, 120, and 130. In some embodiments, at least one of the conductive components 410 and 420 is in direct contact with at least one step of a plurality of steps (e.g., steps 210a, 220a, and 230a) of the interposer structure 200 and at least one of the plurality of semiconductor chips 110, 120, and 130.

[0039] In some embodiments, the conductive component 410 directly contacts the pad 111 and the interposer structure 200 of the semiconductor chip 110. In some embodiments, the conductive component 410 directly contacts the dummy conductive via 210D1 of the interposer structure 200. In some embodiments, the conductive component 410 directly contacts the conductive via 210A of the interposer structure 200. In some embodiments, the conductive component 420 directly contacts the pad 121 and the interposer structure 120 of the semiconductor chip 120. In some embodiments, the conductive component 420 directly contacts the dummy conductive via 210D2 of the interposer structure 200. In some embodiments, the conductive component 420 directly contacts the conductive via 210C of the interposer structure 200.

[0040] In some embodiments, conductive components 410 and 420 may be made of the same or different material as the conductive vias and / or dummy conductive vias of the interposer structure 200. The arrangement of conductive components 410 and / or 420 can further improve the thermal and electrical conductivity of the stacked semiconductor chip. In some embodiments, conductive components 410 and / or 420 can connect pads (e.g., pads 111 or 121) of the semiconductor chip (e.g., semiconductor chip 110 or 120) to conductive vias (e.g., conductive vias 210A or 210C) connected to conductive elements (e.g., conductive elements 310a or 310c), thereby effectively improving conductivity. In addition, in some embodiments, conductive components 410 and / or 420 may further connect the pads (e.g., pads 111 or 121) of the semiconductor chip (e.g., semiconductor chip 110 or 120) to dummy conductive vias (e.g., dummy conductive vias 210D1 or 210D2), thereby further improving thermal conductivity, further improving heat dissipation of the entire semiconductor device package 30, and thus greatly improving the performance of the semiconductor device package 30.

[0041] In some embodiments, conductive components 410 and 420 may be independently formed or comprised of gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), one or more other metals or alloys, or combinations thereof. In some embodiments, conductive components 410 and 420 are formed of copper (Cu).

[0042] Figure 4 This is a cross-sectional view of a semiconductor device package 40 according to some embodiments of the present disclosure. The semiconductor device package 40 is similar to... Figure 1 The semiconductor device package 10 includes, except for the configuration of the interposer structure 200 (e.g., the arrangement of layers 210, 220 and 230 and steps 210a, 220a and 230a).

[0043] In some embodiments, the steps 230a of the third layer 230 of the intermediary layer structure 200 are located between portions of the steps 210a of the first layer 210 of the intermediary layer structure 200. In some embodiments, the steps 230a of the third layer 230 of the intermediary layer structure 200 are located between portions of the steps 220a of the second layer 220 of the intermediary layer structure 200. In some embodiments, the steps 220a of the second layer 220 of the intermediary layer structure 200 are located between portions of the steps 210a of the first layer 210 of the intermediary layer structure 200.

[0044] In some embodiments, the semiconductor device package 40 further includes a semiconductor chip 140 at a first layer 210 of the interposer structure 200. In some embodiments, a portion of the semiconductor chip 140 is located at the first layer 210, and another portion of the semiconductor chip 140 is stacked on a semiconductor chip 120 at a second layer 220 of the interposer structure 200. The interposer structure 200 can be designed to implement various IC stacks as needed, such as stacking two or more semiconductor chips (e.g., semiconductor chip 110 and semiconductor chip 140) on the same semiconductor chip (e.g., semiconductor chip 120) and increasing the heat dissipation paths of one or more semiconductor chips (e.g., by arranging more conductive vias for semiconductor chip 120).

[0045] Figure 5 This is a cross-sectional view of a semiconductor device package 50 according to some embodiments of the present disclosure. The semiconductor device package 50 is similar to... Figure 1 The semiconductor device package 10 includes, except for the configuration of the interposer structure 200 (e.g., the arrangement of layers 210, 220 and 230 and steps 210a, 220a and 230a).

[0046] In some embodiments, a step 210a of the first layer 210 of the intermediary layer structure 200 is located between portions of a step 230a of the third layer 230 of the intermediary layer structure 200. In some embodiments, a portion of a step 210a of the first layer 210 of the intermediary layer structure 200 is adjacent at one end to a portion of a step 230a of the third layer 230 of the intermediary layer structure 200 and at the opposite end to a portion of a step 220a of the second layer 220 of the intermediary layer structure 200.

[0047] In some embodiments, the semiconductor device package 50 further includes a semiconductor chip 150 at a first layer 210 of the interposer structure 200 and a semiconductor chip 160 at a third layer 230 of the interposer structure 200. In some embodiments, the semiconductor chip 150 is disposed adjacent to the semiconductor chip 160. In some embodiments, the semiconductor chip 160 is a power IC.

[0048] As according to some embodiments of this disclosure Figure 4 and 5 The arrangement of the layers 210, 220 and 230 and the steps 210a, 220a and 230a of the interposer structure 200 of the semiconductor device package shown can be varied according to actual needs to accommodate various semiconductor chips, wherein this disclosure is not limited to the exemplary embodiments shown.

[0049] Figure 6A , 6BFigures 6C and 6D illustrate methods of manufacturing a semiconductor device package 10 according to some embodiments of the present disclosure. The figures have been simplified for a better understanding of various aspects of the present disclosure.

[0050] refer to Figure 6A A first layer 610 with vias is provided. In some embodiments, the first layer 610 may be formed, for example, by providing a silicon substrate, forming vias penetrating the silicon substrate, and filling the vias with a conductive material to form vias in the silicon substrate. In some embodiments, the first layer 610 may further include an electronic circuit structure 260 embedded in the silicon substrate. In some embodiments, the first layer 610 with vias may be referred to as a subsequently formed layer of the interposer structure 200 (e.g., a third layer 230).

[0051] refer to Figure 6B A second layer 620 with vias is disposed on a first portion 610A of the first layer 610, exposing a second portion 610B of the first layer 610. In some embodiments, the second layer 620 with vias is formed by a process similar to that used to form the first layer 610 with vias. In some embodiments, the vias of the second layer 620 are aligned with corresponding vias in the first portion 610A of the first layer 610. A semiconductor chip 130 is then disposed on the second portion 610B of the first layer 610 with vias. In some embodiments, the placement of the second layer 620 with vias on the first portion 610A of the first layer 610 with vias is performed by wafer bonding. In some embodiments, the second layer 620 with vias may be referred to as a subsequent layer of the interposer structure 200 (e.g., a second layer 220).

[0052] refer to Figure 6C A third layer 630 with vias is disposed on a first portion 620A of the second layer 620, exposing a second portion 620B of the second layer 620. In some embodiments, the third layer 630 with vias is formed by a process similar to that used to form the first layer 610 with vias. In some embodiments, the vias of the third layer 630 are aligned with corresponding vias in the first portion 620A of the first layer 620. A semiconductor chip 120 is then disposed on the semiconductor chip 130 and the second portion 620B of the second layer 620. In some embodiments, the placement of the third layer 630 with vias on the first portion 620A of the second layer 620 is performed by wafer bonding. In some embodiments, the third layer 630 with vias may be referred to as a subsequent layer (e.g., first layer 210) of the interposer structure 200.

[0053] refer to Figure 6DThen, semiconductor chip 110 is placed on the third layer 630 and semiconductor chip 120.

[0054] Figure 7A , 7B Figures 7C and 7D illustrate methods of manufacturing a semiconductor device package 10 according to some embodiments of the present disclosure. The figures have been simplified for a better understanding of various aspects of the present disclosure.

[0055] refer to Figure 7A It provides a silicon substrate 710.

[0056] refer to Figure 7B The silicon substrate 710 is partially removed to form a ladder structure 720 having multiple steps 210a, 220a, and 230a at different elevations. In some embodiments, the partial removal of the silicon substrate 710 is performed by etching. In some embodiments, the silicon substrate 710 may be partially removed by performing multiple etching processes on the silicon substrate 710, and each etching process in the etching process contributes to forming each step of the ladder structure 720.

[0057] refer to Figure 7C Conductive vias 210A, 210B, 210C, and 210E are formed in the ladder structure 720. In some embodiments, a plurality of dummy conductive vias 210D1, 210D2, 210D3, and 210D4 are formed in the ladder structure 720. In some embodiments, conductive vias 210A, 210B, 210C, and 210E pass through the ladder structure 720. In some embodiments, dummy conductive vias 210D1, 210D2, 210D3, and 210D4 pass through the ladder structure 720. In some embodiments, conductive vias 210A, 210B, 210C, and 210E and dummy conductive vias 210D1, 210D2, 210D3, and 210D4 can be formed, for example, by forming through-holes penetrating the ladder structure 720 and filling the through-holes with conductive material. In some embodiments, conductive vias and dummy conductive vias corresponding to different layers can be formed in the same process or in separate processes. Thus, an intermediate layer structure 200 is formed.

[0058] refer to Figure 7D Multiple semiconductor chips 110, 120, and 130 are disposed on multiple steps 210a, 220a, and 230a of the already formed interposer structure 200. In some embodiments, semiconductor chip 130 is disposed on step 230a of the third layer 230 of the interposer structure 200, then semiconductor chip 120 is disposed on step 220a of the second layer 220 of the interposer structure 200 and semiconductor chip 130, and then semiconductor chip 110 is disposed on step 210a of the first layer 210 of the interposer structure 200 and semiconductor chip 120.

[0059] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurred precisely or instances where the event or situation was close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the numerical values ​​may be considered “substantially” or “about” the same. For example, "essentially parallel" can refer to an angle range of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "essentially perpendicular" can refer to an angle range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0060] If the displacement between two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar.

[0061] As used herein, the terms “conductive,” “electrically conductive,” and “electrical conductivity” refer to the ability to conduct electric current. Conductive materials generally refer to those materials that offer little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than about 10. 4 S / m, such as at least 10 5 S / m or at least 10 6 Conductive materials with conductivity of S / m. The conductivity of the material may sometimes vary with temperature. Unless otherwise stated, the conductivity of the material is measured at room temperature.

[0062] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural referents. In the description of some embodiments, the description of another component disposed “on” or “above” a component may cover the case where the preceding component is directly located on (e.g., in physical contact with) the following component, as well as the case where there is one or more intermediate components between the preceding and following components.

[0063] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such depictions and illustrations are not limiting of this disclosure. Those skilled in the art will understand that various changes may be made and equivalent components may be substituted within embodiments without departing from the spirit and scope of this disclosure as defined by the claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to variables such as those in the manufacturing process. Other embodiments of this disclosure may exist that are not specifically shown. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it will be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor device package comprising: Multiple semiconductor chips; An interposer structure having multiple layers for accommodating the plurality of semiconductor chips; The interposer structure includes at least one conductive via connected to the pads of the plurality of semiconductor chips, and the interposer structure is a ladder interconnect structure having multiple steps at different elevations. as well as Multiple first electrical contacts, including a first group and a second group at the same elevation, wherein the first group is in direct contact with the first semiconductor chip of the plurality of semiconductor chips and the interposer structure, and the second group is in direct contact with the first semiconductor chip and the second semiconductor chip of the plurality of semiconductor chips.

2. The semiconductor device package according to claim 1, further comprising: A power IC disposed on the interposer structure, wherein the thickness of the power IC is greater than the thickness of the plurality of semiconductor chips.

3. The semiconductor device package of claim 2, wherein the thickness of the power IC is greater than the total thickness of the plurality of steps at different elevations of the interposer structure.

4. The semiconductor device package of claim 1, further comprising a plurality of second electrical contacts, including a third group and a fourth group at the same elevation, wherein the third group is in direct contact with the second semiconductor chip and the interposer structure, and the fourth group is in direct contact with the second semiconductor chip and a third semiconductor chip of the plurality of semiconductor chips.

5. The semiconductor device package of claim 4, wherein the second group of the plurality of first electrical contacts and the plurality of second electrical contacts overlap in a direction perpendicular to the bottom surface of the interposer structure.

6. The semiconductor device package of claim 1, wherein the bottom surface of the interposer structure is an active surface.

7. The semiconductor device package of claim 6, wherein the interposer structure includes an embedded circuit system adjacent to the bottom surface of the interposer structure, wherein the width of the embedded circuit system is smaller than the width of the interposer structure in a direction horizontal to the bottom surface of the interposer structure.

8. The semiconductor device package of claim 1, further comprising: A conductive component disposed between the interposer structure and at least one of the plurality of semiconductor chips; as well as Multiple conductive vias pass through the interposer structure and are in direct contact with the conductive component. The number of the conductive components is less than the number of the plurality of conductive vias that are in direct contact with the conductive components.

9. The semiconductor device package of claim 1, wherein the interposer structure comprises a silicon substrate.

10. The semiconductor device package of claim 6, wherein the interposer structure includes an embedded circuit system adjacent to the bottom surface of the interposer structure, and the distance between the side surfaces of the embedded circuit system is less than the distance between the side surfaces of the interposer structure in a direction horizontal to the bottom surface of the interposer structure.

11. The semiconductor device package of claim 1, wherein the plurality of semiconductor chips includes a first semiconductor chip disposed on a first layer of the plurality of layers and a second semiconductor chip disposed on a second layer of the plurality of layers, wherein the first layer and the second layer are at different elevations, and wherein the upper surface of the first semiconductor chip and the upper surface of the second semiconductor chip are coplanar.

12. The semiconductor device package of claim 1, wherein the interposer structure includes a dummy conductive via through the interposer structure and having a first end exposed from the bottom surface of the interposer structure, wherein the first end of the dummy conductive via is not in contact with any conductive material, wherein the dummy conductive via provides a thermal path for at least one of the plurality of semiconductor chips.

13. The semiconductor device package of claim 1, wherein the interposer structure comprises: An electronic circuit structure, wherein the electronic circuit structure is adjacent to the bottom surface of the interposer structure, and wherein the electronic circuit structure penetrates the at least one conductive via.

14. The semiconductor device package of claim 1, further comprising: A conductive component is disposed between the ladder interconnect structure and at least one of the plurality of semiconductor chips, wherein the conductive component is in direct contact with at least one conductive via and a thermally conductive virtual via.

15. A method for manufacturing a semiconductor device package, the method comprising: This forms a multi-layered intermediary structure; Multiple semiconductor chips are disposed on the multiple layers of the interposer structure, wherein the interposer structure includes at least one conductive via connected to a pad of the multiple semiconductor chips, and the interposer structure is a ladder interconnect structure having multiple steps at different elevations. as well as Multiple first electrical contacts are formed, comprising a first group and a second group at the same elevation, wherein the first group is in direct contact with the first semiconductor chip of the plurality of semiconductor chips and the interposer structure, and the second group is in direct contact with the first semiconductor chip and the second semiconductor chip of the plurality of semiconductor chips.

16. The method of claim 15, wherein forming the intermediary layer structure comprises: A dummy conductive via is formed, which passes through the interposer structure and has a first end exposed from the bottom surface of the interposer structure, wherein the first end of the dummy conductive via does not contact any conductive material.

17. The method of claim 15, further comprising: A power IC is disposed on the interposer structure, wherein the thickness of the power IC is greater than the thickness of the plurality of semiconductor chips.

18. The method of claim 15, further comprising: An embedded circuit system is formed in the interposer structure adjacent to the bottom surface of the interposer structure, wherein the width of the embedded circuit system is smaller than the width of the interposer structure in a direction horizontal to the bottom surface of the interposer structure.

19. The method of claim 15, wherein forming the intermediary layer structure comprises: Provides a silicon substrate; as well as The silicon substrate is partially removed to form a first layer and a second layer of the plurality of layers at different elevations, wherein the plurality of semiconductor chips include a first semiconductor chip disposed on the first layer and a second semiconductor chip disposed on the second layer, wherein the upper surface of the first semiconductor chip and the upper surface of the second semiconductor chip are coplanar.

20. The method of claim 19, further comprising: Multiple second electrical contacts are formed, including a third group and a fourth group at the same elevation, wherein the third group is in direct contact with the second semiconductor chip and the interposer structure, and the fourth group is in direct contact with the second semiconductor chip and a third semiconductor chip of the multiple semiconductor chips.

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