Display devices

Abstract

The present application relates to a display device. The display device includes: a base layer having a first region and a second region, the second region extending at least partially around a periphery of the first region; a conductive pattern located in the second region; an insulating layer located above the conductive pattern in the second region; a first electrode and a second electrode located on the insulating layer; and a plurality of light-emitting elements located between the first electrode and the second electrode in the first region and connected to the first electrode and the second electrode. The first electrode and the second electrode are spaced apart from each other in the first region and are respectively connected to portions of the conductive pattern through contact openings penetrating the insulating layer. The light-emitting elements do not overlap with the conductive pattern and the insulating layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0021714, filed on February 21, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure generally relate to display devices. Background Art

[0004] Recently, a technology for manufacturing micro-light-emitting elements using materials having a highly reliable inorganic crystal structure and a technology for manufacturing light-emitting devices using such light-emitting elements have been developed. For example, a technology for manufacturing light-emitting devices using micro-light-emitting elements having small dimensions (e.g., micrometer- or nanometer-scale dimensions) as light sources has been developed. Such light-emitting devices can be used in (or as) various types of electronic devices, such as display devices or lighting devices.

[0005] A planarization layer that flattens the pixel circuit layer for driving the micro-light-emitting elements may be formed to align the light-emitting elements, and a bank pattern may be formed on the planarized pixel circuit layer to allow light radiated from the light-emitting elements to be emitted forward. For example, additional processes for aligning and emitting light from the micro-light-emitting elements may be required, and the manufacturing process of the display device may be complicated. Summary of the Invention

[0006] Embodiments of the present disclosure provide a display device that can be manufactured through a simplified process.

[0007] According to an embodiment of the present disclosure, a display device includes: a base layer having a first region and a second region, the second region extending at least partially around a perimeter of the first region; a conductive pattern located in the second region; an insulating layer located above the conductive pattern in the second region; a first electrode and a second electrode located on the insulating layer; and a plurality of light-emitting elements located between the first electrode and the second electrode in the first region and connected to the first electrode and the second electrode. The first electrode and the second electrode are spaced apart from each other in the first region and are respectively connected to portions of the conductive pattern via contact openings penetrating the insulating layer. The light-emitting elements do not overlap with the conductive pattern and the insulating layer.

[0008] The display device may also include: a third electrode located on the first electrode and on one end of the light-emitting element to contact the first electrode and one end of the light-emitting element; and a fourth electrode located on the second electrode and on the other end of the light-emitting element to contact the second electrode and the other end of the light-emitting element.

[0009] The display device may further include an inorganic insulating layer on the base layer. At least one of the conductive patterns may be on the inorganic insulating layer. The insulating layer may have an opening exposing the inorganic insulating layer. The light-emitting element may be in the opening.

[0010] The insulating layer may not be between the base layer and the light emitting element.

[0011] A height of a top surface of the inorganic insulating layer located in the first region over the base layer may be smaller than (eg, lower than) a height of a top surface of the inorganic insulating layer located in the second region.

[0012] The inorganic insulating layer may include a first inorganic insulating layer, a second inorganic insulating layer, and a third inorganic insulating layer sequentially stacked on the base layer. The conductive pattern may include: a back gate electrode located between the base layer and the first inorganic insulating layer, the back gate electrode overlapping the semiconductor pattern; a gate electrode located on the first inorganic insulating layer, the gate electrode overlapping the semiconductor pattern; a first capacitor electrode located on the first inorganic insulating layer, the first capacitor electrode overlapping the back gate electrode; a second capacitor electrode located on the second inorganic insulating layer, the second capacitor electrode connected to a region of the semiconductor pattern via a contact opening penetrating the second inorganic insulating layer, the second capacitor electrode overlapping the first capacitor electrode; and a bridge pattern located on the third inorganic insulating layer, the bridge pattern connected to the second capacitor electrode via a contact opening penetrating the third inorganic insulating layer, the bridge pattern being connected to the first electrode via the contact opening penetrating the insulating layer.

[0013] The back gate electrode and the first capacitor electrode may form a first capacitor by overlapping each other, and the first capacitor electrode and the second capacitor electrode may form a second capacitor by overlapping each other.

[0014] The third electrode and the fourth electrode may be formed in the same layer.

[0015] The third electrode and the fourth electrode may be spaced apart from each other in different layers with a second insulating layer therebetween.

[0016] The conductive pattern may include first and second power lines spaced apart from each other along a first direction on a plane, the first and second power lines extending in a second direction intersecting the first direction. One of the first and second power lines may be connected to one of the first and second electrodes. At least a portion of the first region may be defined by the first and second power lines.

[0017] The display device may further include a semiconductor pattern connected to at least some of the conductive patterns. The semiconductor pattern may be located in the second region relative to the first region on a plane. The remaining portion of the first region may be defined by the semiconductor pattern.

[0018] Each of the first electrode and the second electrode may extend in the second direction on a plane and include a protruding portion that protrudes into the first region.

[0019] Each of the light emitting elements may be a rod-type light emitting diode having a size ranging from nanometer to micrometer.The light emitting elements may be arranged along a first direction on a plane.

[0020] The display device may further include an inorganic insulating layer on the base layer. At least one of the conductive patterns may be on the inorganic insulating layer. The insulating layer may include a first dam pattern and a second dam pattern, the first dam pattern and the second dam pattern being spaced apart from each other, and the first region being located between the first dam pattern and the second dam pattern. The inorganic insulating layer may be exposed through a space between the first dam pattern and the second dam pattern.

[0021] According to another embodiment of the present disclosure, a display device includes: a substrate having a plurality of pixel regions, each of the pixel regions having a first region and a second region extending around a perimeter of the first region; a conductive pattern including first and second lines as lines in the second region, the first and second lines being spaced apart from each other in a first direction and extending in a second direction intersecting the first direction; and a light-emitting element located in the first region, the light-emitting element being connected between the first and second lines. At least a portion of the first region is defined by the first and second lines, and the light-emitting element does not overlap with the conductive pattern.

[0022] The display device may further include an insulating layer covering the conductive pattern. The light emitting element may not overlap with the insulating layer.

[0023] The display device may further include a first electrode and a second electrode extending in the second direction, the first electrode and the second electrode being spaced apart from each other in the first region. The light emitting element may be connected between the first electrode and the second electrode. One of the first line and the second line may be connected to one of the first electrode and the second electrode.

[0024] The display device may further include: a third electrode overlapping one end of the light emitting element and the first electrode to contact the one end of the light emitting element and the first electrode; and a fourth electrode overlapping the other end of the light emitting element and the second electrode to contact the other end of the light emitting element and the second electrode.

[0025] Each of the light emitting elements may be a rod-type light emitting diode having a size ranging from nanometer to micrometer.The light emitting elements may be arranged along a first direction on a plane.

[0026] The display device may further include a transistor in the second direction relative to the first region, the transistor being connected to the other of the first line and the second line. The first region may also be defined by the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Now, exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings; however, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0028] Figure 1A is a view showing a light emitting element according to an embodiment of the present disclosure.

[0029] Figure 1B yes Figure 1A A cross-sectional view of the light emitting element shown in .

[0030] Figure 2A is a view showing a light emitting element according to another embodiment of the present disclosure.

[0031] Figure 2B yes Figure 2A A cross-sectional view of the light emitting element shown in .

[0032] Figure 3A is a view showing a light emitting element according to another embodiment of the present disclosure.

[0033] Figure 3B yes Figure 3A A cross-sectional view of the light emitting element shown in .

[0034] Figure 4A is a view showing a light emitting element according to another embodiment of the present disclosure.

[0035] Figure 4B yes Figure 4A A cross-sectional view of the light emitting element shown in .

[0036] Figure 5 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0037] Figure 6 It is shown that the Figure 5 A circuit diagram of an example of a pixel in a display device shown in FIG.

[0038] Figure 7 It is shown that the Figure 5 A plan view of an example of a pixel in a display device shown in FIG.

[0039] Figure 8 It shows Figure 7 0 is a plan view of an example of a first pixel among the pixels shown in .

[0040] Figures 9A to 9E It is shown that the Figure 8A plan view of the conductive layer and the semiconductor layer in the first pixel shown in FIG.

[0041] Figure 9F It shows Figure 7 0 is a plan view of an example of a first pixel among the pixels shown in .

[0042] Figure 10 yes Figure 9F An enlarged plan view of the first area shown in FIG.

[0043] Figure 11A and Figure 11B is shown along Figure 8 sectional views of an example of a first pixel taken along lines II′ and II-II′ shown in FIG.

[0044] Figures 11C to 11E is shown along Figure 8 2 is a cross-sectional view of another example of the first pixel taken along lines II′ and II-II′ shown in FIG.

[0045] Figure 12 is shown along Figure 8 FIG. 4 is a cross-sectional view of another example of the first pixel taken along line II-II′ shown in FIG. DETAILED DESCRIPTION

[0046] The present disclosure can be implemented in various variations and different shapes; therefore, the present disclosure describes exemplary embodiments in detail. However, the described examples do not limit the present disclosure to specific shapes, configurations, etc., but are applicable to all changes and equivalent materials and structures.

[0047] In the following embodiments and drawings, elements not directly related to the present disclosure may be omitted from the description for convenience, and the dimensional relationship between each element in the drawings may be illustrated for easy understanding, but the actual proportions are not limited.

[0048] It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may also be present. When an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. For example, when a first element is described as being “coupled to” or “connected to” a second element, the first element can be directly coupled or connected to the second element, or the first element can be indirectly coupled or connected to the second element via one or more intervening elements.

[0049] The same reference numerals represent the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. In addition, when describing embodiments of the present invention, the use of "may" relates to "one or more embodiments of the present invention". When located after the element of a list, expressions such as "at least one of ... " modify the elements of the entire list without modifying the individual elements in the list. In addition, the term "exemplary" is intended to represent an example or illustration. As used herein, the terms "use (use)", "use (using)" and "use (used)" can be considered to be synonymous with the terms "utilize (utilize)", "utilize (utilizing)" and "utilized (utilized)" respectively. As used herein, the terms "substantially", "about" and similar terms are used as approximate terms and not as degree terms, and are intended to leave a margin for the inherent deviation in the measured value or calculated value recognized by those of ordinary skill in the art.

[0050] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of exemplary embodiments, the first element, first component, first region, first layer or first part discussed below can be referred to as the second element, second component, second region, second layer or second part.

[0051] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is flipped, the elements described as "below" or "below" other elements or features will then be oriented "above" or "above" the other elements or features. Thus, the term "below" can include both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0052] The terms used herein are for the purpose of describing specific exemplary embodiments of the present invention and are not intended to limit the described exemplary embodiments of the present invention. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that when used in this specification, the terms "includes," "including," "comprises," and / or "comprising" specify the presence of the features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof.

[0053] Figure 1A is a view showing a light emitting element according to an embodiment of the present disclosure, and Figure 1B yes Figure 1A A cross-sectional view of the light emitting element shown in . Figure 2A is a view showing a light emitting element according to another embodiment of the present disclosure, and Figure 2B yes Figure 2A A cross-sectional view of the light emitting element shown in . Figure 3A is a view showing a light emitting element according to another embodiment of the present disclosure, and Figure 3B yes Figure 3A A cross-sectional view of the light emitting element shown in . Figure 4A is a view showing a light emitting element according to another embodiment of the present disclosure, and Figure 4B yes Figure 4A A cross-sectional view of the light emitting element shown in .

[0054] The following will describe Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3B , Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3B Each of the diagrams shows a light emitting element manufactured by an etching process, and the following will also describe Figure 4A and Figure 4B , Figure 4A and Figure 4B The light emitting element manufactured by the growth process is shown. Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4Aand Figure 4B The type and / or shape of the light emitting element shown in .

[0055] First, refer to Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3B , each light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In an example, the light emitting element LD may be implemented as a light emitting stacked structure in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0056] In an embodiment, the light emitting element LD may have a shape extending in one direction. When the extending direction of the light emitting element LD is the longitudinal direction, the light emitting element LD may have one end and the other end along the extending direction. Either the first semiconductor layer 11 or the second semiconductor layer 13 may be provided at one end of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the other end of the light emitting element LD.

[0057] The light-emitting element LD may have various suitable shapes. For example, the light-emitting element LD may have a rod-like shape or a bar-like shape, and the light-emitting element LD is long (for example, slender or extended in its length direction) (i.e., has an aspect ratio greater than 1) in its length direction. For example, the length L of the light-emitting element LD in the length direction may be greater than the diameter D (or the width of the cross section) of the light-emitting element LD. The light-emitting element LD may include a light-emitting diode that is manufactured small enough to have a diameter D and / or length L in the micrometer or nanometer order. However, throughout the present disclosure, the size of the light-emitting element LD may be modified to be suitable for the requirements (or design conditions) of the lighting device or self-luminous display device to which the light-emitting element LD is applied.

[0058] The first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include any one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor layer doped with a first conductive dopant (such as Si, Ge, or Sn). However, the first semiconductor layer 11 is not limited to the above materials. The first semiconductor layer 11 may be configured with various suitable materials (for example, may include various suitable materials or may be formed of various suitable materials).

[0059] The active layer 12 is formed on the first semiconductor layer 11 and can be formed as a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 can be appropriately changed in various ways depending on the type of the light-emitting element LD. The active layer 12 can emit light with a wavelength in the range of 400nm to 900nm, and a double heterostructure can be used. A cladding layer doped with a conductive dopant can be formed on the top and / or bottom of the active layer 12. In an example, the cladding layer can be formed as an AlGaN layer or an InAlGaN layer. In some embodiments, materials such as AlGaN or AlInGaN can be used to form the active layer 12. In addition, the active layer 12 can be configured with various suitable materials.

[0060] When an electric field having a reference voltage or greater (e.g., a predetermined voltage or greater) is applied to both ends of the light-emitting element LD (or applied between the two ends), the light-emitting element LD emits light as electron-hole pairs recombine in the active layer 12. By using this principle to control the light emission of the light-emitting element LD, the light-emitting element LD can be used as a light source for various light-emitting devices, which are included in pixels of a display device.

[0061] The second semiconductor layer 13 is formed on the active layer 12 and may include a semiconductor layer having a different type from that of the first semiconductor layer 11. The second semiconductor layer 13 may include at least one p-type semiconductor material. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (such as Mg). However, the second semiconductor layer 13 is not limited to the above materials. The second semiconductor layer 13 may be configured with various suitable materials.

[0062] In the embodiment of the present disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different lengths (or thicknesses) in the length direction of the light emitting element LD. In an example, along the length direction of the light emitting element LD, the first semiconductor layer 11 may have a length (or thickness) that is relatively longer (or thicker) than the length (or thickness) of the second semiconductor layer 13. Figures 1A to 3B As shown in , the active layer 12 of the light emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11 .

[0063] In an embodiment, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 described above, the light emitting element LD may further include an additional electrode 15 disposed on top of the second semiconductor layer 13. In some embodiments, as Figure 3A and Figure 3BAs shown in , the light emitting element LD may further include another additional electrode 16 provided at one end of the first semiconductor layer 11 .

[0064] The additional electrodes 15 and 16 may be ohmic contact electrodes, but the present disclosure is not limited thereto. In some embodiments, the additional electrodes 15 and 16 may be Schottky contact electrodes. The additional electrodes 15 and 16 may include a metal or a metal oxide. For example, the additional electrodes 15 and 16 may include chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), ITO, any oxides or alloys thereof, or a mixture of the foregoing materials, but the present disclosure is not limited thereto.

[0065] The materials included in the additional electrodes 15 and 16, respectively, may be the same as or different from each other (for example, the additional electrodes 15 and 16 may include the same material or different materials). The additional electrodes 15 and 16 may be substantially transparent or translucent. Therefore, light generated in the light-emitting element LD can be emitted to the outside of the light-emitting element LD by passing through the additional electrodes 15 and 16. In some embodiments, the additional electrodes 15 and 16 may include an opaque metal so that light generated in the light-emitting element LD does not pass through the additional electrodes 15 and 16 and is emitted to the outside of the light-emitting element LD through regions other than the two end portions of the light-emitting element LD.

[0066] In an embodiment, the light emitting element LD may further include an insulating film 14. However, in some embodiments, the insulating film 14 may be omitted or provided to cover only portions of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0067] The insulating film 14 can prevent or substantially prevent an electrical short circuit that may occur when the active layer 12 of one light-emitting element LD contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the insulating film 14 is formed so as to reduce or minimize surface defects on (or in) the light-emitting element LD, thereby improving the lifespan and efficiency of the light-emitting element LD. In addition, when a plurality of light-emitting elements LD are densely arranged, the insulating film 14 can prevent or substantially prevent an undesirable short circuit that may occur between the light-emitting elements LD. Whether or not the insulating film 14 is provided is not limited (for example, the insulating film 14 can be omitted), as long as the active layer 12 is prevented or substantially prevented from shorting with an external conductive material.

[0068] like Figure 1A and Figure 1B As shown in , the insulating film 14 may be provided to completely surround the periphery of the light emitting stacked structure including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and the additional electrode 15. For ease of description, Figure 1AThe insulating film 14 shown in the figure has a cut-away portion showing the underlying layers, and the first semiconductor layer 11, active layer 12, second semiconductor layer 13 and additional electrode 15 included in the actual light-emitting element LD may be surrounded by the insulating film 14 (e.g., completely surrounded along the periphery thereof).

[0069] Although an embodiment in which the insulating film 14 is provided in a shape completely surrounding the periphery of each of the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the additional electrode 15 is described in the above embodiment, the present disclosure is not limited thereto.

[0070] In some embodiments, as Figure 2A and Figure 2B As shown in , the insulating film 14 may surround the periphery of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, but may not surround (or may not completely surround) the periphery of the additional electrode 15 provided on the second semiconductor layer 13. In other embodiments, the insulating film 14 may surround only a portion of the periphery of the additional electrode 15, and may not surround (e.g., may expose) another portion of the periphery of the additional electrode 15. However, the insulating film 14 may expose at least two ends of the light emitting element LD. In an example, the insulating film 14 may expose one end of the first semiconductor layer 11 and the additional electrode 15 provided at one end of the second semiconductor layer 13. In some embodiments, as Figure 3A and Figure 3B As shown in , when the additional electrodes 15 and 16 are provided at opposite ends of the light emitting element LD, the insulating film 14 may expose at least one region of each of the additional electrodes 15 and 16. In another embodiment, the insulating film 14 may be omitted.

[0071] According to an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include at least one insulating material selected from the group consisting of SiO2, Si3N4, Al2O3, and TiO2. However, the present disclosure is not limited thereto, and the insulating film 14 may include various suitable materials having insulating properties.

[0072] When the insulating film 14 is provided in the light-emitting element LD, a short circuit between the active layer 12 and the first electrode and / or the second electrode can be prevented (or substantially prevented). In addition, the insulating film 14 is formed so as to reduce or minimize surface defects in the light-emitting element LD, thereby improving the lifespan and efficiency of the light-emitting element LD. In addition, when a plurality of light-emitting elements LD are densely arranged, the insulating film 14 can prevent (or substantially prevent) undesirable short circuits that may occur between the light-emitting elements LD.

[0073] The light-emitting element LD can be used as a light source for various display devices. The light-emitting element LD can be manufactured by a surface treatment process. For example, when a plurality of light-emitting elements LD are mixed in a liquid solution (or solvent) to be provided to each light-emitting area (e.g., the light-emitting area of ​​each pixel or the light-emitting area of ​​each sub-pixel), each light-emitting element LD can be surface-treated so that the light-emitting element LD is not unevenly aggregated in the solution, but is uniformly (or substantially uniformly) dispersed in the solution.

[0074] A light-emitting device including a light-emitting element LD can be used in various types of equipment (including display devices) that require a light source. When multiple light-emitting elements LD are arranged in the light-emitting region of each pixel of a display panel, the light-emitting element LD can serve as the light source of the pixel. However, the application areas of the light-emitting element LD are not limited to the above examples. For example, the light-emitting element LD can be used in other types of equipment (such as lighting equipment) that require a light source.

[0075] Next, we will refer to Figure 4A and Figure 4B The light-emitting element LD manufactured by the growth process is described.

[0076] In the following description of the light-emitting element LD manufactured by the growth process, aspects and features of the light-emitting element LD that are different from those of the above-described embodiment will be mainly described to avoid redundancy. Aspects and features of the light-emitting element LD manufactured by a growth process not specifically described are the same as or substantially similar to those of the above-described embodiment. Components similar to and / or identical to those of the above-described embodiment are denoted by the same reference numerals.

[0077] Reference Figure 4A and Figure 4B The light emitting element LD according to an embodiment of the present disclosure includes a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In some embodiments, the light emitting element LD may include a light emitting pattern 10 having a core-shell structure, the light emitting pattern 10 including the first semiconductor layer 11 at the center thereof, the active layer 12 surrounding at least one side of the first semiconductor layer 11, the second semiconductor layer 13 surrounding at least one side of the active layer 12, and the additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0078] In an embodiment, the first semiconductor layer 11 may be located at the core (e.g., the center (or middle)) of the light emitting element LD. The light emitting element LD may have a shape corresponding to the shape of the first semiconductor layer 11. In an example, when the first semiconductor layer 11 has a hexagonal pyramid shape, the light emitting element LD and the light emitting pattern 10 may also have a hexagonal pyramid shape.

[0079] The active layer 12 may be provided and / or formed in a shape surrounding the outer periphery of the first semiconductor layer 11 in the longitudinal direction of the light emitting element LD. For example, the active layer 12 may be provided and / or formed in a shape surrounding the other region between the two end portions of the first semiconductor layer 11 except for the other end portion provided at the lower side in the longitudinal direction of the light emitting element LD.

[0080] The second semiconductor layer 13 may be disposed and / or formed in a shape surrounding the active layer 12 in the length direction of the light emitting element LD, and may include a semiconductor layer having a different type from that of the first semiconductor layer 11. In an example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

[0081] In an embodiment, the light emitting element LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 may be an ohmic contact electrode or a Schottky contact electrode electrically connected to the second semiconductor layer 13, but the present disclosure is not limited thereto.

[0082] As described above, the light emitting element LD may have a hexagonal pyramid shape having two protruding ends, and may include a light emitting pattern 10 having a core-shell structure, the light emitting pattern 10 including a first semiconductor layer 11 located at the center thereof, an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The first semiconductor layer 11 may be provided at one end (or lower end) of the light emitting element LD having the hexagonal pyramid shape, and the additional electrode 15 may be provided at the other end (or upper end) of the light emitting element LD.

[0083] In some embodiments, the light emitting element LD may further include an insulating film 14 disposed on the outer circumference of the light emitting pattern 10 having the core-shell structure. The insulating film 14 may include a transparent insulating material.

[0084] Figure 5 is a plan view showing a display device according to an embodiment of the present disclosure. In some embodiments, a display device (eg, a display panel PNL provided in the display device) is shown as being capable of being used. Figures 1A to 4B The light emitting element LD described in the embodiment is an example of a device as a light source. In some embodiments, the structure of the display panel PNL is briefly shown based on the display area DA. In some embodiments, at least one driving circuit (e.g., a scan driver and a data driver) and / or multiple lines may also be provided in the display panel PNL.

[0085] Reference Figure 5The display panel PNL may include a base layer SUB (or substrate) and pixels PXL (or subpixels) arranged on the base layer SUB. The display panel PNL and the base layer SUB may have a display area DA in which an image is displayed and a non-display area NDA other than the display area DA.

[0086] In some embodiments, the display area DA is disposed in the central area of ​​the display panel PNL, and the non-display area NDA may be disposed along the edge of the display panel PNL to surround the display area DA (e.g., around the periphery of the display area DA). However, the positions of the display area DA and the non-display area NDA are not limited thereto and may be appropriately changed.

[0087] The base layer SUB may be a base member of the display panel PNL. For example, the base layer SUB may be a base member of a lower panel (eg, a lower plate of the display panel PNL).

[0088] In some embodiments, the base layer SUB may be a rigid substrate or a flexible substrate, so that the material and / or physical properties of the base layer SUB are not particularly limited. In an embodiment, the base layer SUB may be a rigid substrate including glass or tempered glass (or made of glass or tempered glass), and in other embodiments, the base layer SUB may be a flexible substrate including a film including plastic or metal (or made of plastic or metal). In addition, the base layer SUB may be a transparent substrate, but the present disclosure is not limited thereto. In an example, the base layer SUB may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0089] One area on the base layer SUB is defined as a display area DA, and the pixels PXL are arranged in the display area DA. The other area is defined as a non-display area NDA. In an example, the base layer SUB may have a display area DA and a non-display area NDA disposed around the display area DA. The display area DA includes a plurality of pixel areas in which the pixels PXL are formed. Various lines connected to the pixels PXL in the display area DA and / or one or more built-in circuits may be disposed in the non-display area NDA.

[0090] The pixels PXL may each include at least one light emitting element LD (eg, according to Figures 1A to 4B At least one light-emitting element LD is driven by a corresponding scan signal and a corresponding data signal. For example, a pixel PXL may include multiple rod-type LEDs having nanometer- to micrometer-scale dimensions and connected in parallel. These multiple rod-type LEDs may form the light source of the pixel PXL.

[0091] Despite Figure 5, the pixels PXL are arranged in a stripe shape, but the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in various suitable pixel arrangement forms.

[0092] Figure 6 It is shown that the Figure 5 A circuit diagram of an example of a pixel in a display device shown in FIG.

[0093] Reference Figure 6 The pixel PXL may include a light emitting unit EMU and a pixel driving circuit DC for driving the light emitting unit EMU.

[0094] The light emitting unit EMU may be connected between a first power supply VDD (or a first driving power supply) and a second power supply VSS (or a second driving power supply). The light emitting unit EMU may include a plurality of light emitting elements LD connected in parallel between the first power supply VDD (or a first power line PL1 to which the first power supply VDD is applied) and the second power supply VSS (or a second power line PL2 to which the second power supply VSS is applied).

[0095] The light emitting unit EMU may include a first electrode ELT1 (or a first alignment electrode) connected to a first power supply VDD via a pixel driving circuit DC, a second electrode ELT2 (or a second alignment electrode) connected to a second power supply VSS, and a plurality of light emitting elements LD connected in parallel between the first electrode ELT1 and the second electrode ELT2 in the same direction. For example, the first electrode ELT1 may be an anode electrode, and the second electrode ELT2 may be a cathode electrode.

[0096] Each of the light-emitting elements LD included in the light-emitting unit EMU may include a first end connected to a first power source VDD via a first electrode ELT1 and a second end connected to a second power source VSS via a second electrode ELT2. The first power source VDD may be a high potential power source, and the second power source VSS may be a low potential power source. During the emission period of the pixel PXL, the potential difference between the first power source VDD and the second power source VSS may be set to a threshold voltage of the light-emitting element LD or greater.

[0097] As described above, the light emitting elements LD connected in parallel between the first electrode ELT1 and the second electrode ELT2 , which are respectively supplied with voltages having different potentials, in the same direction (eg, forward direction) may form an effective light source.

[0098] The light-emitting elements LD of the light-emitting units EMU can emit light having a brightness corresponding to the drive current supplied by the corresponding pixel drive circuit DC. For example, the pixel drive circuit DC can supply a drive current corresponding to the grayscale value of the corresponding frame data to the light-emitting units EMU during each frame period. The drive current supplied to the light-emitting units EMU can be divided and flowed through the light-emitting elements LD connected in the same direction. Therefore, when each light-emitting element LD emits light having a brightness corresponding to the current flowing through it, the light-emitting units EMU emit light having a brightness corresponding to the drive current.

[0099] In some embodiments, in addition to the light-emitting elements LD forming the corresponding effective light sources, the light-emitting unit EMU may further include at least one ineffective light source. For example, at least one light-emitting element LDr (hereinafter referred to as "reverse light-emitting element LDr") may be reversely connected between the first electrode ELT1 and the second electrode ELT2 of the light-emitting unit EMU. The reverse light-emitting element LDr is connected in parallel between the first electrode ELT1 and the second electrode ELT2 together with the light-emitting element LD forming the effective light source, but the reverse light-emitting element LDr may be connected between the first electrode ELT1 and the second electrode ELT2 in a direction opposite to the direction in which the light-emitting element LD is connected. Although a reference driving voltage (e.g., a forward driving voltage) is applied between the first electrode ELT1 and the second electrode ELT2, the reverse light-emitting element LDr may remain in an inactive state (e.g., may not emit light), and therefore, no current may flow (or substantially no current may flow) through the reverse light-emitting element LDr.

[0100] In an embodiment of the present disclosure, the pixel driving circuit DC may include a first transistor M1, a second transistor M2, a third transistor M3, and a storage capacitor Cst.

[0101] A first electrode of a first transistor (e.g., a driving transistor) M1 may be connected to a first power supply VDD, and a second electrode of the first transistor M1 may be electrically connected to a first electrode ELT1 of the light emitting unit EMU. A gate electrode of the first transistor M1 may be connected to a first node N1. The first transistor M1 may control the amount of driving current supplied to the light emitting element LD in accordance with the voltage at the first node N1.

[0102] In addition, the first transistor M1 may further include a back gate electrode connected to the first electrode ELT1. The back gate electrode may be provided to overlap with the gate electrode with an insulating layer interposed therebetween, forming (or constituting) a body of the first transistor M1 and serving as a gate electrode.

[0103] A first electrode of a second transistor (e.g., a switching transistor) M2 may be connected to a data line DL, and a second electrode of the second transistor M2 may be connected to a first node N1. The first electrode and the second electrode of the second transistor M2 are different electrodes. For example, when the first electrode is a source electrode, the second electrode may be a drain electrode. A gate electrode of the second transistor M2 may be connected to a scan line SL.

[0104] When a scan signal having a voltage (e.g., a gate-on voltage) at which the second transistor M2 can be turned on is supplied from the scan line SL, the second transistor M2 can be turned on to electrically connect the data line DL and the first node N1. A data signal of a corresponding frame can be supplied to the data line DL. Thus, the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be stored in the storage capacitor Cst.

[0105] One electrode of the storage capacitor Cst may be connected to the first node N1, and the other electrode of the storage capacitor Cst may be connected to the first electrode ELT1 of the light emitting unit EMU (or the second electrode of the first transistor M1). The storage capacitor Cst may be charged with a voltage corresponding to the data signal supplied to the first node N1 and may maintain the charged voltage until a data signal of the next frame is supplied.

[0106] The gate electrode of the third transistor M3 can be connected to the sensing signal line SSL. One electrode of the third transistor M3 can be connected to the sensing line SENL, and the other electrode of the third transistor M3 can be connected to the first electrode ELT1 of the light-emitting unit EMU. The third transistor M3 can transmit the voltage (e.g., voltage value) at the first electrode ELT1 of the light-emitting unit EMU (or the voltage at the anode electrode of the light-emitting element LD) to the sensing line SENL based on the sensing signal provided to the sensing signal line SSL during the sensing period. The voltage transmitted through the sensing line SENL can be provided to an external circuit (e.g., a timing controller), and the external circuit can extract characteristic information of the pixel PXL (e.g., the threshold voltage of the first transistor M1, etc.) based on the provided voltage value. The extracted characteristic information can be used to convert image data, thereby compensating for characteristic variations of the pixel PXL.

[0107] For ease of description, although Figure 6 , an embodiment in which the pixel PXL includes three transistors and one capacitor is shown, but the present disclosure is not limited thereto. In other embodiments, various appropriate modifications may be made to the structure of the pixel driving circuit DC. In this example, the pixel driving circuit DC may additionally include various suitable transistors, such as an initialization transistor for initializing the first node N1 and / or an emission control transistor for controlling the emission time of the light-emitting element LD, or other circuit elements such as a boost capacitor for boosting the voltage at the first node N1.

[0108] Despite Figure 6 , all transistors included in the pixel driving circuit DC (e.g., the first transistor M1, the second transistor M2, and the third transistor M3) are N-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor M1, the second transistor M2, and the third transistor M3 included in the pixel driving circuit DC may be changed to a P-type transistor.

[0109] Figure 7 It is shown that the Figure 5 A plan view of an example of a pixel in a display device shown in FIG. Based on a pixel driving circuit DC (see, for example, FIG. 1 ) driving a light emitting element LD. Figure 6 ),exist Figure 7 Shown in Figure 5 The structure of the pixel PXL in the area AA is shown in FIG. Figure 8 It shows Figure 7 0 is a plan view of an example of a first pixel among the pixels shown in . Figures 9A to 9E It shows Figure 8 A plan view of the conductive layer and the semiconductor layer of the first pixel shown in FIG. Figure 9F It shows Figure 7 0 is a plan view of an example of a first pixel among the pixels shown in . Figure 10 yes Figure 9F Based on the light emitting element LD, in Figure 10 The structure of the pixel PXL is shown in FIG. Figure 11A and Figure 11B is shown along Figure 8 sectional views of an example of a first pixel taken along lines II′ and II-II′ shown in FIG.

[0110] First, refer to Figure 7 Region AA may include a first pixel PXL1 (or a first pixel region PXA1), a second pixel PXL2 (or a second pixel region PXA2), and a third pixel PXL3 (or a third pixel region PXA3). The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may together form (or constitute) a unit pixel PXL.

[0111] In some embodiments, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can emit light of different colors. In an example, the first pixel PXL1 can be a red pixel that emits red light, the second pixel PXL2 can be a green pixel that emits green light, and the third pixel PXL3 can be a blue pixel that emits blue light. However, the color, type, and / or number of pixels that make up a unit pixel are not particularly limited. In an example, the color of light emitted from each pixel can be changed differently. In some embodiments, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can emit light of the same color. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be blue pixels that emit blue light.

[0112] The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 are identical to or substantially similar to each other. Therefore, hereinafter, the first pixel PXL1 will be described as an example.

[0113] Reference Figure 8 and Figure 11A , the first pixel PXL1 (or the base layer SUB) may have a first area A1 located at a central portion of the first pixel area PXA1 and a second area A2 surrounding the first area A1.

[0114] The first pixel PXL1 may include a first conductive layer BML, a buffer layer BFL, a semiconductor layer, a first insulating layer GI, a second conductive layer GAT, a second insulating layer ILD1, a third conductive layer SD1, a third insulating layer ILD2, a fourth conductive layer SD2, and a fourth insulating layer (eg, a protective layer) PW. Figure 11A As shown in FIG, the first conductive layer BML, the buffer layer BFL, the semiconductor layer, the first insulating layer GI, the second conductive layer GAT, the second insulating layer ILD1, the third conductive layer SD1, the third insulating layer ILD2, the fourth conductive layer SD2, and the fourth insulating layer PW may be sequentially stacked on the base layer SUB. In addition, the first conductive layer BML, the semiconductor layer, the second conductive layer GAT, the third conductive layer SD1, and the fourth conductive layer SD2 may be provided only at the second area A2 of the base layer SUB and may not overlap with the first area A1 (or extend into the first area A1).

[0115] The first conductive layer BML may be disposed at the second area A2 of the base layer SUB and include a back gate electrode BGE, a first capacitor electrode Cst_E1 , and a horizontal sensing line SENL_H.

[0116] like Figure 8 and Figure 9AAs shown in FIG, the back gate electrode BGE may be located at the lower side of the first region A1 on a plane and may completely cover the first transistor M1, which will be described in more detail below. The back gate electrode BGE may be the same as that described above with reference to FIG. Figure 6 The described back-gate electrodes are substantially the same and may form the back-gate electrode of the first transistor M1 .

[0117] The first capacitor electrode Cst_E1 may extend from the back gate electrode BGE in the second direction DR2 and may be disposed at the right side of the first area A1 on a plane. The first capacitor electrode Cst_E1 may form the above reference Figure 6 The other electrode of the storage capacitor Cst is described.

[0118] The horizontal sensing line SENL_H may be spaced apart from the back gate electrode BGE and may be disposed at the lowermost side of the first pixel region PXA1 in a plane. The horizontal sensing line SENL_H may extend in a first direction DR1 and may extend across the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be connected to one (e.g., the same) horizontal sensing line SENL_H.

[0119] The first conductive layer BML may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer BML may have a single-layer structure or a multi-layer structure.

[0120] Back to reference Figure 11A The buffer layer (BFL) may be disposed over the entire surface of the base layer (SUB). The buffer layer (BFL) may prevent (or substantially prevent) the diffusion of impurity ions and the penetration of moisture and / or external air, and may also perform a surface planarization function. The buffer layer (BFL) may include silicon nitride, silicon oxide, silicon oxynitride, or the like. Depending on the type of base layer (SUB) (e.g., the material of the base layer (SUB)), process conditions, and the like, the buffer layer (BFL) may be omitted.

[0121] The semiconductor layer may be disposed on the buffer layer BFL (or on the base layer SUB when the buffer layer BFL is omitted). The semiconductor layer may be an active layer forming channels of the first transistor M1, the second transistor M2, and the third transistor M3.

[0122] The semiconductor layer may include a first semiconductor pattern ACT1 , a second semiconductor pattern ACT2 , and a third semiconductor pattern ACT3 spaced apart from each other.

[0123] Reference Figure 8 and Figure 9B The first semiconductor pattern ACT1 may be located at a lower side of the first area A1 in plane, and may form a channel of the first transistor M1.

[0124] The second semiconductor pattern ACT2 may be located at an upper side of the first area A1 in plane and may form a channel of the second transistor M2. The second semiconductor pattern ACT2 may be adjacent to an upper side (eg, an upper edge) of the first area A1 and may define an upper side of the first area A1.

[0125] The third semiconductor pattern ACT3 may be located at a lower side of the first area A1 in plane. The third semiconductor pattern ACT3 may be located at a lower side of the first semiconductor pattern ACT1 and may form a channel of the third transistor M3.

[0126] Each of the first, second, and third semiconductor patterns ACT1, ACT2, and ACT3 may include a source region and a drain region, respectively contacting a first transistor electrode (or source electrode) and a second transistor electrode (or drain electrode).

[0127] The semiconductor layer may include an oxide semiconductor. The channel region of the semiconductor pattern is a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The source region and the drain region may be semiconductor patterns doped with impurities (e.g., n-type impurities). In some embodiments, the semiconductor layer may include a silicon semiconductor. For example, the semiconductor layer may be a semiconductor pattern including polycrystalline silicon, amorphous silicon, low-temperature polycrystalline silicon (LTPS), etc. (or made of polycrystalline silicon, amorphous silicon, low-temperature polycrystalline silicon (LTPS), etc.).

[0128] Return Reference Figure 11A A first insulating layer (e.g., a gate insulating layer) GI may be provided on the semiconductor layer and the buffer layer BFL (or the base layer SUB). The first insulating layer GI may be provided (e.g., substantially provided) to extend over the entire surface of the base layer SUB. The first insulating layer GI may be a gate insulating layer having a gate insulating function.

[0129] The first insulating layer GI may include an inorganic insulating material such as a silicon compound or a metal oxide. For example, the first insulating layer GI may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or any combination thereof. The first insulating layer GI may be a single layer or a multilayer structure in which layers including (or made of) different materials are stacked.

[0130] The second conductive layer GAT may be disposed on the first insulating layer GI. The second conductive layer GAT may include the scan line SL, the second capacitor electrode Cst_E2, the sensing signal line SSL, and the first power line PL1 (and / or the second power line PL2).

[0131] Reference Figure 8 and Figure 9C The scan line SL may extend in the first direction DR1 and may extend all the way to another unit pixel region. The scan line SL is located at the upper side of the first area A1 in a plane and may be disposed at the uppermost side of the first pixel region PXA1. The scan line SL may overlap with the second semiconductor pattern ACT2 and may form a gate electrode of the second transistor M2.

[0132] The second capacitor electrode Cst_E2 may extend in the second direction DR2 and may be disposed at the right side of the first area A1 on a plane. The second capacitor electrode Cst_E2 may overlap with the first capacitor electrode Cst_E1 and may form a storage capacitor Cst (eg, see Figure 6 ). In addition, the second capacitor electrode Cst_E2 may overlap the first semiconductor pattern ACT1 and may form a gate electrode of the first transistor M1.

[0133] The sensing signal line SSL may extend in the first direction DR1 and may extend all the way to another unit pixel region. The sensing signal line SSL may be disposed at a lower side of the first area A1 on a plane. The sensing signal line SSL may overlap the third semiconductor pattern ACT3 and may form a gate electrode of the third transistor M3.

[0134] The first power line PL1 (and / or the second power line PL2) may extend in the first direction DR1 and may extend all the way to another unit pixel region. The first power line PL1 (and / or the second power line PL2) may be disposed at the lower side of the first area A1 on a plane and may be disposed at the lowermost side of the first pixel region PXA1.

[0135] The first power line (eg, first horizontal power line) PL1 and the second power line (eg, second horizontal power line) PL2 (eg, see Figure 6 ) may be alternately and repeatedly arranged along the second direction DR2. For example, the first power line PL1 may be disposed at a lower portion of the first pixel region PXA1, and the second power line PL2 may be located outside the first pixel region PXA1 while being adjacent to an upper portion of the first pixel region PXA1.

[0136] The first power line PL1 and the second power line PL2 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first power line PL1 and the second power line PL2 may have a single-layer structure or a multi-layer structure.

[0137] Return Reference Figure 11A The second insulating layer (e.g., interlayer insulating layer) ILD1 may be disposed on the second conductive layer GAT and may be disposed (e.g., substantially disposed) across the entire surface of the base layer SUB. The second insulating layer ILD1 may be an interlayer insulating layer that insulates the second conductive layer GAT and the third conductive layer SD1 from each other.

[0138] The second insulating layer ILD1 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide. However, the present disclosure is not limited thereto, and the second insulating layer ILD1 may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The second insulating layer ILD1 may be a single layer or may have a multilayer structure in which layers including (or made of) different materials are stacked.

[0139] The third conductive layer SD1 may be disposed on the second insulating layer ILD1 and may include a third capacitor electrode Cst_E3, a data line DL, a vertical sensing line SENL_V, and first, second, third, fourth, and fifth bridge patterns BRP1, BRP2, BRP3, BRP4, and BRP5.

[0140] Reference Figure 8 and Figure 9D, the third capacitor electrode Cst_E3 can be arranged to overlap with the second capacitor electrode Cst_E2 (and the first capacitor electrode Cst_E1). The third capacitor electrode Cst_E3, together with the first capacitor electrode Cst_E1, can form another electrode of the storage capacitor Cst. For example, the storage capacitor Cst can include a first capacitor formed by the second capacitor electrode Cst_E2 and the first capacitor electrode Cst_E1, and a second capacitor formed by the second capacitor electrode Cst_E2 and the third capacitor electrode Cst_E3, and the first capacitor and the second capacitor can be connected in parallel to each other. The overlapping structure of the first capacitor electrode Cst_E1, the second capacitor electrode Cst_E2, and the third capacitor electrode Cst_E3 can ensure sufficient capacitance of the storage capacitor Cst in the limited space outside the first area A1.

[0141] The data line DL may extend in the second direction DR2 and may extend all the way to another unit pixel region. The data line DL may be disposed on the left side of the first area A1. The data line DL may overlap with a portion of the second semiconductor pattern ACT2 (or the source region of the second transistor M2) and may be connected to a portion of the second semiconductor pattern ACT2 through a contact opening (e.g., a contact hole) CNT. A portion of the data line DL may form a first transistor electrode of the second transistor M2.

[0142] The vertical sensing line SENL_V may extend in the second direction DR2 and may extend all the way to another unit pixel region. The vertical sensing line SENL_V may be disposed to the left of the first area A1 (and the data line DL) and may be disposed for each unit pixel including the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The vertical sensing line SENL_V may overlap with the horizontal sensing line SENL_H and may be connected to the horizontal sensing line SENL_H exposed through the contact opening CNT.

[0143] The first bridge pattern BRP1 may be provided at the upper side of the first area A1. The first bridge pattern BRP1 may overlap with a partial area of ​​the second semiconductor pattern ACT2 (or the drain area of ​​the second transistor M2), may be connected to a partial area of ​​the second semiconductor pattern ACT2 exposed by the contact opening (e.g., contact hole) CNT, and may form a second transistor electrode of the second transistor M2. In addition, the first bridge pattern BRP1 may overlap with the second capacitor electrode Cst_E2 and may be connected to the second capacitor electrode Cst_E2 through the contact opening (e.g., contact hole) CNT. Therefore, the second transistor electrode of the second transistor M2 may be connected to the second capacitor electrode Cst_E2 (i.e., the storage capacitor Cst (e.g., see Figure 6 ) of the other electrode).

[0144] The second bridge pattern BRP2 may extend downward from the third capacitor electrode Cst_E3 and may overlap with a portion of the first semiconductor pattern ACT1 (or the drain region of the first transistor M1) and a portion of the third semiconductor pattern ACT3 (or the source region of the third transistor M3). The second bridge pattern BRP2 may be connected to a portion of the first semiconductor pattern ACT1 exposed by the contact opening (e.g., contact hole) CNT and may form the second transistor electrode of the first transistor M1. Furthermore, the second bridge pattern BRP2 may be connected to a portion of the third semiconductor pattern ACT3 exposed by the contact opening (e.g., contact hole) CNT and may form the first transistor electrode of the third transistor M3.

[0145] In addition, the second bridge pattern BRP2 may be connected to the first capacitor electrode Cst_E1 exposed through the contact opening (eg, contact hole) CNT. The second bridge pattern BRP2 may be integrally formed with the third capacitor electrode Cst_E3. Thus, the third capacitor electrode Cst_E3 may be connected to the first capacitor electrode Cst_E1 and may form a storage capacitor Cst (eg, see Figure 6 ) of the other electrode.

[0146] The third bridging pattern BRP3 may be disposed at the lower side of the first area A1, may overlap with a partial area of ​​the first semiconductor pattern ACT1 (or the source area of ​​the first transistor M1), may be connected to a partial area of ​​the first semiconductor pattern ACT1 exposed by the contact opening (e.g., contact hole) CNT, and may form a first transistor electrode of the first transistor M1.

[0147] The fourth bridge pattern BRP4 may overlap a portion of the third semiconductor pattern ACT3 (or the drain region of the third transistor M3), may be connected to a portion of the third semiconductor pattern ACT3 exposed by the contact opening (e.g., contact hole) CNT, and may form a second transistor electrode of the third transistor M3. Furthermore, the fourth bridge pattern BRP4 may overlap with the horizontal sense line SENL_H and may be connected to the horizontal sense line SENL_H through the contact opening (e.g., contact hole) CNT. Thus, the third transistor M3 can be connected to the vertical sense line SENL_V through the horizontal sense line SENL_H.

[0148] The fifth bridge pattern BRP5 may overlap the first power line PL1 (and / or the second power line PL2 ) and may be connected to the first power line PL1 (and / or the second power line PL2 ) through a contact opening (eg, a contact hole) CNT.

[0149] The third conductive layer SD1 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer SD1 may have a single-layer structure or a multi-layer structure.

[0150] Return Reference Figure 11A The third insulating layer (e.g., interlayer insulating layer) ILD2 may be disposed on the third conductive layer SD1 and may be disposed (e.g., substantially disposed) over the entire surface of the base layer SUB. The third insulating layer ILD2 may be an interlayer insulating layer such that it insulates the third conductive layer SD1 and the fourth conductive layer SD2 from each other.

[0151] Similar to the second insulating layer ILD1 , the third insulating layer ILD2 may include an inorganic insulating material, and may be a single layer or may have a multi-layer structure in which layers including (or made of) different materials are stacked.

[0152] Because the conductive pattern is not provided in the first area A1 of the base layer SUB, the top surface of the third insulating layer ILD2 in the first area A1 may be flat (or substantially flat). Based on the base layer SUB, the top surface of the third insulating layer ILD2 in the first area A1 may be lower than the top surface of the third insulating layer ILD2 in the second area A2.

[0153] The fourth conductive layer SD2 may be disposed on the third insulating layer ILD2. The fourth conductive layer SD2 may include the first vertical power line PL1_V, the second vertical power line PL2_V, and the sixth bridge pattern BRP6.

[0154] Reference Figure 8 and Figure 9E , the first vertical power line PL1_V may extend in the second direction DR2 and may extend all the way to another unit pixel region. The first vertical power line PL1_V may be disposed on the right side of the first area A1 and may define the right side of the first area A1. The first vertical power line PL1_V may include a protruding portion (e.g., a bump) that overlaps with the third bridge pattern BRP3 and may be connected to the third bridge pattern BRP3 via a contact opening (e.g., a contact hole) CNT (and the protruding portion). Therefore, the first vertical power line PL1_V may be connected to the first transistor M1 via the third bridge pattern BRP3.

[0155] Furthermore, the first vertical power line PL1_V may overlap with the fifth bridge pattern BRP5 and may be connected to the fifth bridge pattern BRP5 via a contact opening (e.g., a contact hole) CNT. Thus, the first vertical power line PL1_V may be connected to the first power line PL1 via the fifth bridge pattern BRP5. Thus, the first vertical power line PL1_V and the first power line PL1 may form a mesh structure throughout the display device.

[0156] The second vertical power line PL2_V may extend in the second direction DR2 and may extend all the way to another unit pixel region. The second vertical power line PL2_V may be disposed at the left side of the first area A1. The second vertical power line PL2_V may be adjacent to the left side of the first area A1 and may define the left side of the first area A1. The second vertical power line PL2_V may be connected to the second electrode ELT2 (e.g., see FIG. 1 ) through a second contact opening (e.g., a second contact hole) CNT2. Figure 9F ), which will be described in more detail below.

[0157] The sixth bridge pattern BRP6 may be disposed on the right side (or upper right side) of the first area A1 and may overlap the third capacitor electrode Cst_E3. The sixth bridge pattern BRP6 may be connected to the third capacitor electrode Cst_E3 exposed through the contact opening (e.g., contact hole) CNT. The sixth bridge pattern BRP6 may be connected to the first electrode ELT1 (e.g., see FIG. 1 ) through the first contact opening (e.g., first contact hole) CNT1. Figure 9F ), which will be described in more detail below. Figure 9F ) may be connected to the second transistor electrode of the first transistor M1 through the sixth bridge pattern BRP6 and the third capacitor electrode Cst_E3 (and the second bridge pattern BRP2).

[0158] Return Reference Figure 11A , the fourth insulating layer PW may be disposed over the fourth conductive layer SD2 and may be disposed (eg, substantially disposed) on the entire surface of the base layer SUB.

[0159] The fourth insulating layer PW may include an insulating layer including an inorganic material and / or an organic material. In an example, the first to third bank patterns may include at least one inorganic layer including various suitable inorganic insulating materials, such as silicon nitride (SiN x ) or silicon oxide (SiO xIn other embodiments, the fourth insulating layer PW may include at least one organic layer and / or at least one photoresist layer including various suitable organic insulating materials, or may be configured as a single-layer or multi-layer insulator including organic / inorganic materials. For example, the fourth insulating layer PW may be variously modified to include different suitable materials.

[0160] In some embodiments, the fourth insulating layer PW may include an opening exposing the third insulating layer ILD2 in the first area A1.

[0161] like Figure 10 As shown in , the fourth insulating layer PW may include an opening aligned with (eg, corresponding to) the first area A1 and may surround (eg, surround the periphery of) the first area A1 in a plane. The first area A1 may be defined by the fourth insulating layer PW.

[0162] The width of the opening in the fourth insulating layer PW (eg, the width in the first direction DR1) may be greater than the length of the light emitting element LD (eg, the length in the first direction DR2). Figures 1A to 4B The length L) in the middle is long.

[0163] In an embodiment, the fourth insulating layer PW may have a cross-section having a trapezoidal shape, the width of which narrows as it approaches the top of the trapezoidal shape at the first opening (e.g., a portion adjacent to the first area A1). The fourth insulating layer PW may have an inclined surface at the side surface adjacent to the first area A1. However, the shape of the fourth insulating layer PW is not limited thereto, and the fourth insulating layer PW may have a cross-section having a semicircular or semi-elliptical shape, the width of which narrows as it approaches the top of the semicircular or semi-elliptical shape. The fourth insulating layer PW may have a curved surface at the side surface adjacent to the first area A1. For example, in the present disclosure, the shape of the fourth insulating layer PW is not particularly limited and may be variously modified as appropriate.

[0164] In an embodiment, the fourth insulating layer PW may be a reflective member. In an example, the fourth insulating layer PW together with the first and second electrodes ELT1 and ELT2 disposed on top thereof may function as a reflective member that improves the optical efficiency of the first pixel PXL1 (or pixel) by directing light emitted from each light emitting element LD in a desired direction.

[0165] Return Reference Figure 11A , the first electrode ELT1 and the second electrode ELT2 may be disposed on the fourth insulating layer PW. The first electrode ELT1 and the second electrode ELT2 may be disposed in the first area A1 and spaced apart from each other.

[0166] The first electrode ELT1 and the second electrode ELT2 may have a shape corresponding to the shape of the fourth insulating layer PW. For example, the first electrode ELT1 and the second electrode ELT2 may protrude in the thickness direction (e.g., the third direction DR3) and respectively have an inclined surface or a curved surface corresponding to the fourth insulating layer PW (e.g., corresponding to the first portion PW_S1 and the second portion PW_S2 of the fourth insulating layer PW).

[0167] refer to Figure 9F The first electrode ELT1 may extend in the second direction DR2 (e.g., may extend substantially in the second direction DR2) and may be disposed on the right side of the first area A1. The first electrode ELT1 may overlap with the sixth bridge pattern BRP6 and may be connected to the sixth bridge pattern BRP6 via a first contact opening CNT1 exposing the sixth bridge pattern BRP6. Thus, the first electrode ELT1 may be connected to the second transistor electrode of the first transistor M1 via the sixth bridge pattern BRP6 and the third capacitor electrode Cst_E3 (and the second bridge pattern BRP2).

[0168] The first electrode ELT1 may include a first protruding portion (e.g., a first protrusion) protruding in the first direction DR1 in the first area A1. The length of the first protruding portion in the second direction DR2 may be similar to the length of the first area A1 in the second direction DR2. For example, the length of the first protruding portion in the second direction DR2 may be less than the length of the first area A1 in the second direction DR2.

[0169] The second electrode ELT2 may extend in the second direction DR2 (eg, may extend substantially in the second direction DR2 ) and may be disposed at the left side of the first area A1 . In addition, the second electrode ELT2 may extend all the way to another pixel area.

[0170] The second electrode ELT2 may overlap the second vertical power line PL2_V and may be connected to the second vertical power line PL2_V through the second contact opening CNT2 exposing the second vertical power line PL2_V.

[0171] The second electrode ELT2 may include a second protruding portion (e.g., a second protrusion) that protrudes in the first direction DR1 in the first area A1. The second protruding portion may face the first protruding portion of the first electrode ELT1 and may be spaced apart from the first protruding portion of the first electrode ELT1. The length of the second protruding portion in the second direction DR2 may be similar to the length of the first area A1 in the second direction DR2. For example, the length of the second protruding portion in the second direction DR2 may be equal to the length of the first protruding portion of the first electrode ELT1 in the second direction DR2.

[0172] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. In an example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one material selected from metals (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or any alloy thereof), conductive oxides (such as ITO, IZO, ZnO, or ITZO), and conductive polymers (such as PEDOT), but the present disclosure is not limited thereto.

[0173] Furthermore, each of the first electrode ELT1 and the second electrode ELT2 can be configured as a single-layer structure or a multi-layer structure. In an example, each of the first electrode ELT1 and the second electrode ELT2 can include at least one reflective electrode layer. Furthermore, each of the first electrode ELT1 and the second electrode ELT2 can also optionally include at least one of at least one transparent electrode layer disposed on top and / or bottom of the reflective electrode layer and at least one conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer.

[0174] In some embodiments, the reflective electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be made of a conductive material having uniform reflectivity. In embodiments, the reflective electrode layer may include at least one metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and alloys thereof, but the present disclosure is not limited thereto. That is, the reflective electrode layer may be made of various suitable reflective conductive materials. When each of the first electrode ELT1 and the second electrode ELT2 includes a reflective electrode layer, the first electrode ELT1 and the second electrode ELT2 may allow light emitted from both ends of each of the light-emitting elements LD (e.g., the first end EP1 and the second end EP2) to travel further in the direction of displaying an image (e.g., the forward direction). For example, when the first and second electrodes ELT1 and ELT2 are provided to face the first and second end portions EP1 and EP2 of each of the light emitting elements LD while having an inclined surface or a curved surface corresponding to the shape of the fourth insulating layer PW (for example, the shape of the side surface at the first area A1), light emitted from the first and second end portions EP1 and EP2 of each of the light emitting elements LD may be reflected by the first and second electrodes ELT1 and ELT2 to be displayed on the display panel PNL (for example, see FIG. Figure 5 ) further advances in the front direction of the substrate (eg, the upper direction of the base layer SUB). Therefore, the light extraction efficiency of the light emitting element LD can be improved.

[0175] In addition, the transparent electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may include various suitable transparent electrode materials (or may be made of various suitable transparent electrode materials). In an example, the transparent electrode layer may include ITO, IZO, or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a three-layer structure including a stacked structure of ITO / Ag / ITO. As described above, when each of the first electrode ELT1 and the second electrode ELT2 is provided as a multilayer structure including a plurality of (e.g., at least two) layers, the voltage drop caused by the RC delay may be reduced or minimized. Therefore, the desired voltage may be efficiently transmitted to the light-emitting element LD.

[0176] In addition, when each of the first electrode ELT1 and the second electrode ELT2 includes a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer, etc. of each of the first electrode ELT1 and the second electrode ELT2 may not be damaged due to defects occurring in the manufacturing process of the pixel PXL, etc. However, the first electrode ELT1 and the second electrode ELT2 may selectively include a conductive capping layer. In some embodiments, the conductive capping layer may be omitted. In addition, the conductive capping layer may be considered a component of each of the first electrode ELT1 and the second electrode ELT2, or may be considered a separate component provided on each of the first electrode ELT1 and the second electrode ELT2.

[0177] The fifth insulating layer INS1 may be provided on a region (e.g., a portion) of the first electrode ELT1 and the second electrode ELT2. For example, the fifth insulating layer INS1 may be formed to cover (or partially cover) the curved portion of the first electrode ELT1 and the second electrode ELT2, and may include an opening exposing other regions (e.g., a flat portion) of the first electrode ELT1 and the second electrode ELT2.

[0178] In an embodiment, the fifth insulating layer INS1 may be primarily formed to completely cover the first and second electrodes ELT1 and ELT2. After the light emitting element LD is provided and aligned on the fifth insulating layer INS1, the fifth insulating layer INS1 may be partially opened (or removed) to expose the first and second electrodes ELT1 and ELT2 at the first and second contact portions. In another embodiment, after the light emitting element LD is provided and aligned, the fifth insulating layer INS1 may be patterned in the form of a separate pattern locally provided on the bottom of the light emitting element LD.

[0179] For example, the fifth insulating layer INS1 is interposed between the first and second electrodes ELT1 and ELT2 and the light-emitting element LD, and may expose at least one region of each of the first and second electrodes ELT1 and ELT2. After forming the first and second electrodes ELT1 and ELT2, the fifth insulating layer INS1 may be formed to cover the first and second electrodes ELT1 and ELT2, thereby preventing damage to the first and second electrodes ELT1 and ELT2 in subsequent processes (or reducing changes to the first and second electrodes ELT1 and ELT2 in subsequent processes) or preventing or substantially preventing the generation of metal in subsequent processes. Furthermore, the fifth insulating layer INS1 may stably support the light-emitting element LD. In some embodiments, the fifth insulating layer INS1 may be omitted.

[0180] The light emitting element LD may be provided and aligned in the light emitting area EMA (e.g., the first area A1) in which the fifth insulating layer INS1 is formed. In an example, the light emitting element LD may be provided in the light emitting area EMA by an inkjet process or the like, and may be aligned between the first electrode ELT1 and the second electrode ELT2 by applying an alignment voltage (e.g., a predetermined alignment voltage or an alignment signal) to the first electrode ELT1 and the second electrode ELT2.

[0181] The sixth insulating layer INS2 may be disposed above the light emitting element LD, for example, on top of the light emitting element LD aligned between the first electrode ELT1 and the second electrode ELT2, and may expose the first end EP1 and the second end EP2 of the light emitting element LD. For example, the sixth insulating layer INS2 does not cover the first end EP1 and the second end EP2 of the light emitting element LD, but may be only partially disposed on top of a region of the light emitting element LD. The sixth insulating layer INS2 may be formed as an independent pattern, but the present disclosure is not limited thereto. In addition, as Figure 11B As shown in FIG, when a separation space exists between the fifth insulating layer INS1 and the light emitting element LD before the sixth insulating layer INS2 is formed, the space may be filled with the sixth insulating layer INS2. Therefore, the light emitting element LD may be supported more stably.

[0182] The first contact electrode CNE1 and the second contact electrode CNE2 may be provided on the first electrode ELT1 and the second electrode ELT2 and the first end portion EP1 and the second end portion EP2 of the light emitting element LD. Figure 11A As shown in FIG, the first contact electrode CNE1 and the second contact electrode CNE2 may be provided in the same layer. The first contact electrode CNE1 and the second contact electrode CNE2 may include the same conductive material (or may be formed of the same conductive material) through the same process, but the present disclosure is not limited thereto.

[0183] The first and second contact electrodes CNE1 and CNE2 may electrically connect the first and second end portions EP1 and EP2 of the light emitting element LD to the first and second electrodes ELT1 and ELT2 , respectively.

[0184] For example, the first contact electrode CNE1 may be provided on the first electrode ELT1 to contact the first electrode ELT1. In an example, the first contact electrode CNE1 may be provided to contact the first electrode ELT1 at a region of the first electrode ELT1 not covered by the fifth insulating layer INS1. Furthermore, the first contact electrode CNE1 may be provided on a first end portion EP1 of at least one light-emitting element LD (e.g., each of a plurality of light-emitting elements LD) adjacent to the first electrode ELT1 to contact the first end portion EP1. For example, the first contact electrode CNE1 may be provided to cover the first end portion EP1 of each light-emitting element LD and at least one region of the first electrode ELT1 corresponding to the light-emitting element LD. Thus, the first end portion EP1 of each light-emitting element LD may be electrically connected to the first electrode ELT1.

[0185] Similarly, a second contact electrode CNE2 can be provided on the second electrode ELT2 to contact the second electrode ELT2. In an example, the second contact electrode CNE2 can be provided to contact the second electrode ELT2 at a region of the second electrode ELT2 that is not covered by the fifth insulating layer INS1. Furthermore, the second contact electrode CNE2 can be provided on a second end portion EP2 of at least one light-emitting element LD (e.g., each of a plurality of light-emitting elements LD) adjacent to the second electrode ELT2 to contact the second end portion EP2. For example, the second contact electrode CNE2 can be provided to cover the second end portion EP2 of each light-emitting element LD and at least one region of the second electrode ELT2 corresponding to the light-emitting element LD. Thus, the second end portion EP2 of each light-emitting element LD can be electrically connected to the second electrode ELT2.

[0186] The seventh insulating layer INS3 may be formed and / or disposed on one surface of the base layer SUB to cover the fourth insulating layer PW, the first and second electrodes ELT1 and ELT2, the light-emitting element LD, and the first and second contact electrodes CNE1 and CNE2. The fourth insulating layer PW, the first and second electrodes ELT1 and ELT2, the light-emitting element LD, and the first and second contact electrodes CNE1 and CNE2 are formed on the one surface of the base layer SUB. The seventh insulating layer INS3 may include a thin film encapsulation layer including at least one inorganic layer and / or at least one organic layer, but the present disclosure is not limited thereto. In some embodiments, at least one overcoat layer may be further disposed on top of the seventh insulating layer INS3.

[0187] In some embodiments, each of the fifth insulating layer INS1, the sixth insulating layer INS2, and the seventh insulating layer INS3 may be provided as a single layer or a multi-layer structure, and may include at least one inorganic insulating material and / or at least one organic insulating material. For example, each of the fifth insulating layer INS1, the sixth insulating layer INS2, and the seventh insulating layer INS3 may include various suitable organic / inorganic insulating materials (including silicon nitride (SiN x ), but one or more materials constituting each of the fifth insulating layer INS1, the sixth insulating layer INS2, and the seventh insulating layer INS3 are not particularly limited. In addition, the fifth insulating layer INS1, the sixth insulating layer INS2, and the seventh insulating layer INS3 may include different insulating materials, but in some embodiments, at least some of the fifth insulating layer INS1, the sixth insulating layer INS2, and the seventh insulating layer INS3 may include the same insulating material.

[0188] As reference Figures 7 to 11B As described, the base layer SUB or the pixel region (eg, the first pixel region PXA1) may have a first region A1 and a second region A2 surrounding the first region A1, forming a pixel driving circuit DC (eg, see Figure 6 ) can be provided in the second area A2, and only the insulating layers (e.g., the first insulating layer GI, the second insulating layer ILD1, and the third insulating layer ILD2) can be provided in the first area A1. The first area A1 can be defined by the second vertical power line PL2_V, the second semiconductor pattern ACT2, and the capacitor electrodes (e.g., the third capacitor electrode Cst_E3 and / or the first capacitor electrode Cst_E1) (or the first vertical power line PL1_V). Therefore, no step difference caused by the conductive pattern occurs in the first area A1, eliminating the need to form an organic insulating layer to planarize the surface on which the light-emitting element LD is provided (e.g., the top surface of the third insulating layer ILD2). Therefore, the manufacturing process of the display device can be further simplified.

[0189] Despite Figure 11A and Figure 11B illustratively shows an embodiment in which the opening of the fourth insulating layer PW may have a trapezoidal shape (eg, may have a partial trapezoidal shape) in cross section and the first and second contact electrodes CNE1 and CNE2 are provided in the same layer, but the present disclosure is not limited thereto.

[0190] Figures 11C to 11E is shown along Figure 8 1 is a cross-sectional view of another example of the first pixel taken along lines II′ and II-II′. Figures 11C to 11E Shown in Figure 11B The corresponding figure.

[0191] First, refer to Figure 11C , the fourth insulating layer PW may have a cross-section in a semicircular or semi-elliptical shape (eg, having a curved side surface) whose width narrows as it approaches a top thereof in the opening formed in the first area A1.

[0192] Reference Figure 11D The first contact electrode CNE1 may be provided on the first electrode ELT1 to contact a region of the first electrode ELT1. Furthermore, the first contact electrode CNE1 may be provided on the first end portion EP1 of the light emitting element LD to contact the first end portion EP1. The first end portion EP1 of the light emitting element LD may be electrically connected to the first electrode ELT1 via the first contact electrode CNE1.

[0193] The eighth insulating layer INS4 may be disposed on the first contact electrode CNE1. In some embodiments, the eighth insulating layer INS4 may cover the sixth insulating layer INS2 and the first contact electrode CNE1.

[0194] In some embodiments, similar to the fifth insulating layer INS1, the sixth insulating layer INS2, and the seventh insulating layer INS3, the eighth insulating layer INS4 can be provided as a single layer or a multi-layer structure, and can include at least one inorganic insulating material and / or at least one organic insulating material. For example, the eighth insulating layer INS4 can include various suitable organic / inorganic materials (including silicon nitride (SiN x )). In addition, the eighth insulating layer INS4 may include an insulating material different from those of the fifth insulating layer INS1, the sixth insulating layer INS2, and the seventh insulating layer INS3, or may include the same insulating material as at least some of the fifth insulating layer INS1, the sixth insulating layer INS2, and the seventh insulating layer INS3.

[0195] The second contact electrode CNE2 may be disposed on the eighth insulating layer INS4. In some embodiments, the second contact electrode CNE2 may be disposed on the second electrode ELT2 to contact a region of the second electrode ELT2. Furthermore, the second contact electrode CNE2 may be disposed on the second end portion EP2 of the light-emitting element LD to contact the second end portion EP2. The second end portion EP2 of the light-emitting element LD may be electrically connected to the second electrode ELT2 via the second contact electrode CNE2.

[0196] In some embodiments, the opening of the fourth insulating layer PW may have various polygonal shapes. Figure 11DAs shown in , the fourth insulating layer PW (or the first portion PW_S1 and the second portion PW_S2 of the fourth insulating layer PW) may have a trapezoidal cross-section whose width narrows as it approaches its top. In another example, as Figure 11E As shown in the figure, the fourth insulating layer PW (or the first part PW_S1 and the second part PW_S2 of the fourth insulating layer PW) may have a surface having a semicircular or semi-elliptical shape (for example, a side surface having a curved shape), and the width of the semicircular or semi-elliptical shape becomes narrower as it approaches its top.

[0197] Figure 12 is shown along Figure 8 FIG. 1 is a cross-sectional view of another example of the first pixel taken along line II-II′. Figure 12 and Figure 11A For ease of description, the fourth insulating layer PW is schematically shown (for example, see Figure 11A ) is configured as shown in the figure below. In addition, redundant descriptions between these figures can be omitted.

[0198] Apart from Figure 12 The first pixel PXL1 shown in FIG. 1 includes a first bank pattern PW1 and a second bank pattern PW2 instead of (or replacing) the fourth insulating layer PW. Figure 12 The first pixel PXL1 shown in FIG. 1 may be substantially similar to Figure 11A The first pixel PXL1 is shown in FIG.

[0199] The first embankment pattern PW1 may be disposed below the first electrode ELT1, and the first electrode ELT1 may overlap the first embankment pattern PW1. The second embankment pattern PW2 may be disposed below the second electrode ELT2, and the second electrode ELT2 may overlap the second embankment pattern PW2. The first embankment pattern PW1 and the second embankment pattern PW2 may be disposed to be spaced apart from each other, and the first area A1 (e.g., the light emitting area EMA) is interposed between the first embankment pattern PW1 and the second embankment pattern PW2. For example, the first embankment pattern PW1 may cover Figure 9E The first vertical power line PL1_V shown in FIG, and the second bank pattern PW2 may cover Figure 9E The second vertical power line PL2_V is shown in . The third insulating layer ILD2 may be exposed through a space between the first bank pattern PW1 and the second bank pattern PW2 .

[0200] Portions of the first electrode ELT1 and the second electrode ELT2 may protrude upward due to the first and second bank patterns PW1 and PW2. For example, due to the first bank pattern PW1, the first electrode ELT1 may be provided on the first bank pattern PW1 to protrude in the height direction (e.g., thickness direction) of the base layer SUB, and due to the second bank pattern PW2, the second electrode ELT2 may be provided on the second bank pattern PW2 to protrude in the height direction of the base layer SUB.

[0201] In the display device according to the present disclosure, only the light-emitting element and the insulating layer are provided in the first region (e.g., the light-emitting region), and the conductive pattern forming the pixel driving circuit is provided only in the second region surrounding the first region. The first region is defined by the power lines and the semiconductor pattern. Therefore, any step difference caused by the conductive pattern will not appear in the first region (e.g., the step difference appears or exists outside the first region). Therefore, there is no need to form an organic insulating layer to flatten the surface on which the light-emitting element is provided, and the manufacturing process of the display device can be further simplified.

[0202] Exemplary embodiments have been disclosed herein, and although specific terms are used, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically stated. Therefore, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims and their equivalents.

Claims

1. Display devices, including: a base layer having a first region and a second region, the second region extending at least partially around a perimeter of the first region; a conductive pattern located in the second region; an insulating layer located above the conductive pattern in the second region; a first electrode and a second electrode located on the insulating layer, the first electrode and the second electrode being spaced apart from each other in the first region, the first electrode and the second electrode being respectively connected to portions of the conductive pattern through contact openings penetrating the insulating layer; a light emitting element located between the first electrode and the second electrode in the first region, the light emitting element being connected to the first electrode and the second electrode, and an inorganic insulating layer on the base layer, wherein the light emitting element does not overlap with the conductive pattern and the insulating layer; wherein at least one of the conductive patterns is located on the inorganic insulating layer, wherein the insulating layer has an opening exposing the inorganic insulating layer, wherein the light emitting element is in the opening; The inorganic insulating layer includes a first inorganic insulating layer, a second inorganic insulating layer and a third inorganic insulating layer sequentially stacked on the base layer, and Wherein, the conductive pattern includes: a back gate electrode, located between the base layer and the first inorganic insulating layer, The back gate electrode overlaps with the semiconductor pattern; a gate electrode, located on the first inorganic insulating layer, wherein the gate electrode overlaps the semiconductor pattern; a first capacitor electrode, located on the first inorganic insulating layer, wherein the first capacitor electrode overlaps with the back gate electrode; a second capacitor electrode located on the second inorganic insulating layer, the second capacitor electrode being connected to a region of the semiconductor pattern through a contact opening penetrating the second inorganic insulating layer, the second capacitor electrode overlapping the first capacitor electrode; and A bridge pattern is located on the third inorganic insulating layer, the bridge pattern is connected to the second capacitor electrode through a contact opening penetrating the third inorganic insulating layer, and the bridge pattern is connected to the first electrode through a contact opening penetrating the insulating layer.

2. The display device according to claim 1, further comprising: a third electrode located on the first electrode and on one end of the light emitting element so as to contact the first electrode and the one end of the light emitting element; as well as A fourth electrode is located on the second electrode and the other end of the light emitting element to contact the second electrode and the other end of the light emitting element.

3. The display device according to claim 2, wherein The third electrode and the fourth electrode are formed in the same layer.

4. The display device according to claim 2, in, At least one of the conductive patterns is located on the inorganic insulating layer, wherein the insulating layer includes a first bank pattern and a second bank pattern spaced apart from each other, and the first region is located between the first bank pattern and the second bank pattern; and The inorganic insulating layer is exposed through a space between the first bank pattern and the second bank pattern.

5. The display device according to claim 2, wherein The third electrode and the fourth electrode are spaced apart from each other in different layers with a second insulating layer therebetween. The display device according to claim 1 , wherein: The insulating layer is not between the base layer and the light emitting element.

7. The display device according to claim 1, wherein A height of a top surface of the inorganic insulating layer in the first region over the foundation layer is smaller than a height of the top surface of the inorganic insulating layer in the second region.

8. The display device according to claim 1, wherein The back gate electrode and the first capacitor electrode form a first capacitor by overlapping each other, and The first capacitor electrode and the second capacitor electrode overlap with each other to form a second capacitor.

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