Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. In an embodiment, a structure includes: a gate stack located above a channel region of a substrate; a source / drain region adjacent to the channel region; a first interlayer dielectric (ILD) layer located above the source / drain region; a silicide located between the first ILD layer and the source / drain region, the silicide contacting the top surface of the source / drain region and the bottom surface of the source / drain region; and a first source / drain contact having a first portion and a second portion, the first portion of the first source / drain contact being disposed between the silicide and the first ILD layer, the second portion of the first source / drain contact extending through the first ILD layer and contacting the silicide.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to a first aspect of the present disclosure, a semiconductor device structure is provided, comprising: a gate stack located above a channel region of a substrate; a source / drain region adjacent to the channel region; a first interlayer dielectric (ILD) layer located above the source / drain region; a silicide located between the first ILD layer and the source / drain region, the silicide contacting a top surface of the source / drain region and a bottom surface of the source / drain region; and a first source / drain contact having a first portion and a second portion, the first portion of the first source / drain contact being disposed between the silicide and the first ILD layer, the second portion of the first source / drain contact extending through the first ILD layer and contacting the silicide.

[0005] According to a second aspect of the present disclosure, a semiconductor device structure is provided, comprising: a gate stack located on a substrate; a gate spacer adjacent to the gate stack; a source / drain region adjacent to the gate spacer; a silicide located on the source / drain region, the silicide contacting the sidewall of the gate spacer; a source / drain contact located on the silicide, the source / drain contact contacting the sidewall of the gate spacer; and an interlayer dielectric (ILD) layer located on a lower portion of the source / drain contact, the ILD layer surrounding an upper portion of the source / drain contact.

[0006] According to a third aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising: depositing a contact etch stop layer (CESL) over a source / drain region; depositing an interlayer dielectric (ILD) layer over the CESL; etching an opening in the ILD layer; extending the opening through the CESL using a first etching process, the first etching process being anisotropic;

[0007] A second etching process is used to widen a lower portion of the opening to form an undercut between the ILD layer and the source / drain region, wherein the second etching process is isotropic; a silicide is formed in the opening and the undercut, wherein the silicide is in contact with the source / drain region; and a source / drain contact is formed in the opening and the undercut, wherein the source / drain contact is in contact with the silicide. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 An example of a FinFET in a three-dimensional view is shown in accordance with some embodiments.

[0010] Figure 2 and Figure 3 is a three-dimensional view of an intermediate stage in fabricating a FinFET according to some embodiments.

[0011] Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A and Fig. 14B is a cross-sectional view of another intermediate stage in fabricating a FinFET according to some embodiments.

[0012] Fig.15A and Fig. 15B is a cross-sectional view of a FinFET according to some other embodiments.

[0013] Fig.16A and Fig. 16B is a cross-sectional view of a FinFET according to some other embodiments.

[0014] Fig.17A and Fig. 17B is a cross-sectional view of a FinFET according to some other embodiments.

[0015] Fig.18A and Fig.18B is a cross-sectional view of a FinFET according to some other embodiments.

[0016] Fig.19A and Fig.19B is a cross-sectional view of a FinFET according to some other embodiments.

[0017] Fig. 20A and Fig. 20B is a cross-sectional view of a FinFET according to some other embodiments.

[0018] Fig.21A and Fig.21B is a cross-sectional view of a FinFET according to some other embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0021] According to some embodiments, an undercut is formed in a contact etch stop layer (CESL), wherein the undercut is disposed between a source / drain region and an upper interlayer dielectric (ILD) layer. Forming the undercut exposes the surface of the source / drain region and thus allows silicide and contacts for the source / drain region to contact a larger surface area of ​​the source / drain region. Thus, the contact resistance with the source / drain region can be reduced, thereby improving the performance of the resulting transistor.

[0022] Figure 1 An example of a simplified fin field effect transistor (FinFET) in a three-dimensional view according to some embodiments is shown. For clarity of illustration, some other features of the FinFET (discussed below) are omitted. The FinFET shown can be electrically coupled in some way to operate as, for example, one transistor or multiple transistors (e.g., four transistors).

[0023] The FinFET includes a fin 52 extending from a substrate 50. A shallow trench isolation (STI) region 56 is disposed above the substrate 50, and the fin 52 protrudes from between adjacent STI regions 56 and protrudes higher than adjacent STI regions 56. Although the STI regions 56 are described / illustrated as being separate from the substrate 50, the term "substrate" as used herein may be used to refer to only a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 52 is shown as a single continuous material of the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this article, the fin 52 refers to a portion extending between adjacent STI regions 56.

[0024] The gate structure 80 is located above the channel region of the fin 52. The gate structure 80 includes a gate dielectric 82 and a gate electrode 84. The gate dielectric 82 is along the sidewalls of the fin 52 and above the top surface of the fin 52, and the gate electrode 84 is located above the gate dielectric 82. The source / drain region 70 is disposed in an opposite side of the fin 52 relative to the gate dielectric 82 and the gate electrode 84. The gate spacer 66 separates the source / drain region 70 from the gate structure 80. In embodiments where multiple transistors are formed, the source / drain region 70 may be shared between the respective transistors. In embodiments where one transistor is formed from multiple fins 52, adjacent source / drain regions 70 may be electrically coupled, such as by agglomerating the source / drain regions 70 by epitaxial growth, or by coupling the source / drain regions 70 to the same source / drain contact. One or more interlayer dielectric (ILD) layers (discussed further below) are located over the source / drain regions 70 and / or the gate electrode 84 through which contacts (discussed further below) are formed to the source / drain regions 70 and / or the gate electrode 84 .

[0025] Figure 1 Several reference cross sections are further shown. Cross section AA is along the longitudinal axis of the fin 52 and in the direction of current flow, for example, between the source / drain regions 70 of the FinFET. Cross section BB is perpendicular to cross section AA and extends through the source / drain regions 70 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0026] Some embodiments discussed herein are discussed in the context of FinFETs formed using gate-last processes. In other embodiments, gate-first processes may be used. Furthermore, some embodiments contemplate aspects used in planar devices such as planar FETs.

[0027] Figure 2 and Figure 3 is a three-dimensional view of an intermediate stage in fabricating a FinFET according to some embodiments. Figure 2 and Figure 3 Shown with Figure 1 A similar view except that three gate structures are shown.

[0028] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (for example, with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, for example, a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, for example, a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof.

[0029] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form an n-type device, such as an NMOS transistor, such as an n-type FinFET. The region 50P can be used to form a p-type device, such as a PMOS transistor, such as a p-type FinFET. The region 50N can be physically separated from the region 50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the region 50N and the region 50P.

[0030] Fin 52 is formed to extend from substrate 50. Fin 52 is a semiconductor strip. In some embodiments, fin 52 may be formed in substrate 50 by etching trenches in substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), etc. Etching may be anisotropic.

[0031] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines photolithography and a self-aligned process, thereby allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the spacers (or other masks) may remain on the fins 52.

[0032] STI region 56 is formed over substrate 50 and between adjacent fins 52. As an example of forming STI region 56, an insulating material is formed over the intermediate structure. The insulating material may be an oxide, such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., deposition of a material based on chemical vapor deposition (CVD) in a remote plasma system, and post-curing to convert it into another material, such as an oxide), or the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material is formed so that excess insulating material covers the fin 52. Although STI region 56 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner may first be formed along the surface of substrate 50 and fin 52. Thereafter, a filling material such as discussed above may be formed over the liner. A removal process is applied to the insulating material to remove excess insulating material over the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes the fin 52 so that after the planarization process is completed, the top surfaces of the fin 52 and the insulating material are coplanar. In embodiments where the mask remains on the fin 52, the planarization process may expose the mask or remove the mask so that after the planarization process is completed, the top surfaces of the mask or fin 52 and the insulating material are coplanar, respectively. The insulating material is then recessed, wherein the remaining portion of the insulating material forms an STI region 56. The insulating material is recessed so that the upper portions of the fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56. The exposed portion of the fin 52 includes a portion that will become the channel region of the resulting FinFET.

[0033] In addition, the top surface of STI region 56 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dishing), or a combination thereof. The top surface of STI region 56 can be formed to be flat, convex, and / or concave by appropriate etching. STI region 56 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of fin 52). For example, oxide removal using an acid such as dilute hydrofluoric acid (dHF) can be used.

[0034] The above process is only one example of how the fin 52 is formed. In some embodiments, the fin 52 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure can be epitaxially grown in the groove, and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin 52. In addition, in some embodiments, a heteroepitaxial structure can be used for the fin 52. For example, after the insulating material of the STI region 56 is planarized for the fin 52, the fin 52 can be recessed, and a material different from the fin 52 can be epitaxially grown on the recessed fin 52. In such embodiments, the fin 52 includes a recessed material and an epitaxially grown material disposed on the recessed material. In another embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a different material than substrate 50, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form fin 52. In some embodiments where the homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may eliminate previous and subsequent implants, although in situ doping and implant doping may be used together.

[0035] In addition, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium (SiGe). x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0036] Furthermore, appropriate wells may be formed in fin 52 and / or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.

[0037] In embodiments with different well types, a photoresist or other mask may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N, such as an NMOS region. The n-type impurity may be phosphorus, arsenic, antimony, etc., and may be implanted at a rate equal to or less than 10 18 cm -3 The concentration (e.g., at about 10 16 cm -3 to about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0038] After implanting region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may act as a mask to substantially prevent the p-type impurity from being implanted into region 50P, such as a PMOS region. The p-type impurity may be boron, boron fluoride, indium, etc., and may be formed at a density equal to or less than 10 18 cm -3 The concentration (e.g., at about 10 16 cm -3 to about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0039] After implantation of regions 50N and 50P, annealing may be performed to repair implant damage and activate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may eliminate implantation, although in-situ doping and implantation doping may be used together.

[0040] exist Figure 3In the embodiment of the present invention, a dummy dielectric 60 is formed on the fin 52, and a dummy gate 62 is formed on the dummy dielectric 60. The dummy dielectric 60 and the dummy gate 62 may be collectively referred to as a “dummy gate stack”, wherein each dummy gate stack includes a dummy dielectric 60 and a dummy gate 62. The dummy gate stack extends along the sidewall of the fin 52.

[0041] As an example of forming a dummy dielectric 60 and a dummy gate 62, a dummy dielectric layer is formed on the fin 52. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed on the dummy dielectric layer, and a mask layer is formed on the dummy gate layer. The dummy gate layer can be deposited on the dummy dielectric layer, and then planarized, for example, by CMP. The mask layer can be deposited on the dummy gate layer. The dummy gate layer can be a conductive material or a non-conductive material, and can be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide and metal. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit selected materials. The dummy gate layer can be made of other materials with high etching selectivity to the etching of the STI region 56. The mask layer may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer and a single mask layer are formed across region 50N and region 50P. The mask layer is then patterned using acceptable photolithography and etching techniques to form a mask 64. Then, the pattern of mask 64 is transferred to the dummy gate layer by an acceptable etching technique to form a dummy gate 62. The pattern of mask 64 may optionally be further transferred to a dummy dielectric layer to form a dummy dielectric 60. Dummy gate 62 covers the corresponding channel region 58 of fin 52. The pattern of mask 64 may be used to separate each dummy gate 62 from an adjacent dummy gate entity. Dummy gate 62 may also have a length direction substantially perpendicular (within process limitations) to the length direction of the corresponding fin 52. Although dummy dielectric 60 is shown as covering STI region 56, it should be understood that dummy dielectric 60 may be formed in other ways. In some embodiments, such as when the dummy dielectric layer is thermally grown, the dummy dielectric 60 is formed to cover only the fins 52 .

[0042] 4A to 14B is a cross-sectional view of another intermediate stage in fabricating a FinFET according to some embodiments. Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A and Fig.14A It is along Figure 1 Reference cross section AA shows a cross-sectional view except that three gate structures are shown. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B It is along Figure 1 Reference cross section BB shows a cross-sectional view, except that only two fins are shown. 4A to 14B Features in either region 50N or region 50P are shown. For example, 4A to 14B The structure shown may apply to both region 50N and region 50P. Differences in the structures of region 50N and region 50P, if any, are described herein.

[0043] exist Figure 4A and Figure 4B In the embodiment, the gate spacer 66 is formed on the exposed surface of the dummy gate 62, the mask 64 and / or the fin 52. The gate spacer 66 can be formed by forming an insulating material and then etching the insulating material. The insulating material of the gate spacer 66 can be silicon nitride, silicon carbonitride, carbon nitride silicon oxide, a combination thereof, etc., and can be formed by thermal oxidation, deposition, a combination thereof, etc. In some embodiments, the gate spacer 66 is formed of a multilayer insulating material and includes a multilayer. For example, the gate spacer 66 may include a multilayer silicon carbonitride, may include a multilayer silicon carbonitride oxide, or may include a silicon oxide layer disposed between two silicon nitride layers. The etching of the gate spacer 66 may be anisotropic. After etching, the gate spacer 66 may have a straight sidewall or a curved sidewall.

[0044] Prior to or during formation of gate spacers 66, implantation for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. In embodiments having different device types, similar to the implantation discussed, a mask (e.g., photoresist) may be formed over region 50N while exposing region 50P, and an appropriate type (e.g., p-type) impurity may be implanted into exposed fins 52 in region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over region 50P while exposing region 50N, and an appropriate type (e.g., n-type) impurity may be implanted into exposed fins 52 in region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a thickness of approximately 10 nm. 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0045] Then, epitaxial source / drain regions 70 are formed in the fin 52. The epitaxial source / drain regions 70 are formed in the fin 52 so that each dummy gate 62 is disposed between respective adjacent pairs of epitaxial source / drain regions 70. In some embodiments, the epitaxial source / drain regions 70 may extend into portions of the fin 52 below the top surface of the STI region 56. In some embodiments, gate spacers 66 are used to separate the epitaxial source / drain regions 70 from the dummy gates 62 by an appropriate lateral distance so that the epitaxial source / drain regions 70 do not short-circuit the gate of the resulting FinFET that is subsequently formed. The epitaxial source / drain regions 70 may apply stress in the channel region 58 of the fin 52, thereby improving performance.

[0046] The epitaxial source / drain regions 70 in the region 50N (e.g., NMOS region) may be formed by masking the region 50P (e.g., PMOS region) and etching the source / drain regions of the fin 52 in the region 50N to form recesses in the fin 52. The epitaxial source / drain regions 70 in the region 50N are then epitaxially grown in the recesses. The epitaxial source / drain regions 70 may include any acceptable material, such as a material suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain regions 70 in the region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 70 in the region 50N may have surfaces that are raised from the corresponding surfaces of the fin 52 and may have facets.

[0047] The epitaxial source / drain regions 70 in the region 50P (e.g., the PMOS region) can be formed by masking the region 50N (e.g., the NMOS region) and etching the source / drain regions of the fin 52 in the region 50P to form recesses in the fin 52. The epitaxial source / drain regions 70 in the region 50P are then epitaxially grown in the recesses. The epitaxial source / drain regions 70 can include any acceptable material, such as a material suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain regions 70 in the region 50P can include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 70 in the region 50P can also have surfaces that are raised from the corresponding surfaces of the fin 52 and can have small facets.

[0048] The epitaxial source / drain regions 70 and / or the fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions followed by annealing. The impurity concentration of the source / drain regions may be about 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 70 may be doped in-situ during growth.

[0049] As a result of the epitaxial process used to form epitaxial source / drain regions 70, the upper surfaces of epitaxial source / drain regions 70 have facets that extend laterally outward beyond the sidewalls of fins 52. In some embodiments, these facets merge adjacent epitaxial source / drain regions 70 of the same FinFET, such as Figure 4B As shown. For example, when a transistor is formed from multiple fins 52, merged epitaxial source / drain regions 70 can be formed. In other embodiments, adjacent epitaxial source / drain regions 70 remain separated after the epitaxial process is completed. For example, when a transistor is formed from a single fin 52 or when a transistor is formed from multiple fins 52, unmerged epitaxial source / drain regions 70 can be formed. In the embodiment shown, the gate spacers 66 are formed to cover the portions of the sidewalls of the fins 52 that extend over the STI regions 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacers 66 can be adjusted to remove the spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI regions 56.

[0050] Note that the above disclosure generally describes the process of forming spacers, LDD regions, and source / drain regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, steps in different sequences may be used, spacers may be formed and removed, and the like. In some embodiments, gate spacers 66 may be formed after epitaxial source / drain regions 70. In addition, different structures and steps may be used to form n-type and p-type devices. In some embodiments, dummy spacers may be formed in region 50N during the formation of epitaxial source / drain regions 70 in region 50N. The dummy spacers in region 50N may then be removed. Dummy spacers may then be formed in region 50P during the formation of epitaxial source / drain regions 70 in region 50P. The dummy spacers in region 50P may then be removed. Gate spacers 66 may then be formed after epitaxial source / drain regions 70 have been formed in both region 50N and region 50P.

[0051] exist Figure 5A and Figure 5B , CESL 72 is deposited over epitaxial source / drain regions 70, gate spacers 66, mask 64 (if present) or dummy gate 62, and STI regions 56. CESL 72 is formed of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc. In an embodiment, CESL 72 is formed of silicon nitride.

[0052] Then, a first ILD layer 74 is deposited over the CESL 72. The first ILD layer 74 is formed of a dielectric material having a different etch rate than the material of the CESL 72, and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include an oxide, such as silicon oxide, phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc.; a nitride, such as silicon nitride; or the like. Other insulating materials formed by any acceptable process may be used. After formation, the first ILD layer 74 may be planarized, such as by CMP.

[0053] The CESL 72 is formed to a relatively large thickness T1, for example, a thickness T1 in the range of about 3 nm to about 10 nm. As discussed further below, an undercut will be formed in the CESL 72 between the epitaxial source / drain regions 70 and the first ILD layer 74. A subsequently formed source / drain contact will be formed to extend into the undercut, thereby increasing the contact surface area of ​​the epitaxial source / drain regions 70. Forming the CESL 72 to a relatively large thickness T1 helps provide sufficient space for subsequently forming the source / drain contact.

[0054] exist Fig. 6A and Figure 6B In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD layer 74 flush with the top surface of the mask 64 (if present) or the dummy gate 62. The planarization process may remove the mask 64 on the dummy gate 62 and the portion of the gate spacer 66 along the sidewall of the mask 64. The planarization process may also remove the portion of the CESL 72 above the dummy gate 62 and the gate spacer 66. After the planarization process, the top surfaces of the dummy gate 62, the gate spacer 66, the CESL 72, and the first ILD layer 74 are coplanar. Therefore, the top surface of the dummy gate 62 is exposed through the first ILD layer 74. In some embodiments, the mask 64 may be retained, in which case the planarization process makes the top surface of the first ILD layer 74 flush with the top surface of the mask 64.

[0055] exist Fig. 7A and Figure 7BIn the embodiment of the present invention, the dummy gate 62 and the optional dummy dielectric 60 are removed and replaced by the gate structure 80. The gate structure 80 includes a gate dielectric 82 and a gate electrode 84. As an example of forming the gate structure 80, the dummy gate 62 and the mask 64 (if present) are removed in one or more etching steps so that a groove is formed. The portion of the dummy dielectric 60 in the groove may also be removed. In some embodiments, only the dummy gate 62 is removed, and the dummy dielectric 60 is retained and exposed by the groove. In some embodiments, the dummy dielectric 60 is removed from the groove in the first region of the die (e.g., the core logic region) and retained in the groove in the second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 62 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases, which selectively etches the dummy gate 62 without etching the first ILD layer 74, the CESL 72, or the gate spacer 66. Each groove exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 70. During removal, the dummy dielectric 60 can be used as an etch stop layer when etching the dummy gate 62. Then, after removing the dummy gate 62, the dummy dielectric 60 can be optionally removed. After removal, a gate dielectric 82 is conformally deposited in the groove, for example, on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate spacer 66. The gate dielectric 82 can also be formed on the top surface of the first ILD layer 74. According to some embodiments, the gate dielectric 82 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric 82 includes a high-k dielectric material, and in these embodiments, the gate dielectric 82 can have a k value greater than about 7.0, and can include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric 82 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. In an embodiment where a portion of the dummy dielectric 60 remains in the groove, the gate dielectric 82 includes the material of the dummy dielectric 60 (e.g., silicon oxide). The gate electrodes 84 are deposited on the gate dielectric 82, respectively, and fill the remaining portion of the groove. The gate electrode 84 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or a multilayer thereof. For example, although a single-layer gate electrode 84 is shown, each gate electrode 84 may include any number of liner layers, any number of work function adjustment layers, and filling materials. After filling the gate electrode 84, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric 82 and the material of the gate electrode 84, which are above the top surface of the first ILD layer 74.The gate electrode 84 and the remaining portion of the gate dielectric 82 material form the gate structure 80 of the resulting FinFET. The gate structure 80 may also be referred to as a “gate stack” or a “metal gate.” The gate structure 80 may extend along the sidewalls of the channel region 58 of the fin 52 .

[0056] The formation of gate structures 80 in regions 50N and 50P may occur simultaneously, such that gate dielectrics 82 in each region are formed of the same material, and gate electrodes 84 in each region are formed of the same material. In some embodiments, gate structures 80 in each region may be formed by different processes, such that gate dielectrics 82 in each region may be different materials, and gate electrodes 84 in each region may be different materials. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0057] exist Fig. 8A and Figure 8B In the embodiment of the present invention, the second ILD layer 90 is deposited on the first ILD layer 74. The second ILD layer 90 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.; a nitride, such as silicon nitride; or the like. After formation, the second ILD layer 90 may be planarized, for example, by CMP. In some embodiments, an etch stop layer is formed between the first ILD layer 74 and the second ILD layer 90. The etch stop layer may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., having an etch rate different from the etch rate of the material of the second ILD layer 90. In some embodiments, before forming the second ILD layer 90, a gate mask may be formed over the gate dielectric 82 and the gate electrode 84, which may protect the gate dielectric 82 and the gate electrode 84 during contact formation.

[0058] exist Fig.9A and Fig. 9BIn the process, source / drain contact openings 92 are formed through the ILD layers 74, 90. The openings may be formed using acceptable photolithography and etching techniques. The etching may be performed by dry etching that is selective to the material of the ILD layers 74, 90 (e.g., etching the material of the ILD layers 74, 90 at a faster rate than etching the material of the CESL 72). Thus, the CESL 72 stops etching the source / drain contact openings 92. For example, when the ILD layers 74, 90 are formed of silicon oxide, the etching may be dry (e.g., plasma) etching, such as reactive ion etching (RIE), and may be performed using one or more reactive gases (e.g., hexafluoro-1,3-butadiene (C4F6), octafluorocyclopentene (C5F8), octafluorocyclobutane (C4F8), etc.). Plasma may be generated during etching using H2, O2, CO2, etc. As Fig. 9B As shown in the cross-section of FIG. 1 , the source / drain contact opening 92 exposes the first portion 72A of the CESL, e.g., the portion above the epitaxial source / drain region 70, but does not expose the second portion 72B of the CESL, e.g., the portion below the epitaxial source / drain region 70 and on the STI region 56. Notably, some portion of the first ILD layer 74 remains on the second portion 72B of the CESL. The portion of the first ILD layer 74 that remains on the second portion 72B of the CESL has a thickness T2, which may be in the range of about 0 nm to about 50 nm. Leaving some portion of the first ILD layer 74 at the bottom of the source / drain contact opening 92 may help protect the STI region 56 during a subsequent process for forming an undercut in the CESL 72.

[0059] exist Fig. 10A and Fig. 10B In the embodiment, the CESL 72 is opened to expose the epitaxial source / drain regions 70. The CESL 72 is opened by extending the source / drain contact openings 92 through the CESL 72 using an etching process. Fig. 10A As shown in the cross-section of FIG. 1 , after etching, the source / drain contact opening 92 has a width W1 in the CESL 72, which may be in the range of about 8 nm to about 200 nm. Fig. 10B As shown in the cross-section of FIG. 1 , the etching does not remove the second portion 72B of the CESL, but removes the first portion 72A of the CESL (see FIG. 1 ). Fig. 9B ). Therefore, after etching, the top surface of the epitaxial source / drain region 70 is exposed, but the bottom surface of the epitaxial source / drain region 70 is not exposed.

[0060] The etching process used to open CESL 72 is different from the reference Fig.9A and Fig. 9BThe etching process discussed for forming the source / drain contact openings 92 through the ILD layers 74, 90 (e.g., the etching process for opening the CESL 72 is performed using different etching parameters, different etchants, and / or different types of etching than the etching process for forming the source / drain contact openings 92 through the ILD layers 74, 90). The etching may be a wet etch or a dry etch that is selective to the material of the CESL 72 (e.g., etches the material of the CESL 72 at a faster rate than etching the material of the ILD layers 74, 90). As described above, the CESL 72 is formed to a greater thickness T1 (see Figure 5A ). Thus, in some embodiments, the etching may be anisotropic etching. For example, when the CESL 72 is formed of silicon nitride, the etching may be dry (e.g., plasma) etching, such as reactive ion etching (RIE), and may be performed using one or more reactive gases (e.g., fluoromethane (CH3F), etc.). Plasma may be generated during etching using H2, O2, CO2, etc.

[0061] exist Fig.11A and Fig. 11B In the embodiment, the lower portion of the source / drain contact opening 92 is laterally expanded (e.g., widened), thereby forming an undercut 94 (e.g., a gap) between the epitaxial source / drain region 70 and the first ILD layer 74. Therefore, the surface area of ​​the epitaxial source / drain region 70 exposed by the source / drain contact opening 92 is increased. The subsequently formed source / drain contact will be formed to extend at least partially into the undercut 94, thereby increasing the contact surface area of ​​the epitaxial source / drain region 70. Fig.11A As shown in the cross-section of FIG. 8 , the undercut 94 may expose portions of the sidewalls of the gate spacer 66. Fig. 11B As shown in the cross-section of FIG. 7 , the second portion 72B of the CESL is etched to form an undercut 94 at least partially below the epitaxial source / drain regions 70. Thus, after etching, portions of the bottom surfaces of the epitaxial source / drain regions 70 are exposed.

[0062] The etching process used to laterally expand (eg, widen) the lower portion of the source / drain contact opening 92 is different from the reference Fig. 10A and Fig. 10BThe etching process discussed for opening the CESL 72 (e.g., the etching process for laterally expanding (e.g., widening) the lower portion of the source / drain contact opening 92 is performed using different etching parameters, different etchants, and / or different types of etching than the etching process for opening the CESL 72). The etching may be a wet etch or a dry etch that is selective to the material of the CESL 72 (e.g., etching the material of the CESL 72 at a faster rate than etching the material of the ILD layers 74, 90). In some embodiments, the etching is an isotropic etch (or at least etches the CESL 72 to a greater degree of isotropy than the etching process for opening the CESL 72). For example, when the CESL 72 is formed of silicon nitride, the etching may be a wet etch, such as a chemical wet etch, and may be performed using one or more etching chemistries (e.g., phosphoric acid (H3PO4), such as a phosphoric acid solution (e.g., H3PO4:H2O)). The etching may be performed at a high temperature (e.g., in a temperature range of about 100° C. to about 180° C.) for a long duration (e.g., in a range of about 10 seconds to about 30 seconds), which allows the undercut 94 to extend a distance in a range of about 5 nm to about 10 nm below the first ILD layer 74. Forming the undercut 94 with a large size helps provide sufficient space for the subsequent formation of source / drain contacts.

[0063] After forming the undercut 94, the etched portion of the epitaxial source / drain region 70 may have a reduced height. The height of the epitaxial source / drain region 70 may be reduced by the thickness of the CESL 72 (see FIG. Fig. 10A and Fig. 10B ) and / or forming an undercut 94 (see Fig.11A and Fig. 11B ) by one or more of the etching processes of the epitaxial source / drain regions 70. For example, the height of the epitaxial source / drain regions 70 can be reduced by a distance D1, which can be about 1% to about 6% of the original height of the epitaxial source / drain regions 70. In some embodiments, the distance D1 can be from about 0.5 nm to about 3 nm. The size (e.g., height) of the undercut 94 can thus be increased, helping to provide sufficient space for the subsequent formation of source / drain contacts in the undercut 94.

[0064] exist Fig. 12A and Fig. 12BIn the embodiment, silicide 96 is formed in the source / drain contact openings 92 and undercuts 94, for example, on the portions of the epitaxial source / drain regions 70 exposed by the source / drain contact openings 92 and undercuts 94. The silicide 96 can be formed by depositing a metal in the source / drain contact openings 92 and annealing. The metal can be, for example, titanium, cobalt, nickel, etc., and can be deposited by, for example, ALD, CVD, PVD, etc. The silicide 96 is physically and electrically coupled to the epitaxial source / drain regions 70. As shown in FIG. Fig. 12A As shown in the cross-section of FIG. 1 , the silicide 96 contacts the portion of the sidewall of the gate spacer 66 that is exposed by the undercut 94. Fig. 12B As shown in the cross-section of FIG. 9 , the silicide 96 also contacts the bottom surface of the epitaxial source / drain region 70 and the second portion 72B of the CESL exposed by the undercut 94. Therefore, at least some portions of the silicide 96 are disposed between the epitaxial source / drain region 70 and the first ILD layer 74.

[0065] Forming silicide 96 in undercut 94 helps increase the surface area of ​​epitaxial source / drain regions 70 in contact with silicide 96. In addition, as described above, the height of epitaxial source / drain regions 70 can be increased by the thickness of the substrate used to open CESL 72 (see Fig. 10A and Fig. 10B ) and / or forming an undercut 94 (see Fig.11A and Fig. 11B ) by one or more of the etching processes of the above embodiment. The silicide 96 can thus have a large thickness T3, such as a thickness T3 in the range of about 2 nm to about 5 nm (e.g., about 1 nm). Increasing the surface area and thickness of the silicide 96 can help reduce the contact resistance with the epitaxial source / drain regions 70.

[0066] exist Fig.13A and Fig. 13B In the source / drain contact opening 92 and the undercut 94 (see Fig. 12A ) is formed in the source / drain contact openings 92 and undercuts 94. A liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed on the silicide 96 in the source / drain contact openings 92 and undercuts 94. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD layer 90. The remaining liner and conductive material form source / drain contacts 102 in the source / drain contact openings 92 and undercuts 94. The source / drain contacts 102 are physically and electrically coupled to the silicide 96 and are therefore connected to the epitaxial source / drain regions 70. After formation, the source / drain contacts 102 extend through the ILD layers 74, 90. As Fig.13AAs shown in the cross-section of FIG. 1 , the source / drain contacts 102 and the sidewalls of the gate spacers 66 are partially (eg, undercut 94 (see FIG. 1 ) Fig. 12A ) exposed portion). Similarly, the source / drain contacts 102 are in contact with the remaining portion of the CESL 72 extending along the sidewalls of the gate spacers 66. In addition, the first ILD layer 74 is in contact with the top surface of the lower portion of the source / drain contacts 102, and the first ILD layer 74 also surrounds the upper portion of the source / drain contacts 102.

[0067] Forming silicide 96 and source / drain contacts 102 in undercut 94 helps increase the contact surface area of ​​epitaxial source / drain regions 70. Increasing the contact surface area can help reduce the contact resistance with epitaxial source / drain regions 70, especially when the resulting FinFET is formed on a small technology node. In addition, as described above, the height of the epitaxial source / drain regions 70 can be increased by using the CESL 72 (see FIG. Fig. 10A and Fig. 10B ) and / or forming an undercut 94 (see Fig.11A and Fig. 11B ) to reduce one or more of the etching processes of the gate electrode 84 and the source / drain contact 102. Therefore, the portions of the source / drain contact 102 that extend along the surface of the epitaxial source / drain region 70 (e.g., those portions in the undercut 94) can have a large thickness T4, such as a thickness T4 in the range of about 1 nm to about 5 nm. Increasing the thickness of the source / drain contact 102 can help reduce the contact resistance with the epitaxial source / drain region 70. Finally, the parasitic capacitance between the gate electrode 84 and the source / drain contact 102 can be reduced. Therefore, the performance of the FinFET can be improved.

[0068] exist Fig.14A and Fig. 14B In the embodiment of the present invention, a gate contact 104 is formed through the second ILD layer 90. An opening for the gate contact 104 is formed through the second ILD layer 90. The opening can be formed using acceptable photolithography and etching techniques. A liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD layer 90. The remaining liner and conductive material form a gate contact 104 in the opening. The gate contact 104 is physically and electrically coupled to the gate electrode 84, and is therefore connected to the gate electrode 84. The gate contact 104 may penetrate the gate mask (if present) above the gate electrode 84.

[0069] In other embodiments, the order of some of the steps discussed above may be changed. For example, the source / drain contacts 102 and the gate contact 104 may be formed using different processes, or may be formed using the same process. In some embodiments, the gate contact 104 is formed simultaneously with the source / drain contacts 102, for example, the opening for the gate contact 104 is formed simultaneously with the opening for the source / drain contacts 102. The gate electrode 84 may not be substantially used to open the CESL 72 (see Fig. 10A and Fig. 10B ) and / or forming an undercut 94 (see Fig.11A and Fig. 11B ). In addition, although the source / drain contacts 102 and the gate contacts 104 are shown in the same cross section, each of the source / drain contacts 102 and the gate contacts 104 may be formed in a different cross section, which may avoid short circuiting of the contacts.

[0070] Fig.15A and Fig. 15B is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to reference Fig.14A and Fig. 14B The embodiment is described except that the source / drain contact 102 includes a separate lower source / drain contact 102A and an upper source / drain contact 102B. The lower source / drain contact 102A extends through the first ILD layer 74, and the upper source / drain contact 102B extends through the second ILD layer 90. Thus, the lower source / drain contact 102A is disposed between the upper source / drain contact 102B and the silicide 96.

[0071] As an example of forming the lower source / drain contact 102A, an opening and an undercut for the lower source / drain contact 102A may be formed in the first ILD layer 74 and the CESL 72 before forming the second ILD layer 90. FIG. 9A to FIG. 11B The openings are then formed using a process similar to that discussed in reference FIG. 12A to FIG. 13B Silicide 96 and lower source / drain contacts 102A are formed in the openings and undercuts in a similar process to that discussed above. After formation, the top surfaces of gate spacers 66, CESL 72, first ILD layer 74, gate electrode 84, and lower source / drain contacts 102A are coplanar.

[0072] As an example of forming an upper source / drain contact 102B, after forming the second ILD layer 90, an opening for an upper source / drain contact 102B is formed through the second ILD layer 90. Acceptable photolithography and etching techniques can be used to form the opening. A liner (e.g., a diffusion barrier, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD layer 90. The remaining liner and conductive material form an upper source / drain contact 102B in the opening. The upper source / drain contact 102B is connected to the lower source / drain contact 102A, and the lower source / drain contact 102A is connected to the epitaxial source / drain region 70. The upper source / drain contacts 102B and the gate contact 104 may be formed in different processes, or may be formed in the same process. After formation, the top surfaces of the second ILD layer 90, the upper source / drain contacts 102B, and the gate contact 104 are coplanar.

[0073] It should be understood that some embodiments may be combined with FIG. 14A to FIG. 15B For example, the source / drain contacts in the first region of the die (eg, the input / output region) may be continuous conductive features (eg, Fig.14A and Fig. 14B ), while the source / drain contacts in the second region of the die (eg, the core logic region) may have separate upper and lower conductive features in the corresponding ILD layer (eg, Fig.15A and Fig. 15B shown).

[0074] Fig.16A and Fig. 16B is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to reference Fig.14A and Fig. 14B The embodiment described above does not include some portions of undercut 94 remaining after forming source / drain contacts 102. When the material of silicide 96 and / or source / drain contacts 102 is formed by a deposition process having low step coverage, portions of undercut 94 may remain. For example, when CVD is used to deposit the metal for silicide 96, some portions of undercut 94 may not be filled. Fig.16A As shown in the cross-section of FIG. 1 , some portions of the undercut 94 may remain between the gate spacer 66 and each of the silicide 96 and the source / drain contact 102, and expose the gate spacer 66 and each of the silicide 96 and the source / drain contact 102. Fig. 16B As shown in the cross-section of FIG. 1 , the other part of the undercut 94 can remain between the epitaxial source / drain region 70 and the first ILD layer 74, and expose the epitaxial source / drain region 70 and the first ILD layer 74. The undercut 94 in each cross-section can be continuous, or can be discontinuous. The remaining undercut 94 can be referred to as an air gap or void. The void is filled with air, vacuum, etc., and therefore has a low k value, thereby reducing the capacitance between the source / drain contact 102 and the gate electrode 84.

[0075] It should be understood that some embodiments may combine Fig.14A , Fig. 14B , Fig.16A and Fig. 16B For example, some portion of the undercut 94 may remain above the epitaxial source / drain regions 70 (see Fig.16A ), while no undercut remains below the epitaxial source / drain regions 70 and the first ILD layer 74 (see Fig. 14B Likewise, some portion of undercut 94 may remain beneath epitaxial source / drain regions 70 (see Fig. 16B ), while no undercut remains over the epitaxial source / drain regions 70 and the first ILD layer 74 (see Fig.14A ).

[0076] Fig.17A and Fig. 17B is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to reference Fig.16A and Fig. 16B The embodiment is depicted except that the source / drain contact 102 includes separate lower source / drain contacts 102A and upper source / drain contacts 102B.

[0077] Fig.18A and Fig.18B is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to reference Fig.14A and Fig. 14B The embodiment described, except that the silicide 96 contacts a smaller surface area of ​​the epitaxial source / drain regions 70. Reference Return to Fig.11A and Fig. 11BBy reducing the size of the undercut 94, the silicide 96 can be formed to contact less surface area of ​​the epitaxial source / drain region 70. Specifically, the undercut 94 can be formed to extend a smaller distance below the first ILD layer 74 so that the undercut 94 does not expose a portion of the sidewall of the gate spacer 66, and so that a portion of the CESL 72 remains between the first ILD layer 74 and the epitaxial source / drain region 70. Therefore, the sidewall of the CESL 72 above the epitaxial source / drain region 70 is exposed by the undercut 94. The width of the undercut 94 can be reduced by changing the parameters of the etch used to form the undercut 94. For example, the etch can be performed for a shorter duration (e.g., a duration in the range of about 2 seconds to about 10 seconds), or at a lower temperature (e.g., a temperature in the range of about 25° C. to about 100° C.), which allows the undercut 94 to extend a distance in the range of about 1 nm to about 5 nm below the first ILD layer 74. Forming the undercut 94 with a smaller size helps to reduce the manufacturing cost of the FinFET.

[0078] Fig.19A and Fig.19B is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to reference Fig.18A and Fig.18B The embodiment is depicted except that the source / drain contact 102 includes separate lower source / drain contacts 102A and upper source / drain contacts 102B.

[0079] Fig. 20A and Fig. 20B is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to reference Fig.18A and Fig.18B The embodiment described above is described except that some portions of undercut 94 remain after forming source / drain contacts 102. When the material of silicide 96 and / or source / drain contacts 102 is formed by a deposition process with low step coverage, portions of undercut 94 may remain. For example, when CVD is used to deposit the metal for silicide 96, some portions of undercut 94 may not be filled. Fig. 20A As shown in the cross-section of FIG. 1 , undercut 94 may remain between CESL 72 and each of silicide 96 and source / drain contacts 102. Fig. 20B As shown in the cross-section of FIG. 8 , an undercut 94 may remain between the epitaxial source / drain regions 70 and the first ILD layer 74 .

[0080] It should be understood that some embodiments may combine Fig.18A , Fig.18B , Fig. 20A and Fig. 20BFor example, some portion of the undercut 94 may remain above the epitaxial source / drain regions 70 (see Fig. 20A ), while no undercut remains below the epitaxial source / drain regions 70 and the first ILD layer 74 (see Fig.18B Likewise, some portion of undercut 94 may remain beneath epitaxial source / drain regions 70 (see Fig. 20B ), while no undercut remains over the epitaxial source / drain regions 70 and the first ILD layer 74 (see Fig.18A ).

[0081] Fig.21A and Fig.21B is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to reference Fig. 20A and Fig. 20B The embodiment is depicted except that the source / drain contact 102 includes separate lower source / drain contacts 102A and upper source / drain contacts 102B.

[0082] Embodiments can achieve advantages. Forming the undercut 94 allows the silicide 96 and the source / drain contact 102 to contact more surface area of ​​the epitaxial source / drain region 70. Increasing the contact surface area can help reduce the contact resistance with the epitaxial source / drain region 70, especially when the resulting FinFET is formed on a small technology node. In addition, forming the undercut 94 allows increasing the thickness of the silicide 96 and the portion of the source / drain contact 102 in the undercut 94. Increasing the thickness of the silicide 96 and the source / drain contact 102 can help reduce the contact resistance with the epitaxial source / drain region 70. Finally, by reducing the amount of dielectric material around the epitaxial source / drain region 70, the parasitic capacitance between the gate electrode 84 and the source / drain contact 102 can be reduced. Therefore, the performance of the FinFET can be improved.

[0083] In an embodiment, a structure includes: a gate stack located above a channel region of a substrate; a source / drain region adjacent to the channel region; a first interlayer dielectric (ILD) layer located above the source / drain region; a silicide located between the first ILD layer and the source / drain region, the silicide contacting a top surface of the source / drain region and a bottom surface of the source / drain region; and a first source / drain contact having a first portion and a second portion, the first portion of the first source / drain contact being disposed between the silicide and the first ILD layer, the second portion of the first source / drain contact extending through the first ILD layer and contacting the silicide.

[0084] In some embodiments, the structure further comprises: a gate spacer separating the source / drain region from the gate stack; a sidewall of the gate spacer in contact with the silicide and the first source / drain contact; and a contact etch stop layer (CESL) extending along the sidewall of the gate spacer, the CESL in contact with the first source / drain contact. In some embodiments, the structure further comprises: a gate spacer separating the source / drain region from the gate stack; a contact etch stop layer (CESL) extending along the sidewall of the gate spacer; and a void between the CESL and the source / drain region, the void exposing the surface of the gate spacer, the silicide, and the first source / drain contact. In some embodiments, the structure further comprises: a gate spacer separating the source / drain region from the gate stack; and a contact etch stop layer (CESL) extending along the sidewall of the gate spacer and the top surface of the source / drain region, the CESL in contact with the silicide and the first source / drain contact. In some embodiments, the structure further comprises: a gate spacer separating the source / drain region from the gate stack; a contact etch stop layer (CESL) extending along the sidewalls of the gate spacer and the top surface of the source / drain region; and a void located between the first ILD layer and the source / drain region, the void exposing the surface of the CESL, the silicide, and the first source / drain contact. In some embodiments, the structure further comprises: a second ILD layer located on the first ILD layer; and a second source / drain contact extending through the second ILD layer, the second source / drain contact contacting the first source / drain contact; and a gate contact extending through the second ILD layer, the gate contact contacting the gate stack, wherein the top surfaces of the first ILD layer, the first source / drain contact, and the gate stack are coplanar, and wherein the top surfaces of the second ILD layer, the second source / drain contact, and the gate contact are coplanar. In some embodiments, the structure further includes: a second ILD layer located on the first ILD layer, the first source / drain contact extending through the second ILD layer; and a gate contact extending through the second ILD layer, the gate contact contacting the gate stack, wherein top surfaces of the second ILD layer, the first source / drain contact, and the gate contact are coplanar.

[0085] In an embodiment, a structure includes: a gate stack located on a substrate; a gate spacer adjacent to the gate stack; a source / drain region adjacent to the gate spacer; a silicide located on the source / drain region, the silicide contacting the sidewall of the gate spacer; a source / drain contact located on the silicide, the source / drain contact contacting the sidewall of the gate spacer; and an interlayer dielectric (ILD) layer located on a lower portion of the source / drain contact, the ILD layer surrounding an upper portion of the source / drain contact.

[0086] In some embodiments, the structure further comprises: a contact etch stop layer (CESL) in contact with a top surface of the source / drain contact, a sidewall of the gate spacer, and a sidewall of the ILD layer. In some embodiments of the structure, the silicide has a first portion and a second portion, the first portion being disposed between a top surface of the source / drain region and the source / drain contact, and the second portion being disposed between a bottom surface of the source / drain region and the ILD layer. In some embodiments, the structure further comprises: a void exposing a bottom surface of the source / drain region, a surface of the ILD layer, and a surface of the silicide.

[0087] In an embodiment, a method includes: depositing a contact etch stop layer (CESL) over source / drain regions; depositing an interlayer dielectric (ILD) layer over the CESL; etching an opening in the ILD layer; extending the opening through the CESL using a first etching process, the first etching process being anisotropic; widening a lower portion of the opening to form an undercut between the ILD layer and the source / drain regions using a second etching process, the second etching process being isotropic; forming a silicide in the opening and the undercut, the silicide contacting the source / drain regions; and forming a source / drain contact in the opening and the undercut, the source / drain contact contacting the silicide.

[0088] In some embodiments, the method further includes: forming a gate spacer adjacent to the source / drain region, wherein, after widening the lower portion of the opening, the undercut exposes a sidewall of the gate spacer. In some embodiments of the method, after forming the source / drain contact and the silicide, the sidewall of the gate spacer contacts each of the source / drain contact and the silicide. In some embodiments of the method, after forming the source / drain contact and the silicide, a portion of the undercut remains between the sidewall of the gate spacer and each of the source / drain contact and the silicide. In some embodiments of the method, the CESL is formed of silicon nitride, the ILD layer is formed of silicon oxide, the first etching process is a dry etching performed using fluoromethane, and the second etching process is a wet etching performed using phosphoric acid, wherein the second etching process is performed at a temperature of 100° C. to 180° C. for a duration of 10 seconds to 30 seconds. In some embodiments of the method, after widening the lower portion of the opening, the undercut exposes the sidewall of the CESL. In some embodiments of the method, after forming the source / drain contacts and the silicide, a sidewall of the CESL contacts each of the source / drain contacts and the silicide. In some embodiments of the method, after forming the source / drain contacts and the silicide, a portion of the undercut remains between the sidewall of the CESL and each of the source / drain contacts and the silicide. In some embodiments of the method, the CESL is formed of silicon nitride, the ILD layer is formed of silicon oxide, the first etching process is dry etching performed using fluoromethane, and the second etching process is wet etching performed using phosphoric acid, wherein the second etching process is performed at a temperature of 25° C. to 100° C. for a duration of 2 seconds to 10 seconds.

[0089] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0090] Example 1. A semiconductor device structure, comprising: a gate stack located above a channel region of a substrate; a source / drain region adjacent to the channel region; a first interlayer dielectric (ILD) layer located above the source / drain region; a silicide located between the first ILD layer and the source / drain region, the silicide contacting a top surface of the source / drain region and a bottom surface of the source / drain region; and a first source / drain contact having a first portion and a second portion, the first portion of the first source / drain contact being disposed between the silicide and the first ILD layer, the second portion of the first source / drain contact extending through the first ILD layer and contacting the silicide.

[0091] Example 2. The structure according to Example 1 further includes: a gate spacer separating the source / drain region from the gate stack, the sidewalls of the gate spacer contacting the silicide and the first source / drain contact; and a contact etch stop layer (CESL) extending along the sidewalls of the gate spacer, the CESL contacting the first source / drain contact.

[0092] Example 3. The structure according to Example 1 further includes: a gate spacer separating the source / drain region from the gate stack; a contact etch stop layer (CESL) extending along the sidewalls of the gate spacer; and a gap located between the CESL and the source / drain region, the gap exposing the surface of the gate spacer, the silicide and the first source / drain contact.

[0093] Example 4. The structure according to Example 1 further includes: a gate spacer separating the source / drain region from the gate stack; and a contact etch stop layer (CESL) extending along the sidewalls of the gate spacer and the top surface of the source / drain region, the CESL being in contact with the silicide and the first source / drain contact.

[0094] Example 5. The structure according to Example 1 further includes: a gate spacer separating the source / drain region from the gate stack; a contact etch stop layer (CESL) extending along the sidewalls of the gate spacer and the top surface of the source / drain region; and a gap located between the first ILD layer and the source / drain region, the gap exposing the surface of the CESL, the silicide and the first source / drain contact.

[0095] Example 6. The structure according to Example 1 further includes: a second ILD layer located on the first ILD layer; a second source / drain contact extending through the second ILD layer, the second source / drain contact contacting the first source / drain contact; and a gate contact extending through the second ILD layer, the gate contact contacting the gate stack, wherein the top surfaces of the first ILD layer, the first source / drain contact and the gate stack are coplanar, and wherein the top surfaces of the second ILD layer, the second source / drain contact and the gate contact are coplanar.

[0096] Example 7. The structure according to Example 1 further includes: a second ILD layer located on the first ILD layer, the first source / drain contact extending through the second ILD layer; and a gate contact extending through the second ILD layer, the gate contact contacting the gate stack, wherein the top surfaces of the second ILD layer, the first source / drain contact and the gate contact are coplanar.

[0097] Example 8. A semiconductor device structure, comprising: a gate stack located on a substrate; a gate spacer adjacent to the gate stack; a source / drain region adjacent to the gate spacer; a silicide located on the source / drain region, the silicide contacting the sidewall of the gate spacer; a source / drain contact located on the silicide, the source / drain contact contacting the sidewall of the gate spacer; and an interlayer dielectric (ILD) layer located on a lower portion of the source / drain contact, the ILD layer surrounding an upper portion of the source / drain contact.

[0098] Example 9. The structure of Example 8, further comprising: a contact etch stop layer (CESL) in contact with top surfaces of the source / drain contacts, sidewalls of the gate spacers, and sidewalls of the ILD layer.

[0099] Example 10. The structure of Example 8, wherein the silicide has a first portion and a second portion, the first portion being disposed between a top surface of the source / drain region and the source / drain contact, and the second portion being disposed between a bottom surface of the source / drain region and the ILD layer.

[0100] Example 11. The structure of Example 10, further comprising: a gap exposing a bottom surface of the source / drain region, a surface of the ILD layer, and a surface of the silicide.

[0101] Example 12. A method for manufacturing a semiconductor device, comprising: depositing a contact etch stop layer (CESL) over a source / drain region; depositing an interlayer dielectric (ILD) layer over the CESL; etching an opening in the ILD layer; extending the opening through the CESL using a first etching process, the first etching process being anisotropic; widening a lower portion of the opening using a second etching process to form an undercut between the ILD layer and the source / drain region, the second etching process being isotropic; forming a silicide in the opening and the undercut, the silicide contacting the source / drain region; and forming a source / drain contact in the opening and the undercut, the source / drain contact contacting the silicide.

[0102] Example 13. The method of Example 12, further comprising: forming a gate spacer adjacent to the source / drain region, wherein after widening the lower portion of the opening, the undercut exposes a sidewall of the gate spacer.

[0103] Example 14. The method of Example 13, wherein after forming the source / drain contacts and the silicide, a sidewall of the gate spacer contacts each of the source / drain contacts and the silicide.

[0104] Example 15. The method of Example 13, wherein after forming the source / drain contacts and the silicide, a portion of the undercut remains between a sidewall of the gate spacer and each of the source / drain contacts and the silicide.

[0105] Example 16. A method according to Example 13, wherein the CESL is formed of silicon nitride, the ILD layer is formed of silicon oxide, the first etching process is dry etching performed using fluoromethane, and the second etching process is wet etching performed using phosphoric acid, wherein the second etching process is performed at a temperature of 100° C. to 180° C. for a duration of 10 seconds to 30 seconds.

[0106] Example 17. The method of Example 12, wherein after widening the lower portion of the opening, the undercut exposes a sidewall of the CESL.

[0107] Example 18. The method of Example 17, wherein after forming the source / drain contacts and the silicide, a sidewall of the CESL is in contact with each of the source / drain contacts and the silicide.

[0108] Example 19. The method of Example 17, wherein after forming the source / drain contacts and the silicide, a portion of the undercut remains between a sidewall of the CESL and each of the source / drain contacts and the silicide.

[0109] Example 20. A method according to Example 17, wherein the CESL is formed of silicon nitride, the ILD layer is formed of silicon oxide, the first etching process is dry etching performed using fluoromethane, and the second etching process is wet etching performed using phosphoric acid, wherein the second etching process is performed at a temperature of 25°C to 100°C for a duration of 2 seconds to 10 seconds.

Claims

1. A semiconductor device structure, comprising: a gate stack located above the channel region of the substrate; a source / drain region adjacent to the channel region; a gate spacer separating the source / drain region from the gate stack; A contact etch stop layer CESL extending along a sidewall of the gate spacer; A first interlayer dielectric ILD layer, located on the source / drain region; a silicide, located between the first ILD layer and the source / drain region, the silicide contacting a top surface of the source / drain region and a bottom surface of the source / drain region; a first source / drain contact having a first portion and a second portion, wherein the first portion of the first source / drain contact is disposed between the silicide and the first ILD layer, and the second portion of the first source / drain contact extends through the first ILD layer and contacts the silicide; Wherein, the structure further comprises: a gap located between the CESL and the source / drain region, the gap exposing surfaces of the gate spacer, the silicide and the first source / drain contact; or The CESL also extends along the top surface of the source / drain region; and the structure further includes: a gap located between the first ILD layer and the source / drain region, the gap exposing surfaces of the CESL, the silicide and the first source / drain contact.

2. The structure according to claim 1, further comprising: a second ILD layer, located on the first ILD layer; a second source / drain contact extending through the second ILD layer, the second source / drain contact contacting the first source / drain contact; as well as a gate contact extending through the second ILD layer, the gate contact contacting the gate stack, wherein the top surfaces of the first ILD layer, the first source / drain contact, and the gate stack are coplanar, and Wherein top surfaces of the second ILD layer, the second source / drain contacts and the gate contact are coplanar.

3. The structure according to claim 1, further comprising: a second ILD layer disposed on the first ILD layer, the first source / drain contact extending through the second ILD layer; as well as a gate contact extending through the second ILD layer, the gate contact being in contact with the gate stack, Wherein top surfaces of the second ILD layer, the first source / drain contacts and the gate contact are coplanar.

4. A semiconductor device structure, comprising: a gate stack disposed on the substrate; a gate spacer adjacent to the gate stack; a source / drain region adjacent to the gate spacer; a silicide located on the source / drain region, the silicide contacting a sidewall of the gate spacer; a source / drain contact, located on the silicide, the source / drain contact being in contact with a sidewall of the gate spacer; an interlayer dielectric ILD layer located on a lower portion of the source / drain contact, the ILD layer surrounding an upper portion of the source / drain contact, and A gap is formed to expose the bottom surface of the source / drain region, the surface of the ILD layer, and the surface of the silicide.

5. The structure according to claim 4, further comprising: A contact etch stop layer CESL contacts top surfaces of the source / drain contacts, sidewalls of the gate spacers, and sidewalls of the ILD layer.

6. The structure according to claim 4, wherein: The silicide has a first portion disposed between a top surface of the source / drain region and the source / drain contact and a second portion disposed between a bottom surface of the source / drain region and the ILD layer.

7. A method for forming a semiconductor device, comprising: forming a gate spacer adjacent to the source / drain region; depositing a contact etch stop layer (CESL) on the source / drain region; depositing an interlayer dielectric ILD layer on the CESL; etching an opening in the ILD layer; extending the opening through the CESL using a first etching process, the first etching process being anisotropic; widening a lower portion of the opening by etching the CESL to form an undercut between the ILD layer and the source / drain regions using a second etching process, wherein the second etching process is isotropic; forming a silicide in the opening and the undercut, the silicide being in contact with the source / drain region; as well as forming source / drain contacts in the opening and the undercut, the source / drain contacts being in contact with the silicide, wherein the undercut exposes a sidewall of the gate spacer after widening a lower portion of the opening, and a portion of the undercut remains between the sidewall of the gate spacer and each of the source / drain contact and the silicide after forming the source / drain contact and the silicide; or wherein after widening a lower portion of the opening, the undercut exposes a sidewall of the CESL, and after forming the source / drain contacts and the silicide, a portion of the undercut remains between the sidewall of the CESL and each of the source / drain contacts and the silicide.

8. The method according to claim 7, wherein: The CESL is formed of silicon nitride, the ILD layer is formed of silicon oxide, the first etching process is dry etching performed using fluoromethane, and the second etching process is wet etching performed using phosphoric acid.

9. The method according to claim 8, wherein: In the case where the undercut exposes the sidewalls of the gate spacers, the second etching process is performed at a temperature of 100° C. to 180° C. for a duration of 10 seconds to 30 seconds.

10. The method according to claim 8, wherein: In the case where the undercut exposes the sidewall of the CESL, the second etching process is performed at a temperature of 25° C. to 100° C. for a duration of 2 seconds to 10 seconds.

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