Display panel, preparation method thereof and display device

Abstract

The display panel and the manufacturing method thereof and the display device belong to the technical field of display. The display panel comprises a substrate, a driving circuit layer, a pixel layer and a thin film packaging layer which are sequentially stacked. The thin film packaging layer comprises a first inorganic packaging layer, an organic packaging layer and a second inorganic packaging layer which are sequentially stacked on the side of the pixel layer away from the substrate. The display panel comprises a display area and a peripheral area surrounding the display area; the edges of the first inorganic packaging layer and the second inorganic packaging layer are located in the peripheral area. The slope angle of the edge of the first inorganic packaging layer is in the range of 40°-90°; the slope angle of the edge of the second inorganic packaging layer is in the range of 40°-90°. The display panel can reduce the frame width of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] In AMOLED (active matrix organic light-emitting diode) display panels, a thin film encapsulation layer is usually required to prevent water and oxygen intrusion. However, in the prior art, the boundary of the thin film encapsulation layer is difficult to accurately define, resulting in a large border of the display panel.

[0003] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the Invention

[0004] The present disclosure aims to provide a display panel, a method for manufacturing the same, and a display device, which can reduce the width of a display panel frame.

[0005] To achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0006] According to a first aspect of the present disclosure, a display panel is provided, comprising a base substrate, a driving circuit layer, a pixel layer, and a thin film encapsulation layer stacked in sequence; wherein the thin film encapsulation layer comprises a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence on a side of the pixel layer away from the base substrate;

[0007] The display panel includes a display area and a peripheral area surrounding the display area; edges of the first inorganic encapsulation layer and the second inorganic encapsulation layer are located in the peripheral area;

[0008] The slope angle of the edge of the first inorganic encapsulation layer is within a range of 40° to 90°; the slope angle of the edge of the second inorganic encapsulation layer is within a range of 40° to 90°.

[0009] In an exemplary embodiment of the present disclosure, the material of the second inorganic encapsulation layer is an oxygen-free inorganic material, and the second inorganic encapsulation layer covers an edge of the first inorganic encapsulation layer.

[0010] In an exemplary embodiment of the present disclosure, the thin film encapsulation layer further includes a third inorganic encapsulation layer, and the third inorganic encapsulation layer is located between the organic encapsulation layer and the second inorganic encapsulation layer;

[0011] The slope angle of the edge of the third inorganic encapsulation layer is in the range of 40° to 90°; the edge of the third inorganic encapsulation layer is flush with the edge of the first inorganic encapsulation layer.

[0012] In an exemplary embodiment of the present disclosure, in the peripheral area, the display panel is provided with a blocking dam and a crack prevention dam;

[0013] The driving circuit layer includes an inorganic dielectric layer and a passivation layer stacked in sequence on one side of the base substrate;

[0014] The inorganic dielectric layer is provided with a partition groove between the blocking dam and the crack prevention dam, and the partition groove penetrates the inorganic dielectric layer and exposes the base substrate.

[0015] In an exemplary embodiment of the present disclosure, the second inorganic encapsulation layer is disposed on a surface of the passivation layer on a side of the first inorganic encapsulation layer away from the display area.

[0016] In an exemplary embodiment of the present disclosure, the peripheral area includes a fan-out area and a non-fan-out area adjacent to the fan-out area; the driving circuit layer is provided with a fan-out trace in the fan-out area;

[0017] The partition groove includes a first partition groove located in the non-fan-out area;

[0018] In the first partition groove, the passivation layer is provided with a partition hole exposing the base substrate.

[0019] In an exemplary embodiment of the present disclosure, the display panel is further provided with a crack detection line; in the non-fan-out area, the crack detection line is located between the first partition groove and the blocking dam.

[0020] In an exemplary embodiment of the present disclosure, the peripheral area includes a fan-out area and a non-fan-out area adjacent to the fan-out area; the driving circuit layer is provided with a fan-out trace in the fan-out area;

[0021] The partition groove includes a second partition groove located in the fan-out area;

[0022] The passivation layer covers the second partition groove; and the fan-out wiring is arranged on a side of the passivation layer away from the base substrate.

[0023] According to a first aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0024] According to a first aspect of the present disclosure, a method for manufacturing a display panel is provided. The display panel includes a display area and a peripheral area surrounding the display area. The method for manufacturing the display panel includes:

[0025] providing a substrate;

[0026] forming a driving circuit layer on one side of the base substrate;

[0027] forming a pixel layer on a side of the driving circuit layer away from the base substrate;

[0028] forming a first packaging material layer covering the display area and the peripheral area on a side of the pixel layer away from the base substrate;

[0029] performing a patterning operation on the first encapsulation material layer to form a first inorganic encapsulation layer, wherein an edge of the first inorganic encapsulation layer is located in the peripheral region;

[0030] forming an organic encapsulation layer on a side of the first inorganic encapsulation layer away from the base substrate;

[0031] forming a second encapsulation material layer covering the display area and the peripheral area on a side of the organic encapsulation layer away from the base substrate;

[0032] The second encapsulation material layer is patterned to form a second inorganic encapsulation layer, wherein an edge of the second inorganic encapsulation layer is located in the peripheral region. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

[0034] Figure 1 This is a structural diagram of a display panel in related technology.

[0035] Figure 2 It is a structural schematic diagram of a display device in one embodiment of the present disclosure.

[0036] Figure 3 FIG1 is a schematic top view of the structure of a display panel in one embodiment of the present disclosure.

[0037] Figure 4 It is a schematic cross-sectional view of the structure of a display panel in one embodiment of the present disclosure.

[0038] Figure 5 It is a schematic structural diagram of forming a first inorganic encapsulation layer in one embodiment of the present disclosure.

[0039] Figure 6 It is a schematic structural diagram of forming a second packaging material layer in one embodiment of the present disclosure.

[0040] Figure 7 It is a schematic structural diagram of forming a second inorganic encapsulation layer in one embodiment of the present disclosure.

[0041] Figure 8 It is a schematic structural diagram of forming a partition hole in one embodiment of the present disclosure.

[0042] Figure 9 This is a schematic diagram comparing the structures of a display panel disclosed herein and a display panel in related art at the frame.

[0043] Figure 10 It is a schematic structural diagram of forming a first packaging material layer in one embodiment of the present disclosure.

[0044] Figure 11 It is a schematic structural diagram of forming a third packaging material layer in one embodiment of the present disclosure.

[0045] Figure 12 It is a schematic structural diagram of forming a first inorganic encapsulation layer and a third inorganic encapsulation layer in one embodiment of the present disclosure.

[0046] Figure 13 It is a schematic structural diagram of forming a second packaging material layer in one embodiment of the present disclosure.

[0047] Figure 14 This is a schematic diagram comparing the structures of a display panel disclosed herein and a display panel in related art at the frame.

[0048] Figure 15 This is a schematic diagram comparing the structures of a display panel disclosed herein and a display panel in related art on the fan-out area side.

[0049] Figure 16 This is a process flow chart of a display panel according to an embodiment of the present disclosure.

[0050] The main components in the figure are described as follows:

[0051] F100, base substrate; F200, driving circuit layer; F201, buffer material layer; F204, first gate insulating layer; F205, second gate insulating layer; F206, interlayer dielectric layer; F207, first source and drain metal layer; F208, passivation layer; F209, second source and drain metal layer; F210, planarization layer; F300, pixel layer; F301, pixel electrode layer; F302, pixel definition layer; F303, support column layer; F400, thin film encapsulation layer; F401, first inorganic encapsulation layer; F402, second inorganic encapsulation layer; F403, third inorganic encapsulation layer; F500, anti-crack dam; F600, supporting substrate; F700, crack detection trace; G100, partition groove; G101, partition hole; AA, display area; BB, peripheral area; CC, binding area; DD, fan-out area; BD, bending area. DETAILED DESCRIPTION

[0052] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the present disclosure.

[0053] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

[0054] The described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be adopted. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main technical ideas of the present disclosure.

[0055] When a structure is “on” another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” disposed on the other structure, or that the structure is “indirectly” disposed on the other structure via another structure.

[0056] The terms "a," "an," and "the" are used to indicate the presence of one or more elements / components; the terms "including" and "having" are used to indicate an open-ended inclusiveness and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc. The terms "first," "second," etc. are used merely as labels and do not limit the quantity of the items to which they refer.

[0057] In the embodiments of the present disclosure, a display panel and a display device using the display panel are provided. Figure 4 The display panel includes a base substrate F100, a driving circuit layer F200, a pixel layer F300, and a thin film encapsulation layer F400 stacked in sequence. The pixel layer F300 may be provided with a light-emitting element as a sub-pixel, and the driving circuit layer F200 is provided with a pixel driving circuit for driving the light-emitting element.

[0058] In the present disclosure, the substrate F100 can be a substrate F100 of an inorganic material, or a substrate F100 of an organic material. For example, the material of the substrate F100 can be a glass material such as soda-lime glass, quartz glass, sapphire glass, or can be a metal material such as stainless steel, aluminum, nickel, etc. For another example, the material of the substrate F100 can be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyethersulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof.

[0059] Optionally, the base substrate F100 may be a flexible base substrate F100, and thus the display panel of the present disclosure may be a flexible display panel. In one embodiment of the present disclosure, the base substrate F100 may be made of a layer of flexible organic material, such as polyimide (PI). In other embodiments, the flexible base substrate F100 may be a composite of multiple layers including flexible organic material, such as polyimide layers and barrier layers between the polyimide layers.

[0060] Optionally, the base substrate F100 may be made of a transparent material, so that the display panel of the present disclosure can be used as a transparent display panel.

[0061] For example, in one embodiment of the present disclosure, the material of the base substrate F100 may include one or more layers of organic transparent flexible material layers (e.g., polyimide layers, etc.). When the number of organic transparent flexible material layers is multiple, an inorganic material layer may be sandwiched between adjacent organic transparent flexible material layers, such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. In this example, the base substrate F100 is a flexible and transparent base substrate F100, so that the display panel of the present disclosure is a flexible and transparent display panel. See Figure 2In the display device of the present disclosure, the flexible transparent display panel PNL can be attached to a rigid transparent substrate WG for transparent display, and the display panel can be adapted to either a flat or curved substrate. Furthermore, the rigid transparent substrate F600 can be window glass, such as a shop window or a car window.

[0062] In this disclosure, see Figure 4 The driving circuit layer F200 is provided with a pixel driving circuit for driving sub-pixels. Any pixel driving circuit may include a transistor F200M and a storage capacitor ( Figure 4 (not shown in the figure). Furthermore, the transistor may be a thin film transistor. The thin film transistor may be a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor. In one embodiment of the present disclosure, the thin film transistor is a low-temperature polycrystalline silicon transistor.

[0063] It is understood that, among the transistors in the pixel driving circuit, the types of any two transistors may be the same or different. For example, in one embodiment, in a pixel driving circuit, some transistors may be N-type transistors and some transistors may be P-type transistors. For another example, in another embodiment of the present disclosure, in a pixel driving circuit, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material.

[0064] Optionally, the driving circuit layer F200 may include a semiconductor layer F203, a gate insulating layer F240, a gate layer F250, an interlayer dielectric layer F206, a source-drain metal layer SD, a planarization layer F210, etc. stacked between the base substrate F100 and the pixel layer F300. Each thin film transistor and storage capacitor may be formed by film layers such as a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a source-drain metal layer, etc. The positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor. For example, in one embodiment of the present disclosure, the driving circuit layer F200 may include a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a source-drain metal layer stacked in sequence, and the thin film transistor formed in this way is a top-gate thin film transistor. For another example, in another embodiment of the present disclosure, the driving circuit layer F200 may include a gate layer, a gate insulating layer, a semiconductor layer, an interlayer dielectric layer, and a source-drain metal layer stacked in sequence, and the thin film transistor formed in this way is a bottom-gate thin film transistor.

[0065] Optionally, the driving circuit layer F200 may also adopt a dual-gate layer structure, that is, the gate layer may include a first gate layer and a second gate layer, and the gate insulating layer F240 may include a first gate insulating layer F204 for isolating the semiconductor layer and the first gate layer, and a second gate insulating layer F205 for isolating the first gate layer and the second gate layer. For example, in one embodiment of the present disclosure, the driving circuit layer F200 may include a semiconductor layer, a first gate insulating layer F204, a first gate layer, a second gate insulating layer F205, a second gate layer, an interlayer dielectric layer, and a source / drain metal layer, which are sequentially stacked on one side of the base substrate F100.

[0066] Optionally, the driving circuit layer F200 may also adopt a dual source-drain metal layer structure, that is, the source-drain metal layer SD may include a first source-drain metal layer F207 and a second source-drain metal layer F209, and the two source-drain metal layers may be isolated by an insulating medium. The insulating medium may be an inorganic material (for example, a silicon nitride layer serving as a passivation layer F208), an organic material (for example, a resin layer serving as a planarization layer), or a stack of inorganic and organic materials (for example, a passivation layer F208 stacked on the first source-drain metal layer F207 and a planarization layer stacked on the passivation layer F208). For example, in one embodiment of the present disclosure, the driving circuit layer F200 may include a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer F206, a first source-drain metal layer F207, a passivation layer F208, and a second source-drain metal layer F209 stacked in sequence on one side of the base substrate F100. In one embodiment of the present disclosure, the driver circuit layer F200 employs a dual-gate layer and dual-source / drain metal layer structure. For example, the driver circuit layer F200 includes a semiconductor layer, a first gate insulating layer F204, a first gate layer, a second gate insulating layer F205, a second gate layer, an interlayer dielectric layer F206, a first source / drain metal layer F207, a passivation layer F208, a second source / drain metal layer F209, and a planarization layer F210, stacked in sequence.

[0067] Optionally, the drive circuit layer F200 may further include a buffer material layer F201 disposed between the base substrate F100 and the semiconductor layer, with the semiconductor layer, gate layer, etc. all located on the side of the buffer material layer F201 away from the base substrate F100. The buffer material layer F201 may be made of an inorganic insulating material such as silicon oxide or silicon nitride. The buffer material layer F201 may be a single inorganic material layer or a plurality of stacked inorganic material layers. The buffer layer can improve the bonding strength between the drive circuit layer F200 and the base substrate F100 and provide a stable environment for the drive circuit layer F200.

[0068] In the present disclosure, the pixel layer F300 may be provided with a light-emitting element electrically connected to a corresponding pixel driving circuit, and the light-emitting element may serve as a sub-pixel of the display panel. In this way, the pixel layer F300 is provided with light-emitting elements distributed in an array, and each light-emitting element emits light under the control of the pixel driving circuit. In the present disclosure, the light-emitting element may be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot-organic light-emitting diode (QD-OLED) or other types of light-emitting elements. For example, in one embodiment of the present disclosure, the light-emitting element is an organic light-emitting diode (OLED), and the display panel is an OLED display panel. As follows, taking the light-emitting element as an organic light-emitting diode as an example, an exemplary introduction to a feasible structure of the pixel layer F300 is given.

[0069] In this exemplary OLED display panel, the pixel layer F300 may include a pixel electrode layer F301, a pixel definition layer F302, a support column layer F303, an organic light-emitting functional layer F304, and a common electrode layer F305, which are stacked in sequence. Among them, the pixel electrode layer F301 has a plurality of pixel electrodes in the display area AA of the display panel; the pixel definition layer F302 has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes in the display area AA, and any pixel opening exposes at least a portion of the corresponding pixel electrode. The support column layer F303 includes a plurality of support columns in the display area AA, and the support columns are located on the surface of the pixel definition layer F302 away from the base substrate F100 so as to support the fine metal mask (Fine Metal Mask, FMM) during the evaporation process. The organic light-emitting functional layer at least covers the pixel electrodes exposed by the pixel definition layer F302. Among them, the organic light-emitting functional layer may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer. The various film layers of the organic light-emitting functional layer can be prepared by an evaporation process, and a fine metal mask or an open mask (OpenMask) can be used to define the pattern of each film layer during evaporation. The common electrode layer can cover the organic light-emitting functional layer in the display area AA. In this way, the pixel electrode, the common electrode layer and the organic light-emitting functional layer located between the pixel electrode and the common electrode layer form an organic electroluminescent diode F300D, and any organic electroluminescent diode can be used as a sub-pixel of the display panel.

[0070] In some embodiments, the pixel layer F300 may further include a light extraction layer located on a side of the common electrode layer away from the base substrate F100 to enhance the light extraction efficiency of the organic light emitting diode.

[0071] In the present disclosure, the thin film encapsulation layer F400 is disposed on the surface of the pixel layer F300 away from the base substrate F100 and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic encapsulation layer effectively blocks external moisture and oxygen, preventing moisture and oxygen from invading the organic light-emitting functional layer and causing material degradation.

[0072] In one embodiment of the present disclosure, the thin film encapsulation layer F400 may include a first inorganic encapsulation layer F401, an organic encapsulation layer IJP, and a second inorganic encapsulation layer F402, which are sequentially stacked on the side of the pixel layer F300 away from the base substrate F100. The organic encapsulation layer IJP may be located between adjacent first and second inorganic encapsulation layers F401, F402, to achieve planarization and reduce stress between the inorganic encapsulation layers. In one embodiment of the present disclosure, the materials of the first and second inorganic encapsulation layers F401, F402 may be different. Specifically, the oxygen content of the first inorganic encapsulation layer F401 may be higher than that of the second inorganic encapsulation layer F402. In this way, the first inorganic encapsulation layer F401 has a higher oxygen content, which can facilitate the preparation of the organic encapsulation layer, especially the leveling of the organic liquid material used to prepare the organic encapsulation layer. The second inorganic encapsulation layer F402 has a lower oxygen content or even no oxygen, and therefore has a better water and oxygen barrier effect, which can improve the encapsulation effect of the display panel.

[0073] Optionally, the first inorganic encapsulation layer F401 can be made of an inorganic dielectric material containing oxygen, such as silicon oxide or silicon oxynitride, to facilitate the preparation of the organic encapsulation layer, especially the leveling of the organic liquid material used to prepare the organic encapsulation layer. When preparing the organic encapsulation layer, inkjet printing can be used to add an organic liquid material (such as an organic ink) to the side of the first encapsulation layer F401 away from the base substrate F100. After the organic liquid material is leveled, it solidifies to form the organic encapsulation layer. The edge of the organic encapsulation layer does not extend beyond the edge of the first inorganic encapsulation layer F401.

[0074] Optionally, the thickness of the first inorganic encapsulation layer F401 can be 0.01 to 1.5 microns, for example, 1 micron, 1.1 microns, or 1.2 microns. Optionally, the material of the second inorganic encapsulation layer F402 can be an oxygen-free inorganic material, that is, an inorganic dielectric material without oxygen elements. The oxygen-free second inorganic encapsulation layer F402 can effectively block external moisture and oxygen, prevent moisture and oxygen from invading the organic light-emitting functional layer, thereby causing material degradation, and prevent pixel failure, thereby improving the yield and life of the display panel. Furthermore, the second inorganic encapsulation layer F402 can cover the edge of the first inorganic encapsulation layer F401. Furthermore, the material of the second inorganic encapsulation layer F402 is silicon nitride.

[0075] Optionally, on the side of the first inorganic encapsulation layer F401 away from the display area AA, the second inorganic encapsulation layer F402 can be arranged on the surface of the passivation layer F208. In the present disclosure, since the second inorganic encapsulation layer F402 does not contain oxygen, it can block the corrosion of moisture and oxygen on the first inorganic encapsulation layer F401. In addition, in order to prevent moisture and oxygen from corroding the lower part of the first inorganic encapsulation layer F401, the second inorganic encapsulation layer F402 can be arranged on the surface of the passivation layer F208. Since the material of the passivation layer F208 is also silicon nitride that does not contain oxygen, the first inorganic encapsulation layer F401 is completely covered by the silicon nitride material.

[0076] See also Figure 3 From a top view, the display panel may include a display area AA and a peripheral area BB surrounding the display area AA. The edges of the first inorganic encapsulation layer F401 and the second inorganic encapsulation layer F402 are located in the peripheral area BB. The edge of the organic encapsulation layer may be located between the edge of the display area AA and the edge of the first inorganic encapsulation layer F401.

[0077] See also Figure 3 The display panel has a bonding area CC in the peripheral area BB, which is equipped with bonding pads for connecting to a circuit board or chip. Between the bonding area CC and the display area AA, the peripheral area BB has a fan-out area DD, which is equipped with fan-out traces that electrically connect the display area AA and the bonding area CC. Thus, along the direction surrounding the display area AA, the peripheral area BB can be divided into a fan-out area DD with fan-out traces and a non-fan-out area without fan-out traces.

[0078] In some embodiments, see Figure 3 The peripheral area BB may also be provided with a bending area BD, which is located between the bonding area CC and the display area AA. The display panel can be bent within the bending area BD to bend the bonding pad to the back of the display panel. In one embodiment of the present disclosure, the bending area BD may be located between the fan-out area DD and the bonding area CC.

[0079] See also Figure 3 In the peripheral area BB of the display panel, the display panel may include a barrier dam DAM and a crack prevention dam F500. The barrier dam DAM is located between the crack prevention dam F500 and the display area AA and can block the organic liquid material to constrain the boundary of the organic encapsulation layer.

[0080] The barrier dam DAM can be formed by stacking the organic layer / inorganic layer in the driving circuit layer F200 and the pixel layer F300, and in particular, by stacking the organic layer. The first inorganic encapsulation layer F401 and the second inorganic encapsulation layer F402 can cover the barrier dam DAM, that is, the edges of the first inorganic encapsulation layer F401 and the second inorganic encapsulation layer F402 can be located between the barrier dam DAM and the anti-crack dam F500. In this way, the barrier dam DAM also extends the contact length between the first inorganic encapsulation layer F401 and the pixel layer F300, and between the first inorganic encapsulation layer F401 and the second inorganic encapsulation layer F402, thereby extending the water and oxygen intrusion path and improving the encapsulation effect. In some embodiments, the barrier dam DAM can be a closed ring to surround the display area AA. In other embodiments, the barrier dam DAM can be provided only in the non-fan-out area, and it passes through the non-fan-out area along the direction surrounding the display area AA.

[0081] The crack prevention dam F500 can be located at the edge of the display panel to prevent cracks caused by cutting the display panel from extending toward the display area AA, thereby reducing the risk of crack extension causing failure in the display area AA or the peripheral area BB of the display panel. In some embodiments, the crack prevention dam F500 can be in a closed ring shape to surround the display area AA. In other embodiments, the crack prevention dam F500 can be located only in the non-fan-out area, extending through the non-fan-out area in a direction surrounding the display area AA.

[0082] The display panel provided by the present disclosure is shown in FIG. Figure 16 , can be prepared by the following preparation method:

[0083] Step S110, providing a base substrate F100;

[0084] Step S120 , forming a driving circuit layer F200 on one side of the base substrate F100 ;

[0085] Step S130 , forming a pixel layer F300 on a side of the driving circuit layer F200 away from the base substrate F100 ;

[0086] Step S140 , forming a first inorganic encapsulation layer F401 and an organic encapsulation layer on a side of the pixel layer F300 away from the base substrate F100 ; the organic encapsulation layer is located on a side of the first inorganic encapsulation layer F401 away from the base substrate F100 ;

[0087] In step S150 , a second inorganic encapsulation layer F402 is formed on a side of the organic encapsulation layer away from the base substrate F100 .

[0088] In the related art, step S140 and step S150 adopt an open mask process to form a first inorganic encapsulation layer F401 and a second inorganic encapsulation layer F402. Specifically, in step S140, an inorganic material can be deposited under the cover of an open mask plate to form a first inorganic encapsulation layer F401. In step S150, an inorganic material can be deposited under the cover of an open mask plate to form a second inorganic encapsulation layer F402. Since there is a certain gap between the open mask plate and the substrate, the deposition gas can be carried out along the gap under the mask plate to form an encapsulation shadow, which exceeds the boundary defined by the open mask. According to the related art, the structure of the display panel PNL0 obtained is as follows Figure 1 In the related art, the width of the package shadow often exceeds 20 microns, for example, more than 20 to 40 microns. Figure 1 Due to the presence of the encapsulation shadow, the first and second inorganic encapsulation layers F401 and F402 have very small slope angles at their edges, occupying a large amount of frame space. Furthermore, to prevent the encapsulation shadow from overlapping the anti-crack dam F500, the display panel needs to have a sufficient distance between the barrier dam DAM and the anti-crack dam F500 to fully accommodate the encapsulation shadow, resulting in a wider frame for the display panel.

[0089] To solve the above problems, see Figures 5 to 7 In step S140, the present disclosure forms the first inorganic encapsulation layer F401 by the following method: Figure 5 , forming a first encapsulation material layer covering the display area AA and the peripheral area BB on a side of the pixel layer F300 away from the base substrate F100; and patterning the first encapsulation material layer to form a first inorganic encapsulation layer F401.

[0090] Furthermore, the present disclosure forms the second inorganic encapsulation layer F402 in step S150 by the following method: Figure 6 , forming a second encapsulation material layer covering the display area AA and the peripheral area BB on a side of the organic encapsulation layer away from the base substrate F100; Figure 7 , the second encapsulation material layer is patterned to form a second inorganic encapsulation layer F402 , wherein an edge of the second inorganic encapsulation layer F402 is located in the peripheral area BB.

[0091] In step S140 of the present disclosure, a first encapsulation material layer can be deposited directly on the substrate without using a mask plate; at this time, the first encapsulation material layer covers the display area AA and the peripheral area BB, and the thickness is uniform at all locations. Then, the first encapsulation material layer is patterned using a photolithography process to form the required first inorganic encapsulation layer F401. Since the thickness of the first encapsulation material layer is uniform at all locations, the edge of the first inorganic encapsulation layer F401 and the thickness of the display area AA are the same. Since the first encapsulation material layer is patterned using a photolithography process, the slope angle of the edge of the first inorganic encapsulation layer F401 is relatively large, ranging from 40° to 90°, and in particular, can be within the range of 50° to 80°. In this way, on the one hand, the boundary of the first inorganic encapsulation layer F401 can be accurately defined, and there is no need to reserve redundant space for the encapsulation shadow; on the other hand, the slope angle of the first inorganic encapsulation layer F401 is relatively large, and the space occupied by the edge is small. Since there is no encapsulation shadow interfering with the boundary of the first inorganic encapsulation layer F401, there is no need to reserve corresponding space for the encapsulation shadow between the blocking dam DAM and the anti-crack dam F500, which can effectively reduce the border width of the display panel.

[0092] In step S150 of the present disclosure, a second encapsulation material layer can be deposited directly on the substrate without using a mask plate; at this time, the second encapsulation material layer covers the display area AA and the peripheral area BB, and the thickness is uniform at all locations. Then, the second encapsulation material layer is patterned using a photolithography process to form the required second inorganic encapsulation layer F402. Since the second encapsulation material layer has a uniform thickness at all locations, the edge of the second inorganic encapsulation layer F402 and the thickness of the display area AA are the same. Since the second encapsulation material layer is patterned using a photolithography process, the slope angle of the edge of the second inorganic encapsulation layer F402 is relatively large, ranging from 40° to 90°, and in particular, can be within the range of 50° to 80°. In this way, on the one hand, the boundary of the second inorganic encapsulation layer F402 can be very accurately defined, without reserving redundant space for encapsulation shadows; on the other hand, the slope angle of the second inorganic encapsulation layer F402 is relatively large, and the space occupied by the edge is small. Since there is no encapsulation shadow interfering with the boundary of the second inorganic encapsulation layer F402, there is no need to reserve corresponding space for the encapsulation shadow between the blocking dam DAM and the anti-crack dam F500, which can effectively reduce the border width of the display panel.

[0093] Figure 9 The display panel PNL prepared in this embodiment is shown, as well as the display panel PNL0 in the related art. Figure 9The positions of the cutting lines of these display panels are also shown. Figure 9 In the display panel PNL of this embodiment, since there is no encapsulation shadow interfering with the boundary of the second inorganic encapsulation layer F402, there is no need to reserve corresponding space for the encapsulation shadow between the blocking dam DAM and the anti-crack dam F500, which can effectively reduce the border width of the display panel.

[0094] In some embodiments, through the above-mentioned preparation method of the present disclosure, the border of the display panel can be reduced by 20 to 60 microns in the non-fan-out area, for example, by 40 microns.

[0095] In some embodiments, through the above-mentioned manufacturing method of the present disclosure, the border of the display panel can be reduced by 100 to 400 microns in the fan-out region DD, for example, by 300 microns.

[0096] In one embodiment of the present disclosure, the patterning of the first encapsulation material layer may be completed before the organic encapsulation layer is prepared. For example, step S140 may specifically include:

[0097] Step S210: forming a first packaging material layer covering the display area AA and the peripheral area BB on a side of the pixel layer F300 away from the base substrate F100;

[0098] Step S220 , patterning the first packaging material layer to form a first inorganic packaging layer F401 ;

[0099] In step S230 , an organic encapsulation layer is formed on a side of the first inorganic encapsulation layer F401 away from the base substrate F100 .

[0100] According to this embodiment, the first inorganic encapsulation layer F401 of the display panel obtained includes a first inorganic encapsulation layer F401, an organic encapsulation layer, and a second inorganic encapsulation layer F402 stacked in sequence. The first inorganic encapsulation layer F401 and the second inorganic encapsulation layer F402 are formed in two different patterning operations, so their edges may not be consistent. In one embodiment of the present disclosure, the edge of the second inorganic encapsulation layer F402 may be outside the edge of the first inorganic encapsulation layer F401, so that the second inorganic encapsulation layer F402 covers the edge of the first inorganic encapsulation layer F401, achieving a better water and oxygen barrier effect.

[0101] Optionally, in this embodiment, the thickness of the second inorganic encapsulation layer F402 can be 0.01 to 1.5 microns, for example, 1 micron, 1.1 microns, 1.2 microns, etc. In this way, the organic encapsulation layer is covered by the thicker second inorganic encapsulation layer F402, which can ensure the longitudinal water and oxygen barrier effect of the first inorganic encapsulation layer F401.

[0102] refer to Figures 10 to 13 In another embodiment of the present disclosure, the patterning of the first encapsulation material layer may be completed after the organic encapsulation layer is prepared. For example, step S140 may specifically include:

[0103] Step S310, reference Figure 10 , forming a first packaging material layer covering the display area AA and the peripheral area BB on a side of the pixel layer F300 away from the base substrate F100;

[0104] Step S320 , forming an organic encapsulation layer on a side of the first encapsulation material layer away from the base substrate F100 ;

[0105] Step S330, see Figure 11 , forming a third encapsulation material layer covering the display area AA and the peripheral area BB on a side of the organic encapsulation layer away from the base substrate F100;

[0106] Step S340, see Figure 12 , patterning the first encapsulation material layer and the third encapsulation material layer to form a first inorganic encapsulation layer F401 and a third inorganic encapsulation layer F403. Figure 14 The display panel PNL in the third inorganic encapsulation layer F403 is sandwiched between the organic encapsulation layer ( Figure 14 not shown) and between the second inorganic encapsulation layer F402.

[0107] refer to Figure 14 According to this embodiment, the first inorganic encapsulation layer F401 of the display panel PNL obtained includes a first inorganic encapsulation layer F401, an organic encapsulation layer ( Figure 14 The first and third inorganic encapsulation layers F401 and F403 are formed in the same patterning operation, so their edges are flush. Furthermore, the edges of the third inorganic encapsulation layer F403 have a relatively large slope angle, ranging from 40° to 90°, and more particularly, from 50° to 80°. Figure 14 1 also shows the display panel PNL0 in the related art, and shows the display panel PNL and the cutting line of the display panel PNL0. Figure 14It can be seen that the display panel PNL of the present disclosure can accurately define the boundaries of the first inorganic encapsulation layer F401, the third inorganic encapsulation layer F403 and the second inorganic encapsulation layer F402 without shadows, and thus has a smaller frame than the display panel PNL0 in the related art.

[0108] Optionally, in this embodiment, the material of the third inorganic encapsulation layer F403 may be the same as that of the second inorganic encapsulation layer F402 to further improve the water and oxygen barrier effect of the first inorganic encapsulation layer F401.

[0109] Optionally, in this embodiment, the thickness of the third inorganic encapsulation layer F403 may be in the range of 0.01 to 1.5 micrometers, for example, in the range of 0.6 to 1.0 micrometers. For example, the thickness of the third inorganic encapsulation layer F403 may be 0.7 micrometers.

[0110] Optionally, in this embodiment, the thickness of the second inorganic encapsulation layer F402 may be in the range of 0.01 to 1.5 micrometers, for example, in the range of 0.2 to 0.5 micrometers. For example, the thickness of the second inorganic encapsulation layer F402 may be 0.3 micrometers.

[0111] In the present disclosure, the inorganic insulating dielectric film layers between the base substrate F100 and the passivation layer F208 in the drive circuit layer F200 can be collectively defined as an inorganic dielectric layer. Thus, the drive circuit layer F200 includes the inorganic dielectric layer and the passivation layer F208 stacked sequentially on one side of the base substrate F100. It is understood that different film layer structures in the drive circuit layer F200 will result in different film layers included in the inorganic dielectric layer, with the film layers located between the base substrate F100 and the passivation layer F208 being the preferred layer.

[0112] In some embodiments of the present disclosure, when preparing the driving circuit layer F200, a partition groove G100 can be formed on the inorganic dielectric layer, which penetrates the inorganic dielectric layer and exposes the base substrate F100. The partition groove G100 is located between the blocking dam DAM and the anti-crack dam F500 in the inorganic dielectric layer. In this way, in the display panel obtained, the inorganic dielectric layer is provided with a partition groove G100 between the blocking dam DAM and the anti-crack dam F500. The partition groove G100 penetrates the inorganic dielectric layer and exposes the base substrate F100. In this way, the inorganic material in the inorganic dielectric layer is removed at the position of the partition groove G100. The partition groove G100 can further prevent the cracks caused by cutting the display panel from spreading to the display area AA, thereby preventing the display area AA from being affected by the cracks generated during cutting, thereby improving the life of the display panel. In particular, in the present disclosure, due to the reduction of the border of the display panel, the display area AA is more susceptible to cracks; and the partition groove G100 can cooperate with the anti-crack dam F500 to block the extension of cracks to the display area AA when the anti-crack dam F500 fails, thereby improving the stability of the display panel and overcoming the potential risks brought about by the reduction of the border.

[0113] The partitioning groove G100 can be set at a local position of the peripheral area BB, or can be set around the display area AA. For example, in one embodiment of the present disclosure, the partitioning groove G100 may include a first partitioning groove G110 located in the non-fan-out area. Along the direction surrounding the display area AA, the first partitioning groove runs through the non-fan-out area. For another example, in another embodiment of the present disclosure, the partitioning groove G100 may include a second partitioning groove G120 located in the fan-out area DD. Along the direction surrounding the display area AA, the second partitioning groove runs through the fan-out area DD. For another example, the partitioning groove G100 may include a first partitioning groove and a second partitioning groove, and the first partitioning groove and the second partitioning groove may be connected to each other to form a closed ring around the display area AA.

[0114] In some embodiments of the present disclosure, in the first partition groove, the passivation layer F208 is provided with a partition hole G101 that exposes the base substrate F100. The partition hole G101 can pass through the first partition groove along the extension direction of the first partition groove. In this way, the blocking effect of the partition groove G100 on cracks can be further improved. In one embodiment of the present disclosure, the size (i.e., width) of the partition hole G101 in the direction away from the display area AA can be 2 to 6 microns, for example, 3 microns. It is worth noting that the design size of the partition hole G101 can be appropriately increased or decreased according to the process, for example, it can be 4 microns, 5 microns, 6 microns, etc.

[0115] In one embodiment of the present disclosure, in the non-fan-out region, the dimension between the edge of the first inorganic encapsulation layer F401 and the first partition groove is 3 to 8 microns, for example, 5 microns. The dimension between the edge of the first partition groove and the edge of the partition hole G101 can be 3 to 8 microns, for example, 5 microns. In one embodiment of the present disclosure, the dimension between the first partition groove and the crack dam can be 3 to 8 microns, for example, 5 microns.

[0116] Optionally, in the non-fan-out area, the edge of the second inorganic encapsulation layer F402 does not extend beyond the edge of the partition hole G101 on the side closest to the display area AA. In this way, the second inorganic encapsulation layer F402 does not cover the partition hole G101, thereby ensuring the crack-blocking effect of the partition groove G100. Furthermore, in one embodiment of the present disclosure, the edge of the second inorganic encapsulation layer F402 extends into the first partition groove.

[0117] In some embodiments of the present disclosure, the passivation layer F208 may cover the second partition trench, and the fan-out traces may be disposed on a side of the passivation layer F208 away from the substrate F100, for example, on the second source / drain metal layer F209. Furthermore, the fan-out traces may be covered by a planarization layer F210.

[0118] Optional, see Figure 3 The display panel further includes a crack detection line F700. In the non-fan-out area, the crack detection line F700 is located between the partition groove G100 and the anti-crack dam F500. In this way, the crack detection line F700 can more sensitively detect cracks that break through the anti-crack dam F500. Of course, in other embodiments of the present disclosure, see Figure 8 and Figure 14 The crack detection line F700 can also be located between the partition groove G100 and the barrier dam DAM. In this way, the crack detection line F700 can detect cracks that break through the inner side of the partition groove G100 (the side close to the display area), thereby more intuitively reflecting the risks faced by the display area.

[0119] Alternatively, during the manufacturing process of the display panel of the present disclosure, a supporting substrate F600 may be provided first, and then a base substrate F100, a driving circuit layer F200, a pixel layer F300, and a thin film encapsulation layer F400 may be sequentially formed on one side of the supporting substrate F600. After the display panel is manufactured, the supporting substrate F600 may be peeled off to obtain the display panel.

[0120] In one embodiment of the present disclosure, the support substrate F600 may be a glass substrate.

[0121] Optionally, during the preparation of the display panel of the present disclosure, a large-sized substrate can be provided as a motherboard, which can provide a support substrate F600 for multiple display panels. After the display panel is prepared, it can be cut along cutting lines (e.g., laser cutting) to obtain multiple display panels.

[0122] Optionally, in the preparation process of the display panel disclosed herein, after the thin film encapsulation layer F400 is formed, a temporary protective film (TPF) can be attached to the side of the thin film encapsulation layer F400 away from the base substrate F100, and then the temporary protective film is cut to expose the various binding pads of the display panel, so as to facilitate electrical testing and grading of the display panel. Figure 15 The display panel PNL0 in the related art and the display panel PNL of the present disclosure are shown, and the cutting position of the temporary protective film is cut on the fan-out area side. Figure 15 When preparing the display panel PNL of the present disclosure, the temporary protective film is cut along the side of the bending region BD away from the display region AA. This avoids the need for a temporary protective film cutting area between the bending region BD and the display region AA, thereby preventing the temporary protective film cutting area from weakening the bezel reduction effect of the inorganic encapsulation layer of the present disclosure. In contrast, in related art, the temporary protective film is typically cut on the side of the bending region BD closer to the display region AA, resulting in a larger bezel on the fan-out side of the display panel.

[0123] It should be noted that although the steps of the method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additional or alternative steps, such as omitting certain steps, combining multiple steps into one step, and / or decomposing a step into multiple steps, should all be considered part of this disclosure.

[0124] It should be understood that the present disclosure is not limited in its application to the detailed structure and arrangement of the components set forth in this specification. The present disclosure is capable of other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All of these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A display panel, characterized in that: The display panel includes a base substrate, a driving circuit layer, a pixel layer and a thin film encapsulation layer stacked in sequence; wherein the thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer stacked in sequence on a side of the pixel layer away from the base substrate; The display panel includes a display area and a peripheral area surrounding the display area; the edges of the first inorganic encapsulation layer and the second inorganic encapsulation layer are located in the peripheral area; in the peripheral area, the display panel is provided with a blocking dam and a crack prevention dam; the driving circuit layer includes a passivation layer and an inorganic dielectric layer composed of various inorganic insulating film layers between the passivation layer and the base substrate; the inorganic dielectric layer is provided with a partition groove between the blocking dam and the crack prevention dam, the partition groove penetrating the inorganic dielectric layer and exposing the base substrate; Among them, the slope angle of the edge of the first inorganic encapsulation layer is in the range of 40° to 90°; the slope angle of the edge of the second inorganic encapsulation layer is in the range of 40° to 90°; the material of the second inorganic encapsulation layer is an oxygen-free inorganic material, and the second inorganic encapsulation layer covers the edge of the first inorganic encapsulation layer; the peripheral area includes a fan-out area and a non-fan-out area adjacent to the fan-out area; the driving circuit layer is provided with a fan-out trace in the fan-out area; the partition groove includes a first partition groove located in the non-fan-out area; in the first partition groove, the passivation layer is provided with a partition hole exposing the base substrate; the display panel is also provided with a crack detection trace; in the non-fan-out area, the crack detection trace is located between the first partition groove and the blocking dam.

2. The display panel according to claim 1, wherein: The thin film encapsulation layer further includes a third inorganic encapsulation layer, wherein the third inorganic encapsulation layer is located between the organic encapsulation layer and the second inorganic encapsulation layer; The slope angle of the edge of the third inorganic encapsulation layer is in the range of 40° to 90°; the edge of the third inorganic encapsulation layer is flush with the edge of the first inorganic encapsulation layer.

3. The display panel according to claim 1, wherein: The second inorganic encapsulation layer is disposed on a surface of the passivation layer on a side of the first inorganic encapsulation layer away from the display area.

4. The display panel according to claim 1, wherein: The peripheral area includes a fan-out area and a non-fan-out area adjacent to the fan-out area; the driving circuit layer is provided with a fan-out trace in the fan-out area; The partition groove includes a second partition groove located in the fan-out area; The passivation layer covers the second partition groove; and the fan-out wiring is arranged on a side of the passivation layer away from the base substrate.

5. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 4.

6. A method for preparing a display panel, characterized in that: The display panel includes a display area and a peripheral area surrounding the display area. The method for preparing the display panel includes: providing a substrate; forming a driving circuit layer on one side of the base substrate; forming a pixel layer on a side of the driving circuit layer away from the base substrate; forming a first packaging material layer covering the display area and the peripheral area on a side of the pixel layer away from the base substrate; performing a patterning operation on the first encapsulation material layer to form a first inorganic encapsulation layer, wherein an edge of the first inorganic encapsulation layer is located in the peripheral region; forming an organic encapsulation layer on a side of the first inorganic encapsulation layer away from the base substrate; forming a second encapsulation material layer covering the display area and the peripheral area on a side of the organic encapsulation layer away from the base substrate; performing a patterning operation on the second encapsulation material layer to form a second inorganic encapsulation layer, wherein an edge of the second inorganic encapsulation layer is located in the peripheral region; In which, when preparing the driving circuit layer, a partition groove is formed on the inorganic dielectric layer, which penetrates the inorganic dielectric layer and exposes the base substrate, and the partition groove is located in the inorganic dielectric layer between the blocking dam and the anti-crack dam; the inorganic dielectric layer is composed of the passivation layer in the driving circuit layer and the various inorganic insulating film layers between the base substrate; the material of the second inorganic packaging layer is an oxygen-free inorganic material, and the second inorganic packaging layer covers the edge of the first inorganic packaging layer; the peripheral area includes a fan-out area and a non-fan-out area adjacent to the fan-out area; the driving circuit layer is provided with a fan-out line in the fan-out area; the partition groove includes a first partition groove located in the non-fan-out area; in the first partition groove, the passivation layer is provided with a partition hole exposing the base substrate; the display panel is also provided with a crack detection line; in the non-fan-out area, the crack detection line is located between the first partition groove and the blocking dam.

Images