Image sensor and imaging device including the same

Abstract

An imaging device includes: a pixel array having a plurality of pixels, each pixel configured to generate a reset signal and an image signal; and a sampling circuit including a plurality of samplers connected to column lines, wherein each sampler generates a first comparison signal by comparing the reset signal with a ramp signal, and generates a second comparison signal by comparing the image signal with the ramp signal. An ADC converts each of the first and second comparison signals into a digital signal. Each sampler performs an auto-zero operation to initialize itself before performing a comparison with the reset signal in a first mode, and performs a corresponding auto-zero operation before performing a comparison with each of the reset signal and the image signal in a second mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2020-0022363 filed on February 24, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate generally to an image sensor and an imaging device including the same, and more particularly to a high dynamic range image sensor. Background Art

[0004] An image sensor is a semiconductor-based sensor that generates electrical signals in response to light. An image sensor may include a pixel array having a plurality of pixels and logic circuitry configured to drive the pixel array and generate an image. Each pixel may include a photodiode configured to generate an electrical charge in response to light and pixel circuitry configured to convert the charge generated by the photodiode into an electrical signal. Image sensors are widely applicable to cameras that capture still images or video, where the camera may be a standalone camera or part of a smartphone, tablet PC, laptop computer, television, vehicle, or the like.

[0005] In a high dynamic range (HDR) image sensor, the illuminance sensed by each pixel can be determined to be within a low or high illuminance range. With this approach, the analog-to-digital converter (ADC) used to digitize illuminance values with a fixed number of bits can distinguish illuminance values with a higher overall dynamic range. As a result, variations within areas of the image frame that would otherwise be indistinguishable due to areas being too bright or too dark can be more accurately captured with representative grayscale values. Summary of the Invention

[0006] Example embodiments of the present disclosure provide an imaging device and an image sensor including a sampler that can perform an auto-zero operation in a high-gain sampling operation in a different manner than in a low-gain sampling operation, thereby removing reset noise and significantly reducing power consumption.

[0007] According to an exemplary embodiment of the present disclosure, an imaging device includes: a pixel array including a plurality of pixels connected to a plurality of row lines and a plurality of column lines, wherein each of the plurality of pixels is configured to generate a reset signal and an image signal. A sampling circuit may include a plurality of sampling circuits connected to the plurality of column lines. Each of the sampling circuits is configured to generate a first comparison signal by comparing the reset signal with a ramp signal, and to generate a second comparison signal by comparing the image signal with the ramp signal. An analog-to-digital converter is configured to convert each of the first comparison signal and the second comparison signal into a corresponding digital signal. A column driver is configured to generate image data based on the first comparison signal and the second comparison signal converted into the digital signals. Each of the sampling circuits performs an auto-zero operation for initializing itself before performing a comparison with the reset signal in a first mode, and performs a corresponding auto-zero operation before performing a comparison with each of the reset signal and the image signal in a second mode.

[0008] According to an example embodiment of the present disclosure, an image sensor includes: a pixel array including a plurality of pixels connected to a plurality of row lines and a plurality of column lines, wherein each of the plurality of pixels is configured to generate a pixel signal; a plurality of samplers connected to the plurality of column lines and configured to output a comparison signal by comparing the pixel signal with a ramp signal; and an analog-to-digital converter configured to generate image data by converting the comparison signal into a digital signal, wherein each of the plurality of samplers includes: a comparator; a first auto-zero switch configured to be connected between a first input node and a first output node of the comparator; a second auto-zero switch configured to be connected between a second input node and a second output node of the comparator; a first capacitor configured to be connected between the first input node and the first node; a second capacitor connected between the second input node and the second node; a first switch connected between the first node and an input terminal of the ramp signal; a second switch connected between the first node and an input terminal of the pixel signal; and a third switch and a fourth switch connected in parallel between the second node and the input terminal of the pixel signal.

[0009] According to an exemplary embodiment of the present inventive concept, an image sensor includes: a plurality of pixels connected to a plurality of row lines and a plurality of column lines and configured to generate a reset signal, a first image signal, and a second image signal; a plurality of sampling circuits connected to the plurality of column lines and configured to generate a comparison signal by sequentially comparing each of the reset signal, the first image signal, and the second image signal with an up-ramp signal or a down-ramp signal; and an analog-to-digital converter configured to generate image data by converting the comparison signal into a digital signal. Each sampling circuit operates at a first amplification gain in a first mode and generates the comparison signal using the down-ramp signal, and operates at a second amplification gain less than the first amplification gain in a second mode and generates the comparison signal using the up-ramp signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a diagram illustrating an imaging device according to an exemplary embodiment of the present disclosure;

[0012] Figure 2 is a diagram illustrating an image sensor according to an example embodiment of the present disclosure;

[0013] Figure 3 is a circuit diagram illustrating a ramp signal generator included in an image sensor according to an example embodiment of the present disclosure;

[0014] Figure 4 is a diagram illustrating a layout of an image sensor according to an example embodiment of the present disclosure;

[0015] Figure 5 is a circuit diagram illustrating a pixel included in an image sensor according to an example embodiment of the present disclosure;

[0016] Figure 6 is a circuit diagram illustrating a sampling circuit included in an image sensor according to an example embodiment of the present disclosure;

[0017] Figure 7 It shows Figure 6 A circuit diagram of a comparator and a first peripheral circuit of the sampling circuit shown;

[0018] Figure 8 is a diagram illustrating an operating method of a sampling circuit according to an example embodiment of the present disclosure;

[0019] Figure 9 is a timing diagram illustrating an example of the sampling circuit operating in the first mode;

[0020] Figure 10Ais a diagram illustrating a state of a sampling circuit in an auto-zero period when the sampling circuit operates in a first mode according to an example embodiment of the present disclosure, and Figure 10B is a diagram illustrating a state of a sampling circuit in a comparison period when the sampling circuit operates in a first mode according to an example embodiment of the present disclosure;

[0021] Figure 11 is a timing diagram illustrating an example of the sampling circuit operating in the second mode;

[0022] Figure 12A is a diagram illustrating a state of a sampling circuit in an auto-zero period when the sampling circuit operates in a second mode according to an example embodiment of the present disclosure;

[0023] Figure 12B is a diagram illustrating a state of a sampling circuit in a comparison period when the sampling circuit operates in a second mode according to an example embodiment of the present disclosure;

[0024] Figure 13 is a circuit diagram illustrating a pixel included in an image sensor according to an example embodiment of the present disclosure;

[0025] Figure 14 is a cross-sectional view showing the vertical structure of a 2PD pixel;

[0026] Figure 15A and Figure 15B is a diagram of an operating method of a sampling circuit according to an example embodiment of the present disclosure;

[0027] Figure 16 is a timing diagram illustrating an example in which the sampling circuit according to an example embodiment of the present disclosure operates in a first mode;

[0028] Figure 17 is a timing diagram illustrating an example in which the sampling circuit operates in the second mode according to an example embodiment of the present disclosure; and

[0029] Figure 18 is a block diagram illustrating an electronic device including an image sensor according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0031] Figure 1is a diagram illustrating an imaging device 10 according to an example embodiment. The imaging device 10 may include an image sensor 100 and an image signal processor (ISP) 200. The image sensor 100 may sense light from a scene (such as light reflected from an object) to represent an image of the scene. The image sensor 100 may include a pixel array 110, a row driver 120, a readout circuit 130, a column driver 140, and a timing controller 150.

[0032] The pixel array 110 may include a plurality of pixels PX arranged in an array along a plurality of row lines and a plurality of column lines. (The following discussion regarding the pixel PX applies to any of the plurality of pixels PX.) The pixel PX may include a photoelectric conversion element configured to generate charge in response to incident light, such as a photodiode, a phototransistor, a pinned photodiode, or the like. The pixel PX may include at least two photoelectric conversion elements. The pixel PX may include two or more photoelectric conversion elements to generate pixel signals corresponding to light of various colors or to provide an autofocus function.

[0033] Pixels PX can use photoelectric conversion elements to sense light within a specific spectral range. For example, multiple pixels PX may include red pixels for sensing light within the red spectral range, green pixels for sensing light within the green spectral range, and blue pixels for sensing light within the blue spectral range. In other embodiments, additional or alternative color pixels, such as white, are included. A color filter for transmitting light within a specific spectral range can be placed on any pixel PX. The illuminance measurement method and circuit disclosed herein can be applied separately to pixels of different colors.

[0034] Depending on the intensity of light incident on the photoelectric conversion element, a pixel PX can be in a high-illuminance state corresponding to a sensed illuminance within a high-illuminance range, for example, above a threshold, or in a low-illuminance state corresponding to a sensed illuminance within a low-illuminance range, for example, below a threshold. Under the assumption that a pixel PX can be in either state at any given time, embodiments herein can perform illuminance measurements for each pixel PX. Hereinafter, the term "high-illuminance pixel" may be used to refer to a pixel PX that is considered or determined to be in a high-illuminance state, while "low-illuminance pixel" may be used to refer to a pixel PX that is considered or determined to be in a low-illuminance state. In embodiments, current measurements for both states are performed for each pixel PX in each frame, and each pixel PX is determined to be in either a low-illuminance or a high-illuminance state based on the results of the current measurements. The analog values associated with one range or the other can then be used to more accurately perform overall A / D conversion for all pixels PX. With this capability, the image sensor 100 can be understood as a high dynamic range (HDR) image sensor.

[0035] In another embodiment, high-illuminance pixels and low-illuminance pixels can be distinguished from each other based on the pixel values of the previous frame. For example, among a plurality of pixels PX, pixels whose pixel values in the previous frame are equal to or higher than a specific threshold can be defined as high-illuminance pixels, while pixels whose pixel values in the previous frame are lower than the specific threshold can be defined as low-illuminance pixels. Information related to illuminance values, pixel classification, etc. can be stored in an internal memory or an external memory of the image sensor 100 and can be used to perform sampling operations, etc.

[0036] The pixel PX may include a pixel circuit for generating a pixel signal. The pixel circuit may include a transfer transistor, a drive (source follower) transistor, a select transistor, and a reset transistor. The pixel signal may be an analog signal and may include a reset signal and an image signal. The reset signal may be a voltage signal corresponding to a specific power supply voltage, and the image signal may be a voltage signal corresponding to the charge generated by the photoelectric conversion element.

[0037] The row driver 120 may drive the pixel array 110 via row line units. For example, the pixel array 110 may generate a transfer control signal for controlling a transfer transistor for a pixel signal, a reset control signal for controlling a reset transistor, or a selection control signal for controlling a selection transistor. In an example embodiment, the row driver 120 may sequentially drive a plurality of row lines of the pixel array 110. The pixel array 110 may generate pixel signals in response to control signals generated by the row driver 120.

[0038] The readout circuit 130 may convert pixel signals generated by the pixel array 110 into digital signals and may output the digital signals. The readout circuit 130 may include a sampling circuit and an analog-to-digital converter (ADC).

[0039] The sampling circuit may include a plurality of sampler circuits (hereinafter, "samplers"). In an example embodiment, the sampler may be a correlated double sampler (CDS). The sampler may be selectively connected to the pixels PX included in the row selected by the row driver 120 via a column line, and may detect a reset signal and an image signal from the pixels PX of the selected row. The sampler may compare each of the reset signal and the image signal with a specific ramp signal, and may output a comparison signal as a result of the comparison. By performing this process row by row for the remaining rows of the pixel array, image data for the entire image frame may be sampled.

[0040] The samplers may be initialized by performing an auto-zero operation before performing a comparison operation. In an example embodiment, the plurality of samplers may perform auto-zero operations on high-illuminance pixels and low-illuminance pixels in different manners. For example, the samplers may perform an auto-zero operation on low-illuminance pixels before performing the first comparison operation. Furthermore, the samplers may perform an auto-zero operation on high-illuminance pixels before performing each comparison operation.

[0041] With respect to low-illuminance pixels, since the amplification gain (interchangeably, simply "gain") may be relatively high in the comparison operations of the sampler, it may be beneficial to significantly reduce the reset noise (or kT / C noise) generated during the initialization process. Therefore, the sampler may perform a single auto-zero operation for all comparison operations for low-illuminance pixels. With respect to high-illuminance pixels, since the gain may be relatively low in the comparison operations of the sampler, the effect of the reset noise generated during the initialization process of the sampler affecting the comparison operations may be relatively low, but it may be desirable to reduce the headroom voltage corresponding to the drive current of the sampler in terms of driving at low power. Therefore, the sampler may perform another auto-zero operation (multiple auto-zero operations) for each comparison operation for high-illuminance pixels.

[0042] The analog-to-digital converter (ADC) can be configured as a single-slope analog-to-digital converter. The ADC may include multiple counters. In an example embodiment, the multiple counters may be up / down counters or bitwise inversion counters. The multiple counters may be connected to multiple samplers, respectively, and may count the comparison signals output from the samplers and output digital signals. For example, the multiple counters may convert the reset signal into a digital signal by counting the time period corresponding to the result of the comparison between the reset signal and the ramp signal in the comparison signal, and may output the digital signal. In addition, the multiple counters may convert the image signal into a digital signal by counting the time period corresponding to the result of the comparison between the image signal and the ramp signal in the comparison signal, and may output the digital signal.

[0043] The column driver 140 may include a latch or a buffer that can temporarily store digital signals. The column driver 140 may process the digital signal received from the readout circuit 130 and may output image data. For example, the column driver 140 may generate image data based on the difference between the count value generated from the reset signal and the count value generated from the image signal, and may output the generated image data to the image signal processor 200.

[0044] The timing controller 150 may control operations or timings of the row driver 120 , the readout circuit 130 , and the column driver 140 .

[0045] Image signal processor 200 may generate an image by processing image data output from column driver 140. For example, image signal processor 200 may generate an image by performing signal processing operations such as color interpolation, color correction, gamma correction, color space conversion, edge correction, and the like.

[0046] Since the imaging device 10 in the example embodiment includes the image sensor 100 having the sampler configured to perform a single auto-zero operation on low-illuminance pixels and multiple auto-zero operations on high-illuminance pixels, image quality may be improved and power consumption may be reduced.

[0047] Figure 2 is a diagram illustrating an image sensor according to example embodiments.

[0048] refer to Figure 2 , the image sensor 300 may include a pixel array 310 , a row driver 320 , and a readout circuit 330 .

[0049] The pixel array 310 may include a plurality of pixels PX11 to PXMN disposed at intersections where a plurality of row lines RL intersect a plurality of column lines CL.

[0050] The row driver 320 can input signals required to control the plurality of pixels PX11 to PXMN through the plurality of row lines RL. For example, the row driver 320 can provide a reset control signal RG, a transfer control signal TG, or a selection control signal SEL to the plurality of pixels PX11 to PXMN through the plurality of row lines RL. The row driver 320 can sequentially select each of the plurality of row lines RL. The row driver 320 can select one of the plurality of row lines RL during a specific horizontal period.

[0051] The readout circuit 330 may include a ramp signal generator 331, a sampling circuit 332, and an analog-to-digital converter 333. The data DATA output by the analog-to-digital converter 333 may be input to a column driver.

[0052] The ramp signal generator 331 may generate a ramp signal RMP in response to the ramp control signal. The ramp signal RMP may include an up-ramp signal having a voltage that increases over time and a down-ramp signal having a voltage that decreases over time. In an example embodiment, the ramp signal generator 331 may generate a down-ramp signal to perform a sampling operation on low-illuminance pixels. Also, the ramp signal generator 331 may generate an up-ramp signal to perform a sampling operation on high-illuminance pixels. Figure 3 A specific example of the ramp signal generator 331 is shown in FIG.

[0053] refer to Figure 3The ramp signal generator 331 may include a variable current source Iramp and a resistor Rramp connected in series between a first power supply voltage node VDD and a second power supply voltage node VSS. When a ramp current generated by the variable current source Iramp flows through the resistor Rramp, a ramp voltage Vramp may be generated. The ramp signal generator 331 may generate an up-ramp signal Vup_ramp or a down-ramp signal Vdn_ramp by adjusting the magnitude of the ramp current in response to a ramp control signal CSramp. Figure 3 1 shows an example in which the ramp signal generator 331 includes a variable current source Iramp and a resistor Rramp, but example embodiments thereof are not limited thereto. The ramp signal generator 331 may include a constant current source and a variable resistor. Figure 3 Unlike the example shown, the waveform of the up-ramp signal Vup_ramp or the down-ramp signal Vdn_ramp may be changed.

[0054] Return Reference Figure 2 , the sampling circuit 332 can obtain a reset signal and an image signal from the plurality of pixels PX11 to PXMN. The sampling circuit 332 may include a plurality of samplers SA, and the plurality of samplers SA may be correlated double samplers CDS. Each of the plurality of samplers SA may receive a ramp signal RMP from the ramp signal generator 331 via a first node, and may receive a reset signal and an image signal from the plurality of pixels PX11 to PXMN via a second node. Each of the plurality of samplers SA may compare each of the reset signal and the image signal with the ramp signal RMP, and may output a comparison signal as a result of the comparison.

[0055] The analog-to-digital converter 333 may output the image data DATA by converting the comparison signal output from the sampling circuit 332 into a digital signal.

[0056] Figure 4 is a diagram illustrating a layout of an image sensor according to example embodiments.

[0057] refer to Figure 4 The image sensor 400 may be a stacked type image sensor 400 including a first substrate SUB1 and a second substrate SUB2 stacked in a vertical direction. The first substrate SUB1 may include a sensing region SR and a first pad region PA1, and the second substrate SUB2 may include a circuit region CA and a second pad region PA2.

[0058] The sensing region SR may include a plurality of pixels PX arranged along a plurality of row lines and a plurality of column lines. A plurality of first pads PAD1 may be included in the first pad area PA1, and the plurality of first pads PAD1 may be configured to transmit and receive electrical signals to and from the circuit area CA and the second pad area PA2 of the second substrate SUB2.

[0059] The circuit area CA may include a logic circuit block LC and may include a plurality of circuit devices included in a row driver, a readout circuit, a column driver, etc. The circuit area CA may provide a plurality of control signals to the sensing area SR and may control outputs from a plurality of pixels PX. A plurality of first pads PAD1 disposed in the first pad area PA1 may be electrically connected to second pads PAD2 disposed in the second pad area PA2 through a connection portion CV.

[0060] The layout of the image sensor 400 is not limited to Figure 4 For example, the image sensor 400 may further include at least one substrate disposed below the second substrate SUB2 and including a memory chip such as a DRAM, an SRAM, or the like.

[0061] Figure 5 is a circuit diagram illustrating an example pixel PX included in an image sensor according to an example embodiment. The example pixel PX may include a photodiode PD and a pixel circuit. The pixel circuit may include a floating diffusion region FD, a reset transistor RX, a drive transistor DX, a select transistor SX, and a transfer transistor TX.

[0062] The photodiode PD may generate charges in response to incident light. The charges generated by the photodiode PD may be accumulated in the floating diffusion region FD.

[0063] When the reset transistor RX is turned on by the reset control signal RG, the voltage of the floating diffusion area FD can be reset to the power supply voltage VDD. When the voltage of the floating diffusion area FD is reset, the selection transistor SX can be turned on by the selection control signal SEL, and a reset signal can be output to the column line COL through the pixel node PN.

[0064] When the transfer transistor TX is turned on by the transfer control signal TG after the reset voltage is output to the column line COL, the charges generated by the photodiode PD may move to the floating diffusion area FD.

[0065] The drive transistor DX operates as a source-follower amplifier to amplify the voltage of the floating diffusion area FD. When the select transistor SX is turned on by the select control signal SEL, an image signal corresponding to the charge generated by the photodiode PD is output to the column line COL via the pixel node PN. Each of the reset signal and the image signal can be detected by a sampling circuit connected to the column line COL.

[0066] Figure 6 is a circuit diagram illustrating a sampling circuit included in an image sensor according to example embodiments.

[0067] refer to Figure 6 The sampling circuit 500 may include a comparator 510, a first peripheral circuit 530, and a second peripheral circuit 550. The first peripheral circuit 530 may include first and second auto-zero switches AZ1 and AZ2, and first and second capacitors C1 and C2. The second peripheral circuit 550 may include first to fourth switches SW1 to SW4.

[0068] The first switch SW1 can be connected between an input terminal of the ramp signal RMP and the first node N1. The second switch SW2 can be connected to an input terminal of the pixel signal PIX and the first node N1. The third switch SW3 and the fourth switch SW4 can be connected in parallel between the input terminal of the pixel signal PIX and the second node N2. The first switch SW1 and the third switch SW3 can be switched in response to a first control signal S1. The second switch SW2 and the fourth switch SW4 can be switched in response to a second control signal S2.

[0069] The sampling circuit 500 may receive the ramp signal RMP and the pixel signal PIX according to the switching operation of the first to fourth switches SW1 to SW4, and may perform a sampling operation and output a result of a comparison between the ramp signal RMP and the pixel signal PIX. In an example embodiment, the sampling circuit 500 may perform a correlated double sampling operation and output a result of a comparison between the ramp signal RMP and the pixel signal PIX.

[0070] The ramp signal RMP may include a down-ramp signal having a voltage that decreases over time and an up-ramp signal having a voltage that increases over time. In an example embodiment, the down-ramp signal may be input to the comparator 510 to perform a sampling operation on low-illuminance pixels. Furthermore, the up-ramp signal may be input to the comparator 510 to perform a sampling operation on high-illuminance pixels.

[0071] The pixel signal PIX may be an analog signal output through a column line of the pixel array, and may include a reset signal corresponding to a specific power supply voltage and an image signal corresponding to charges generated by the photoelectric conversion element.

[0072] Depending on the switching states of the first to fourth switches SW1 to SW4, various combinations of signals may be input to the comparator 410. In an exemplary embodiment, the ramp signal RMP and the pixel signal PIX may be input to the comparator 510 to perform a sampling operation on low-illuminance pixels. In addition, to perform a sampling operation on high-illuminance pixels, only the pixel signal PIX may be input to the comparator 510 during the auto-zero period, and the ramp signal RMP and the pixel signal PIX may be input to the comparator 510 during the comparison period (hereinafter, simply referred to as a "period" or "interval").

[0073] The first capacitor C1 may be connected between the first node N1 and the first input node IN1 of the comparator 510, and the second capacitor C2 may be connected between the second node N2 and the second input node IN2 of the comparator 510. The ramp signal RMP or the pixel signal PIX may be input to the first input node IN1 of the comparator 510 through the first capacitor C1. Also, the pixel signal PIX may be input to the second input node IN2 of the comparator 510 through the second capacitor C2.

[0074] The comparator 510 may compare the ramp signal RMP with the pixel signal PIX input through the first capacitor C1 and the second capacitor C2, and may output a comparison signal CMP through the second output node OUT2 as a result of the comparison. In an example embodiment, the comparator 410 may be a differential amplifier and may be implemented by an operational transconductance amplifier (OTA), an operational amplifier, etc.

[0075] A first auto-zero switch AZ1 may be connected between a first input node IN1 and a first output node OUT1 of the comparator 510. A second auto-zero switch AZ2 may be connected between a second input node IN2 and a second output node OUT2 of the comparator 510. The first auto-zero switch AZ1 and the second auto-zero switch AZ2 may be switched in response to an auto-zero control signal AZS. The comparator 510 may be initialized by turning on the first auto-zero switch AZ1 and the second auto-zero switch AZ2 during an auto-zero period of operation of the comparator 510.

[0076] The sampling circuit 500 can operate in a first mode for low-illuminance pixels and can perform a single initialization process. In the process of calculating the difference between the count value obtained from the reset signal and the count value obtained from the image signal, the reset noise generated in the initialization process can be removed. The sampling circuit 500 can operate in a second mode with respect to high-illuminance pixels and can perform multiple initialization processes. Although it is not possible to remove the reset noise generated in multiple initialization processes, since the gain (e.g., x1) applied to the high-illuminance pixels may be relatively low, its effect on the comparison result may be negligible and negligible. Figure 7 An example of a comparator 510 and a first peripheral circuit 530 is shown in FIG.

[0077] Figure 7 It shows Figure 6 FIG2 is a circuit diagram of a comparator and a first peripheral circuit of a sampling circuit shown in FIG2 . Here, the comparator 610 may include first to fifth transistors M1 to M5 .

[0078] The first transistor M1 may be connected between the first output node OUT1 and the common node CN, and the gate of the first transistor M1 may be connected to the first input node IN1. The second transistor M2 may be connected between the second output node OUT2 and the common node CN, and the gate of the second transistor M2 may be connected to the second input node IN2. The third transistor M3 may be connected between the first power supply voltage VDDA node and the first output node OUT1. The fourth transistor M4 may be connected between the first power supply voltage VDDA node and the second output node OUT2.

[0079] A gate of the third transistor M3 and a gate of the fourth transistor M4 may be connected to the first output node OUT1. The third transistor M3 and the fourth transistor M4 may be included in a current mirror circuit.

[0080] In example embodiments, the first transistor M1 and the second transistor M2 may be implemented as NMOS transistors, and the third transistor M3 and the fourth transistor M4 may be implemented as PMOS transistors. Alternatively, the first transistor M1 and the second transistor M2 may be implemented as PMOS transistors, and the third transistor M3 and the fourth transistor M4 may be implemented as NMOS transistors.

[0081] The fifth transistor M5 may be connected between the common node CN and a second power voltage VSSA node. The second power voltage VSSA may be a voltage having a lower voltage level than the first power voltage VDDA, for example, a ground voltage.

[0082] The fifth transistor M5 may operate as a current source of the comparator 510. For example, the fifth transistor M5 may receive a specific bias voltage VBIAS through a gate and generate a drive current Idrive corresponding to the sum of first and second currents flowing through the first and second transistors M1 and M2, respectively.

[0083] The first peripheral circuit 630 may include first and second auto-zero switches AZ1 and AZ2 and first and second capacitors C1 and C2.

[0084] The first auto-zero switch AZ1 can be connected between the first output node OUT1 and the first input node IN1. The second auto-zero switch AZ2 can be connected between the second output node OUT2 and the second input node IN2. The first auto-zero switch AZ1 and the second auto-zero switch AZ2 can be implemented as transistors that are turned on in response to the auto-zero control signal AZS input through each gate. For example, the first auto-zero switch AZ1 and the second auto-zero switch AZ2 can be implemented as PMOS transistors.

[0085] The first capacitor C1 may be connected between the first node N1 to which the ramp signal RMP or the pixel signal PIX is selectively input and the first input node IN1. The second capacitor C2 may be connected between the second node N2 to which the pixel signal PIX is input and the second input node IN2.

[0086] As a result of comparing the ramp signal RMP with the pixel signal PIX, a comparison signal CMP may be output through the second output node OUT2 .

[0087] When the second power supply voltage VSSA is a ground voltage, the first power supply voltage VDDA may have a voltage level equal to or higher than the sum of the first voltage V1 to the third voltage V3 and the swing width Vsig of the pixel signal PIX to drive the comparator 610. The first voltage V1 may be the source-gate voltage (Vsg, M3, and M4) of each of the third transistor M3 and the fourth transistor M4 to allow current to flow in the fifth transistor M5. The second voltage V2 may be the source-gate voltage (Vsg, M1, and M2) of each of the first transistor M1 and the second transistor M2 to allow current to flow in the fifth transistor M5. The third voltage V3 may be the drain-source voltage (Vds, M5) of the fifth transistor M5 to keep the fifth transistor M5 in a saturated state. For example, when the first voltage V1 is 0.8V, the second voltage V2 is 0.5V, the third voltage V3 is 0.3V, and the swing Vsig of the pixel signal PIX is 1V, the first power supply voltage VDDA may have a voltage level equal to or higher than 2.6V to drive the comparator 510 .

[0088] During the auto-zero period when the first and second auto-zero switches AZ1 and AZ2 are turned on, the voltage levels of the first and second input nodes IN1, IN2, and OUT1 and OUT2 can be initialized to specific values. For example, in an example where the first power supply voltage VDDA has a voltage level of 2.6V or higher, the auto-zero operation can initialize the voltage level of the first input node IN1 to VDDA-0.8V. Because the auto-zero control signal AZS has the same voltage level as the first power supply voltage VDDA, when the ramp signal RMP increases by 1V, which is the same as the swing amplitude Vsig of the pixel signal PIX, a charge overflow phenomenon may occur, in which the charge accumulated in the first capacitor C1 moves to the first output node OUT1. Since the charge overflow phenomenon may increase random noise and pixel settling time, this may hinder the implementation of high frame rate (HFR) video capture. In order to solve the above problem, the image sensor in the example embodiment can perform an auto-zero operation for each of the reset signal and the image signal in the sampling operation for the high-illuminance pixel, so that the charge overflow phenomenon can be prevented and the headroom voltage corresponding to the driving current flowing in the fifth transistor M5 can be reduced, thereby reducing power consumption.

[0089] During the auto-zero period when the first auto-zero switch AZ1 and the second auto-zero switch AZ2 are turned on, the voltage levels of the first input node IN1, the second input node IN2, the first output node OUT1, and the second output node OUT2 can be the same. In this case, the voltages of the first input node IN1, the second input node IN2, the first output node OUT1, and the second output node OUT2 can be referred to as the auto-zero voltage. Furthermore, during the auto-zero period, the voltage of the common node CN can be referred to as the saturation voltage and can vary depending on the characteristics of the fifth transistor M5. The input range of the comparator 610 can be determined based on the auto-zero voltage and the saturation voltage.

[0090] Figure 8 is a diagram illustrating an operating method of a sampling circuit according to example embodiments.

[0091] refer to Figure 8 and Figure 6 The sampling circuit 500 may perform sampling operations on the reset signal and the image signal in sequence. For example, the sampling circuit 500 may perform a first sampling operation on the reset signal and a second sampling operation on the image signal.

[0092] In an example embodiment, the sampling circuit 500 may perform sampling operations with different gains for high-illuminance pixels and low-illuminance pixels. The sampling circuit 500 may perform a first sampling operation with a first gain for low-gain pixels in a first mode. The sampling circuit 500 may perform a second sampling operation with a second gain lower than the first gain for high-illuminance pixels in a second mode. In other words, the first mode may be a mode for measuring the illuminance of the pixel PX within a first range corresponding to the low-illuminance state of the pixel PX, and the second mode may be a mode for measuring the illuminance of the pixel PX within a second range corresponding to the high-illuminance state of the pixel PX.

[0093] The sampling circuit 500 may control the auto-zero operation AZ differently depending on the operating mode. In an example embodiment, the sampling circuit 500 may perform the auto-zero operation AZ only once before performing the first sampling operation in the first mode. Furthermore, in the second mode, the sampling circuit 500 may perform the auto-zero operation AZ twice by performing the auto-zero operation AZ before performing the first sampling operation and before performing the second sampling operation. Since the auto-zero operation AZ can be performed once in the first mode, the auto-zero operation AZ may be referred to as a single auto-zero operation. Additionally, since the auto-zero operation AZ is performed twice in the second mode, the auto-zero operation AZ may be referred to as a double auto-zero operation.

[0094] The sampling circuit 500 can ensure the accuracy of the comparison result between the ramp signal and the pixel signal by performing a single auto-zero operation in a first mode in which the sampling circuit 500 operates at a relatively high first gain. In addition, the sampling circuit 500 can reduce power consumption by performing a double auto-zero operation in a second mode in which the sampling circuit 500 operates at a second gain that is smaller than the first gain, thereby reducing the headroom voltage corresponding to the drive current.

[0095] Figure 9 is a timing chart showing an example in which the sampling circuit operates in the first mode.

[0096] refer to Figure 9 and Figure 6 When the first control signal S1 is activated and the second control signal S2 is deactivated, the first switch SW1 and the third switch SW3 may be turned on, and the second switch SW2 and the fourth switch SW4 may be turned off. In an example embodiment, the first control signal S1 and the second control signal S2 may be activated when having a high logic value H, and may be deactivated when having a low logic value L. When the first switch SW1 and the third switch SW3 are turned on, the ramp signal RMP may be input to the first input node IN1 of the comparator 510 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2.

[0097] When the auto-zero control signal AZS is activated in the first time period T1, the sampling circuit 500 may perform an auto-zero operation. In an example embodiment, the auto-zero control signal AZS may be activated when it has a high logic value H, and may be deactivated when it has a low logic value L. The sampling circuit 500 may be initialized by performing the auto-zero operation.

[0098] The voltage VIN1 of the first input node IN1 of the comparator 510 may be the same as the voltage of the ramp signal RMP. In addition, the voltage VIN2 of the second input node IN2 of the comparator 510 may be the same as the voltage of the pixel signal PIX. The pixel signal PIX input to the comparator 510 in the first period T1 may be a reset signal and may have the same voltage level as the initial voltage of the ramp signal RMP.

[0099] In the second time period T2, an offset may be added to the ramp signal RMP. Thereafter, the ramp signal RMP may decrease to have a specific slope. By counting a third time period T3 from the time point at which the ramp signal RMP decreases to the time point at which the ramp signal RMP falls below the pixel signal PIX using a specific clock signal, analog-to-digital conversion may be performed on the reset signal.

[0100] In the fourth period T4, the ramp signal RMP may have the same voltage level as the voltage level in the second period T2. An image signal may be input to the comparator 410 as the pixel signal PIX, and the image signal may have a voltage level lower than the initial voltage of the ramp signal RMP. The voltage difference between the image signal and the initial voltage of the ramp signal RMP may correspond to the amount of charge generated by the photodiode.

[0101] After that, the ramp signal RMP may decrease to have a specific slope. By counting the fifth period T5 from the time point when the ramp signal RMP decreases to the time point when the ramp signal RMP falls below the pixel signal PIX using a specific clock signal, analog-to-digital conversion of the image signal may be performed. In addition, in the sixth period T6, the ramp signal RMP may be initialized for a subsequent sampling operation.

[0102] The image sensor in example embodiments may generate image data by calculating a difference between a count value of a fifth period T5 corresponding to a digital value of an image signal and a count value of a second period T2 corresponding to a digital value of a reset signal.

[0103] Meanwhile, the first period T1 may be referred to as an auto-zero period, and the second to sixth periods T2 to T6 may be referred to as comparison periods. In the following description, a connection relationship in the sampling circuit 500 in the auto-zero period and the comparison period in the first mode will be described.

[0104] Figure 10A is a diagram illustrating a state of a sampling circuit in an auto-zero period when the sampling circuit operates in a first mode according to an example embodiment. Figure 10B is a diagram illustrating a state of a sampling circuit in a comparison period when the sampling circuit operates in a first mode according to an example embodiment. Figure 10A The sampling circuit 700a and Figure 10B The configuration and function of the sampling circuit 700b in Figure 6 The configuration and function of the sampling circuit 500 in FIG. 5 are the same, and therefore, repeated description will not be provided.

[0105] refer to Figure 10A When the first switch SW1 and the third switch SW3 are turned on during the auto-zero period in the first mode, the ramp signal RMP can be input to the first input node IN1 of the comparator 710 through the first capacitor C1, and the pixel signal PIX can be input to the second input node IN2 through the second capacitor C2. In addition, the comparator 710 can be initialized when the first auto-zero switch AZ1 and the second auto-zero switch AZ2 are turned on.

[0106] refer to Figure 10B When the first switch SW1 and the third switch SW3 are turned on during the comparison period in the first mode, the ramp signal RMP can be input to the first input node IN1 of the comparator 710 through the first capacitor C1, and the pixel signal PIX can be input to the second input node IN2 through the second capacitor C2. In addition, when the first auto-zero switch AZ1 and the second auto-zero switch AZ2 are turned off, the comparator 710 can output the comparison signal CMP obtained by comparing the ramp signal RMP and the pixel signal PIX through the second output node OUT2.

[0107] Figure 11 is a timing chart showing an example in which the sampling circuit operates in the second mode.

[0108] refer to Figure 11 and Figure 6 When the auto-zero control signal AZS is activated in the first period T1, the sampling circuit 500 may perform a first auto-zero operation. The sampling circuit 500 may be initialized by the first auto-zero operation.

[0109] In addition, when the first control signal S1 is deactivated and the second control signal S2 is activated, the first switch SW1 and the third switch SW3 can be turned off, and the second switch SW2 and the fourth switch SW4 can be turned on. When the second switch SW2 and the fourth switch SW4 are turned on, the pixel signal PIX can be input to the first input node IN1 and the second input node IN2 of the comparator 510 through the first capacitor C1 and the second capacitor C2. Therefore, the voltage VIN1 of the first input node IN1 and the voltage VIN2 of the second input node IN2 of the comparator 510 can be the same as the voltage of the pixel signal PIX. The pixel signal PIX input to the comparator 510 in the first period T1 can be a reset signal and can have a voltage level higher than the ramp signal RMP. The voltage difference between the pixel signal PIX and the ramp signal RMP can be considered as an offset of the ramp signal RMP.

[0110] In the second period T2, when the first control signal S1 is activated and the second control signal S2 is deactivated, the first switch SW1 and the third switch SW3 may be turned on, while the second switch SW2 and the fourth switch SW4 may be turned off. When the first switch SW1 and the third switch SW3 are turned on, the ramp signal RMP may be input to the first input node IN1 of the comparator 710 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2. Therefore, the voltage VIN1 of the first input node IN1 of the comparator 510 may become the same as the voltage of the ramp signal RMP, and the voltage VIN2 of the second input node IN2 may become the same as the voltage of the pixel signal PIX.

[0111] By counting a third period T3 from the time point when the ramp signal RMP increases to the time point when the ramp signal RMP is greater than the pixel signal PIX using a specific clock signal, analog-to-digital conversion for the reset signal can be performed.

[0112] When the auto-zero control signal AZS is activated during the fourth period T4, the sampling circuit 500 may perform a second auto-zero operation. The sampling circuit 500 may be reinitialized through the second auto-zero operation. Furthermore, when the first control signal S1 is deactivated and the second control signal S2 is activated, the first switch SW1 and the third switch SW3 may be disconnected, and the second switch SW2 and the fourth switch SW4 may be turned on. When the second switch SW2 and the fourth switch SW4 are turned on, the pixel signal PIX may be input to the first input node IN1 and the second input node IN2 of the comparator 510 via the first capacitor C1 and the second capacitor C2. During the fourth period T4, the ramp signal RMP may have a voltage level lower than the initial voltage. An image signal may be input to the comparator 510 as the pixel signal PIX, and the decrease in the voltage of the pixel signal PIX caused by the input of the image signal may be considered as an offset of the ramp signal RMP.

[0113] After that, the ramp signal RMP may increase again to have a specific slope. By counting the fifth period T5 from the time point when the ramp signal RMP increases to the time point when the ramp signal RMP is greater than the pixel signal PIX using a specific clock signal, analog-to-digital conversion of the image signal may be performed. In addition, in the sixth period T6, the ramp signal RMP may be initialized for a subsequent sampling operation.

[0114] The image sensor in the example embodiment may generate image data by calculating the difference between the count value of the fifth period T5 corresponding to the digital value of the image signal and the count value of the third period T3 corresponding to the digital value of the reset signal. When the sampling circuit 500 performs a sampling operation using the up-ramp signal, in the example embodiment, the image data may be generated by subtracting the difference between the count value corresponding to the image signal and the count value corresponding to the reset signal from 2n (n is the resolution of the analog-to-digital converter).

[0115] The first period T1 and the fourth period T4 may be referred to as auto-zero periods, and the second period T2, the third period T3, the fifth period T5, and the sixth period T6 may be referred to as comparison periods. In the following description, the connection relationship in the sampling circuit 500 during the auto-zero period and the comparison period in the second mode will be described.

[0116] Figure 12A is a diagram illustrating a state of a sampling circuit in an auto-zero period when the sampling circuit operates in a second mode according to an example embodiment, and Figure 12B is a diagram illustrating a state of a sampling circuit in a comparison period when the sampling circuit operates in a second mode according to an example embodiment. Figure 12A The sampling circuit 800a and Figure 12BThe configuration and function of the sampling circuit 800 b may be the same as those of the sampling circuit 500 of 6 , and thus a repeated description will not be provided.

[0117] refer to Figure 12A In the second mode, when the first control signal S1 is deactivated and the second control signal S2 is activated during the auto-zero period, the first switch SW1 and the third switch SW3 may be turned off, while the second switch SW2 and the fourth switch SW4 may be turned on. When the second switch SW2 and the fourth switch SW4 are turned on, the pixel signal PIX may be input to the first input node IN1 and the second input node IN2 of the comparator 810 through the first capacitor C1 and the second capacitor C2. Furthermore, the comparator 810 may be initialized when the first auto-zero switch AZ1 and the second auto-zero switch AZ2 are turned on.

[0118] refer to Figure 12B In the second mode, when the first switch SW1 and the third switch SW3 are turned on during the comparison period, the ramp signal RMP may be input to the first input node IN1 of the comparator 810 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2. Furthermore, when the first auto-zero switch AZ1 and the second auto-zero switch AZ2 are turned off, the comparator 810 may output a comparison signal CMP obtained by comparing the ramp signal RMP and the pixel signal PIX.

[0119] The image sensor described in the aforementioned example embodiment can remove reset noise and ensure the accuracy of comparison operations by performing a single auto-zero operation during a sampling operation for low-illuminance pixels (a first mode). The image sensor can also reduce power consumption by performing a double auto-zero operation during a sampling operation for high-illuminance pixels (a second mode) to reduce the headroom voltage corresponding to the drive current. The following description will describe in more detail an example embodiment in which each pixel in the image sensor includes two photodiodes.

[0120] Figure 13 1 is a circuit diagram illustrating a pixel included in an image sensor according to an example embodiment. Here, a pixel PX′ in the image sensor 100 may include two photodiodes PD1 and PD2 and a pixel circuit ( Figure 13). The pixel circuit can process the charge generated by the two photodiodes PD1 and PD2 and can output an electrical signal at a node PN. The pixel circuit may include two transfer transistors TX1 and TX2, a reset transistor RX, a drive transistor DX, and a select transistor SX. The first transfer transistor TX1 can be connected to the first photodiode PD1, and the second transfer transistor TX2 can be connected to the second photodiode PD2. In the following description, a pixel PX' including two photodiodes PD1 and PD2 may be referred to as a 2PD pixel. In various embodiments, the two photodiodes PD1 and PD2 can be used for autofocus during an autofocus mode. During imaging mode, the photocharges from both the photodiodes PD1 and PD2 can be used to achieve HDR resolution or for other purposes using the methods disclosed herein.

[0121] The reset transistor RX can be turned on and off by the reset control signal RG, and when the reset transistor RX is turned on, the voltage of the floating diffusion area FD can be reset to the power supply voltage VDD. When the voltage of the floating diffusion area FD is reset, the selection transistor SX can be turned on by the selection control signal SEL, and a reset signal can be output to the column line COL.

[0122] When the first transfer transistor TX1 is turned on after the reset voltage is output to the column line COL, the charge generated by the first photodiode PD1 exposed to light can be moved to the floating diffusion area FD. The drive transistor DX can operate as a source follower amplifier for amplifying the voltage of the floating diffusion area FD, and when the selection transistor SX is turned on by the selection control signal SEL, a first image signal corresponding to the charge generated by the photodiode PD can be output to the column line COL.

[0123] When the second transfer transistor TX2 is turned on after the first image signal is output to the column line COL, the charges generated by the second photodiode PD2 exposed to light can be moved to the floating diffusion area FD. When the selection transistor SX is turned on by the selection control signal SEL, a second image signal corresponding to the charges generated by the photodiode PD can be output to the column line COL.

[0124] Each of the reset signal and the first and second image signals can be detected by a sampling circuit connected to the column line COL. The sampling circuit may include a plurality of samplers, each of the samplers having a first input terminal for receiving the ramp signal and a second input terminal for receiving the reset signal and the first and second image signals.

[0125] The sampler may compare the reset signal and each of the first image signal and the second image signal with the ramp signal. An analog-to-digital converter (ADC) may be connected to an output terminal of the sampler. The ADC may output first image data based on a count value corresponding to the first image signal and a count value corresponding to the reset signal. The ADC may also output second image data based on a count value corresponding to the second image signal and a count value corresponding to the reset signal. Furthermore, an image signal processor (ISP) may generate an image using the first image data and the second image data.

[0126] Figure 14 is a cross-sectional view showing the vertical structure of a 2PD pixel.

[0127] refer to Figure 14 , each of the pixels PX1 and PX2 of the pixel array PXA may include two photodiodes PD1 and PD2 and PD1 ′ and PD2 ′.

[0128] Each of the pixels PX1 and PX2 may include a color filter and a microlens disposed on two photodiodes PD1 and PD2 and PD1 ′ and PD2 ′, respectively.

[0129] Two photodiodes PD1 and PD2, as well as PD1' and PD2', may be formed in a silicon substrate, and deep trench isolation (DTI) may be formed between the two photodiodes PD1 and PD2, as well as PD1' and PD2'. For example, an intra-pixel DTI may be formed between the two photodiodes PD1 and PD2, as well as PD1' and PD2', and an inter-pixel DTI may be formed between pixels PX1 and PX2.

[0130] Metal wiring, multilayer wiring, or wiring layers may be formed in a circuit region formed between the two photodiodes PD1 and PD2 and PD1' and PD2' and the color filter. A lens buffer or a planarization layer may be formed between the microlens and the color filter.

[0131] Include reference Figure 13 and Figure 14 The described 2PD pixel image sensor may include Figure 6 The sampling circuit shown is equivalent to the sampling circuit shown in FIG. In the following description, the sampling operation of the 2PD pixel will be described in detail.

[0132] Figure 15A and Figure 15B is a diagram illustrating a method of operating a sampling circuit according to example embodiments.

[0133] refer to Figure 15A and Figure 6, the sampling circuit 500 can sequentially perform sampling operations on multiple pixel signals of the 2PD pixel, such as a reset signal, a first image signal, and a second image signal. For example, the sampling circuit 500 can perform a first sampling operation on the first reset signal and a second sampling operation on the second reset signal. In addition, the sampling circuit 500 can perform a third sampling operation on the first image signal and a fourth sampling operation on the second image signal. A counting method can be used to monitor the comparison signal generated in response to the sampling operation of the sampling circuit 500 to determine the analog level of each sampled signal. The analog level can be converted into a digital signal and can be stored in a latch or a buffer. The column driver can generate image data by performing a differential calculation using the count value as a digital signal stored in the latch or buffer.

[0134] In an example embodiment, the sampling circuit 500 may perform sampling operations on low-illuminance pixels and high-illuminance pixels at different gains. In a first mode, the sampling circuit 500 may perform a first sampling operation on low-illuminance pixels at a first gain. The sampling circuit 500 may perform a second sampling operation on high-illuminance pixels at a second gain that is smaller than the first gain.

[0135] The sampling circuit 500 may perform the auto-zero operation AZ differently depending on the operating mode. In an example embodiment, the sampling circuit 500 may perform the auto-zero operation AZ only once before performing the first sampling operation in the first mode. Since the auto-zero operation AZ is performed only once in the first mode, the auto-zero operation AZ may be referred to as a single auto-zero operation. Compared to the above example, the sampling circuit 500 may perform the auto-zero operation AZ before performing the first to fourth sampling operations in the second mode. Since the auto-zero operation AZ may be performed four times in the second mode, the auto-zero operation AZ may be referred to as a multiple auto-zero operation.

[0136] refer to Figure 15B , sampling circuit 500 can sequentially sample the reset signal, first image signal, and second image signal of the 2PD pixel. Furthermore, for each pixel illumination measurement, sampling circuit 500 can perform only one sampling operation on the reset signal. For example, sampling circuit 500 can perform a first sampling operation on the reset signal, a second sampling operation on the first image signal, and a third sampling operation on the second image signal.

[0137] The sampling circuit 500 may perform the auto-zero operation AZ differently depending on the operation mode. In an example embodiment, the sampling circuit 500 may perform the auto-zero operation AZ only once before performing the first sampling operation in the first mode. Unlike the above example, the sampling circuit 500 may perform the auto-zero operation AZ before performing the first to third sampling operations, so that the sampling circuit 500 may perform the auto-zero operation AZ three times.

[0138] refer to Figure 15A and Figure 15B Since the sampling circuit 500 performs a single auto-zero operation in the first mode in which the sampling circuit 500 has a relatively high first gain, the accuracy of the comparison result between the ramp signal and the pixel signal can be ensured. In addition, since the sampling circuit 500 performs a multiple auto-zero operation in the second mode in which the sampling circuit 500 has a second gain smaller than the first gain, the headroom voltage corresponding to the drive current can be reduced, so that power consumption can be reduced.

[0139] In the following description, the following will be based on the Figure 15B The sampling method shown describes the first mode and the second mode of the sampling circuit in more detail.

[0140] Figure 16 is a timing diagram illustrating an example in which the sampling circuit according to example embodiments operates in the first mode.

[0141] refer to Figure 16 and Figure 6 When the first control signal S1 is activated (e.g., activated to a high logic value) and the second control signal S2 is deactivated (e.g., deactivated to a low logic value), the first switch SW1 and the third switch SW3 may be turned on, while the second switch SW2 and the fourth switch SW4 may be turned off. When the first switch SW1 and the third switch SW3 are turned on, the ramp signal RMP may be input to the first input node IN1 of the comparator 510 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2.

[0142] When the auto-zero control signal AZS is activated (eg, activated to a high logic value) in the first period T1, the sampling circuit 500 may perform an auto-zero operation. The sampling circuit 500 may be initialized by the auto-zero operation.

[0143] The voltage VIN1 of the first input node IN1 of the comparator 510 may be the same as the voltage of the ramp signal RMP. In addition, the voltage VIN2 of the second input node IN2 of the comparator 510 may be the same as the voltage of the pixel signal PIX. The pixel signal PIX input to the comparator 510 in the first period T1 may be a reset signal and may have a voltage level equal to the initial voltage of the ramp signal RMP.

[0144] In the second period T2, an offset may be added to the ramp signal RMP. Thereafter, the ramp signal RMP may decrease to have a specific slope. By counting a third period T3 from the time point at which the ramp signal RMP decreases to the time point at which the ramp signal RMP falls below the pixel signal PIX using a specific clock signal, analog-to-digital conversion may be performed on the reset signal.

[0145] In the fourth period T4, the ramp signal RMP may have a voltage level equal to the voltage level in the second period T2. The first image signal may be input to the comparator 510 as the pixel signal PIX. The first image signal may be an electrical signal corresponding to the charge generated by the first photodiode of the pixel and may have a first voltage level lower than the initial voltage of the ramp signal RMP. The difference in initial voltage between the first image signal and the ramp signal RMP may correspond to the amount of charge generated by the first photodiode.

[0146] By counting a fifth period T5 from the time point when the ramp signal RMP decreases to the time point when the ramp signal RMP is lower than the pixel signal PIX using a specific clock signal, analog-to-digital conversion can be performed on the first image signal.

[0147] In the sixth period T6, the ramp signal RMP may have a voltage level equal to the voltage level in the second period T2. The second image signal may be input to the comparator 510 as the pixel signal PIX. The second image signal may be an electrical signal corresponding to the charge generated by the second photodiode of the pixel and may have a second voltage level lower than the initial voltage of the ramp signal RMP. The difference in initial voltage between the second image signal and the ramp signal RMP may correspond to the amount of charge generated by the second photodiode.

[0148] After that, the ramp signal RMP may decrease to have a specific slope. By counting the seventh period T7 from the time point when the ramp signal RMP decreases to the time point when the ramp signal RMP falls below the pixel signal PIX using a specific clock signal, analog-to-digital conversion of the second image signal may be performed. Furthermore, in the eighth period T8, the ramp signal RMP may be initialized for a subsequent sampling operation.

[0149] The image sensor in the example embodiment may generate first image data by calculating the difference between a count value in a fifth period T5 corresponding to the digital value of the first image signal and a count value in a second period T2 corresponding to the digital value of the reset signal. Furthermore, the image sensor in the example embodiment may generate second image data by calculating the difference between a count value in a seventh period T7 corresponding to the digital value of the second image signal and a count value in the second period T2 corresponding to the digital value of the reset signal. Thereafter, the image signal processor (ISP) may generate an image using the first image data and the second image data.

[0150] Figure 17 is a timing diagram illustrating an example in which the sampling circuit according to example embodiments operates in the second mode.

[0151] refer to Figure 17 and Figure 6 When the auto-zero control signal AZS is activated (eg, activated to a high logic value) in the first period T1, the sampling circuit 500 may perform a first auto-zero operation. The sampling circuit 500 may be initialized by the first auto-zero operation.

[0152] In addition, when the first control signal S1 is deactivated (e.g., activated to a low logic value) and the second control signal S2 is activated (e.g., activated to a high logic value), the first switch SW1 and the third switch SW3 can be disconnected, while the second switch SW2 and the fourth switch SW4 can be turned on. When the second switch SW2 and the fourth switch SW4 are turned on, the pixel signal PIX can be input to the first input node IN1 and the second input node IN2 of the comparator 510 through the first capacitor C1 and the second capacitor C2. Therefore, the voltage VIN1 of the first input node IN1 and the voltage VIN2 of the second input node IN2 of the comparator 510 can be the same as the voltage of the pixel signal PIX. The pixel signal PIX input to the comparator 510 in the first period T1 can be a reset signal and can have a voltage level higher than the voltage level of the ramp signal RMP. The voltage difference between the pixel signal PIX and the ramp signal RMP can be considered as an offset of the ramp signal RMP.

[0153] When the first control signal S1 is activated and the second control signal S2 is deactivated in the second period T2, the first switch SW1 and the third switch SW3 may be turned on, while the second switch SW2 and the fourth switch SW4 may be turned off. When the first switch SW1 and the third switch SW3 are turned on, the ramp signal RMP may be input to the first input node IN1 of the comparator 510 through the first capacitor C1, and the pixel signal PIX may be input to the second input node IN2 through the second capacitor C2. Therefore, the voltage VIN1 of the first input node IN1 of the comparator 510 may become the same as the voltage of the ramp signal RMP, and the voltage VIN2 of the second input node IN2 may become the same as the voltage of the pixel signal PIX.

[0154] By counting a third period T3 from the time point when the ramp signal RMP increases to the time point when the ramp signal RMP is greater than the pixel signal PIX using a specific clock signal, analog-to-digital conversion for the reset signal can be performed.

[0155] When the auto-zero control signal AZS is activated again in the fourth period T4, the sampling circuit 500 may perform a second auto-zero operation. The sampling circuit 500 may be reinitialized by the second auto-zero operation. Furthermore, when the first control signal S1 is deactivated and the second control signal S2 is activated, the first switch SW1 and the third switch SW3 may be disconnected, and the second switch SW2 and the fourth switch SW4 may be turned on. When the second switch SW2 and the fourth switch SW4 are turned on, the pixel signal PIX may be input to the first input node IN1 and the second input node IN2 of the comparator 510 through the first capacitor C1 and the second capacitor C2. Therefore, the voltage VIN1 of the first input node IN1 and the voltage VIN2 of the second input node IN2 of the comparator 510 may be the same as the voltage of the pixel signal PIX.

[0156] In the fourth period T4, the ramp signal RMP may have a voltage level lower than its initial voltage. The first image signal may be input to the comparator 510 as the pixel signal PIX, and a decrease in the voltage of the pixel signal PIX caused by the input of the first image signal may be considered as an offset of the ramp signal RMP.

[0157] Thereafter, the ramp signal RMP may increase again to have a specific slope. By counting a fifth period T5 from the time point when the ramp signal RMP increases to the time point when the ramp signal RMP is greater than the pixel signal PIX using a specific clock signal, analog-to-digital conversion for the image signal may be performed.

[0158] When the auto-zero control signal AZS is activated during the sixth period T6, the sampling circuit 500 may perform a third auto-zero operation. The sampling circuit 500 may be reinitialized by the third auto-zero operation. Furthermore, when the first control signal S1 is deactivated and the second control signal S2 is activated, the first switch SW1 and the third switch SW3 may be turned off, and the second switch SW2 and the fourth switch SW4 may be turned on. When the second switch SW2 and the fourth switch SW4 are turned on, the pixel signal PIX may be input to the first input node IN1 and the second input node IN2 of the comparator 510 via the first capacitor C1 and the second capacitor C2. Therefore, the voltage VIN1 of the first input node IN1 and the voltage VIN2 of the second input node IN2 of the comparator 510 may be the same as the voltage of the pixel signal PIX.

[0159] The pixel signal PIX input to the comparator 510 in the seventh period T7 may be a second image signal and may have a voltage level higher than that of the ramp signal RMP. The voltage difference between the pixel signal PIX and the ramp signal RMP may be considered as an offset of the ramp signal RMP.

[0160] After that, the ramp signal RMP may increase again to have a specific slope. By counting the eighth period T8 from the time point when the ramp signal RMP increases to the time point when the ramp signal RMP is greater than the pixel signal PIX using a specific clock signal, analog-to-digital conversion of the image signal may be performed. In the ninth period T9, the ramp signal RMP may be initialized for a subsequent sampling operation.

[0161] The image sensor in the example embodiment may generate the first image data by calculating the difference between the count value of the fifth period T5 corresponding to the digital value of the first image signal and the count value of the third period T3 corresponding to the digital value of the reset signal. In addition, the image sensor in the example embodiment may generate the second image data by calculating the difference between the count value of the eighth period T8 corresponding to the digital value of the second image signal and the count value of the third period T3 corresponding to the digital value of the reset signal.

[0162] When the sampling circuit 500 performs a sampling operation using an up-ramp signal, the first image data and the second image data may be generated by subtracting a difference between count values corresponding to the first image signal and the second image signal and a count value corresponding to the reset signal from 2n (n is the resolution of the analog-to-digital converter).

[0163] Thereafter, the image signal processor ISP may generate an image using the first image data and the second image data.

[0164] Figure 18 is a block diagram illustrating an electronic device including an image sensor according to example embodiments.

[0165] refer to Figure 18 , the electronic device 1000 may include a memory 1010, an imaging device 1020, a processor 1030, a communication module 1040, and the like.

[0166] exist Figure 18 Among the elements shown, the electronic device 1000 may be provided with a communication module 1040 to communicate with a video card, a sound card, a memory card, a USB device, etc. The electronic device 1000 may include general desktop computers and laptop computers, and may also include smartphones, tablet PCs, smart wearable devices, etc.

[0167] The memory 1010 may be implemented by a storage medium for storing data required for the operation of the electronic device 1000, multimedia data, etc. The memory 1010 may include a storage device configured based on a non-volatile memory device. In addition, the memory 1010 may include at least one of a solid-state drive (SSD), a hard disk drive (HDD), and an optical disk drive (ODD) as a storage device.

[0168] The processor 1030 may perform specific calculations or process commands and tasks. The processor 1030 may be implemented by a central processing unit (CPU) or a microprocessor unit (MCU), a system on a chip (SoC), etc., and may communicate with the memory 1010 and the imaging device 1020 through a bus 1050 and with other devices connected to the electronic device 1000 through a communication module 1040.

[0169] Included in Figure 18 The imaging device 1020 in the electronic device 1000 shown may include the image sensor described in the aforementioned exemplary embodiments. As an example, the imaging device 1020 may be configured as described in the reference image sensor. Figures 1 to 17 The foregoing example embodiments are described to operate.

[0170] According to the aforementioned example embodiments, the image sensor may perform a single auto-zero operation in a high gain mode, so that reset noise may be removed and image quality may be improved.

[0171] Furthermore, the image sensor may perform multiple auto-zero operations in a sampling operation for high-illuminance pixels, so that a headroom voltage corresponding to a driving current may be reduced, and thus power consumption may be reduced.

[0172] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. An imaging device comprising: a pixel array comprising a plurality of pixels connected to a plurality of row lines and a plurality of column lines, wherein each of the plurality of pixels is configured to generate a reset signal and an image signal; a sampling circuit comprising a plurality of sampler circuits connected to the plurality of column lines, wherein each of the plurality of sampler circuits is configured to generate a first comparison signal by comparing a reset signal with a ramp signal and to generate a second comparison signal by comparing an image signal with the ramp signal; an analog-to-digital converter configured to convert each of the first comparison signal and the second comparison signal into a corresponding digital signal; and a column driver configured to generate image data based on the first comparison signal and the second comparison signal converted into digital signals, wherein each of the plurality of sampler circuits performs, in a first mode, for low-illuminance pixels, a first auto-zero operation for initializing itself before performing a comparison against a reset signal, and, in a second mode, for high-illuminance pixels: (i) performs a second auto-zero operation before performing a comparison against the reset signal, and (ii) performs a third auto-zero operation before performing a comparison against an image signal.

2. The imaging device according to claim 1, wherein The first mode is a mode for measuring illuminance of pixels within a first range corresponding to a low illuminance state of the pixels, and the second mode is a mode for measuring illuminance of pixels within a second range corresponding to a high illuminance state of the pixels.

3. The imaging device according to claim 1, wherein An amplification gain of each of the plurality of sampler circuits is higher in the first mode than in the second mode.

4. The imaging device according to claim 1, further comprising: a ramp signal generator configured to generate a ramp signal under the control of the timing controller and output the ramp signal to the sampling circuit; The ramp signal includes an up-ramp signal and a down-ramp signal.

5. The imaging device according to claim 4, wherein Each of the plurality of sampler circuits performs a comparison operation using a falling ramp signal in a first mode.

6. The imaging device according to claim 4, wherein Each of the plurality of sampler circuits performs a comparison operation using the up-ramp signal in the second mode.

7. The imaging device according to claim 1, wherein The analog-to-digital converter generates a first count value by counting a first comparison signal, and generates a second count value by counting a second comparison signal.

8. The imaging device according to claim 7, wherein The column driver generates the image data by calculating a difference between a first count value and a second count value.

9. The imaging device according to claim 1, wherein Each of the plurality of sampler circuits performs an auto-zero operation using a ramp signal and a reset signal in a first mode.

10. The imaging device according to claim 1, wherein Each of the plurality of sampler circuits performs an auto-zero operation using the reset signal and the image signal in the second mode.

Images