Fabrication of wafers with electrical contacts on surfaces parallel to the active surface

Abstract

The content provided herein includes various examples of methods for various aspects of manufacturing devices and sensor systems. The method may include obtaining a first carrier bonded to the upper surface of a silicon wafer. The wafer includes a through silicon via (TSV) extending through an opening in a passivation stack, wherein electrical contacts are coupled to portions of the TSV exposed by the openings. The method may include debonding the first carrier from the upper surface of the silicon wafer. The method may include cutting the silicon wafer into sub-portions including a die.

Description

[0001] Related patent applications

[0002] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 62 / 906,515, filed on September 26, 2019, the contents of which are incorporated herein by reference in their entirety and for all purposes. Background Art

[0003] Various schemes in biological or chemical research involve carrying out controlled reactions. The specified reaction can then be observed or detected, and subsequent analysis can help identify or reveal the characteristics of the chemicals involved in the reaction. In some multiple determinations, an unknown analyte with an identifiable label (e.g., a fluorescent label) can be exposed to thousands of known probes under controlled conditions. Each known probe can be placed in a corresponding well of a microplate. Any chemical reaction occurring between the known probe and the unknown analyte in the observation well can help identify or reveal the characteristics of the analyte. Other examples of such schemes include known DNA sequencing processes, such as sequencing by synthesis (SBS) or cycle array sequencing.

[0004] In some fluorescence detection schemes, an optical system is used to direct the excitation light to a fluorophore (e.g., a fluorescently labeled analyte), and is also used to detect the fluorescence emission signal light that can be emitted from the analyte with a connected fluorophore. However, such optical systems may be relatively expensive and involve a relatively large tabletop footprint. For example, an optical system may include the arrangement of a lens, an optical filter, and a light source. In other proposed detection systems, the controlled reaction in the flow cell is limited by a solid-state light sensor array (e.g., a complementary metal oxide semiconductor (CMOS) detector). These systems do not involve large optical components for detecting fluorescence emission. However, in some existing flow cells including CMOS, in order to achieve this function, the top layer is not completely transparent or does not include light diffusion or light scattering features, because in these exemplary flow cells, these features can block or interfere with excitation or emission light paths. Therefore, certain mechanisms that improve the performance of non-CMOS flow cells are excluded, such as the integration of electronic components (e.g., electrodes) or physical structures (e.g., herringbone grooves) that achieve faster SBS kinetics, thereby affecting the performance of these flow cells in SBS. Summary of the invention

[0005] Therefore, it may be beneficial that the circulation cell is a small and inexpensive device. In a relatively small circulation cell, it may be beneficial to utilize as many sensor effective areas of the light detection device as possible and / or provide as large a sensor or detector effective area as possible. The sensor or detector area (referred to as an active surface) may include the surface of the detector and the area packaged with the detector; the area extends beyond the horizontal distance (e.g., fan-out area) of the detector. In the example where a CMOS sensor is used as a detector in a circulation cell, fan-out refers to the additional horizontal distance on each side of the horizontal boundary of the CMOS sensor. In these configurations, in order to achieve electrical connection with the sensor area, a bump is formed on the front side of the CMOS detector. However, when a CMOS sensor is used as a detection device and / or an image sensor, the surface (including the fan-out area extending the surface) is an active surface, and the flatness and transparency of the detector above the active surface are related to its utility. Therefore, the bump on the surface has an adverse effect on the function. In some examples, described herein is the formation of bumps that are added to bonding through silicon via (TSV) pads on the back side of a CMOS (light) detection device, which is possible because one or more TSVs provide electrical connections from the active (i.e., photosensitive) surface of the CMOS detector to the TSV pads (i.e., the back side of the CMOS image sensor) by extending through at least one base substrate to at least one redistribution layer (RDL).

[0006] Activities utilizing the resulting device, including DNA sequencing, utilize the flat surface between the die and the CMOS surface formed by the fan-out process, and while incorporating TSVs into the design provides this flat surface to fabricate the TSVs, it also introduces certain challenges in the process of fabricating the structure. For example, the silicon wafer in the device is thinned by backside polishing to a thickness in a range (e.g., about 70-140 μm), which makes it challenging to process the wafer based on this thickness. Specifically, forming the structure presents challenges that are addressed by various aspects of the process described herein, including, but not limited to, stripping the carrier glass that holds the TSVs while forming the bumps, and thinning the wafer.

[0007] Thus, the disadvantages of the prior art can be overcome, and the benefits as described later in the present disclosure can be achieved by providing a method for manufacturing a device for use in a sensor system. Various examples of the method are described below, and the method (including and excluding the additional examples listed below) overcomes these disadvantages in any combination (provided that these combinations are not inconsistent). The method includes: obtaining a first carrier bonded to the upper surface of a silicon wafer, wherein one or more silicon through vias extend through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below the bottom surface of the silicon wafer, wherein a portion of each of the one or more silicon through vias is exposed through an opening of one or more openings in the passivation stack, wherein each exposed portion is coupled to one or more electrical contacts; debonding the first carrier from the upper surface of the silicon wafer; and cutting the silicon wafer into sub-portions including dies, so that each die includes a portion of the upper surface of the silicon wafer, at least one of the one or more silicon through vias, and at least one of the one or more electrical contacts on the second surface of the die, the portion of the upper surface of the silicon wafer including an active surface, and the second surface of the die is parallel to the active surface.

[0008] In some examples, the method also includes forming a fan-out region, the formation including: coupling the active surfaces of the tube core to the fan-out carrier, the coupling forming a first space adjacent to the first edge of each active surface of each tube core and a second space adjacent to the second edge of each active surface of each tube core; forming a molding layer, specifically by depositing a mold on the second surface of the tube core and in each first space and each second space to form the molding layer above the fan-out carrier; and polishing the top surface of the molding layer so that one or more electrical contacts on the second surface of each tube core form an adjacent surface with the polished top surface of the molding layer.

[0009] In some examples, the abutment surfaces include planar electrical contacts of equal height and thickness.

[0010] In some examples, the method further includes forming a metallization layer by coating the metal in a pattern on the adjacent surface.

[0011] In some examples, the metallization layer includes a fan-out redistribution layer based on a pattern that distributes the additional electrical contacts at locations different than locations of the one or more electrical contacts on the second surface of each die.

[0012] In some examples, the metallization layer includes an underbump layer based on a pattern that distributes the additional electrical contacts at a location of at least one of the one or more electrical contacts on the second surface of each die.

[0013] In some examples, coating the metal on the adjacent surfaces includes: forming a pattern using photolithography; electroplating the pattern, wherein the electroplating includes depositing on the one or more openings, wherein the one or more openings include photoresist; and stripping the photoresist to expose the metallization layer.

[0014] In some examples, the method also includes forming a new passivation layer on the adjacent surface to planarize the adjacent surface; forming an opening in the new passivation layer to expose at least one of the one or more electrical contacts on the second surface of each tube core; and forming a metallization layer by coating metal in a pattern on the new passivation layer.

[0015] In some examples, the method further includes depositing an electrical short prevention passivation layer on the metallization layer; and opening the electrical short prevention passivation layer at one or more locations using photolithography to form pads for electrical connection to the metallization layer.

[0016] In some examples, the method also includes peeling off the fan-out carrier to expose an active device surface, the active device surface including an active surface of the tube core and surfaces of the first space and the second space adjacent to the active surface, the peeling including: attaching the second carrier to the anti-electrical short passivation layer with an adhesive material; and detaching the fan-out carrier from the active surface of the tube core using a technique selected from the following: applying mechanical pressure, heating the fan-out carrier, and applying a solvent.

[0017] In some examples, the second carrier is comprised of a material selected from the group consisting of: glass, silicon, metal, polyethylene terephthalate, and tape.

[0018] In some examples, the method further includes preparing the active device surface to act as a sensor. In some examples, the preparing includes: washing the active device surface; and treating the active device surface using a technique selected from the group consisting of: spin coating the active device surface with a chemical solution, applying a chemical solution by sol-gel, spraying the active device surface with a chemical solution, mechanically polishing the active device surface, and baking the active device surface.

[0019] In some examples, the method further includes: forming a fluid flow channel above the active device surface, including: attaching one or more caps to a portion of the mold to form the fluid flow channel between the active device surface and the one or more caps; and removing the second carrier from the anti-electrical shorting passivation layer to form a resulting structure.

[0020] In some examples, the method further includes cutting the resulting structure into substructures, wherein each substructure includes at least one die and at least one cap.

[0021] In some examples, the passivation stack includes a metallization layer.

[0022] In some examples, the metallization layer includes a redistribution layer.

[0023] In some examples, obtaining includes fabricating one or more electrical contacts on one or more openings in the passivation stack.

[0024] In some examples, fabrication is accomplished using a technique selected from the group consisting of: an electroplating technique and a sputtering technique.

[0025] In some examples, the first carrier includes a glass carrier, and wherein the carrier is bonded to the active surface of the image sensor by a bonding agent selected from the group consisting of: epoxy, resin, and adhesive.

[0026] In some examples, the silicon wafer includes a complementary metal oxide semiconductor.

[0027] In some examples, the method further includes placing the silicon wafer on another carrier before dicing the silicon wafer into sub-portions such that the other carrier is coupled to the passivation stack; and peeling the other carrier from the silicon wafer before forming the fan-out region.

[0028] In some examples, the second carrier includes an adhesive tape, and wherein the stripping includes applying an element selected from the group consisting of: thermal energy and ultraviolet radiation.

[0029] In some examples, coupling the active surface of the die to the fan-out carrier includes forming a temporary adhesive layer between the active surface and the fan-out carrier, wherein the temporary adhesive layer protects the active surface during formation of the fan-out region.

[0030] In some examples, the molding layer is deposited to reach a height that is higher than a height of at least one electrical contact on the second surface of each die.

[0031] In some examples, each die includes a light detection device.

[0032] In some examples, forming the mold layer further includes curing the mold to obtain mechanical stability.

[0033] In some examples, curing is performed at a temperature of about one hundred degrees Celsius to about one hundred and eighty degrees Celsius.

[0034] In some examples, curing lasts from about thirty minutes to about three hundred minutes.

[0035] In some examples, the electrical short prevention passivation layer includes a material selected from the group consisting of: polyamide, epoxy resin, and solder resist.

[0036] In some examples, the one or more electrical contacts include one or more stud bumps.

[0037] The disadvantages of the prior art can be overcome, and the benefits as described later in the present disclosure can be achieved by providing a method for manufacturing a device for use in a sensor system. Various examples of the method are described below, and the method (including and excluding the additional examples listed below) overcomes these disadvantages in any combination (provided that these combinations are not inconsistent). The method includes: obtaining a first carrier bonded to the upper surface of a silicon wafer, wherein one or more silicon through vias extend through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below the bottom surface of the silicon wafer, wherein a portion of each of the one or more silicon through vias is exposed through an opening of one or more openings in the passivation stack; manufacturing one or more column bumps on the openings in the passivation stack; debonding the first carrier from the upper surface of the silicon wafer; and cutting the silicon wafer into sub-portions including a tube core.

[0038] In some examples, each of the dies includes a portion of an upper surface of a silicon wafer, at least one of one or more through-silicon vias, and at least one of one or more pillar bumps on a second surface of the die, the portion of the upper surface of the silicon wafer including an active surface, the second surface of the die being parallel to the active surface.

[0039] In some examples, the method also includes: coupling the active surfaces of the tube core to the fan-out carrier, the coupling forming a first space adjacent to the first edge of each active surface of each tube core and a second space adjacent to the second edge of each active surface of each tube core; forming a molding layer, specifically by depositing a mold on the second surface of the tube core and in each first space and each second space to form the molding layer above the fan-out carrier; and polishing the top surface of the molding layer so that at least one of the one or more column bumps on the second surface of each tube core forms an adjacent surface with the polished top surface of the molding layer.

[0040] In some examples, the method further includes: forming a metallization layer by coating metal in a pattern on adjacent surfaces; depositing an electrical short protection passivation layer on the metallization layer; opening the electrical short protection passivation layer at one or more locations to form pads for electrical connection to the metallization layer; peeling off the fan-out carrier to expose an active device surface, the active device surface including the active surface of the die and surfaces of the first space and the second space adjacent to the active surface; and preparing the active device surface to act as a sensor.

[0041] In some examples, the method further includes: attaching one or more caps to a portion of the mold to form a space for a fluid flow channel between the active device surface and the one or more caps; and cutting the resulting structure into substructures, wherein each substructure includes at least one tube core and at least one cap, and wherein each substructure includes a sensor system.

[0042] In some examples, the metallization layer includes a fan-out redistribution layer based on a pattern that distributes additional pillar bumps at locations different than a location of at least one of the one or more pillar bumps on the second surface of each die.

[0043] In some examples, the metallization layer includes an underbump layer based on a pattern that distributes the additional pillar bumps at a location of at least one of the one or more pillar bumps on the second surface of each die.

[0044] In some examples, peeling the fan-out carrier includes: attaching a second carrier to the anti-electrical short passivation layer with an adhesive material; and detaching the fan-out carrier from the active surface of the die using a technique selected from: applying mechanical pressure, heating the fan-out carrier, and applying a solvent.

[0045] In some examples, preparing the active device surface to act as a sensor includes: washing the active device surface; and treating the active device surface using a technique selected from the following: spin coating the active device surface with a chemical solution, applying a chemical solution through sol-gel, spraying the active device surface with a chemical solution, mechanically polishing the active device surface, and baking the active device surface.

[0046] In some examples, the method further includes removing the second carrier from the anti-electrical short passivation layer.

[0047] The disadvantages of the prior art can be overcome, and the benefits as described later in the present disclosure can be achieved by providing a method for manufacturing a device for use in a sensor system. Various examples of the method are described below, and the method (including and excluding the additional examples listed below) overcomes these disadvantages in any combination (provided that these combinations are not inconsistent). The method includes: obtaining a first carrier bonded to the upper surface of a silicon wafer, wherein one or more silicon through vias extend through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below the bottom surface of the silicon wafer, wherein a portion of each of the one or more silicon through vias is exposed through an opening of one or more openings in the passivation stack, wherein one or more electrical contacts are disposed on the one or more openings in the passivation stack; debonding the first carrier from the upper surface of the silicon wafer; and cutting the silicon wafer into sub-portions including a die.

[0048] In some examples, each die includes a portion of an upper surface of a silicon wafer, at least one of one or more through-silicon vias, and at least one of one or more electrical contacts on a second surface of the die, wherein the portion of the upper surface of the silicon wafer includes an active surface, and the second surface of the die is parallel to the active surface.

[0049] In some examples, the method further includes fabricating electrical contacts on the one or more openings, wherein the electrical contacts include stud bumps.

[0050] In some examples, the method further includes: coupling the active surfaces of the tube core to the fan-out carrier, the coupling forming a first space adjacent to the first edge of each active surface of each tube core and a second space adjacent to the second edge of each active surface of each tube core; forming a molding layer, specifically by depositing a mold on the second surface of the tube core and in each first space and each second space to form the molding layer above the fan-out carrier; polishing the top surface of the molding layer so that at least one of the one or more electrical contacts on the second surface of each tube core forms an adjacent surface with the polished top surface of the molding layer; forming a new passivation layer on the adjacent surface to planarize the adjacent surface; forming an opening in the new passivation layer to expose at least one of the one or more electrical contacts on the second surface of each tube core at least one electrical contact; forming a metallization layer by coating metal in a pattern on the new passivation layer; depositing an electrical short-circuit prevention passivation layer on the metallization layer; opening the electrical short-circuit prevention passivation layer at one or more locations to form a pad for electrical connection to the metallization layer; peeling off the fan-out carrier to expose the active device surface, the active device surface including the active surface of the tube core and the surfaces of the first space and the second space adjacent to the active surface; preparing the active device surface to act as a sensor; attaching one or more caps to a portion of the mold to form a space for a fluid flow channel between the active device surface and the one or more caps; and cutting the resulting structure into substructures, wherein each substructure includes at least one tube core and at least one cap, and wherein each substructure includes a sensor system.

[0051] In some examples, the metallization layer includes a fan-out redistribution layer based on a pattern that distributes the additional electrical contacts at a location different from a location of at least one of the one or more electrical contacts on the second surface of each die.

[0052] In some examples, the metallization layer includes an underbump layer based on a pattern that distributes the additional electrical contacts at a location of at least one of the one or more electrical contacts on the second surface of each die.

[0053] In some examples, peeling the fan-out carrier includes: attaching a second carrier to the anti-electrical short passivation layer with an adhesive material; and detaching the fan-out carrier from the active surface of the die using a technique selected from: applying mechanical pressure, heating the fan-out carrier, and applying a solvent.

[0054] In some examples, preparing the active device surface to act as a sensor includes: washing the active device surface; and treating the active device surface using a technique selected from the following: spin coating the active device surface with a chemical solution, applying a chemical solution through sol-gel, spraying the active device surface with a chemical solution, mechanically polishing the active device surface, and baking the active device surface.

[0055] In some examples, the method further includes removing the second carrier from the electrical short preventing passivation layer.

[0056] In some examples, the one or more additional electrical contacts include one or more stud bumps.

[0057] Additional features are achieved through the techniques described herein. Other examples and aspects are described in detail herein and are considered part of the aspects protected by the claims. These and other objects, features and advantages of the present disclosure will become apparent from the following detailed description of the various aspects of the present disclosure in conjunction with the accompanying drawings.

[0058] It should be appreciated that all combinations of the foregoing aspects and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the present subject matter and achieve the advantages disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the end of this specification. The foregoing contents and objects, features and advantages of one or more aspects will be apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0060] Figure 1 An example of a flow cell comprising an active (photosensitive) surface of a silicon wafer is depicted;

[0061] Figure 2 Depicts a workflow that illustrates the process of fabricating a device for use in a sensor system such as Figure 1 The process of the flow cell;

[0062] Figure 3 Depicted through e.g. Figure 2 Example of a wafer structure integrated into a flow cell for workflow;

[0063] Figure 4 Depicted is a stud bump Figure 3 An example of the initial structure of;

[0064] FIG. 5A to FIG. 5B Shown after the first carrier is debonded Figure 4 Different examples of structures;

[0065] Figure 6 yes FIG. 5A to FIG. 5B An example of a die shown physically coupled at its active surface to a fan-out carrier;

[0066] Figure 7 Describes a workflow that precisely describes Figure 2 Examples of some aspects of the workflow include forming fan-out regions;

[0067] Figure 8 A structure is shown in which a molding layer over the die is formed on the surface of the die having stud bumps;

[0068] FIG. 9A to FIG. 9B The mold layer is polished to produce a mold layer with two different heights. Figure 8 An example of a structure;

[0069] Fig.10 Shown by including Figure 2 An example of a structure formed by the method of the method, when compared to the structure of FIG. 9 , the structure includes a metallization layer, a fan-out redistribution layer, and an additional passivation layer;

[0070] Fig.11 Depicts the addition of a passivation layer to prevent electrical short circuits Fig.10 An example of a structure;

[0071] FIG. 12A to FIG. 12C shows a structure discussed herein at various points in the process of removing a fan-out carrier from the structure, the process including utilizing the carrier at the back side of the structure and adding a coating to the active surface of the structure;

[0072] Fig.13 Depicted is a workflow illustrating an example of a process for preparing and implementing a structure described herein as a sensor or detector into a flow cell 100;

[0073] FIG. 14A to FIG. 14B Various examples of attaching a cover to a mold to form a fluid flow channel between an active surface and the cover of a flow cell formed using the methods disclosed herein are shown;

[0074] FIG. 15A to FIG. 15B is a workflow depicting various aspects of a method for manufacturing a sensor system; and

[0075] FIG. 16A to FIG. 16B is a workflow illustrating various aspects of a method for manufacturing a sensor system. DETAILED DESCRIPTION

[0076] The accompanying drawings further illustrate embodiments of the present invention and, together with the detailed description of the embodiments, are used to explain the principles of the embodiments of the present invention, in which like reference numerals refer to the same or functionally similar elements throughout the individual views, and the accompanying drawings are incorporated in and form a part of this specification. As will be appreciated by those skilled in the art, the accompanying drawings are provided to facilitate understanding and illustrate various aspects of certain examples of embodiments of the present invention. The embodiments are not limited to the examples depicted in the accompanying drawings.

[0077] The terms "connected," "connected," "contacted," "coupled," and the like are broadly defined herein to encompass a variety of discrete arrangements and assembly techniques. These arrangements and techniques include, but are not limited to: (1) the direct engagement of one component with another component without intervening components (i.e., the components are in direct physical contact); and (2) the engagement of one component with another component with one or more components in between, provided that the one component is "connected to" or "contacted with" or "coupled to" the other component to some extent in operational communication (e.g., electrical, fluidic, physical, optical communication, etc.) with the other component (although there are one or more additional components in between). It should be understood that some components that are in direct physical contact with each other may or may not be in electrical and / or fluidic contact with each other. In addition, two components that are electrically connected, electrically coupled, optically connected, optically coupled, fluidically connected, or fluidically coupled may or may not be in direct physical contact, and one or more other components may be disposed between the two components.

[0078] As used herein, the terms "including" and "comprising" are synonymous.

[0079] The terms "substantially," "approximately," "about," "relatively," or other such similar terms that may be used throughout this disclosure (including the claims) are used to describe and illustrate small fluctuations from a reference or parameter, for example, due to changes in processing. Such small fluctuations also include zero fluctuations from a reference or parameter. For example, they may refer to less than or equal to ±10%, such as less than or equal to ±5%, such as less than or equal to ±2%, such as less than or equal to ±1%, such as less than or equal to ±0.5%, such as less than or equal to ±0.2%, such as less than or equal to ±0.1%, such as less than or equal to ±0.05%. If used herein, the terms "substantially," "approximately," "about," "relatively," or other such similar terms may also refer to no fluctuations.

[0080] As used herein, "circulation cell" may include a device with a cap extending above the reaction structure to form a flow channel communicating with multiple reaction sites of the reaction structure therebetween, and may include a detection device for detecting a specified reaction occurring at or near the reaction site. The circulation cell may include a solid-state light detection or "imaging" device, such as a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) (light) detection device. As a specific example, the circulation cell may be fluidically coupled and electrically coupled to a box (with an integrated pump), which may be fluidically coupled and / or electrically coupled to a bioassay system. The box and / or the bioassay system may deliver the reaction solution to the reaction site of the circulation cell according to a predetermined scheme (e.g., sequencing while synthesizing), and perform multiple imaging events. For example, the box and / or the bioassay system may guide one or more reaction solutions through the flow channel of the circulation cell, thereby flowing along the reaction site. At least one of the reaction solutions may include four types of nucleotides with the same or different fluorescent labels. In some examples, the nucleotides are bound to the reaction site of the circulation cell, such as the corresponding oligonucleotides bound to the reaction site. The cartridge and / or bioassay system in these examples then illuminates the reaction site using an excitation light source (e.g., a solid-state light source, such as a light emitting diode (LED)). In some examples, the excitation light has one or more predetermined wavelengths, including a range of wavelengths. The fluorescent markers excited by the incident excitation light can provide an emission signal (e.g., light of one or more wavelengths that are different from the excitation light and may be different from each other) that can be detected by the light sensor of the flow cell.

[0081] Flow cell as described herein performs various biological or chemical processes. More specifically, flow cell as described herein can be used for various processes and systems in which it is desired to detect events, attributes, quality or features indicating a specified reaction. For example, flow cell as described herein can include light detection equipment, sensors (including but not limited to biosensors and parts thereof), and bioassay systems operated with sensors (including biosensors), or integrated with the aforementioned equipment.

[0082] The circulation cell promotes multiple specified reactions that can be detected individually or together. The circulation cell performs multiple cycles, wherein the multiple specified reactions occur in parallel. For example, the circulation cell can be used to sequence a dense array of DNA features through iterative cycles of enzyme manipulation and light or image detection / collection. Therefore, the circulation cell can be in fluid communication with one or more microfluidic channels, and the microfluidic channels deliver reagents or other reaction components in the reaction solution to the reaction sites of the circulation cell. The reaction sites can be provided or spaced apart in a predetermined manner, such as provided or spaced apart in a uniform or repeated pattern. Alternatively, the reaction sites can be randomly distributed. Each reaction site can be associated with one or more light guides and one or more light sensors that detect light from the associated reaction site. In one example, the light guide includes one or more filters for filtering light of certain wavelengths. The light guide can be, for example, an absorption filter (e.g., an organic absorption filter) so that the filter material absorbs a specific wavelength (or wavelength range) and allows at least one predetermined wavelength (or wavelength range) to pass therethrough. In some circulation cells, the reaction site can be located in a reaction groove or reaction chamber, which can at least partially separate the specified reactions therein.

[0083] As used herein, a "specified reaction" includes a change in at least one of the chemical, electrical, physical, or optical properties (or mass) of a chemical or biological substance of interest (e.g., an analyte of interest). In a particular flow cell, the specified reaction is a positive binding event, for example, the binding of a fluorescently labeled biomolecule to an analyte of interest. More generally, a specified reaction can be a chemical transformation, a chemical change, or a chemical interaction. A specified reaction can also be a change in an electrical property. In a particular flow cell, a specified reaction includes binding a fluorescently labeled molecule to an analyte. The analyte can be an oligonucleotide, and the fluorescently labeled molecule can be a nucleotide. A specified reaction can be detected when excitation light is directed to an oligonucleotide having a labeled nucleotide and the fluorophore emits a detectable fluorescent signal. In another example of a flow cell, the detected fluorescence is the result of chemiluminescence or bioluminescence. A specified reaction can also be, for example, to increase fluorescence (or ) resonance energy transfer (FRET), reducing FRET by separating the donor and acceptor fluorophores, increasing fluorescence by separating the quencher from the fluorophore, or decreasing fluorescence by colocalizing the quencher and fluorophore.

[0084] As used herein, "electrically coupled" and "optically coupled" refer to the transfer of electrical energy and light waves, respectively, between any combination of power sources, electrodes, conductive portions of substrates, droplets, conductive traces, wires, waveguides, nanostructures, other circuit segments, etc. The terms "electrically coupled" and "optically coupled" may be used in conjunction with direct or indirect connections, and may be through various intermediaries, such as fluid intermediaries, air gaps, etc.

[0085] As used herein, "reaction solution," "reaction component," or "reactant" includes any substance that can be used to obtain at least one specified reaction. For example, possible reaction components include, for example, reagents, enzymes, samples, other biomolecules, and buffers. The reaction components can be delivered to and / or fixed at the reaction sites in the flow cells disclosed herein. The reaction components can interact directly or indirectly with another substance, such as an analyte of interest fixed at the reaction site of the flow cell.

[0086] As used herein, the term "reaction site" is a local area where at least one specified reaction can occur. The reaction site can include a reaction structure or a support surface of a substrate on which a substance can be fixed. For example, the reaction site can include a surface (can be located in a channel of a circulation cell) of a reaction structure with a reactive component (such as a nucleic acid colony thereon). In some circulation cells, the nucleic acid in the colony has the same sequence, for example, a cloned copy of a strand or double-stranded template. However, in some circulation cells, the reaction site can only include a single nucleic acid molecule, such as a strand or double-stranded form.

[0087] The term "fan-out" is used herein to characterize the area packaged with the detector that extends beyond the horizontal distance of the detector. For example, in the example where a CMOS sensor is used as a detector in a flow cell, the fan-out refers to the additional horizontal distance on each side of the horizontal boundary of the CMOS sensor.

[0088] As used herein, the term "pillar bump" is used to describe the electrical contacts in the examples shown and described herein. In various embodiments of the present invention, various examples of electrical contacts may also be used wherever the term "pillar bump" is used. The electrical contact, which may be a pillar bump, may include a conductive material, such as a metallic material (e.g., Cu (copper), Au (gold), W (tungsten), Al (aluminum), or a combination thereof), but it should be understood that other conductive materials may be utilized.

[0089] Reference will now be made to the drawings, which are not drawn to scale for ease of understanding, and in which the same reference numerals are used throughout the different drawings to designate the same or similar components.

[0090] The detection device and image sensor that can be used as a sensor (such as a biosensor) in a circulation pool include an image sensor or detector containing a CMOS and a fan-out area. The surface of the CMOS and the fan-out area (on either side) form an active surface. Generally speaking, in order to realize electrical connection in a CMOS detector, a bump is formed on the front side (active surface) of the CMOS. However, when using CMOS as an image sensor, as in the example discussed herein, the surface (including the fan-out area extending the surface) is an active surface, and its transparency affects its utility. Therefore, the formation of a bump on the surface has an adverse effect on the function. In contrast, the example of the present disclosure describes a process in which a bump is added to the bonding (TSV) pad on the back side of the CMOS image sensor, but the electrical connectivity with the CMOS is maintained because one or more TSVs provide an electrical connection from the active (i.e., photosensitive) surface of the CMOS to the TSV pad (i.e., the back side of the CMOS image sensor) by extending through the bottom substrate, for example, to the redistribution layer (RDL).

[0091] This disclosure describes an example of a process capable of forming a device including a CMOS (used as an image sensor or detector) (which can be used as a sensor, such as a biosensor), wherein one or more TSVs provide electrical connections from the CMOS through a substrate to a layer having bumps. The wafer is used for a wafer-level fan-out process capable of fluidic fan-out and electrical fan-out.

[0092] Because the activities utilizing the resulting device include a flat surface between the die and the surface of the CMOS to accommodate the fan-out wafer, and incorporating at least one TSV to fabricate the TSV, in particular, certain challenges are introduced in the process of fabricating the structure. For example, the silicon wafer is thinned by backside polishing to a thickness in a desired range (e.g., 70-140 μm), which makes it challenging to process the wafer based on this thickness. Forming the structure presents challenges that are addressed by various aspects of the process described herein, including, but not limited to, stripping the carrier glass that holds the TSV while forming the bumps, and thinning the wafer to a thickness within the desired range described above.

[0093] Figure 1 An example of a flow cell 100 formed using the methods described herein is provided. Figure 1As shown in the example of , the flow cell includes an active (photosensitive) surface 110 of a silicon wafer 130 (e.g., CMOS) for light-sensitive activities (e.g., DNA sequencing). A chemical coating 108 has been applied to the active surface 110. A (micro) fluid flow channel 192 is located above the active surface 110 of the silicon wafer 130, wherein the active surface includes the chemical coating 108, and the flow channel 192 is defined by a cover 190 of the flow cell 100 on one side of the flow channel and an adjacent surface on the other side of the flow channel, wherein the adjacent surface includes the active surface 110 of the silicon wafer 130 and portions of the molded fan-out area 180 on either side of the surface of the silicon wafer 130. The (micro) fluid flow channel 192 is also defined by a barrier 147 (also called an insert) on each side. When the silicon wafer 130 is used as a digital image sensor, the active surface 110 of the digital image sensor includes photosites or pixels for sensing light. In these examples, non-limiting examples of sensor functionality include, for example, light sensing (e.g., having a predetermined range of wavelengths sensed), detecting the presence of one or more substances (e.g., biological or chemical substances), and detecting changes in the concentration of something (e.g., ion concentration).

[0094] exist Figure 1 In the flow cell 100, one or more TSVs 120 are formed through the silicon wafer 130 to reach at least a passivation layer 140 on one or more backside metallization layers, and in some examples, the one or more backside metallization layers are metallization layers for RDL. In some examples, the passivation layer 140 is a polyamide layer deposited and cured at a higher temperature (e.g., about 100°C-180°C). Connection with the TSV 120 and thus with the silicon wafer 130 is facilitated by opening the region 150 in the passivation layer 140. These open regions are used to form an electrical connection with the passivation layer 140 to form a pad 160. Electrical contacts, commonly referred to as column bumps 170 or column bumps, are formed on the pad 160. The column bump 170 may include any suitable material, including a conductive material. For example, the column bump 170 may include a conductive material, such as a metal material (e.g., Cu (copper), Au (gold), W (tungsten), Al (aluminum) or a combination thereof), but it should be understood that other conductive materials may be used. In one implementation, the metal (e.g., Cu (copper), Au (gold), W (tungsten), Al (aluminum), or a combination thereof) may be an element, an alloy, or a composite material containing the metal. Note that although the term "copper pillar bump" is used, copper is only used as a demonstration material of the pillar bump, and the pillar bump is not required to consist of or include copper.

[0095] return Figure 1, column bumps 170 are formed on pads 160. These column bumps 170 extend through the molded fan-out area 180. At least one RDL or other passivation layer 182 (e.g., polyamide) is formed on the mold of the fan-out area 180. Openings are formed in the RDL or other passivation layer 182 to provide access to the column bumps 170 (for electrical connection). Another passivation layer 184 (e.g., polyamide, epoxy resin, solder resist, etc.) deposited on the RDL or other passivation layer 182 protects the RDL or other passivation layer 182, increases reliability and prevents electrical shorts. The openings 186 in the other passivation layers 184 enable the pads to be electrically connected to the RDL or other passivation layer 182.

[0096] As described above, a flow cell (such as Figure 1 The flow cell in the RDL includes various manufacturing challenges associated with including TSVs and forming stud bumps on the back side of the silicon wafer. As shown in this article, certain processing activities can alleviate these challenges, including but not limited to: 1) fabricating / depositing stud bumps on the openings in the RDL using electroplating techniques and sputtering techniques; 2) debonding the TSV glass carrier from the surface of the CMOS to clean the (now exposed) surface of the CMOS; 3) placing the resulting (after debonding) thin wafer on an easily peelable carrier or tape and frame; 4) removing the TSVs from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 5) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 6) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 7) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 8) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 9) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 10) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 11) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 12) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 13) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 14) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 15) removing the stud bumps from the glass carrier and placing the stud bumps on the back side of the silicon wafer; 16) removing the stud bumps from the glass carrier and placing the st CMOS die with pillar bumps on RDL pads is placed on fan-out carrier, wafer is diced and fan-out process starts (active surfaces are protected with sacrificial / temporary bonding layer); 5) mold is deposited on fan-out wafer and carrier; 6) mold is cured; 7) wafer on mold side is polished to expose bumps; 8) metallization is performed on wafer forming metallization layer (e.g., second RDL (or fan-out RDL) or under-bump metallization (UBM) layer) according to Cu bump locations (e.g., to redistribute bump locations to external pads); 8) photoresist deposited during electroplating is stripped, thereby retaining RDL and / or UBM layer; 9) depositing a passivation layer on the RDL and / or UBM layer to protect the layer, increase reliability and prevent electrical shorts, and using photolithography technology; 10) applying sensors (e.g., biosensors) to the active surface of the CMOS fan-out wafer (e.g., by spin coating, by sol-gel application and / or spraying on the wafer); 11) forming (micro) fluid flow channels on the CMOS; 12) removing the temporary carrier using laser technology or mechanically (leaving the cap (wafer level or single) on the molded CMOS); and 13) dividing by mechanical means (e.g., sawing (cutting)).

[0097] Figure 2 200 is a flow chart illustrating a method of manufacturing a device for a sensor system such as Figure 1In the illustrative example, the method includes obtaining a first carrier (205) bonded to an upper surface of a silicon wafer (eg, via epoxy, resin and / or adhesive). Figure 3 As an illustrative example of the resulting structure 300, the structure includes a first carrier 312 (eg, a TSV glass carrier) bonded to an upper surface 310 of a silicon wafer 330. Figure 3 As shown, (one or more) TSVs 320 extend through a silicon wafer 330 and a passivation layer 340. The passivation layer 340 may include one or more layers and may also be understood as a passivation stack in some examples, which may include a metallization layer, which may be a redistribution layer (RDL). The passivation layer 340 is disposed below a bottom surface 342 of the silicon wafer 330. A portion of each of the TSVs is exposed through each opening 350 in the passivation layer 340.

[0098] return Figure 2 The method also includes fabricating one or more stud bumps (215) over the openings in the passivation stack. In some examples, the resulting structure includes stud bumps (or other electrical contacts) and the method does not include fabricating the contacts. Figure 4 Yes Figure 3 FIG. 4 is an illustration of an initial structure reinforcement structure 400 having a column bump 470 added to the Figure 2 The various methods for achieving this manufacturing include, but are not limited to, electroplating technology and sputtering technology. Figure 4 , in some examples, the pillar bump 470 is manufactured and / or deposited on the opening 450 using one or more of an electroplating technique and / or a sputtering technique. The passivation layer 440 may be an RDL. The above-mentioned opening 450 in the passivation layer 440, which is an RDL in some examples, is formed using one or more of an electroplating technique and a sputtering technique. From a logistics perspective, the manufacture of the pillar bump 470 is sometimes completed in the same facility where the TSV is manufactured and / or in a facility where the fan-out process is performed, which will be discussed later in this disclosure. The flexibility of the circumstances in which certain processes may be performed is based at least in part on the ease with which the wafer 330, 430 can be transported during the manufacture while the wafer 330, 430 remains bonded to the first carrier 312, 412, which in some examples is a glass carrier. When the wafer 330, 430 remains bonded to the first carrier 312, 412, the structure 300, 400 is more stable than when there is no carrier 312, 412, and therefore can be transported from one location to another to perform Figure 2 Different parts of the method shown.

[0099] See again Figure 2, the method shown also includes debonding the first carrier from the upper surface of the silicon wafer (225). For example, such debonding can be promoted by applying a solvent to the first carrier and the upper surface of the silicon wafer to debond the first carrier from the upper surface of the silicon wafer and clean the upper surface of the silicon wafer. In other examples, debonding is promoted by using mechanical force, ultraviolet waves, heat, etc. The resulting structure can be placed on a second carrier (such as a tape frame), which is selected to be easy to peel off. The second carrier can be a tape, and in some examples, the peeling of the tape is achieved by applying one or more of thermal energy and / or ultraviolet (UV) radiation. As with the case of the now debonded first carrier, if necessary, the second carrier is structurally stable for the structure of transportation. In some examples, the method includes cutting the silicon wafer into sub-portions including tube cores (235). When the method is completed, each tube core can be used as a light detection device. In an example using the second carrier, the second carrier is peeled off from the structure and then forms a fan-out area (245), which is a process described in more detail below.

[0100] Figure 5A An example of die 573a-573c is depicted (this particular number is chosen for illustrative purposes only) at a point in the method after the first carrier is debonded, the second carrier 572 is attached, and the wafer is diced. Figure 5A As shown, each die 573a-573c includes a portion of an upper (active) surface 510 of a silicon wafer 530, which portion of the upper surface of the silicon wafer includes an active surface. In this illustrative example, each die 573a-573c also includes at least two TSVs 520 and at least two stud bumps 570 on a final bottom surface 540 of the die 573a-573c (this surface of the die is parallel to the active surface).

[0101] Figure 5B Also depicted is an example of die 573a-573c at some point in the method after the first carrier is debonded, the second carrier 572 is attached, and the wafer is cut, but instead of attaching the second carrier 572 to the portion of the bottom surface 540 that becomes the die 573a-573c, a (easily releasable) second carrier 572 (e.g., a tape that is releasable using heat and / or UV radiation) is attached to the active surface 510 of the wafer 530.

[0102] In some examples of the method, the silicon wafer is placed on another carrier (the other carrier is coupled to the passivation stack) before the silicon wafer is cut into sub-portions (235). The other carrier is peeled off from the silicon wafer before forming the fan-out region (245).

[0103] return Figure 2As described above, the method also includes forming a fan-out region (245). In an example using an easily peelable carrier (e.g., tape), on any surface of the wafer (e.g., FIG. 5A to FIG. 5B 573a-573c from the second carrier 572. For example, a pick and place tool may be used to pick up the die 573a-573c from the bottom of the second carrier 572 (e.g., tape) and peel the die from the second carrier 572 by positioning a vacuum probe on top of the die 573a-573c. In some examples, utilizing a vacuum probe of a softer material (such as plastic rather than metal) may reduce, and in some cases even minimize, any risk of scratching and / or chipping of the silicon of the wafer 530. In applications such as Figure 5A In the example shown, where the stud bumps 570 are in contact with a second carrier 572 (e.g., tape) on tape, a flip operation can be used with a pick and place tool to place the active surface 510 of the die on another carrier (see, e.g., Figure 6 , 688). Distributing any forces applied during the pick and place process over a larger surface area can mitigate the risk of potential damage to sensitive areas of the silicon wafer 530, including the active surface 510 of the die 573a-573c.

[0104] Figure 7 The fan-out regions (eg, Figure 2 , 245) of the exemplary workflow 700. See Figure 7 To form the fan-out region, the active surface of the die is physically coupled to the fan-out carrier (705). As described above, Figure 6 This coupling is shown because each die 673a-673c is physically coupled to the fan-out carrier 688 at its active surface 610. Each die 673a-673c on the TSVRDL pads 660 (including stud bumps 670, each stud bump connected to TSV 620) is placed on the fan-out carrier 688. Figure 6 In the example shown, a sacrificial or temporary bonding layer 684 is located on top of the fan-out carrier and is in direct contact with the active surfaces 610 of the die 673a-673c, thereby forming a bond between the fan-out carrier 688 and 673a-673c. The sacrificial or temporary bonding layer 684 protects the active surfaces 610 of the die 673a-673c from mechanical and chemical processing steps and debris. This placement leaves spaces 691 between the die 673a-673c such that there is a first space adjacent to a first edge of each active surface 610 of each die 673a-673c and a second space adjacent to a second edge of each active surface 610 of each die 673a-673c.

[0105] return Figure 7 , forming the fan-out region includes forming a molding layer, specifically by depositing a mold on the second surface of the die (the surface with the column bumps) and in each first space and each second space to form the molding layer above the fan-out carrier (715). Figure 8 8 shows a structure in which a molding layer 853 is formed over the die 873a-873c on the surface of the die having the pillar bumps 870. Figure 8 As shown, the height and / or thickness of the mold can be higher than the pillar bump 870. In the example of adopting this height, the increased height of the molding layer 853 above the pillar bump 870 can compensate for the tolerance in the manufacture of the pillar bump 870. The mold can be cured at a temperature of about 100°C-180°C for a time of about 0.5-5 hours to cure the mold until the mold reaches a mechanically stable level. See Fig.9A as well as Figure 7 , the mold layer 953 over the dies 973a-973c is polished until the stud bumps 970 on the second surface of each die 973a-973c and the polished top surface of the mold layer 953 form an abutment surface (725). In some examples, the abutment surface includes planar stud bumps of equal height and thickness.

[0106] return Figure 2 , the method described includes forming a metallization layer by applying a metal in a pattern on the adjacent surface. In some examples, the metallization layer 1013 (e.g. Fig.10 ) is a wire-bondable metal stack of a metal combination, the metal including but not limited to titanium, nickel (Ni), tungsten-titanium (TiW) and / or gold (Au) (e.g., Ti / Au, Ti / Ni / Au, Ni / Au, Ni / TiW / Au, Ti / Ni / TiW / Au, etc.). The thickness of the metallization layer is, for example, about 0.2 μm to about 5 μm. The processes involved in coating the metal on the adjacent surfaces may include: forming a pattern using photolithography; electroplating the pattern; and stripping the photoresist to expose the metallization layer. The electroplating includes, for example, depositing metal (during electroplating) on ​​the photoresist exposed in the opening area. In some examples, when the photoresist is stripped, as described below, an under bump layer (UBM) or RDL remains on the wafer. The process of forming the metallization layer may include a combination of: 1) metal sputtering (covering existing structures without intentionally patterning the metal on the wafer, in contrast to redistributing stud bumps in a pattern at specific locations), for example, using titanium (Ti) as a seed layer; 2) photolithography, which is used to pattern the metallization layer; and 3) electroplating. During the electroplating, metal is deposited on the photoresist opening areas, so when the photoresist is stripped, the RDL or UBM layer remains on the wafer.

[0107] The additional pillar bumps distributed via the metallization determine whether the next layer is an underbump layer (UBM) or an RDL. In various examples of the method, patterning includes distributing additional pillar bumps on the structure (e.g., Fig.9A , 900): at a location different from the location of an existing column bump and / or on an existing column bump (e.g., Fig.9A , 970). Based on the pattern of distributing additional pillar bumps at the existing positions of the pillar bumps on each tube core, the metallization layer is an underbump layer (UBM). Based on the pattern of distributing additional pillar bumps at different positions, the metallization layer is an RDL, which can be understood as a fan-out RDL.

[0108] Fig. 9B yes Fig.9A 900, but with a thicker layer of mold layer 953. This example can be utilized where this thicker layer is desired, and based on the available manufacturing processes, pillar bumps 970 are not manufactured as tall as mold layer 953. For example, dicing tape (the tape on which the wafer rests during dicing) may not be commercially available or may not be cost-effective for pillar bumps above a certain height (e.g., about 100 μm). In this example, as Fig. 9B As shown, the mold layer 953 may be polished and / or buffed to a certain height to obtain mechanical stability of the structure 900. Due to the height difference between the mold layer 953 and the pillar bump 970, a hole 968 is formed in the mold layer 953 to open a path to the pillar bump 970, for example, for electrical contact. The hole may be formed using various techniques, including but not limited to photolithography and etching, and / or using a laser drilling process according to a pattern. When adding the metallization layer 1013 (e.g., Fig.10 ), as described below, a metallization layer 1013 is added to fill the hole 968 with a conductive material (e.g., Cu, Ti, W, Al) comprising the metallization layer 1013. In this example, the metallization both fills the hole 968 to create an electrical connection and also forms a (e.g., patterned) fan-out distribution layer.

[0109] Fig.10 A structure 1000 is depicted, the structure comprising: 1) Fig.9A 1) the above-mentioned metallization layer 1013; and 3) an additional passivation layer 1077. Fig.10In the example shown, the metallization layer 1013 is a fan-out RDL. In addition to adding the metallization layer 1013, the method may also include forming the above-mentioned additional passivation layer 1077 (e.g., polyamide) to produce additional smoothness and planarization on the surface of the mold area 1053, which may be rough after polishing. If the additional passivation layer 1077 is added as part of the manufacturing method, the additional passivation layer is added and then openings 1061 are formed to the pillar bumps 1070 before forming the metallization layer 1013. These openings 1061 can be used to expose the pillar bumps 1070 on the bottom surface 1042 of each tube core 1073a-1073c of the original silicon wafer.

[0110] return Figure 2 In this example, the method includes depositing an anti-electrical short circuit passivation layer (255) on the metallization layer. This aspect may be referred to as metallization distribution. Therefore, in some cases, the passivation layer is referred to as an anti-electrical short circuit layer because it is deposited on the RDL layer (and / or UMP layer) to increase reliability and prevent electrical short circuits. Different materials are used to form this layer, including but not limited to polyamide, epoxy resin and / or solder resist. The layer can be opened at one or more locations using photolithography to form pads for electrical connection to the metallization layer. Fig.11 Depicts the addition of an electrical short-preventing passivation layer 1118 (e.g., polyamide, epoxy, and / or solder resist) Fig.10 Openings 1179 are also formed in this layer to expose the stud bumps 1170 on the bottom surface 1142 of each die 1173a-1173c of the original silicon wafer.

[0111] return Figure 2 and Figure 7 , when forming the fan-out region (245), the active surface of the die is physically coupled to the fan-out carrier (705), and Figure 2 In the example shown, the fan-out carrier is stripped. Thus, the method includes stripping the fan-out carrier (265). Stripping the carrier exposes the active device surface (i.e., the active surface of the die and the surfaces of the first and second spaces adjacent to the active surface). FIG. 12A to FIG. 12B 1 shows the structure at different times during the fan-out carrier removal process discussed herein. Fig. 12A As shown, stripping carrier 1288 may include attaching a second carrier 1204 (e.g., glass, silicon, metal, polyethylene terephthalate, and / or tape) to anti-electrical short passivation layer 1218 with an adhesive material. For example, the height of the second carrier 1204 may be about 0.25 mm to about 1 mm. If tape is used as the second carrier 1204, its height may be about 0.1 mm to about 0.3 mm. A possible reason for applying the second carrier 1204 is to achieve mechanical stability during the removal of the fan-out carrier 1288.

[0112] In some examples, the second carrier 1204 is held to an anti-electrical short passivation layer 1218, for example a temporary adhesive layer 1206, such as a tape (e.g., double-sided) or an adhesive material (e.g., adhesive epoxy). In order to release the fan-out carrier from the active surface of the die, various (layer peeling) techniques may be employed, including but not limited to applying mechanical pressure, heating the fan-out carrier, and / or applying a solvent. Once the carrier 1288 has been peeled off, as Fig. 12B As shown, follow Figure 2 The active surface 1210 is prepared so that it can be used, for example, as a sensor (e.g., a biosensor) (265). Preparing the sensor (265) can involve washing the active surface 1210 and treating the active surface 1210. Various techniques can be used in the preparation, including but not limited to: spin coating the active device surface with a chemical solution, applying a chemical solution through sol-gel, spraying the active device surface with a chemical solution, mechanically polishing the active device surface, and / or baking the active surface 1210. The preparation of the surface produces a chemical coating 108 ( Figure 1 As described above, the second carrier 1204 may be a tape, and thus, before preparing the active surface 1210, the second carrier 1204 may be replaced with a more rigid carrier material (eg, glass, silicon, polyethylene terephthalate (PET), and / or metal). Fig. 12C shows the sensor after it has been prepared. FIG. 12A to FIG. 12B The structure 1200 thus includes a chemical coating 1208 on a portion of the active surface 1210 of each die 1273a-1273c.

[0113] return Figure 2 , the depicted method includes utilizing the resulting structure as a sensor in a flow cell (275). Fig.13 1300, which illustrates converting the resulting structure 1200 (e.g., Fig. 12C ) is prepared and implemented into the flow cell 100 as a sensor or detector (e.g., Figure 1 ) for details of a public example of the process in . Fig.13 , using the resulting structure to include forming fluid flow channels above the active surface (e.g., Figure 1 , 192)(1305). Forming the channel includes, for example, attaching a cover (e.g., a glass cover) to a mold (e.g., Fig. 12C , 1253) to be applied on active surfaces (e.g. Fig. 12C , 1210) and the cover to form a fluid flow channel (1315). Forming a channel (e.g., Figure 1 , 192) also includes a short-circuit protection passivation layer (e.g., Fig. 12C , 1218) remove the second carrier (e.g., Fig. 12C, 1204)(1325) to form a given structure. Forming a channel (e.g., Figure 1 , 192) also includes cutting a given structure into substructures; each substructure includes at least one die and at least one cap (e.g., Figure 1 , 100)(1325). The substructure can be used as a flow cell.

[0114] FIG. 14A to FIG. 14B Attaching the cover to the mold (e.g. Fig. 12C , 1253) to be applied on active surfaces (e.g. Fig. 12C , 1210) and capping (e.g., Fig.13 , 1315) form two examples of fluid flow channels. Fig.14A In the embodiment, the covers 1490a-1490c are attached at the wafer level by forming the barriers 1447a-1447b (e.g., in epoxy or adhesive) (also referred to as inserts) in this example. The (micro)fluid flow channels 1492 are formed between the 1447a-1447b, the covers 1490a-1490c and the active surfaces (e.g., Fig. 12C , 1210). In the depicted example, the barriers 1447a-1447b are adhesives used to bond the caps 1490a-1490c to the structure 1401 (e.g., a wafer package), i.e., the bottom of the flow cell 1400. In some examples, the thickness of the barriers 1447a-1447b is in the range of about 40 μm-120 μm. Fig. 14B 14, each cap 1490a-1490c is picked and placed to be installed on the structure 1401. In this example, the cap is attached to the mold area 1453 of the structure 1401. The attachment can be completed with an adhesive or epoxy, followed by temperature curing.

[0115] See also Fig.13 , a second vector (e.g., FIG. 14A to FIG. 14B , 1404) from a given structure (e.g., FIG. 14A to FIG. 14B , 1400) removed (1335). In this specific implementation, this removal is performed on a structure (e.g., a chip package, a molded CMOS) (e.g., FIG. 14A to FIG. 14B , 1401) leaving a cover (e.g., FIG. 14A to FIG. 14B , 1490a-1490c). Techniques for removing the carrier may include, but are not limited to, laser techniques, mechanical techniques (e.g., applying pressure or peeling off tape or adhesive). Fig.13As shown, (after removing the second carrier) the resulting structure is segmented (1345). Segmentation can be achieved using one or more of the following techniques: cutting the resulting structure or placing the structure on a dicing tape and then cutting the structure. The cutting process may include scribing and breaking, mechanical sawing, and / or laser cutting. The cutting process may be performed in a vertical direction. During segmentation, in some cases, a protective tape is applied to the cover to seal the cover and protect the cover, including preventing water from leaking into the flow channel from the cutting process.

[0116] FIG. 15A to FIG. 15B is a workflow 1500 depicting a method for manufacturing a sensor system, including but not limited to a biosensor system, such as Figure 1 The sensor system is shown. The method includes obtaining a first carrier (1505) bonded to an upper surface of a silicon wafer (eg, via epoxy, resin, and / or adhesive). Figure 3 As an illustrative example of the resulting structure 300, the structure includes a first carrier 312 (eg, a TSV glass carrier) bonded to an upper surface 310 of a silicon wafer 330. Figure 3 As shown, (one or more) TSVs 320 extend through a silicon wafer 330 and a passivation layer 340. The passivation layer 340 may include one or more layers and may also be understood as a passivation stack in some examples, which may include a metallization layer, which may be a redistribution layer (RDL). The passivation layer 340 is disposed below a bottom surface 342 of the silicon wafer 330. A portion of each of the TSVs is exposed through each opening 350 in the passivation layer 340.

[0117] return FIG. 15A to FIG. 15B The method also includes fabricating a pillar bump (as an example of an electrical contact) on the opening in the passivation stack (1515). As described above, Figure 4 Yes Figure 3 FIG. 4 is a diagram of an initial structure of a reinforcement structure 400 having a column bump 470. Figure 4 In some examples, the column bump 470 is manufactured and / or deposited on the opening 450 by using one or more of an electroplating technique and / or a sputtering technique. The passivation layer 440 may be an RDL. The above-mentioned opening 450 in the passivation layer 440, which is an RDL in some examples, is formed using one or more of an electroplating technique and a sputtering technique. The method includes debonding the first carrier from the upper surface of the silicon wafer (1525). For example, such debonding may be facilitated by various layer peeling techniques, including but not limited to applying a solvent to the first carrier and the upper surface of the silicon wafer to debond the first carrier from the upper surface of the silicon wafer and clean the upper surface of the silicon wafer. In other examples, debonding is facilitated by utilizing mechanical force, ultraviolet waves, heat, etc.

[0118] like FIG. 15A to FIG. 15B As shown, the method disclosed in the present invention may include cutting a silicon wafer (in the illustrated example, vertically cutting) into sub-portions including tube cores, so that each tube core includes a portion of the upper surface of the silicon wafer, at least two TSVs of one or more TSVs, and at least two of the one or more column bumps on the second surface of the tube core, the portion of the upper surface of the silicon wafer includes an active surface, and the second surface of the tube core is parallel to the active surface (1535). The method includes coupling the active surface of the tube core to a fan-out carrier, the coupling forming a first space adjacent to the first edge of each active surface of each tube core and a second space adjacent to the second edge of each active surface of each tube core (1545). On the other hand, the method includes forming a molding layer, specifically by depositing a mold on the second surface of the tube core and in each first space and each second space to form the molding layer above the fan-out carrier (1555). Another aspect of this example is polishing the top surface of the molding layer, so that at least two of the one or more column bumps on the second surface of each tube core form an adjacent surface with the polished top surface of the molding layer (1565).

[0119] In this example, there is an aspect of forming a metallization layer by coating a metal in a pattern on an adjacent surface (1575). The method continues with depositing an electrical short protection passivation layer on the metallization layer (1585). Based on a pattern of distributing additional column bumps at locations different from the locations of at least two of the one or more column bumps on the second surface of each tube core, the metallization layer may include, for example, a fan-out redistribution layer. Based on a pattern of distributing additional column bumps at locations of at least two of the one or more column bumps on the second surface of each tube core, the metallization layer may include a bump underlayer.

[0120] return FIG. 15A to FIG. 15B In this example, the method includes opening the anti-electrical short circuit passivation layer at one or more locations to form a pad for electrically connecting to the metallization layer (1586). The method includes peeling off the fan-out carrier to expose the active device surface, which includes the active surface of the tube core and the surfaces of the first space and the second space adjacent to the active surface (1587). To peel off the fan-out carrier, examples of the processes used include: 1) attaching the second carrier to the anti-electrical short circuit passivation layer using an adhesive material; and 2) detaching the fan-out carrier from the active surface of the tube core using various layer peeling techniques, including but not limited to: applying mechanical pressure, heating the fan-out carrier, and applying a solvent.

[0121] return FIG. 15A to FIG. 15BThe method includes preparing an active device surface to act as a sensor (1588). The preparation may involve: washing the active device surface; and treating the active device surface using a technique selected from the group consisting of: spin coating the active device surface with a chemical solution, applying a chemical solution through sol-gel, spraying the active device surface with a chemical solution, mechanically polishing the active device surface, and baking the active device surface.

[0122] The method also includes attaching one or more caps to a portion of the mold to form a space for a fluid flow channel between the active device surface and the one or more caps (1592). To form a sensor system, the method includes cutting the resulting structure into substructures and removing the second carrier from the anti-electrical short passivation layer (1595). Each substructure includes at least one mold and at least one cap; each substructure includes a sensor system.

[0123] FIG. 16A to FIG. 16B Also depicted is a workflow 1600 of a method for manufacturing a sensor system such as Figure 1 The sensor system is shown. The method includes obtaining a first carrier (1605) bonded to an upper surface of a silicon wafer (eg, via epoxy, resin, and / or adhesive). Figure 3 As an illustrative example of the resulting structure 300, the structure includes a first carrier 312 (eg, a TSV glass carrier) bonded to an upper surface 310 of a silicon wafer 330. Figure 3 As shown, (one or more) TSVs 320 extend through a silicon wafer 330 and a passivation layer 340. The passivation layer 340 may include one or more layers and may also be understood as a passivation stack in some examples, which may include a metallization layer, which may be a redistribution layer (RDL). The passivation layer 340 is disposed below a bottom surface 342 of the silicon wafer 330. A portion of each of the TSVs is exposed through each opening 350 in the passivation layer 340.

[0124] return FIG. 16A to FIG. 16B The method also includes fabricating a pillar bump (1615) over the opening in the passivation stack. As described above, Figure 4 Yes Figure 3 FIG. 4 is a diagram of an initial structure of a reinforcement structure 400 having a column bump 470. Figure 4In some examples, the column bump 470 is manufactured and / or deposited on the opening 450 by using one or more of the electroplating technology and / or sputtering technology. The passivation layer 440 can be an RDL. The above-mentioned opening 450 in the passivation layer 440, which is an RDL in some examples, is formed using one or more of the electroplating technology and sputtering technology. The method includes debonding the first carrier from the upper surface of the silicon wafer (1625). For example, such debonding can be promoted by applying a solvent to the first carrier and the upper surface of the silicon wafer to debond the first carrier from the upper surface of the silicon wafer and clean the upper surface of the silicon wafer. In other examples, debonding is promoted by using mechanical force, ultraviolet waves, heat, etc.

[0125] like FIG. 16A to FIG. 16B As shown, the method disclosed in the present invention may include cutting a silicon wafer into sub-portions including tube cores, so that each tube core includes a portion of the upper surface of the silicon wafer, at least two of the one or more silicon through-holes, and at least two of the one or more column bumps on the second surface of the tube core, the portion of the upper surface of the silicon wafer includes an active surface, and the second surface of the tube core is parallel to the active surface (1635). The method includes coupling the active surface of the tube core to a fan-out carrier, and the coupling forms a first space adjacent to the first edge of each active surface of each tube core and a second space adjacent to the second edge of each active surface of each tube core (1645). On the other hand, the method includes forming a molding layer, specifically by depositing a mold on the second surface of the tube core and in each first space and each second space to form the molding layer above the fan-out carrier (1655). On the other hand, the top surface of the molding layer is polished, so that at least two of the one or more column bumps on the second surface of each tube core form an adjacent surface with the polished top surface of the molding layer (1665).

[0126] and FIG. 15A to FIG. 15B In contrast, the method further includes forming a new passivation layer on the adjacent surface to planarize the adjacent surface (1666). The method includes forming openings in the new passivation layer to expose at least two of the one or more stud bumps on the second surface of each die (1667).

[0127] In this example, there is an aspect of forming a metallization layer by coating a metal on a new passivation layer (1675). The method continues with depositing an electrical short protection passivation layer on the metallization layer (1685). Based on a pattern of distributing additional column bumps at locations different from the locations of at least two of the one or more column bumps on the second surface of each tube core, the metallization layer may include, for example, a fan-out redistribution layer. Based on a pattern of distributing additional column bumps at locations of at least two of the one or more column bumps on the second surface of each tube core, the metallization layer may include a bump underlayer.

[0128] return FIG. 16A to FIG. 16B In this example, the method includes opening the anti-electrical short circuit passivation layer at one or more locations to form a pad for electrically connecting to the metallization layer (1686). The method includes peeling off the fan-out carrier to expose the active device surface, which includes the active surface of the tube core and the surfaces of the first space and the second space adjacent to the active surface (1687). To peel off the fan-out carrier, examples of the processes used include: 1) attaching the second carrier to the anti-electrical short circuit passivation layer using an adhesive material; and 2) detaching the fan-out carrier from the active surface of the tube core using a technique selected from the following: applying mechanical pressure, heating the fan-out carrier, and applying a solvent.

[0129] return FIG. 16A to FIG. 16B The method includes preparing an active device surface to act as a sensor (1688). The preparation may involve: washing the active device surface; and treating the active device surface using a technique selected from the group consisting of: spin coating the active device surface with a chemical solution, applying a chemical solution through sol-gel, spraying the active device surface with a chemical solution, mechanically polishing the active device surface, and baking the active device surface.

[0130] The method also includes attaching one or more caps to a portion of the mold to form a space for a fluid flow channel between the active device surface and the one or more caps (1692). To form a sensor system, the method includes cutting the resulting structure into substructures and removing the second carrier from the anti-electrical short passivation layer (1695). Each substructure includes at least one tube core and at least one cap, and each substructure includes a sensor system (1695).

[0131] The flow chart and block diagram in the accompanying drawings show the possible specific implementation architecture, function and operation of the system, method and computer program product of various examples specifically implemented according to the present invention.In this regard, each box in the flow chart or block diagram can represent a module, fragment or part of an instruction, including one or more executable instructions for implementing a specified logical function.In some alternative specific implementations, the function noted in the box may not occur in the order noted in the figure.For example, the two boxes shown in succession can actually be executed substantially at the same time, or these boxes can sometimes be executed in the opposite order, depending on the functions involved.It should also be noted that each box in the block diagram and / or the flow chart diagram and the combination of the boxes in the block diagram and / or the flow chart diagram can be implemented by a system based on dedicated hardware that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0132] The terms used herein are for the purpose of describing specific examples only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0133] The corresponding structures, materials, acts, and equivalents of all means or steps plus functional elements in the following claims, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements specifically claimed. The description of one or more examples has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The examples are selected and described in order to best explain the various aspects and practical applications, and to enable others of ordinary skill in the art to understand the various examples with various modifications suitable for the particular use contemplated.

[0134] It should be understood that all combinations of the foregoing concepts and the additional concepts discussed in more detail below (assuming such concepts are not mutually inconsistent) are contemplated as being part of the subject matter disclosed herein to achieve at least the benefits as described herein. Specifically, all combinations of the claimed subject matter appearing at the end of this disclosure are contemplated as being part of the subject matter disclosed herein. It should also be understood that terms explicitly adopted herein that may also appear in any disclosure incorporated by reference should be given the meaning most consistent with the specific concepts disclosed herein.

[0135] This written description uses examples to disclose the subject matter and also to enable any person skilled in the art to practice the subject matter, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the subject matter is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

[0136] It should be understood that the above description is intended to be illustrative and not restrictive. For example, the above examples (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of various examples, many modifications can be made to adapt specific situations or materials to the teachings of various examples. Although the size and type of materials described herein are intended to define the parameters of various examples, they are by no means restrictive and are provided only by way of example. When viewing the above description, many other examples will be apparent to those skilled in the art. Therefore, the scope of various examples should be determined with reference to the full scope of the appended claims and the equivalents granted by these claims. In the appended claims, the terms "including" and "wherein" are used as the plain English equivalents of the corresponding terms "including" and "wherein". In addition, in the following claims, the terms "first", "second" and "third" etc. are used only as labels and are not intended to impose numerical requirements on their objects. The form of the term "based on" herein covers the relationship in which the element is partially based on and the relationship in which the element is completely based on. The form of the term "defined" covers the relationship in which the element is partially defined and the relationship in which the element is completely defined. Furthermore, the following claim limitations are not written in a means-plus-function format and are not intended to be interpreted based on 35 U.S.C. §112, sixth paragraph, unless and until such claim limitations expressly use the phrase "means for..." followed by a functional recitation without additional structure. It is to be understood that not all such objects or advantages described above may necessarily be achieved according to any particular example. Thus, for example, one skilled in the art will recognize that the systems and techniques described herein may be implemented or performed in a manner that achieves or optimizes one advantage or group of advantages taught herein without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0137] Although only a limited number of examples are described in detail, it should be readily understood that the subject matter is not limited to such disclosed examples. On the contrary, the subject matter may be modified to combine any number of variations, changes, substitutions or equivalent arrangements that have not been described before but are comparable to the essence and scope of the subject matter. In addition, although various examples of the subject matter have been described, it should be understood that the various aspects of the present disclosure may include only some of the examples. In addition, although some examples are described as having a certain number of elements, it should be understood that the subject matter can be practiced with less than or greater than a certain number of elements. Therefore, the subject matter should not be considered to be limited by the foregoing description, but only by the scope of the appended claims.

Claims

1. A method for manufacturing a device for use in a sensor system, comprising: obtaining a first carrier bonded to an upper surface of a silicon wafer, wherein one or more through silicon vias extend through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below a bottom surface of the silicon wafer, wherein a portion of each of the one or more through silicon vias is exposed through an opening of one or more openings in the passivation stack, wherein each exposed portion is coupled to one or more electrical contacts; debonding the first carrier from the upper surface of the silicon wafer; as well as cutting the silicon wafer into sub-portions including dies such that each die includes a portion of the upper surface of the silicon wafer, at least one of the one or more through-silicon vias, at least one of the one or more electrical contacts on a second surface of the die, the portion of the upper surface of the silicon wafer including an active surface, the second surface of the die being parallel to the active surface, The method further comprises: A fan-out region is formed, the forming comprising: coupling the active surfaces of the dies to a fan-out carrier, the coupling forming a first space adjacent to a first edge of each active surface of each die and a second space adjacent to a second edge of each active surface of each die; forming a molding layer, in particular by depositing a mold on the second surface of the die and in each first space and each second space to form the molding layer over the fan-out carrier; and The top surface of the molding layer is polished so that the at least one of the one or more electrical contacts on the second surface of each die forms an abutting surface with the polished top surface of the molding layer. 2 . The method of claim 1 , wherein the abutment surfaces comprise planar electrical contacts of equal height and thickness.

3. The method according to claim 1, further comprising: The metallization layer is formed by applying metal in a pattern onto the adjoining surfaces.

4. The method of claim 3, wherein the metallization layer comprises a fan-out redistribution layer based on the pattern of distributing additional electrical contacts at locations different from the location of the at least one of the one or more electrical contacts on the second surface of each die.

5. The method of claim 3, wherein the metallization layer comprises an under bump layer based on the pattern of distributing additional electrical contacts at the location of the at least one of the one or more electrical contacts on the second surface of each die.

6. The method of claim 3, wherein coating the metal on the abutting surface comprises: Using photolithography technology to form the pattern; electroplating the pattern, wherein the electroplating comprises depositing over the one or more openings, wherein the one or more openings comprise photoresist; and The photoresist is stripped to expose the metallization layer.

7. The method according to claim 1, further comprising: forming a new passivation layer on the adjoining surface to planarize the adjoining surface; forming an opening in the new passivation layer to expose the at least one electrical contact of the one or more electrical contacts on the second surface of each die; as well as A metallization layer is formed by coating metal in a pattern on the new passivation layer.

8. The method according to claim 3, further comprising: Depositing an electrical short circuit protection passivation layer on the metallization layer; as well as The electrical short prevention passivation layer is opened at one or more locations by photolithography to form pads for electrical connection to the metallization layer.

9. The method of claim 8, further comprising stripping the fan-out carrier to expose an active device surface, the active device surface comprising the active surface of the die and surfaces of the first space and the second space adjacent to the active surface, the stripping comprising: attaching a second carrier to the anti-electrical short passivation layer with an adhesive material; as well as The fan-out carrier is released from the active surface of the die using a technique selected from the group consisting of applying mechanical pressure, heating the fan-out carrier, and applying a solvent.

10. The method of claim 9, wherein the second carrier is composed of a material selected from the group consisting of glass, silicon, metal, polyethylene terephthalate, and tape.

11. The method according to claim 9, further comprising: The active device surface is prepared to act as a sensor.

12. The method according to claim 11, wherein the preparing comprises: washing the surface of the active device; as well as The active device surface is processed using a technique selected from the following: spin coating the active device surface with a chemical solution, applying the chemical solution through sol-gel, spraying the active device surface with the chemical solution, mechanically polishing the active device surface, and baking the active device surface.

13. The method according to claim 11, further comprising: Forming a fluid flow channel above the active device surface, comprising: attaching one or more caps to a portion of the mold to form the fluid flow channel between the active device surface and the one or more caps; and The second carrier is removed from the electrical short prevention passivation layer to form a resulting structure.

14. The method according to claim 13, further comprising: The resulting structure is cut into substructures, wherein each substructure includes at least one die and at least one cap.

15. The method of claim 1, wherein the passivation stack comprises a metallization layer. The method of claim 15 , wherein the metallization layer comprises a redistribution layer.

17. The method of claim 1, wherein said obtaining comprises fabricating said one or more electrical contacts over said one or more openings in said passivation stack.

18. The method of claim 17, wherein the manufacturing is accomplished using a technique selected from the group consisting of: an electroplating technique and a sputtering technique.

19. The method of any one of claims 1 to 18, wherein the first carrier comprises a glass carrier, and wherein the carrier is bonded to the active surface of the silicon wafer by a bonding agent selected from the group consisting of: epoxy, resin, and adhesive.

20. The method of any one of claims 1 to 18, wherein the silicon wafer comprises a complementary metal oxide semiconductor.

21. The method according to any one of claims 1 to 18, further comprising: prior to dicing the silicon wafer into sub-portions, placing the silicon wafer on a second carrier such that the second carrier is coupled to the passivation stack; Before forming the fan-out region, the second carrier is peeled off from the silicon wafer.

22. The method of claim 21, wherein the second carrier comprises an adhesive tape, and wherein the stripping comprises applying an element selected from the group consisting of: thermal energy and ultraviolet radiation.

23. The method of any one of claims 1 to 14, wherein coupling the active surface of the die to the fan-out carrier comprises forming a temporary adhesive layer between the active surface and the fan-out carrier, wherein the temporary adhesive layer protects the active surface during the formation of the fan-out region.

24. The method of any one of claims 1 to 14, wherein the molding layer is deposited to a height greater than a height of the at least one electrical contact on the second surface of each die.

25. A method according to any one of claims 1 to 18, wherein each die comprises a light detection device.

26. The method of any one of claims 1 to 14, wherein forming the molding layer further comprises curing the mold to obtain mechanical stability.

27. The method of claim 26, wherein the curing is performed at a temperature of about one hundred degrees Celsius to about one hundred and eighty degrees Celsius.

28. The method of claim 26, wherein the curing lasts from about thirty minutes to about three hundred minutes.

29. The method of claim 8, wherein the anti-electrical short passivation layer comprises a material selected from the group consisting of polyamide, epoxy resin, and solder resist.

30. The method of any one of claims 1 to 18, wherein the one or more electrical contacts comprise one or more stud bumps.

31. A method for manufacturing a device for use in a sensor system, comprising: obtaining a first carrier bonded to an upper surface of a silicon wafer, wherein one or more through silicon vias extend through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below a bottom surface of the silicon wafer, wherein a portion of each of the one or more through silicon vias is exposed through an opening of one or more openings in the passivation stack; fabricating one or more stud bumps over the openings in the passivation stack; debonding the first carrier from the upper surface of the silicon wafer; as well as cutting the silicon wafer into sub-portions including dies, wherein each of the dies comprises a portion of the upper surface of the silicon wafer, at least one of the one or more through-silicon vias, and at least one of the one or more stud bumps on a second surface of the die, the portion of the upper surface of the silicon wafer comprising an active surface, the second surface of the die being parallel to the active surface, The method further comprises: coupling the active surfaces of the dies to a fan-out carrier, the coupling forming a first space adjacent to a first edge of each active surface of each die and a second space adjacent to a second edge of each active surface of each die; forming a molding layer, in particular by depositing a mold on the second surface of the die and in each first space and each second space to form the molding layer over the fan-out carrier; and The top surface of the molding layer is polished so that the at least one of the one or more stud bumps on the second surface of each die forms an abutting surface with the polished top surface of the molding layer.

32. The method of claim 31 further comprising: forming a metallization layer by coating metal in a pattern on the adjoining surfaces; Depositing an electrical short circuit protection passivation layer on the metallization layer; opening the electrical short prevention passivation layer at one or more locations to form pads for electrical connection to the metallization layer; peeling off the fan-out carrier to expose an active device surface, the active device surface comprising the active surface of the die and surfaces of the first space and the second space adjacent to the active surface; as well as The active device surface is prepared to act as a sensor.

33. The method of claim 32, further comprising: attaching one or more caps to a portion of the mold to form a space for a fluid flow channel between the active device surface and the one or more caps; as well as The resulting structure is cut into substructures, wherein each substructure comprises at least one die and at least one cap, and wherein each substructure comprises the sensor system.

34. The method of claim 32, wherein the metallization layer comprises a fan-out redistribution layer based on the pattern of distributing additional pillar bumps at locations different than the location of the at least one of the one or more pillar bumps on the second surface of each die.

35. The method of claim 32, wherein the metallization layer comprises an underbump layer based on the pattern of distributing additional stud bumps at a location of the at least one of the one or more stud bumps on the second surface of each die.

36. The method of claim 32, wherein peeling off the fan-out carrier comprises: attaching a second carrier to the anti-electrical short passivation layer with an adhesive material; as well as The fan-out carrier is released from the active surface of the die using a technique selected from the group consisting of applying mechanical pressure, heating the fan-out carrier, and applying a solvent.

37. The method of claim 32, wherein preparing the active device surface to function as a sensor comprises: washing the surface of the active device; as well as The active device surface is processed using a technique selected from the following: spin coating the active device surface with a chemical solution, applying the chemical solution through sol-gel, spraying the active device surface with the chemical solution, mechanically polishing the active device surface, and baking the active device surface.

38. The method of claim 36, further comprising: The second carrier is removed from the passivation layer preventing electrical short circuits.

39. A method for manufacturing a device for use in a sensor system, comprising: obtaining a first carrier bonded to an upper surface of a silicon wafer, wherein one or more through silicon vias extend through the silicon wafer and a passivation stack, wherein the passivation stack is disposed below a bottom surface of the silicon wafer, wherein a portion of each of the one or more through silicon vias is exposed through an opening of one or more openings in the passivation stack, wherein one or more electrical contacts are disposed over the one or more openings in the passivation stack; debonding the first carrier from the upper surface of the silicon wafer; as well as cutting the silicon wafer into sub-portions including dies, wherein each die comprises a portion of the upper surface of the silicon wafer, at least one of the one or more through-silicon vias, and at least one of the one or more electrical contacts on a second surface of the die, the portion of the upper surface of the silicon wafer comprising an active surface, the second surface of the die being parallel to the active surface, The method further comprises: coupling the active surfaces of the dies to a fan-out carrier, the coupling forming a first space adjacent to a first edge of each active surface of each die and a second space adjacent to a second edge of each active surface of each die; forming a molding layer, specifically by depositing a mold on the second surface of the die and in each first space and each second space to form the molding layer over the fan-out carrier; The top surface of the molding layer is polished so that the at least one of the one or more electrical contacts on the second surface of each die forms an abutting surface with the polished top surface of the molding layer.

40. The method of claim 39, wherein the obtaining comprises fabricating the electrical contacts over the one or more openings, wherein the electrical contacts comprise stud bumps.

41. The method of claim 39, further comprising: forming a new passivation layer on the adjoining surface to planarize the adjoining surface; forming an opening in the new passivation layer to expose the at least one electrical contact of the one or more electrical contacts on the second surface of each die; forming a metallization layer by coating metal in a pattern on the new passivation layer; Depositing an electrical short circuit protection passivation layer on the metallization layer; opening the electrical short prevention passivation layer at one or more locations to form pads for electrical connection to the metallization layer; peeling off the fan-out carrier to expose an active device surface, the active device surface comprising the active surface of the die and surfaces of the first space and the second space adjacent to the active surface; preparing the active device surface to act as a sensor; attaching one or more caps to a portion of the mold to form a space for a fluid flow channel between the active device surface and the one or more caps; as well as The resulting structure is cut into substructures, wherein each substructure comprises at least one die and at least one cap, and wherein each substructure comprises the sensor system.

42. The method of claim 41, wherein the metallization layer comprises a fan-out redistribution layer based on the pattern of distributing additional electrical contacts at locations different than the location of at least one of the one or more electrical contacts on the second surface of each die.

43. The method of claim 41, wherein the metallization layer comprises an under bump layer based on the pattern of distributing additional electrical contacts at the location of the at least one of the one or more electrical contacts on the second surface of each die.

44. The method of claim 41 , wherein peeling off the fan-out carrier comprises: attaching a second carrier to the anti-electrical short passivation layer with an adhesive material; as well as The fan-out carrier is released from the active surface of the die using a technique selected from the group consisting of applying mechanical pressure, heating the fan-out carrier, and applying a solvent.

45. The method of claim 41, wherein preparing the active device surface to function as a sensor comprises: washing the surface of the active device; as well as The active device surface is processed using a technique selected from the following: spin coating the active device surface with a chemical solution, applying the chemical solution through sol-gel, spraying the active device surface with the chemical solution, mechanically polishing the active device surface, and baking the active device surface.

46. ​​The method of claim 44, further comprising: The second carrier is removed from the passivation layer preventing electrical short circuits.

47. The method of claim 42, wherein the additional electrical contacts comprise stud bumps.

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