Solar cell preparation method

Abstract

The present invention relates to a method for manufacturing a solar cell. The method includes: a polysilicon layer formation step of forming a polysilicon layer containing a first dopant on a rear surface of a semiconductor substrate including a base region and formed of single-crystalline silicon material; a front surface texturing step of texturing a front surface of the semiconductor substrate and also removing the polysilicon layer formed on the front surface; a second conductive region formation step of forming a second conductive region by diffusing a second dopant on the front surface of the semiconductor substrate; a passivation film formation step of forming a first passivation film on the polysilicon layer formed on the rear surface of the semiconductor substrate and forming a second passivation film on the second conductive region on the front surface of the semiconductor substrate; and an electrode formation step of forming a first electrode that passes through the first passivation film and is connected to the polysilicon layer and forming a second electrode that passes through the second passivation film on the second conductive region.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a solar cell, and more particularly, to a method for manufacturing a solar cell that can simplify the manufacturing process of the solar cell by isolating a first conductive region and a second conductive region during texturing of the front surface of a semiconductor substrate during the manufacturing process of the solar cell. Background Art

[0002] A solar cell includes an n-type conductive region and a p-type conductive region, and can generate electric power as carriers suitable for each conductive type move toward the n-type conductive region and the p-type conductive region.

[0003] Therefore, when the n-type conductive region and the p-type conductive region are short-circuited, the power generation efficiency of the solar cell is significantly reduced. Therefore, it is necessary to isolate the n-type conductive region and the p-type conductive region from each other.

[0004] As a method for forming isolation, a method of removing the side surface of a semiconductor substrate for a solar cell using reactive ion etching (RIE) is known, and reactive ion etching (RIE) uses sulfur hexafluoride (SF6) gas, chlorine (Cl2) gas, or oxygen (O2) gas.

[0005] However, in the case of forming isolation using RIE, sulfur hexafluoride (SF6) gas, chlorine (Cl2) gas, oxygen (O2) gas, etc. remain on the surface of the semiconductor substrate. Sulfur hexafluoride (SF6), chlorine (Cl2), oxygen (O2) gas, etc. remaining on the surface of the semiconductor substrate during the transfer process of the semiconductor substrate contaminate the outer wall of the semiconductor equipment, resulting in an operation error of the semiconductor equipment. In order to prevent the above problems, a separate additional auxiliary device should be installed in the semiconductor device, thereby increasing the manufacturing cost of the solar cell.

[0006] In addition, in the case of forming isolation using RIE, isolation is formed on each semiconductor substrate in a state where a plurality of semiconductor substrates are arranged in a tray, and here, as much isolation as desired is not formed on the semiconductor substrates arranged on the outer side portion of the tray among the plurality of semiconductor substrates arranged in the tray, thereby increasing the defect rate and cost of the solar cell. Summary of the Invention

[0007] Technical Problem

[0008] The present disclosure provides a method for manufacturing a solar cell, which can minimize the influence on solar cell manufacturing equipment and more stably and naturally achieve an isolation structure.

[0009] Technical Solution

[0010] A method for manufacturing a solar cell forming an isolation structure of a solar cell according to a first embodiment of the present disclosure includes: a polysilicon layer forming operation of forming a polysilicon layer containing a first dopant on a back surface of a semiconductor substrate formed of a single crystal silicon material including a base region; a front surface texturing operation of removing the polysilicon layer formed on the front surface of the semiconductor substrate and texturing the front surface of the semiconductor substrate; a second conductive region forming operation of diffusing a second dopant on the front surface of the semiconductor substrate to form a second conductive region; a passivation layer forming operation of forming a first passivation layer on the polysilicon layer formed on the back surface of the semiconductor substrate and forming a second passivation layer on the second conductive region on the front surface of the semiconductor substrate; and an electrode forming operation of forming a first electrode passing through the first passivation layer and connecting to the polysilicon layer and forming a second electrode passing through the second passivation layer in the second conductive region.

[0011] The second conductive region forming operation may include: a dopant layer forming operation of forming a dopant layer having a second dopant on the front surface of the semiconductor substrate; and a heat treatment operation of heat treating the semiconductor substrate to diffuse the second dopant of the dopant layer to the front surface of the semiconductor substrate.

[0012] The front surface texturing operation may be selectively performed on the front surface of the semiconductor substrate.

[0013] The method may further include performing saw damage etching (SDE) on the semiconductor substrate before forming the polysilicon layer.

[0014] The method may further include forming a control passivation layer on the entire surface of the semiconductor substrate before forming the polysilicon layer.

[0015] In the front surface texturing operation, the control passivation layer and the polysilicon layer formed on the front surface of the semiconductor substrate may be removed simultaneously.

[0016] In the polysilicon layer forming operation, the polysilicon layer may be formed on the back surface of the semiconductor substrate, on the side surface of the semiconductor substrate, and at an edge portion of the front surface of the semiconductor substrate.

[0017] The front surface texturing operation may be performed by wet etching.

[0018] In an example, in the wet etching, in a state where the front surface of the semiconductor substrate is in contact with a roller partially immersed in a texturing etching solution, when the roller rotates, the texturing etching solution present on the surface of the roller may etch the front surface of the semiconductor substrate to form textured recesses and protrusions on the front surface of the semiconductor substrate.

[0019] Here, the texturing etching solution may include potassium hydroxide (KOH) and base deionized water (DI-water).

[0020] The dopant layer formation operation may include forming a dopant layer at the edge portions of the front surface, side surfaces, and back surface of a semiconductor substrate, forming undoped silicate glass (USG) on the dopant layer, and removing the undoped silicate glass and the dopant layer formed at the edge portions of the side surfaces and the back surface of the semiconductor substrate.

[0021] In the heat treatment operation, the first dopant may be activated to form a polysilicon layer as a first conductive region, and the second dopant may diffuse and be activated on the front surface of the semiconductor substrate to form a second conductive region on the front surface of the semiconductor substrate.

[0022] The method may further include a cleaning operation of removing the dopant layer after the heat treatment operation.

[0023] In addition, the method may further include: a mask formation operation that forms a mask layer for preventing texturing etching on the polysilicon layer on the back surface of the semiconductor substrate between the polysilicon layer formation operation and the front surface texturing operation.

[0024] The mask formation operation may include: forming a mask layer on the entire surface of the polysilicon layer and on the entire front surface of the semiconductor substrate; and removing portions of the mask layer other than the portion formed on the polysilicon layer located on the back surface of the semiconductor substrate.

[0025] In a state where the mask layer is formed on the polysilicon layer located on the back surface of the semiconductor substrate, a front surface texturing operation may be performed on the front surface of the semiconductor substrate, and the mask layer may be removed after the front surface texturing operation is completed.

[0026] The front surface texturing operation may be performed in a state where the mask layer is formed on the back surface of the semiconductor substrate, and in a state where the front surface of the semiconductor substrate having the mask layer formed thereon is in contact with a roller partially immersed in a texturing etching solution, when the roller rotates, the texturing etching solution present on the roller may etch the front surface of the semiconductor substrate to form textured recesses and protrusions on the front surface of the semiconductor substrate, or the semiconductor substrate having the mask layer may be immersed in the texturing etching solution filled in a tank to form textured recesses and protrusions on the front surface of the semiconductor substrate.

[0027] A method for manufacturing a solar cell that forms an isolation structure of a solar cell according to a second embodiment of the present disclosure includes: a first conductive region forming operation that forms a first conductive region formed of a polysilicon layer doped with a first conductive type dopant on one surface of a semiconductor substrate including a base region; a second conductive region forming operation that forms a second conductive region doped with a second conductive type dopant opposite to the first conductive region on the other surface of the semiconductor substrate; a coating operation that applies an etching paste to a portion adjacent to an edge of one surface or the other surface of the semiconductor substrate between or after the first conductive region forming operation and the second conductive region forming operation; and an etching operation that etches a portion of the semiconductor substrate adjacent to the edge with the etching paste to form an isolation line.

[0028] The first conductive region forming operation may include a polysilicon layer deposition operation that deposits a polysilicon layer on one surface of the semiconductor substrate, the second conductive region forming operation may include a dopant layer forming operation that forms a dopant layer containing a second conductive type dopant on the other surface of the semiconductor substrate, and each of the first conductive region forming operation and the second conductive region forming operation includes a heat treatment operation that heat-treats the semiconductor substrate after the polysilicon layer deposition operation and the dopant layer forming operation and before the coating operation.

[0029] The method may further include, before the first conductive region forming operation and the second conductive region forming operation: a texturing operation that textures one surface of the semiconductor substrate and the other surface of the semiconductor substrate to form recesses and protrusions; and a control passivation layer deposition operation that forms a control passivation layer on one surface of the semiconductor substrate, where the polysilicon layer is deposited on the control passivation layer.

[0030] In this case, after the heat treatment operation, the coating operation and the etching operation may be performed after the first conductive region forming operation and the second conductive region forming operation, and the etching paste is applied to be spaced apart from the edge of the first conductive region located on one surface of the semiconductor substrate or is applied to be spaced apart from the edge of the second conductive region located on the other surface of the semiconductor substrate.

[0031] The etching paste may be applied at a distance of 2 mm or less from the edge of the first conductive region or the second conductive region, the aspect ratio of the etching paste may be 0.1 to 1, the thickness of the etching paste may be 2 μm to 500 μm, and the line width of the etching paste may be 20 μm to 500 μm.

[0032] The etch paste may include polymer particles and an etch material, and the polymer particles may include at least one of polystyrene, polyacrylate, polyamide, polyimide, polymethacrylate, melamine, polyurethane, benzoguanamine, phenolic resin, silicone resin, fluorinated polymer, and micronized wax, and the etch material may include at least one of ammonium bifluoride (NH4HF2) and phosphoric acid (H3PO4).

[0033] The depth of the isolation line etched by the etching operation may be from 2 μm to 5 μm, and the line width of the isolation line may be from 20 μm to 500 μm.

[0034] Therefore, in the etching operation, a part of the first conductive region or the second conductive region may be etched to expose the base region of the semiconductor substrate.

[0035] In addition, the method may further include: a cleaning operation that removes the etch paste after the etching operation; a passivation layer deposition operation that deposits a first passivation layer on the first conductive region and a second passivation layer on the second conductive region after the cleaning operation; and an electrode formation operation that forms a first electrode connecting to the first conductive region through the first passivation layer and a second electrode connecting to the second conductive region through the second passivation layer.

[0036] Therefore, in the passivation layer deposition operation, the base region of the semiconductor substrate exposed in the etching operation may be covered by the first passivation layer or the second passivation layer.

[0037] In addition, a dopant layer formation operation may be performed between the polysilicon layer deposition operation and the heat treatment operation, and an etching operation and a coating operation included in the isolation operation may be performed on one surface and the other surface of the semiconductor substrate between the dopant layer formation operation and the heat treatment operation.

[0038] A dopant layer formation operation may be performed between the polysilicon layer deposition operation and the heat treatment operation, and an etching operation and a coating operation included in the isolation operation may be performed on one surface of the semiconductor substrate between the polysilicon layer deposition operation and the dopant layer formation operation.

[0039] A solar cell according to an embodiment of the present disclosure may include: a semiconductor substrate having a base region; a first conductive region located on one surface of the semiconductor substrate and formed of a polysilicon layer doped with a first conductive type dopant; a second conductive region located on the other surface of the semiconductor substrate and doped with a second conductive type dopant opposite to the first conductive region; a first electrode connected to the first conductive region; and a second electrode connected to the second conductive region, wherein an isolation line formed by removing a part of the first conductive region or a part of the second conductive region is provided in the form of a line spaced apart from the first electrode or the second electrode and parallel to the edge of one surface or the other surface of the semiconductor substrate.

[0040] In addition, the solar cell may further include a first passivation layer on the first conductive region and a second passivation layer on the second conductive region.

[0041] When the isolation line is located on one surface of the semiconductor substrate, the first passivation layer may pass through the first conductive region at the portion where the isolation line is located and contact the base region of the semiconductor substrate, and when the isolation line is located on the other surface of the semiconductor substrate, the second passivation layer may pass through the second conductive region at the portion where the isolation line is located and contact the base region of the semiconductor substrate.

[0042] The control passivation layer may also be located between the semiconductor substrate and the first conductive region.

[0043] The isolation line may be located on one surface of the semiconductor substrate, and the first passivation layer may pass through the first conductive region and the control passivation layer at the portion where the isolation line is located and contact the base region of the semiconductor substrate.

[0044] Here, the position of the isolation line may be closer to the end of the first electrode or the second electrode than the boundary of the edge of one surface or the other surface of the semiconductor substrate.

[0045] In addition, the depth of the isolation line formed from the surface of the first conductive region or the second conductive region may be greater than the thickness of the first conductive region or the second conductive region, and may be 3 um to 5 um.

[0046] The line width of the isolation line may be 20 um or greater.

[0047] The distance between the isolation line and the edge may be greater than the line width of the isolation line, and may be 2 mm or less.

[0048] Technical Effects

[0049] According to the method of forming an isolation structure using wet etching, an isolation structure in which different conductive regions are naturally spaced apart from each other can be achieved through a front surface texturing operation and a dopant layer forming operation. Therefore, the manufacturing process of the solar cell can be further simplified and facilitated.

[0050] In addition, since the method of manufacturing a solar cell according to the present invention does not use a reactive ion etching (RIE) method to form an isolation structure, contamination of semiconductor equipment can be prevented. In addition, since a separate auxiliary device for preventing contamination of the equipment is not required, the manufacturing cost can be further reduced.

[0051] According to the method of forming isolation lines by etching a part of a semiconductor substrate by applying an etching paste to the edge of one surface or the other surface of the semiconductor substrate, contamination of semiconductor equipment can be minimized, and since the etching paste is applied to each solar cell, the defect rate of the edge isolation structure can be minimized.

[0052] In addition, since the edge isolation structure is formed by performing etching by applying the etching paste, the manufacturing process can be simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 and Figure 2 are diagrams illustrating a solar cell according to the present disclosure.

[0054] Figure 3 is a diagram illustrating an isolation structure of a solar cell according to a first embodiment of the present disclosure.

[0055] Figures 4 to 14 is a diagram illustrating a first embodiment of a solar cell manufacturing method for forming an isolation structure of a solar cell according to a first embodiment of the present disclosure.

[0056] Figures 15 to 21 is a diagram illustrating a second embodiment of a solar cell manufacturing method for forming an isolation structure of a solar cell according to a first embodiment of the present disclosure.

[0057] Figure 22 is an illustration of Figure 4 and Figure 15 another example of the front surface texturing operation shown.

[0058] Figure 23 is a diagram illustrating an isolation structure of a solar cell according to a second embodiment of the present disclosure.

[0059] Figure 24 is along Figure 23 taken along line II-II of Figure 23 a cross-sectional view of the isolation line shown.

[0060] Figures 25 to 35 is a diagram showing a first embodiment of a solar cell manufacturing method for forming an isolation structure of a solar cell according to a second embodiment of the present disclosure.

[0061] Figures 36 to 39 is an illustration of Figures 25 to 35 a variant of the first embodiment shown.

[0062] Figures 40 to 43 is a diagram illustrating a second embodiment of a solar cell manufacturing method for forming an isolation structure of a solar cell according to a second embodiment of the present disclosure.

[0063] Figures 44 to 46 illustrates Figures 40 to 43 a variation of the second embodiment shown.

[0064] Figures 47 to 51 is a diagram illustrating a third embodiment of a method for manufacturing a solar cell for forming an isolation structure according to a second embodiment of the present disclosure. Detailed Embodiment

[0065] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily practice them. As those skilled in the art will realize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description of the present invention are omitted for clarity. Similar reference numerals always refer to similar elements.

[0066] In the drawings, the thicknesses of layers, films, regions, panels, etc. are exaggerated for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be intervening elements. In contrast, when an element is referred to as being "directly" on another element, there are no intervening elements. Also, when an element is "entirely" formed on another element, this means that the element is not formed on a part of the edge of the other element, but on the entire surface of the other element.

[0067] In addition, when the thickness or width of an element is equal to the thickness or width of another element, this means that they are the same within a range of 10% including process errors.

[0068] Figure 1 and Figure 2 is a diagram illustrating a solar cell according to the present disclosure. Specifically, Figure 1 is a partial perspective view of the solar cell, and Figure 2 is a cross-sectional view of the solar cell taken along line I-I Figure 1 shown.

[0069] As Figure 1 and Figure 2 shown, a solar cell according to an embodiment of the present disclosure may include a semiconductor substrate 110, a control passivation layer 160, a first conductive region 170 and a first passivation layer 180, a second conductive region 120, a second passivation layer 130, a first electrode 150, and a second electrode 140.

[0070] Here, the control passivation layer 160, the first passivation layer 180, and the second passivation layer 130 can be omitted. However, if provided, the efficiency of the solar cell can be further improved. Therefore, the case of providing the control passivation layer 160, the first passivation layer 180, and the second passivation layer 130 will be described as an example.

[0071] The semiconductor substrate 110 can be formed of a crystalline semiconductor. For example, the semiconductor substrate 110 can be formed of single-crystalline or polycrystalline semiconductor (e.g., single-crystalline or polycrystalline silicon). Specifically, the semiconductor substrate 110 can be formed of single-crystalline semiconductor (e.g., single-crystalline semiconductor wafer, specifically, single-crystalline silicon wafer). Therefore, when the semiconductor substrate 110 is formed of single-crystalline semiconductor (e.g., single-crystalline silicon), the solar cell based on the semiconductor substrate 110 formed of a crystalline semiconductor with high crystallinity and fewer defects can have excellent electrical characteristics.

[0072] In the present embodiment, the semiconductor substrate 110 can be formed only of the base region 10 without a separate doping region. Thus, when no separate doping region is formed in the semiconductor substrate 110, damage to the semiconductor substrate 110, increase in defects, etc. that may occur during the formation of the doping region can be prevented, thereby providing a semiconductor substrate 110 with excellent passivation characteristics. As a result, surface recombination occurring on the surface of the semiconductor substrate 110 can be minimized. However, the present disclosure is not limited thereto, and in addition to the base region 10, the semiconductor substrate 110 can further include a doping region.

[0073] Hereinafter, an example in which the base region 10 and the second conductive region 120 are provided together in the semiconductor substrate 110 will be described.

[0074] In the present embodiment, a dopant of the first conductive type or the second conductive type is doped on the semiconductor substrate 110 or the base region 10 at a low doping concentration. Therefore, the semiconductor substrate 110 or the base region 10 can have the first conductive type or the second conductive type. Here, compared with one of the first conductive region 170 and the second conductive region 120 having the same conductive type, the semiconductor substrate 110 or the base region 10 can have a lower doping concentration, a higher resistance, or a lower carrier concentration.

[0075] The p-type dopant used as the first conductive type dopant or the second conductive type dopant can include group III elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In). The n-type dopant can include group V elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb). However, the present disclosure is not limited thereto, and various dopants can be used as the first conductive type dopant or the second conductive type dopant.

[0076] In the following, the case where the semiconductor substrate 110 is doped with a dopant of a first conductivity type and the first conductivity type dopant is an n-type dopant will be described as an example. However, the present disclosure is not limited thereto.

[0077] The back surface and / or the front surface of the semiconductor substrate 110 may be textured and thus have recesses and protrusions.

[0078] The textured recesses and protrusions may include, for example, the (111) plane of the semiconductor substrate 110 and may have a pyramidal shape with irregular dimensions. If the surface roughness increases due to the recesses and protrusions formed on the front surface etc. of the semiconductor substrate 110 by texturing, the reflectance of light incident on the front surface etc. of the semiconductor substrate 110 can be reduced. Therefore, the amount of light reaching the p-n junction can be increased, thereby minimizing light loss.

[0079] However, the present disclosure is not limited thereto. Textured recesses and protrusions may be formed on both the back surface and the front surface of the semiconductor substrate 110, and textured recesses and protrusions may not be formed on the back surface and the front surface of the semiconductor substrate 110.

[0080] The control passivation layer 160 is generally located on the back surface of the semiconductor substrate 110 and may be formed of a dielectric material or a silicon material and substantially performs a passivation function on the back surface of the semiconductor substrate 110. In addition, the control passivation layer 160 may allow carriers generated in the semiconductor substrate 110 to pass through it, but this is not necessary.

[0081] The control passivation layer 160 may be formed of a dielectric material such as SiCx or SiOx that is durable even in a high-temperature process of 600 °C or higher, or may be formed of a-Si, silicon nitride (SiNx), hydrogenated SiNx, aluminum oxide (AlOx), silicon oxynitride (SiON), or hydrogenated SiON.

[0082] Therefore, the thickness of the control passivation layer 160 may be formed to be 0.5 nm to 2.5 nm.

[0083] The first conductivity region 170 may be in direct contact with the back surface of the control passivation layer 160 and may be located over the entire area of the back surface of the control passivation layer 160. For example, the first conductivity region 170 may be formed by doping a polysilicon layer with a dopant of the first conductivity type at a concentration higher than that of the semiconductor substrate 110. For example, an n-type dopant may be used as the first conductivity type dopant.

[0084] Accordingly, when the semiconductor substrate 110 contains a dopant of a first conductivity type and the dopant of the first conductivity type is doped in the first conductive region 170 at a higher concentration than the semiconductor substrate 110, the first conductive region 170 can operate as a back surface field (BSF). However, the present disclosure is not limited thereto, and when the semiconductor substrate 110 contains a dopant of a second conductivity type and the dopant of the first conductivity type is doped in the first conductive region 170, the first conductive region 170 operates as an emitter. Hereinafter, a case where the semiconductor substrate 110 contains a dopant of a first conductivity type and the first conductive region 170 operates as a BSF will be described as an example.

[0085] The polysilicon layer forming the first conductive region 170 may be formed by depositing polysilicon on the back surface of the semiconductor substrate 110, or may be formed by depositing amorphous silicon on the back surface of the semiconductor substrate 110 and performing heat treatment to convert the amorphous silicon into polysilicon.

[0086] Accordingly, the first conductive region 170 formed of polysilicon may have a crystal structure different from that of the semiconductor substrate 110 formed of single crystal silicon.

[0087] When the first conductive region 170 has a crystal structure different from that of the semiconductor substrate 110, the output voltage Voc of the solar cell can be further increased and the ohmic contact with the first electrode 150 connected to the first conductive region 170 can be further improved.

[0088] As described above, when the control passivation layer 160 formed of polysilicon is formed on the back surface of the semiconductor substrate 110 while controlling the formation of the passivation layer 160 on the back surface of the semiconductor substrate 110, in terms of the manufacturing process, thermal damage to the semiconductor substrate 110 can be minimized and a high-efficiency solar cell can be realized.

[0089] The thickness T170 of the first conductive region 170 may be, for example, 200 nm to 400 nm. The thickness T170 of the first conductive region 170 is based on the center of the semiconductor substrate, and may be less than or greater than 200 nm to 400 nm at the edge of the semiconductor substrate.

[0090] The first passivation layer 180 may be located on the first conductive region 170 (i.e., on the back surface of the first conductive region 170), may be formed of a dielectric material, and may have a greater thickness than the control passivation layer 160.

[0091] The first passivation layer 180 may include at least one of SiNx, SiOx, SiOxNy, SiCx, or AlOx containing a large amount of hydrogen, and performs a passivation function on the back surface of the first conductive region 170.

[0092] The second conductive region 120 may be located on the front surface of the semiconductor substrate 110 and may be formed by doping a dopant of a second conductive type inside the front surface of the semiconductor substrate 110.

[0093] The second conductive region 120 may be formed by diffusing a dopant of a second conductive type into the front surface of the semiconductor substrate 110. Thus, the second conductive region 120 may be formed of the same crystalline silicon material as the crystalline silicon material of the semiconductor substrate 110.

[0094] For example, when the semiconductor substrate 110 is formed of single-crystalline silicon, the second conductive region 120 may also be formed of single-crystalline silicon. Alternatively, when the semiconductor substrate 110 is formed of polycrystalline silicon, the second conductive region 120 may also be formed of polycrystalline silicon.

[0095] The thickness T120 of the second conductive region 120 may be about 1.5 um to 2.5 um. However, since it is desired that the thickness T120 of the second conductive region 120 is small, the thickness T120 of the second conductive region 120 may be reduced to 0.1 nm to 0.3 nm.

[0096] When the semiconductor substrate 110 contains a dopant of a first conductive type and the second conductive region 120 is doped with a dopant of a second conductive type, the second conductive region 120 may operate as an emitter portion. However, the present disclosure is not limited thereto, and when the semiconductor substrate 110 contains a dopant of a second conductive type and the second conductive region 120 is doped at a higher concentration than the semiconductor substrate 110, the second conductive region 120 may operate as a front electric field. Hereinafter, a case where the semiconductor substrate 110 contains a dopant of a first conductive type and the second conductive region 120 operates as an emitter portion will be described.

[0097] The second passivation layer 130 may be directly located on the front surface of the second conductive region 120 to perform a passivation function on the entire surface of the second conductive region 120. The second passivation layer 130 may be formed of a hydrogen-containing dielectric material. For example, the second passivation layer 130 may be formed of at least one of SiNx, SiOx, SiOxNy, or AlOx.

[0098] The second passivation layer 130 may increase the light transmittance and reduce the reflectance of the light incident on the solar cell, so that the maximum amount of light can be incident on the semiconductor substrate 110.

[0099] The first electrode 150 may be located on the back surface of the semiconductor substrate 110 and may be connected to the first conductive region 170 through the first passivation layer 180.

[0100] The first electrode 150 may include a plurality of first finger electrodes 151 and a plurality of first busbars 152 connected to the plurality of first finger electrodes 151.

[0101] A plurality of first finger electrodes 151 can be electrically and physically connected to the first conductive region 170, and can be spaced apart from each other in the second direction y and extend side by side in the first direction x. The plurality of first finger electrodes 151 can collect carriers moving toward the first conductive region 170.

[0102] A plurality of first bus bars 152 can be electrically and physically connected to the first conductive region 170, and can be spaced apart from each other in the first direction x and extend side by side in the second direction y.

[0103] Here, the plurality of first bus bars 152 can be located on the same layer as the plurality of first finger electrodes 151 and can be electrically and physically connected to the first finger electrodes 151 respectively at the points where the plurality of first bus bars 152 cross the plurality of first finger electrodes 151.

[0104] In some cases, when the plurality of first bus bars 152 are only used to transfer the charges collected from the first finger electrodes 151 to the outside, the plurality of first bus bars 152 may not contact the first conductive region 170 and can be configured to be only connected to the first finger electrodes 151. In this case, an electrode material different from that of the first finger electrodes 151 can also be used.

[0105] Therefore, as Figure 1 shown, the plurality of first finger electrodes 151 have a strip shape extending in the first direction x and the plurality of first bus bars 152 can have a strip shape extending in the second direction y, so that the first electrode 150 can be located on the front surface of the semiconductor substrate 110 in a lattice shape.

[0106] The plurality of first bus bars 152 can not only collect carriers moving from the second conductive region 120, but also collect carriers collected and moved by the plurality of first finger electrodes 151.

[0107] Since the plurality of first bus bars 152 should collect the charges collected by the plurality of first finger electrodes 151 and move the charges in a desired direction, the width of each first bus bar 152 can be formed to be greater than the width of the first finger electrodes 151. However, the present disclosure is not limited thereto, and the first bus bar and the first finger electrode can have the same line width. In this case, the width of the first bus bar 152 can be as small as the width of the first finger electrodes 151.

[0108] The plurality of first bus bars 152 can be connected to an external device and output the collected carriers (e.g., electrons) to the external device.

[0109] The plurality of first finger electrodes 151 and the plurality of first bus bars 152 of the first electrode 150 can be formed of at least one conductive material such as silver (Ag).

[0110] The second electrode 140 may be located on the front surface of the semiconductor substrate 110 and may be connected to the second conductive region 120 through the second passivation layer 130.

[0111] Similar to the first electrode 150, the second electrode 140 may include a plurality of second finger electrodes 141 and a plurality of second bus bars 142 connected to the plurality of second finger electrodes 141, as Figure 1 and Figure 2 shown. The second electrode 140 may be formed in the same pattern as the first electrode 150. However, the pattern of the second electrode 140 may be formed to be different from the pattern of the first electrode 150.

[0112] For example, the second electrode 140 may have second finger electrodes 141 and second bus bars 142 having a lattice structure, while the first electrode 150 may include an electrode layer on the entire back surface of the semiconductor substrate 110, except for the portion where the first bus bar 152 is formed.

[0113] The second electrode 140 may collect carriers moving toward the second conductive region 120.

[0114] In addition, in a solar cell, the first conductive region and the second conductive region may be isolated from each other on one side of the semiconductor substrate.

[0115] As described above, when the front surface of the semiconductor substrate is textured during the solar cell manufacturing process, a structure in which the first conductive region and the second conductive region are isolated may be naturally formed on the side surface of the solar cell.

[0116] The isolation structure formed on the side surface of the solar cell will be described in detail below.

[0117] Figure 3 is a diagram illustrating an isolation structure of a solar cell according to a first embodiment of the present disclosure.

[0118] Figure 3 illustrates the side surface of the solar cell to explain the formation of Figure 1 and Figure 2 the isolation structure formed on the side surface of the solar cell shown.

[0119] As Figure 3 shown, in the solar cell according to the present disclosure, the first conductive region and the second conductive region may be spaced apart from each other on the side surface of the semiconductor substrate to form an isolation structure.

[0120] More specifically, the first conductive region may be formed on a side surface of the semiconductor substrate and mainly formed on a back surface of the semiconductor substrate with respect to a center of the side surface of the semiconductor substrate (i.e., a center of the semiconductor substrate in a thickness direction), and the second conductive region may be mainly formed on a front surface of the semiconductor substrate with respect to the center of the side surface of the semiconductor substrate.

[0121] However, the present disclosure is not limited thereto, and the first conductive region and the second conductive region may hardly be formed on the side surface of the semiconductor substrate.

[0122] In addition, the first conductive region and the second conductive region may be spaced apart from each other in a thickness direction of the semiconductor substrate from a side surface of the semiconductor substrate, and a base region of the semiconductor substrate may be exposed at a portion where the first conductive region and the second conductive region are spaced apart from each other.

[0123] As described above, the first passivation layer or the second passivation layer may be further formed in the base region exposed to the side surface of the semiconductor substrate. For example, as Figure 3 shown, the second passivation layer may be further formed at the base region exposed to the side surface of the semiconductor substrate, and the first passivation layer may be further formed on the second passivation layer, and the second passivation layer is further formed at the base region exposed to the side surface of the semiconductor substrate.

[0124] However, the present disclosure is not limited thereto, and the first passivation layer and the second passivation layer may be sequentially stacked at the base region exposed on the side surface of the semiconductor substrate.

[0125] Hereinafter, a method of manufacturing a solar cell for forming an isolation structure of the solar cell will be described in more detail.

[0126] Figures 4 to 14 is a diagram illustrating an example of a method of manufacturing a solar cell for forming an isolation structure of the solar cell according to a first embodiment of the present disclosure.

[0127] Specifically, Figure 4 is a flowchart illustrating a method of manufacturing a solar cell, while Figures 5 to 14 is an illustration of Figure 4 each step shown.

[0128] The method of manufacturing a solar cell according to the present embodiment may include a passivation layer deposition step S1, a first conductive region 170 formation step S2, S5, a front surface texturing step S3, a second conductive region 120 formation step S4, S5, a cleaning step S6, a passivation layer deposition step S7, and an electrode formation step S8.

[0129] The steps S2 and S5 for forming the first conductive region 170 may include a polysilicon layer deposition step S2 and a heat treatment step S5, while the steps S4 and S5 for forming the second conductive region 120 may include a dopant layer formation step S4 and a heat treatment step S5.

[0130] Here, the heat treatment step S5 in the step of forming the first conductive region 170 and the heat treatment step S5 in the step of forming the second conductive region 120 may be carried out simultaneously in one process, as Figure 4 described in the flowchart of. As a result, the manufacturing process can be further simplified.

[0131] Here, the control passivation layer deposition step S1 and the cleaning step S6 can be omitted in some cases.

[0132] In addition, although not described in the Figure 4 flowchart of, the method may further include texturing or saw damage etching (SDE) of the entire surface of the semiconductor substrate 110 before the control passivation layer deposition step S1.

[0133] For example, when the semiconductor substrate 110 is subjected to saw damage etching before the control passivation layer deposition step S1, the entire surface of the semiconductor substrate 110 can be formed to be substantially flat, as Figure 5 shown. However, the present disclosure is not limited thereto, and after SDE and before the control passivation layer deposition step S1, the entire surface of the semiconductor substrate 110 can be textured.

[0134] For the sake of convenience of description, the case where the control passivation layer deposition step S1 is carried out after performing SDE will be described as an example.

[0135] In the control passivation layer deposition step S1, the control passivation layer 160 can be formed on the entire surface of the semiconductor substrate 110. Here, the material and thickness of the control passivation layer 160 can be the same as those described above with reference to Figures 1 to 3 For example, in the control passivation layer deposition step S1, silicon oxide (SiOx) is deposited on the front surface, back surface, and side surfaces of the semiconductor substrate 110 by using a thermal oxidation process to form the control passivation layer 160.

[0136] In the polysilicon layer deposition step S2, as Figure 7 shown, a polysilicon layer 170' can be deposited on the back surface 110S1 of the semiconductor substrate 110 (i.e., on the control passivation layer) by using CVD equipment to form the first conductive region 170. Here, the thickness of the deposited polysilicon layer 170' can be within 1um. For example, the polysilicon layer 170' can be deposited to have a thickness between 300nm and 400nm.

[0137] The polysilicon layer 170' may be deposited on the side surface of the semiconductor substrate 110 to have a thickness smaller than that formed on the back surface 110S1 of the semiconductor substrate 110 and may be deposited up to the edge portion of the front surface 110S2 of the semiconductor substrate 110. A dopant of a first conductivity type may be doped in the polysilicon layer 170'.

[0138] In the polysilicon layer deposition step S2 of the present disclosure, the case of depositing the polysilicon layer 170' on the back surface 110S1 of the semiconductor substrate 110 from the beginning has been described as an example, but it is not limited thereto. Alternatively, an amorphous silicon layer may be deposited on the back surface 110S1 of the semiconductor substrate 110, and heat treatment may be performed in the heat treatment step S5 to form a polysilicon layer.

[0139] In the front surface texturing step S3, the front surface of the semiconductor substrate 110 may be selectively textured.

[0140] That is, in the front surface texturing step S3, the front surface among the front surface and the back surface of the semiconductor substrate 110 may be selectively textured, and the side surface of the semiconductor substrate 110 may be textured locally or integrally.

[0141] For example, the front surface texturing step S3 may be performed by etching equipment installed online on a solar cell manufacturing process line. Here, a roller R1 as part of the etching equipment may move the semiconductor substrate 110 in the arrow direction along the direction of the online process in a state where a part of the roller R1 is immersed in the texturing etching solution EC1.

[0142] More specifically, in the front surface texturing step S3, as Figure 8 shown, in a state where the front surface of the semiconductor substrate is in contact with the roller R1 partially immersed in the texturing etching solution EC1, when the roller R1 rotates, the texturing etching solution EC1 present on the surface of the roller R1 etches the front surface of the semiconductor substrate 110 to form textured recesses and protrusions on the front surface of the semiconductor substrate 110.

[0143] In this case, as Figure 9 shown, the polysilicon layer 170' and the control passivation layer 160 formed on the side surface of the semiconductor substrate 110 may be etched by the texturing etching solution EC1 present on the surface of the roller, and textured recesses and protrusions may be formed on the front surface of the semiconductor substrate 110.

[0144] That is, when forming the textured recesses and protrusions on the front surface of the semiconductor substrate 110, the control passivation layer 160 and the polysilicon layer 170' formed at a part of the side surface and the edge portion of the front surface of the semiconductor substrate 110, which are in contact with the textured etching solution EC1 existing on the roller, can be etched.

[0145] As described above, the polysilicon layer 170' formed at a part of the side surface and the edge portion of the front surface of the semiconductor substrate 110 can be etched to form an isolation portion that electrically separates the first conductive region 170 and the first conductive region 170 on the side surface of the semiconductor substrate 110.

[0146] The etching depth of the front surface of the semiconductor substrate 110 etched by the textured etching solution EC1 in the front surface texturing step S3 can fall between 5 μm and 20 μm.

[0147] Here, potassium hydroxide (KOH) and base deionized water (DI-water) can be used as the textured etching solution EC1.

[0148] As Figure 9 shown, a dopant layer formation step S4 can be performed to form a dopant layer 190 containing a dopant of a second conductive type on the front surface 110S2 of the semiconductor substrate 110 by atmospheric pressure chemical vapor deposition (APCVD) or plasma enhanced chemical vapor deposition (PECVD), thereby forming a second conductive region 120.

[0149] The dopant layer 190 can be, for example, a borosilicate glass (BSG) film. However, the present disclosure is not limited thereto, and the dopant layer 190 can include only a dopant of a conductive type opposite to the first conductive region 170. For example, a phosphosilicate glass (PSG) layer or a layer containing another conductive type dopant can be used as the dopant layer 190.

[0150] To form the dopant layer 190 on the front surface of the semiconductor substrate 110 as Figure 9 shown by performing the dopant layer formation step S4, the dopant layer 190 can be formed on the back surface, side surface, and edge portion of the front surface of the semiconductor substrate 110 in the dopant layer formation step S4, and then, the dopant layer 190 formed at the edge portions of the back surface and side surface of the semiconductor substrate 110 can be removed.

[0151] In addition, in order to prevent impurities and hydrogen from diffusing out of the dopant layer 190 in the subsequent heat treatment step S5, undoped silicate glass (USG) may be further formed on the dopant layer in the dopant layer formation step S4, and the USG may be removed together with the dopant layer 190 after the heat treatment step S5.

[0152] Here, the dopant layer 190 formed on the edge portions of the back surface and the side surfaces of the semiconductor substrate 110 may be removed by etching with dilute hydrofluoric acid (DHF). In addition, when the dopant layer 190 formed at the edge portions of the back surface and the side surfaces of the semiconductor substrate 110 is removed using hydrofluoric acid diluent (DHF), the semiconductor substrate 110 or the polysilicon layer 170' may not be etched.

[0153] Therefore, as Figure 10 shown, the polysilicon layer 170' for forming the first conductive region 170 and the dopant layer 190 for forming the second conductive region 120 on the side surface of the semiconductor substrate 110 may be spaced apart from each other to be isolated.

[0154] Thereafter, in the heat treatment step S5, the semiconductor substrate 110 may be heat-treated, for example, at a temperature between 800 °C and 1000 °C, and as Figure 11 shown, the second dopant of the dopant layer 190 may diffuse to the front surface of the semiconductor substrate 110 to form the second conductive region 120 that can be formed as a diffusion region in a part of the base region 10 of the semiconductor substrate 110.

[0155] In addition, as Figure 11 shown, the first conductive type dopant contained in the polysilicon layer 170' may be activated through the heat treatment step S5, so that the polysilicon layer 170' can be formed as the first conductive region 170.

[0156] Here, the thickness of the first conductive region 170 may be formed to fall between 300 nm and 400 nm, and the thickness of the second conductive region 120 may be formed to fall between 1.5 μm and 2.5 μm.

[0157] After the heat treatment step S5, in the cleaning step S6, as Figure 12 shown, the residual dopant layer 190 provided on the front surface 110S2 of the semiconductor substrate 110 may be etched off by hydrofluoric acid diluent (DHF), and here, the semiconductor substrate 110 or the first conductive region 170 and the second conductive region 120 may not be etched.

[0158] In the passivation layer deposition step S7, as Figure 13 shown, a second passivation layer 130 may be deposited on the second conductive region 120, and a first passivation layer 180 may be deposited on the first conductive region 170.

[0159] In Figure 13 it, as an example, the case where the second passivation layer 130 is deposited first and then the first passivation layer 180 is deposited is illustrated, but the deposition order of the first passivation layer 180 and the second passivation layer 130 is not limited thereto. That is, the first passivation layer 180 can be deposited first, and then the second passivation layer 130 can be deposited.

[0160] Therefore, on the side surface of the semiconductor substrate 110, the base region 10 exposed because the first conductive region 170 and the second conductive region 120 are spaced apart from each other can be covered by the first passivation layer 180 or the second passivation layer 130.

[0161] Subsequently, in the electrode formation step S8, as Figure 14 shown, the first electrode 150 connected to the first conductive region 170 through the first passivation layer 180 and the second electrode 140 connected to the second conductive region 120 through the second passivation layer 130 can be formed. Therefore, the solar cell described above with reference to Figures 1 to 3 can be manufactured.

[0162] Therefore, in the method for manufacturing a solar cell according to the present disclosure, an isolation structure can be naturally formed while the front surface of the semiconductor substrate 110 is textured in the front surface texturing step S3, without a separate isolation step.

[0163] In addition, since the method for manufacturing a solar cell according to the present disclosure does not use reactive ion etching (RIE) to form the isolation structure, contamination of semiconductor equipment can be prevented, and since an auxiliary device for preventing equipment contamination is not required, the manufacturing cost can be further reduced.

[0164] In addition, since the method for manufacturing a solar cell according to the present disclosure does not use reactive ion etching (RIE), the uniformity problem of the isolation structure can also be solved.

[0165] In addition, since the isolation structure is naturally formed through the front surface texturing step S3, the dopant layer formation step S5, and the cleaning step S6, the manufacturing process of the solar cell can be simplified.

[0166] However, the method for manufacturing a solar cell according to the present disclosure is not limited to the above-described embodiments, but can be modified or added in some steps. Hereinafter, another embodiment in which some components of the method for manufacturing a solar cell are different from the above-described embodiments will be described.

[0167] Figures 15 to 21 is a diagram illustrating another example of a method for manufacturing a solar cell for forming an isolation structure of a solar cell according to a first embodiment of the present disclosure.

[0168] Figure 15 is a flowchart, while Figures 16 to 21 illustrates Figure 15 each step of

[0169] The method for manufacturing a solar cell according to the present embodiment may further include a mask formation step S91 (see Figure 4 ) before the front surface texturing step S3 of the above embodiment, and may further include a mask removal step S92 after the front surface texturing step S3.

[0170] Therefore, the method for manufacturing a solar cell according to the present embodiment may include controlling the passivation layer deposition step S1, the polysilicon layer deposition step S2, the mask formation step S91, the front surface texturing step S3, the mask removal step S92, the dopant layer formation step S4, the heat treatment step S5, the cleaning step S6, the passivation layer deposition step S7, and the electrode formation step S8.

[0171] In the present embodiment, since the processes up to the polysilicon layer deposition step S2 are the same as those of the embodiment described above with reference to Figure 4 , the mask formation step S91 to the mask removal step S92 will be described, and the embodiment of Figure 4 will be used to replace the description of the parts that are the same as those of the above Figure 4 embodiment, and its detailed description will be omitted.

[0172] As Figure 15 shown, the mask formation step S91 may be performed between the polysilicon layer deposition step S2 and the front surface texturing step S3, and as Figure 18 shown, a mask layer 200 for preventing texture etching may be formed on the polysilicon layer 170' on the back surface of 110.

[0173] To this end, as Figure 16 shown, in the mask formation step S91, the mask layer 200 is formed on the entire surface of the polysilicon layer 170' and the entire front surface of the semiconductor substrate 110. As Figure 17 shown, the remaining portion of the mask layer 200 except for the portion formed on the polysilicon layer 170' located on the back surface of the semiconductor substrate 110 may be removed by the mask etching solution EC2, so that the mask layer 200 may remain only on the back surface of the semiconductor substrate 110, as Figure 18 shown.

[0174] More specifically, in order to form Figure 16The shown mask layer 200 can use atmospheric pressure chemical vapor deposition (APCVD) or plasma enhanced chemical vapor deposition (PECVD), and silicon oxide (SiOx) or silicon nitride (SiNx) can be completely formed on the surface of the polysilicon layer 170' and the front surface of the semiconductor substrate 110.

[0175] Thereafter, as Figure 17 shown, the remaining part of the mask layer 200 except for the part formed on the polysilicon layer 170' disposed on the back surface of the semiconductor substrate 110 can be removed by the mask etching solution EC2 including hydrofluoric acid diluent (DHF).

[0176] In this case, in order to retain the mask layer 200 located on the back surface of the semiconductor substrate 110, as Figure 17 shown, a mask etching prevention layer 220 can be coated on the mask layer 200 located on the back surface of the semiconductor substrate 110. The mask etching prevention layer 220 can be formed of a material different from that of the mask layer 200, and can be any material as long as it is not etched by the hydrofluoric acid diluent (DHF).

[0177] For the convenience of the process, the mask etching prevention layer 220 can be in the form of, for example, a tape that can be simply adhered to the mask layer 200.

[0178] Therefore, in the state where the mask etching prevention layer 220 is coated, the semiconductor substrate 110 can be immersed in the hydrofluoric acid diluent (DHF) to remove the remaining part of the mask layer 200 except for the part formed on the polysilicon layer 170' disposed on the back surface of the semiconductor substrate 110.

[0179] In order to shorten the processing time even in the process of removing the remaining part of the mask layer 200, in the state where the roller R2 provided on the line is immersed in the hydrofluoric acid diluent (DHF), the roller R2 can be moved to remove the mask layer 200 located on the front surface and the side surface of the semiconductor substrate 110 to form Figure 18 the shown structure.

[0180] Subsequently, the mask etching prevention layer 220 located on the back surface of the semiconductor substrate 110 can be removed, so that the mask layer 200 can be retained only on the back surface of the semiconductor substrate 110, as Figure 19 shown.

[0181] As Figure 19 shown, the front surface texturing step S3 can be performed in the state where the mask layer 200 is formed on the polysilicon layer 170' disposed on the back surface of the semiconductor substrate 110. After the front surface texturing step S3 is completed, the mask layer 200 can be removed.

[0182] More specifically, in the front surface texturing step S3 of the method for manufacturing a solar cell according to the present embodiment, (1) the front surface texturing step S3 can be performed using the roller R1 provided online as in the embodiment described above Figure 4 or (2) the front surface texturing step S3 can be performed by dipping the semiconductor substrate 110 into a bath.

[0183] More specifically, in the front surface texturing step S3 of the method for manufacturing a solar cell according to the present embodiment, in a state where the mask layer 200 is formed on the back surface of the semiconductor substrate 110, (1) the front surface of the semiconductor substrate 110 on which the mask layer 200 is formed comes into contact with the roller R1 partially immersed in the texturing etching solution EC1, as Figure 19 shown, and the roller is rotated so that the texturing etching solution EC1 present on the surface of the roller R1 etches the front surface of the semiconductor substrate 110 to form textured recesses and protrusions as Figure 20 shown on the front surface of the semiconductor substrate 110; or (2) the semiconductor substrate 110 including the mask layer 200 is dipped into the texturing etching solution EC1 filled in the bath to form textured recesses and protrusions as Figure 20 shown on the front surface of the semiconductor substrate 110.

[0184] In addition, in Figure 20 it is illustrated that only textured recesses and protrusions are formed on the front surface of the semiconductor substrate 110. However, alternatively, the textured recesses and protrusions in the front surface texturing step S3 can also be formed on the side surface of the semiconductor substrate 110 as well as on the front surface of the semiconductor substrate 110.

[0185] Thereafter, in the mask removal step S92, the mask layer 200 remaining on the back surface of the semiconductor substrate 110 can be removed using a diluted hydrofluoric acid (DHF), as Figure 20 shown.

[0186] Thereafter, as described in the embodiment of Figure 4 the dopant layer formation step S4, the heat treatment step S5, the cleaning step S6, the passivation layer deposition step S7, and the electrode formation step S8 can be performed to manufacture the solar cell described above with reference to Figures 1 to 3 description.

[0187] In the method for manufacturing a solar cell according to the present embodiment, while the front surface of the semiconductor substrate 110 is textured by the front surface texturing step S3, an isolation structure can be naturally formed without a separate isolation step, thereby making the manufacturing process easier.

[0188] In addition, since the method for manufacturing a solar cell according to the present disclosure does not use reactive ion etching (RIE) to form an isolation structure, contamination of semiconductor equipment can be prevented, and since an auxiliary device for preventing equipment contamination is not required, the manufacturing cost can be further reduced.

[0189] In addition, since the method for manufacturing a solar cell according to the present disclosure does not use reactive ion etching (RIE), the uniformity problem of the isolation structure can also be solved.

[0190] In the embodiments described above Figure 4 and Figure 15 In the embodiments, the following has been described as an example: in the front surface texturing step, when the roller R1 immersed in the texturing etching solution EC1 and in contact with the front surface of the semiconductor substrate 110 rotates, the front surface of the semiconductor substrate is etched by the texturing etching solution EC1 present on the roller R1.

[0191] However, the front surface texturing step included in the method for manufacturing a solar cell according to the present disclosure is not limited to the above method and can be performed by other methods. This will be described in more detail with reference to Figure 22 below.

[0192] Figure 22 illustrates Figure 4 and Figure 15 Another example of the front surface texturing step shown in

[0193] For example, after performing the polysilicon layer deposition step S2 as shown in Figure 7 , instead of the front surface texturing step S3 of the method for manufacturing a solar cell according to Figure 4 and Figure 8 , the front surface texturing step according to another embodiment of the present disclosure is performed by selectively texturing the front surface of the semiconductor substrate 110 by a spraying method in a state where the back surface of the semiconductor substrate 110 as shown in Figure 22 is in contact with the roller R1.

[0194] More specifically, in the front surface texturing step according to another embodiment of the present disclosure, the roller R1 is not immersed in the texturing etching solution, and the texturing etching solution can be sprayed through a nozzle.

[0195] Therefore, the front surface texturing step can be performed to selectively texture the front surface of the semiconductor substrate by the texturing etching solution sprayed on the front surface of the semiconductor substrate via the nozzle while the semiconductor substrate is conveyed in the arrow direction by the roller.

[0196] By the front surface texturing step according to another embodiment of the present disclosure (see Figure 22) can etch and completely remove the control passivation layer and the polysilicon layer present on the front surface of the semiconductor substrate, and can etch a part of the control passivation layer and the polysilicon layer present on the side surface of the semiconductor substrate to be in the Figure 9 state shown.

[0197] Alternatively, different from Figure 9 , the control passivation layer and the polysilicon layer present on the side surface of the semiconductor substrate can be completely etched and removed.

[0198] Although the front surface texturing step according to another embodiment of the present disclosure (see Figure 22 ) has been described as an example in the case of being applied to the Figure 4 solar cell manufacturing method, the present disclosure is not limited thereto and the front surface texturing step according to another example of the present disclosure can be applied to replace the Figure 15 front surface texturing step S3 of the solar cell manufacturing method.

[0199] That is, after the mask layer forming step S91 in the Figure 15 solar cell manufacturing method, the front surface of the semiconductor substrate 110 can be selectively textured by a spraying method in a state of being in contact with the roller R1 on the back surface of the semiconductor substrate 110 as shown in Figure 22 to perform the front surface texturing step according to another example of the present disclosure.

[0200] Hereinafter, the isolation structure of the solar cell according to the second embodiment of the present disclosure will be described with reference to Figure 23 and Figure 24 , and various embodiments of the solar cell manufacturing method for forming the isolation structure of the solar cell according to the second embodiment of the present disclosure will be described with reference to Figures 25 to 51 .

[0201] The solar cell having the isolation structure according to the second embodiment has the same basic structure as the solar cells shown in Figure 1 and Figure 2 , but there are some differences in the formation positions of the respective layers or films. In the following description, "A" is indicated after the reference numeral of each element.

[0202] Therefore, elements having the same reference numerals in the drawings illustrating the isolation structure of the solar cell according to the above first embodiment and the drawings illustrating the isolation structure of the solar cell according to the following second embodiment can be considered the same elements having the same functions.

[0203] Figure 23 is a diagram illustrating the isolation structure of the solar cell according to the second embodiment of the present disclosure, and Figure 24 is alongFigure 23 taken along line II-II of Figure 23 a cross-sectional view of the isolation line 200 shown in Figure 23 wherein (a) shows the entire pattern of either one of the front surface or the back surface of the solar cell, Figure 23 wherein (b) is Figure 23 an enlarged portion of (a) in Figure 24 wherein (a) shows an example of the cross-section of the isolation line 200, and Figure 24 wherein (b) shows a variation of the cross-section of the isolation line 200.

[0204] As Figure 23 shown in (a) and (b), the isolation line 200 may be provided between the region where the first electrode 150A is formed or the region where the second electrode 140A is formed and the edge of the semiconductor substrate.

[0205] Here, one surface of the semiconductor substrate 110A may be either the front surface or the back surface of the solar cell, and the other surface of the semiconductor substrate 110A may be the opposite surface of one surface. Hereinafter, the case where one surface of the semiconductor substrate 110A is the back surface of the solar cell and the other surface is the front surface of the solar cell will be described as an example. However, the present disclosure is not limited thereto, and vice versa.

[0206] The isolation line 200 may be provided only on one surface or the other surface of the semiconductor substrate 110A. For example, when the isolation line 200 is provided on one surface of the semiconductor substrate 110A, the isolation line 200 may not be provided on the other surface of the semiconductor substrate 110A, and vice versa, when the isolation line is provided on the other surface of the semiconductor substrate 110A, the isolation line 200 may not be provided on one surface of the semiconductor substrate 110A.

[0207] However, the present disclosure is not limited thereto, and the isolation line 200 may be provided on both the one side and the other side of the semiconductor substrate 110A.

[0208] However, for simplicity of the process, the case where the isolation line 200 is provided only on one surface or the other surface of the semiconductor substrate 110A will be described as an example.

[0209] The isolation line 200 may be a line formed by removing a part of the first conductive region 170A or a part of the second conductive region 120A, and may be spaced apart from the first electrode 150A or the second electrode 140A and provided in a line form parallel to the edge of one surface or the other surface of the semiconductor substrate 110A.

[0210] The isolation line 200 can prevent a short circuit between the first conductive region 170A and the second conductive region 120A, thereby preventing a reduction in the efficiency of the solar cell.

[0211] As shown in Figure 23 (b) of FIG. [0000543], the position of the isolation line 200 may be closer to the ends of the finger electrodes 151A and 141A than the edge of one surface or the other surface of the semiconductor substrate 110A.

[0212] For example, the distance D1 between the isolation line 200 and the finger electrodes 151A, 141A may be greater than 20 um, and may be less than the distance D2 between the isolation line 200 and the edge of the semiconductor substrate 110A.

[0213] Within a range less than the distance D1 between the isolation line 200 and the finger electrodes 151A and 141A, the distance D2 between the isolation line 200 and the edge of the semiconductor substrate 110A may be 2 mm or less.

[0214] The distance D1 between the isolation line 200 and the ends of the finger electrodes 151A and 141A may be greater than the line width W200 of the isolation line 200 and may be less than the distance D3 between the finger electrodes 151A and 141A. Here, as an example, the distance D3 between the finger electrodes 151A and 141A may be formed to be 1 mm to 2 mm.

[0215] The line width W200 of the isolation line 200 may be formed to be 20 um or greater. Here, the line widths of the finger electrodes 151A and 141A may be 20 um to 40 um.

[0216] The cross-section of the isolation line 200 is as shown in Figure 24 (a) and (b) of FIG. [0000554].

[0217] Figure 24 (a) of FIG. [0000554] shows the cross-section of the isolation line 200 provided on one surface of the semiconductor substrate, while Figure 24 (b) of FIG. [0000554] illustrates the isolation line 200 provided on the other surface of the semiconductor substrate.

[0218] Either the isolation line 200 according to Figure 24 (a) and (b) of FIG. [0000554] may be provided, or both the isolation lines 200 according to Figure 24 (a) and (b) of FIG. [0000554] may be provided. In the following description, the case of only one of the isolation lines will be described as an example.

[0219] As shown in Figure 24As shown in (a) and (b), the depth H200 of the isolation line 200 formed from the surface of the first conductive region 170A or the second conductive region 120A can be greater than the thickness T170A of the first conductive region 170A or the thickness T120A of the second conductive region 120A, and can be less than 150 times the thickness T170A of the first conductive region 170A or the thickness T120A of the second conductive region 120A.

[0220] For example, the depth H200 of the isolation line 200 can be formed in the range of 2um to 5um, greater than the thickness T170A of the first conductive region 170A or the thickness T120A of the second conductive region 120A, and more preferably, formed in the range of 3um to 4um.

[0221] For example, as Figure 24 shown in (a), when the isolation line 200 is provided on one surface of the semiconductor substrate 110A, the thickness T170A of the first conductive region 170A can be 300nm to 400nm and the depth H200 of the isolation line 200 can be formed in the range of 2um to 5um.

[0222] In addition, as Figure 24 shown in (b), when the isolation line 200 is provided on the other surface of the semiconductor substrate 110A, the thickness T120A of the second conductive region 120A can be formed to be approximately 1.5um to 2.5um, and the depth H200 of the isolation line 200 can be formed in the range of 2um to 5um, greater than the thickness of the second conductive region 120A.

[0223] Here, as Figure 24 shown in (a), when the isolation line 200 is located on one surface of the semiconductor substrate 110A, the first passivation layer 180A can pass through the first conductive region 170A at the portion where the isolation line 200 is located and control the passivation layer 160A to contact the base region 10A of the semiconductor substrate 110A. That is, the first passivation layer 180A can be in direct contact with the base region 10A of the semiconductor substrate 110A.

[0224] Alternatively, as Figure 24 shown in (b), when the isolation line 200 is located on the other surface of the semiconductor substrate 110A, the second passivation layer 130A can pass through the second conductive region 120A at the portion where the isolation line 200 is located and contact the base region 10A of the semiconductor substrate 110A. That is, the second passivation layer 130A can be in direct contact with the base region 10A of the semiconductor substrate 110A.

[0225] In a solar cell having an isolation structure with such a configuration, since the isolation lines 200 are formed at the edges of one surface or the other surface of the semiconductor substrate 110A by an etching paste, the isolation lines 200 can be uniformly formed with a depth H200 over the entire area of one surface or the other surface of the semiconductor substrate 110A while minimizing the contamination of semiconductor equipment, thereby minimizing the defect rate of the edge isolation structure.

[0226] Hereinafter, a method of manufacturing a solar cell having such isolation lines 200 will be described.

[0227] Figures 25 to 35 FIG. is an illustration of a first embodiment of a solar cell manufacturing method for forming an isolation structure of a solar cell according to a second embodiment of the present disclosure.

[0228] The solar cell manufacturing method according to the present embodiment may include a texturing step S11, a controlled passivation layer deposition step S12, a first conductive region 170A formation step S13, S15, a second conductive region 120A formation step S14, S15, an isolation step S16, a passivation layer deposition step S17, and an electrode formation step S18.

[0229] The first conductive region 170A formation steps S13, S15 may include a polysilicon layer deposition step S13 and a heat treatment step S15, while the second conductive region 120A formation steps S14, S15 may include a dopant layer formation step S14 and a heat treatment step S15. The isolation step S16 may be performed after the first conductive region formation step and the second conductive region formation step are completed, and may include a coating step S61, an etching step S62, and a cleaning step S63.

[0230] In the texturing step S11, recesses and protrusions may be formed by texturing one surface 110S1 and the other surface 110S2 or the other surface 110S2 of the semiconductor substrate 110. For example, as Figure 26 shown, in the texturing step S11, textured recesses and protrusions may be formed on the other surface 110S2 of the semiconductor substrate 110A.

[0231] More specifically, after textured recesses and protrusions are formed on one surface 110S1 and the other surface of the semiconductor substrate 110A, the surface 110S1 of the semiconductor substrate 110 may be polished to remove the textured recesses and protrusions, so that textured recesses and protrusions are formed only on the other surface 110S2 of the substrate 110A. However, the texturing step S11 is not limited to Figure 26 the case shown and may be modified. Hereinafter, for ease of description, the case asFigure 26 The situation shown is taken as an example.

[0232] In the step S17 of controlling the deposition of the passivation layer, as Figure 27 shown, the control passivation layer 160A can be formed on one surface 110S1 and the side surface of the semiconductor substrate 110A. To this end, the control passivation layer 160A can be deposited on one surface 110S1 and the side surface of the semiconductor substrate 110A by an oxide film deposition method. Here, for single-sided deposition, two semiconductor substrates 110A can be folded to face each other, and then an oxide film can be deposited.

[0233] In the step of forming the first conductive region 170A, the first conductive region 170A doped with a dopant of the first conductive type can be formed on the polysilicon layer 170' on one surface 110S1 of the semiconductor substrate 110A having the base region 10A (i.e., on the polysilicon layer 170A on the control passivation layer 160A). To this end, the step of forming the first conductive region 170A can include a polysilicon layer deposition step S13 and a heat treatment step S15.

[0234] In the step of forming the second conductive region 120A, the second conductive region 120A doped with a dopant of the second conductive type opposite to that of the first conductive region 170A can be formed on the other surface 110S2 of the semiconductor substrate 110A. To this end, the step of forming the second conductive region 120A can include a dopant layer formation step S14 and a heat treatment step S15.

[0235] In addition, the heat treatment step S15 of the step of forming the first conductive region 170A and the heat treatment step S15 of the step of forming the second conductive region 120A can be executed simultaneously.

[0236] Hereinafter, the situation of executing the dopant layer formation step S14 after the polysilicon layer deposition step S13 will be described as an example. However, alternatively, the polysilicon layer deposition step S13 can also be executed after the dopant layer formation step S14.

[0237] In the polysilicon layer deposition step S13, as Figure 28 shown, in order to form the first conductive region 170A, a polysilicon layer 170'A with a thickness of 200 nm to 400 nm can be deposited on one surface 110S1 of the semiconductor substrate 110A (i.e., on the control passivation layer) using CVD equipment. Here, in order to prevent the polysilicon layer 170'A from being deposited on an unnecessary surface, for single-sided deposition, the polysilicon layer 170'A can be deposited in a state where two semiconductor wafers are folded to face each other.

[0238] Here, the polysilicon layer may also be formed on the side surface of the semiconductor substrate 110A to have a thickness less than the thickness formed on one surface 110S1 of the semiconductor substrate 110A, and is formed on one surface 110S1 of the semiconductor substrate 110A, and may also be locally deposited on the edge portion of the other surface 110S2 of the semiconductor substrate 110A. Here, different from the central portion of the semiconductor substrate on which the polysilicon layer 170'A is deposited in the range of 200 nm to 400 nm, the polysilicon layer 170'A may be deposited at the edge portion to have a thickness of about 1 um. The first conductive type dopant may be doped into the polysilicon layer 170'A.

[0239] In addition, in the polysilicon layer deposition step S13 of the present embodiment, the case where the polysilicon layer 170'A is deposited on one surface 110S1 of the semiconductor substrate 110A from the beginning will be described as an example, but the present disclosure is not limited thereto. That is, an amorphous silicon layer may be deposited on one surface 110S1 of the semiconductor substrate 110A, and the amorphous silicon layer may be heat-treated in a subsequent heat treatment step S15 to form the polysilicon layer 170'A. However, here, the amorphous silicon layer should be deposited about several micrometers thicker than the polysilicon layer.

[0240] As Figure 29 shown, in the dopant layer formation step S14, a dopant layer 190A containing a second conductive type dopant may be formed on the other surface 110S2 of the semiconductor substrate 110A to form a second conductive region 120A. The dopant layer 190A may be, for example, a borosilicate glass (BSG) film. However, the present disclosure is not limited thereto, and the dopant layer 190A may only need to include a dopant of a conductive type opposite to that of the first conductive region 170A. For example, a phosphosilicate glass (PSG) film or another conductive type dopant may be included.

[0241] As Figure 29 shown, both ends of the dopant layer 190A formed on the other surface 110S2 of the semiconductor substrate 110A through the dopant layer formation step may be connected to the ends of the polysilicon layer 170'A containing the first conductive type dopant in an overlapping manner.

[0242] For example, the heat treatment step S15 may be performed after the polysilicon layer deposition step S13 and the dopant layer formation step S14 and before the coating step S61 of the isolation step S16. For example, the semiconductor substrate 110A may be heat-treated at 800 °C to 1000 °C.

[0243] As Figure 30As shown, the first conductive type dopant contained in the polysilicon layer 170′A can be activated through the heat treatment step S15 so that the polysilicon layer 170′ can be formed into a first conductive region 170A, and the second conductive type dopant contained in the dopant layer 190A can be diffused into the other surface 110S2 of the semiconductor substrate 110A to form a second conductive region 120A at a portion of the base region 10A of the semiconductor substrate 110A.

[0244] Here, the thickness T170A of the first conductive region 170A may be 300 nm to 400 nm, and the thickness T120A of the second conductive region 120A may be 0.1 um to 2.5 um.

[0245] After the heat treatment step S15, Figure 31 As shown, the dopant layer 190 disposed on the other surface 110S2 of the semiconductor substrate 110A may be removed by a separate etching solution. Here, the semiconductor substrate 110A or the first conductive region and the second conductive region may not be etched.

[0246] Even after the dopant layer 190A is removed as described above, it is possible to form Figure 31 The structure shown has ends of the first conductive region 170A and the second conductive region contact each other at an edge portion of the other surface 110S2 of the semiconductor substrate 110A, which may reduce the efficiency of the solar cell.

[0247] Therefore, the isolation step S16 of removing the short circuit between the first conductive region 170A and the second conductive region 120A may be performed.

[0248] As in the present embodiment, the isolation step S16 may be performed after the heat treatment step S15. However, this is merely an example, and alternatively, the isolation step S16 may be performed between the heat treatment step S15 and the later step among the polysilicon layer deposition step S13 and the dopant layer formation step S14, or between the polysilicon layer deposition step S13 and the dopant layer formation step S14.

[0249] The isolation step S16 may include a coating step S61 , an etching step S62 , and a cleaning step S63 .

[0250] Through the isolation step S16, the first conductive region 170A and the second conductive region 120A can be electrically insulated from each other, and a portion of the semiconductor substrate 110A can be etched from one surface 110S1 or the other surface 110S2 of the semiconductor substrate 110A to form an isolation line 200 in which a portion of the first conductive region 170A or the second conductive region 120A is removed.

[0251] For the isolation step S16, in the coating step S61, the etch paste 210 can be coated adjacent to the edge of one surface 110S1 or the other surface 110S2 of the semiconductor substrate 110A.

[0252] As a specific example, as Figure 32 shown, the etch paste 210 can be coated spaced apart from the edge of the first conductive region 170A provided on one surface 110S1 of the semiconductor substrate 110A.

[0253] Here, as Figure 23 shown in (a) below, the etch paste 210 coated on the edge of the first conductive region 170A of the semiconductor substrate 110A can be coated outside the region where the finger electrodes 151A are formed on one surface 110S1 of the semiconductor substrate 110A, parallel to the edge of the semiconductor substrate 110A, and can generally have a closed-loop shape.

[0254] The etch paste 210 can be coated at a distance D2 of 2 mm or less from the edge of the first conductive region 170A.

[0255] Here, the aspect ratio of the etch paste 210 (i.e., the thickness T210 of the etch paste 210 / line width W210) can be from 0.1 to 1. Here, the thickness T210 of the etch paste 210 can be, for example, 2 μm to 500 μm, and the line width W210 of the etch paste 210 can be in the range of 20 μm to 500 μm that is equal to or greater than the thickness T210 of the etch paste 210.

[0256] The etch paste 210 can include polymer particles and an etch material. The polymer particles can include at least one of polystyrene, polyacrylate, polyamide, polyimide, and polymethacrylate, melamine, polyurethane, benzoguanamine, phenolic resin, silicone resin, fluorinated polymer, and micronized wax, and the etch material can include at least one of ammonium bifluoride (NH4HF2) and phosphoric acid (H3PO4).

[0257] In the etching step S62, the etch paste 210 can be used to etch the portion adjacent to the edge in the semiconductor substrate 110 to form an isolation line 200 as Figure 33 shown.

[0258] In the etching step S62, when the etch material of the etch paste 210 contains ammonium bifluoride (NH4HF2), the etching step S62 can be performed in the range of 15°C to 40°C. When the etch material of the etch paste 210 contains phosphoric acid (H3PO4), the etching step S62 can be performed in the range of 400°C to 450°C for 1 minute to 5 minutes.

[0259] As Figure 33As shown, the line width W200 of the isolation line 200 etched in the etching step S62 can be from 20 um to 500 um, and the depth H200 of the isolation line etched in the etching step S62 can be from 2 um to 5 um within a range greater than the thickness T170A of the first conductive region 170A. More specifically, the isolation line 200 can have a depth of 3 um to 4 um within a range greater than the thickness T170A of the first conductive region 170A.

[0260] Therefore, in the etching step S62, not only can a part of the first conductive region 170A be etched, but also a part of the base region 10A of the semiconductor substrate 110A can be etched.

[0261] Therefore, in the etching step S62, a part of the first conductive region 170A can be etched to expose the base region 10A of the semiconductor substrate 110A.

[0262] Therefore, the first conductive region 170A (i.e., the first conductive region 170A located outside the isolation line 200 at the edge portion, side surface, and one surface 110S1 of the semiconductor substrate 110A of the other surface 110S2 of the semiconductor substrate 110A) electrically connected to the second conductive region 120A at the edge portion of the other surface 110S2 of the semiconductor substrate 110A can be electrically isolated from the first conductive region 170A located inside the isolation line 200 on one surface 110S1 of the semiconductor substrate 110A, and thus, the first conductive region 170A and the second conductive region 120A can be electrically isolated from each other.

[0263] Thereafter, a cleaning step S63 can be performed to remove the etching paste 210.

[0264] In the cleaning step S63, deionized water (DI) can be used, and organic solvents such as IPA, ethanol, and methanol, which are common paste cleaning materials, are diluted in the deionized water (DI). For example, 0.1 wt% of KOH can be added to the deionized water.

[0265] After the isolation step S16 is completed, as Figure 34 shown, in the passivation layer deposition step S17, a first passivation layer 180A can be deposited on the first conductive region 170A and a second passivation layer 130A can be deposited on the second conductive region 120A.

[0266] Figure 34 An example is illustrated in which the first passivation layer 180A is deposited first and then the second passivation layer 130A is deposited. However, the deposition order of the first passivation layer 180A and the second passivation layer 130A is not limited thereto. On the contrary, the second passivation layer 130A can be deposited first, and then the first passivation layer 180A can be deposited.

[0267] As described above, since the first passivation layer 180A is deposited on the first conductive region 170A where the isolation line 200 is formed, the first passivation layer 180A can be formed to penetrate the first conductive region 170A and contact the base region 10 of the semiconductor substrate 110A at the portion where the isolation line 200 is located, and the first passivation layer 180A can be formed to contact the first conductive region 170A at the portion where the isolation line 200 is not located.

[0268] Therefore, the base region 10A of the semiconductor substrate 110A exposed in the etching step S62 can be covered by the first passivation layer 180A in the passivation layer deposition step S17, so that the base region 10A of the semiconductor substrate 110A exposed at the isolation line 200 can be passivated by the first passivation layer 180A.

[0269] In addition, the second passivation layer 130A can be formed to contact the second conductive region 120A on the other surface 110S2 of the semiconductor substrate 110A.

[0270] Thereafter, in the electrode formation step S18, as Figure 35 shown, a first electrode 150A passing through the first passivation layer 180A and connected to the first conductive region 170A and a second electrode 140A passing through the second passivation layer 130A and connected to the second conductive region 120A can be formed.

[0271] Here, the first electrode 150A and the second electrode 140A can be formed inside the isolation line 200, and the patterns of the first electrode 150A and the second electrode 140A can be the same as those described above with reference to Figure 1 and Figure 2 and Figure 23 and Figure 24 and

[0272] Therefore, the solar cell described above with reference to Figure 1 and Figure 2 and Figure 23 in (a) and Figure 24 can be manufactured.

[0273] Above, an example of a method for forming the isolation line 200 on one surface 110S1 of the semiconductor substrate 110A has been described. Hereinafter, a modification of the first embodiment will be described, in which the isolation line 200 is formed on the other surface 110S2 of the semiconductor substrate 110.

[0274] The method for manufacturing a solar cell according to the present embodiment may have the same process sequence as the method for manufacturing a solar cell according to the Figures 25 to 35 first embodiment.

[0275] However, in accordance with Figure 25In the isolation step S16 of the method for manufacturing a solar cell according to the first embodiment shown, an isolation line can be formed on the other surface 110S2 of the semiconductor substrate 110A.

[0276] The method for manufacturing a solar cell according to this variant may include a texturing step S11, a controlled passivation layer deposition step S12, a first conductive region 170A formation step S13, S15, a second conductive region 120A formation step S14, S15, an isolation step S16, a passivation layer deposition step S17, and an electrode formation step S18. Therefore, hereinafter, the process configurations and sequences that are the same as those of the first embodiment shown will be omitted, and the different parts will be mainly described. Figures 25 to 35 In the method for manufacturing a solar cell according to this variant, after the heat treatment step S15 shown, an etching paste 210 can be applied in the coating step S61 shown, adjacent to the edge of the other surface 110S2 of the semiconductor substrate 110A.

[0277] In the method for manufacturing a solar cell according to this variant, Figure 25 after the heat treatment step S15 shown, an etching paste 210 can be applied in the coating step S61 shown, adjacent to the edge of the other surface 110S2 of the semiconductor substrate 110A. Figure 36 More specifically, the etching paste 210 can be applied to be spaced apart from the edge of the second conductive region 120A located on the other surface 110S2 of the semiconductor substrate 110A.

[0278] Here, the material, position, thickness, width, and coating pattern of the applied etching paste 210 can be the same as those described in the first embodiment above.

[0279] Therefore, the etching paste 210 can be applied at a distance of 2 mm or less from the edge of the second conductive region 120A. Figures 25 to 35 in the first embodiment above.

[0280] Thereafter, the depth H200 of the isolation line 200 etched through the etching step S62 can be etched to 2 μm to 5 μm within a range greater than the thickness T120A of the second conductive region 120A. More specifically, the isolation line 200 can be formed to a depth of 3 μm to 4 μm within a range greater than the thickness T120A of the second conductive region 120A. Therefore, through the etching step S62, not only a part of the second conductive region 120A can be etched, but also a part of the base region 10A of the semiconductor substrate 110A can be etched.

[0281] Therefore, a part of the second conductive region 120A can be etched in the etching step S62 to expose the base region 10A of the semiconductor substrate 110A.

[0282]

[0283] ​Therefore, when the isolation line 200 is located on the other surface 110S2 of the semiconductor substrate 110A, the base region 10A of the semiconductor substrate 110A exposed in the etching step S62 can be covered by the second passivation layer 130A in the passivation layer deposition step S17. Thus, the second passivation layer 130A can contact the base region 10A of the semiconductor substrate 110A through the second conductive region 120A at the portion where the isolation line 200 is located.

[0284] Thereafter, as Figure 39 shown, the first electrode 150A connected to the first conductive region 170A through the first passivation layer 180A and the second electrode 140A connected to the second conductive region 120A through the second passivation layer 130A can be formed in the electrode formation step S18.

[0285] Therefore, the solar cell described above with reference to Figure 24 FIG. (b) can be manufactured.

[0286] In the method for manufacturing a solar cell according to the first embodiment of Figures 25 to 35 and the variant of Figures 36 to 39 , an example of performing the isolation step S16 after the heat treatment step S15 is described, but the present disclosure is not limited thereto, and the isolation step S16 can be performed before the heat treatment step S15. This will be described below.

[0287] Figures 40 to 43 FIG. is a diagram illustrating a second embodiment of a method for manufacturing a solar cell for forming an isolation structure of a solar cell according to a second embodiment of the present disclosure.

[0288] As Figure 40 shown, the method for manufacturing a solar cell according to the present embodiment may include a texturing step S11, a control passivation layer deposition step S12, a first conductive region 170A formation step S13, S15, a second conductive region 120A formation step S14, S15, an isolation step S16, a passivation layer deposition step S17, and an electrode formation step S18.

[0289] The first conductive region 170A formation steps S13, S15 may include a polysilicon layer deposition step S13 and a heat treatment step S15. The second conductive region 120A formation step may include a dopant layer formation step S14 and a heat treatment step S15. The isolation step S16 can be performed between the first conductive region formation step and the second conductive region formation step, and the isolation step S16 includes a coating step S61, an etching step S62, and a cleaning step S63.

[0290] The isolation step S6 can be performed between the heat treatment step S15 and the polysilicon layer deposition step S13 of the first conductive region 170A forming step, and between the heat treatment step S15 and the dopant layer forming step S14 of the second conductive region 120A forming step.

[0291] Therefore, when the heat treatment step S15 of the first conductive region 170A forming step and the heat treatment step S15 of the second conductive region 120A forming step are performed simultaneously, the isolation step S16 can be performed between the dopant layer forming step S14 and the heat treatment step S15.

[0292] Therefore, when the dopant layer forming step S14 is performed after the polysilicon layer deposition step S13, the isolation step S16 can be performed after the dopant layer forming step S14 and before the heat treatment step S15, as Figure 40 shown.

[0293] In the method for manufacturing a solar cell according to the present embodiment, the texturing step S11, the controlled passivation layer deposition step S12, the polysilicon layer deposition step S13, and the dopant layer forming step S14 are the same as those of the method for manufacturing a solar cell according to the Figure 25 first embodiment described above, and thus detailed description thereof will be omitted.

[0294] In the method for manufacturing a solar cell according to the present embodiment, the coating step S61, the etching step S62, and the cleaning step S63 included in the isolation step S16 can be performed on one surface 110S1 of the semiconductor substrate between the dopant layer forming step S14 and the heat treatment step S15.

[0295] Therefore, after the dopant layer forming step S14, as Figure 41 shown, in the coating step S61 of the isolation step S16, the etching paste 210 can be coated adjacent to the edge of the polysilicon layer 170'A deposited on one surface 110S1 of the semiconductor substrate 110A to form the first conductive region 170A.

[0296] In this case, the material, position, line pattern, line width, and thickness of the coated etching paste 210 can be the same as those described in the Figures 25 to 39 embodiment above.

[0297] Thereafter, the etching step S62 can be performed, and as Figure 42 shown, the etching step S62 and the cleaning step S63 can be performed.

[0298] Therefore, as Figure 42 shown, a part of the polysilicon layer 170'A can be etched to expose the base region 10A of the semiconductor substrate 110A.

[0299] As described above, after the isolation step S16 is completed, the heat treatment step S15 may be performed so that the dopant of the first conductivity type contained in the polysilicon layer 170'A on one surface 110S1 of the semiconductor substrate 110A can be activated to allow the polysilicon layer 170'A to be formed as the first conductive region 170A, and the dopant of the second conductivity type contained in the dopant layer 190A can diffuse into the other surface 110S2 of the semiconductor substrate 110A to form the second conductive region 120A at a part of the base region 10A of the semiconductor substrate 110A.

[0300] In the present embodiment, since the isolation step S16 is performed before the heat treatment step S15, the first conductive region 170A and the second conductive region 120A can be electrically isolated from each other even after the heat treatment step S15.

[0301] After the heat treatment step S15, as Figure 40 shown, the passivation layer deposition step S17 and the electrode formation step S18 may be performed to fabricate a solar cell according to an embodiment of the present disclosure.

[0302] Therefore, since the first passivation layer 180A is deposited on the first conductive region 170A on which the isolation line 200 is formed, the first passivation layer 180A can contact the base region 10A of the semiconductor substrate 110A through the first conductive region 170 at the portion where the isolation line is located, and the first passivation layer 180A can contact the first conductive region 170A at the portion where the isolation line 200 is not located.

[0303] In addition, the second passivation layer 130A may contact the second conductive region 120A on one surface 110S1 of the semiconductor substrate 110A.

[0304] In addition, in the method for manufacturing a solar cell according to the present embodiment, the isolation step S16 may be performed on the other surface 110S2 of the semiconductor substrate 110A. This will be described in more detail below.

[0305] Figures 44 to 46 is an example of Figures 40 to 43 a diagram showing a variation of the second embodiment shown.

[0306] The process configuration and sequence of the method for manufacturing a solar cell according to this variation may be the same as those of the method for manufacturing a solar cell described above Figure 40 shown, and may include a texturing step S11, a control passivation layer deposition step S12, a first conductive region 170A formation step S13, S15, a second conductive region 120A formation step S14, S15, an isolation step S16, a passivation layer deposition step S17, and an electrode formation step S18.

[0307] The steps S13 and S15 for forming the first conductive region 170A may include a polysilicon layer deposition step S13 and a heat treatment step S15, and the steps S14 and S15 for forming the second conductive region 120A may include a dopant layer formation step S4 and a heat treatment step S5, and the isolation step S6 may include a coating step S61, an etching step S62, and a cleaning step S63.

[0308] Therefore, hereinafter, the process configurations and sequences identical to those of the second embodiment shown will be omitted, and the different parts will be mainly described. Figure 40 In the method for manufacturing a solar cell according to this variant, an isolation step S16 including a coating step S61, an etching step S62, and a cleaning step S63 may be performed on the other surface 110S2 of the semiconductor substrate 110 between the dopant layer formation step S14 and the heat treatment step S15.

[0309]

[0310] Figure 40 Therefore, after the dopant layer formation step S14 shown, as Figure 44 shown, in the coating step S61 of the isolation step S16, the etching paste 210 may be adjacent to the edge of the other surface 100S2 of the semiconductor substrate 110A.

[0311]

[0312] More specifically, the etching paste 210 may be coated at a distance from the edge of the dopant layer 190A located on the other surface 110S2 of the semiconductor substrate 110A.

[0313] Here, the material, position, thickness, width, and coating pattern of the coated etching paste 210 may be the same as those described in the previous embodiment above.

[0313] Therefore, the etching paste 210 may be coated at a distance of 2 mm or less from the edge of the dopant layer 190A.

[0314] Next, as Figure 46 shown, by the etching step S62, the depth H200 of the etched isolation line 200 may be etched to be 2 um to 5 um in a range greater than the sum of the thicknesses of the dopant layer 190A and the second conductive region 120A formed by the dopant layer 190A, and more specifically, the isolation line 200 may be formed to have a depth of 3 um to 4 um in a range greater than the sum of the thicknesses of the dopant layer 190A and the second conductive region 120A formed by the dopant layer 190A.

[0315] Therefore, by the etching step S62, not only a part of the dopant layer 190A but also a part of the base region 10A of the semiconductor substrate 110A can be etched.

[0316] Therefore, in the etching operation S62, a part of the dopant layer 190A can be etched to expose the base region 10A of the semiconductor substrate 110A.

[0317] Thereafter, a heat treatment step S15 can be performed at 800 °C to 1000 °C so that the first conductivity type dopant contained in the polysilicon layer 170'A can be activated to form the polysilicon layer 170'A into the first conductive region 170A, and the second conductivity type dopant contained in the dopant layer 190A can diffuse into the other surface 110S2 of the semiconductor substrate 110A with a thickness less than the depth H200 of the isolation line 200 to form the second conductive region 120A at a part of the base region 10A of the semiconductor substrate 110A, as Figure 46 shown.

[0318] For example, the thickness of the first conductive region 170A can be 300 nm to 400 nm, while the thickness of the second conductive region 120A can be in the range of 1.5 um to 2.5 um at a thickness thinner than the depth H200 of the isolation line 200.

[0319] Thereafter, as Figure 40 shown, a passivation layer deposition step S17 and an electrode formation step S18 can be performed. The passivation layer deposition step S17 and the electrode formation step S18 can be the same as the above in the solar cell manufacturing method according to the Figure 40 embodiment.

[0320] Therefore, when the isolation line 200 is located on the other surface 110S2 of the semiconductor substrate 110A, the base region 10A of the semiconductor substrate 110A exposed in the etching step S62 can be covered by the second passivation layer 130A in the passivation layer deposition step S17, and thus, the second passivation layer 130A can contact the base region 10A of the semiconductor substrate 110A through the second conductive region 120A at the part where the isolation line 200 is located.

[0321] In addition, the first passivation layer 180A can be formed to contact the first conductive region 170A on one surface 110S1 of the semiconductor substrate 110A.

[0322] In addition, in the solar cell manufacturing method according to the present embodiment, an isolation step S16 can be performed between the polysilicon layer deposition step S13 and the dopant layer formation step S14.

[0323] For example, when the dopant layer formation step S14 is performed after the polysilicon layer deposition step S13 or the polysilicon layer deposition step S13 is performed after the dopant layer formation step S14, the isolation step S16 can be performed between the polysilicon layer deposition step S13 and the dopant layer formation step S14.

[0324] Hereinafter, the case where the isolation step S16 is performed between the polysilicon layer deposition step S13 and the dopant layer formation step S14 when the dopant layer formation step S14 is performed after the polysilicon layer deposition step S13 will be described.

[0325] Figures 47 to 51 FIG. is a diagram illustrating a third embodiment of a method for manufacturing a solar cell, which forms an isolation structure of a solar cell according to a second embodiment of the present disclosure.

[0326] As Figure 47 shown, the method for manufacturing a solar cell according to the present embodiment may include a texturing step S11, a controlled passivation layer deposition step S12, and a first conductive region 170A formation step S13, S15, an isolation step S16, a second conductive region 120A formation step S14, S15, a passivation layer deposition step S17, and an electrode formation step S18.

[0327] The first conductive region 170A formation steps S13, S15 may include a polysilicon layer deposition step S13 and a heat treatment step S15, while the second conductive region 120A formation steps S14, S15 may include a dopant layer formation step S14 and a heat treatment step S15. The isolation step S16 may include a coating step S61, an etching step S62, and a cleaning step S63. The isolation step S16 can be performed in the middle of performing the first conductive region 170A formation step.

[0328] Therefore, as Figure 47 shown, when the dopant layer formation step S14 is performed after the polysilicon layer deposition step S13, the isolation step S16 can be performed between the polysilicon layer deposition step S13 and the dopant layer formation step S14.

[0329] In the method for manufacturing a solar cell according to the present embodiment, the texturing step S11, the controlled passivation layer deposition step S12, and the polysilicon layer deposition step S13 are the same as those of the method for manufacturing a solar cell according to the embodiment described above, and thus their detailed descriptions will be omitted.

[0330] In the method for manufacturing a solar cell according to the present embodiment, the coating step S61, the etching step S62, and the cleaning step S63 included in the isolation step S16 can be performed on one surface 110S1 of the semiconductor substrate 110 between the polysilicon layer deposition step S13 and the dopant layer formation step S4.

[0331] Therefore, after the polysilicon layer deposition step S13, as Figure 48 shown, in the coating step S61 of the isolation step S16, the etching paste 210 can be coated adjacent to the edge of the polysilicon layer 170'A deposited on one surface 110S1 of the semiconductor substrate 110A to form the first conductive region 170A.

[0332] Here, the material, position, line pattern, line width, and thickness of the coated etching paste 210 can be the same as those described above in the embodiments.

[0333] Thereafter, the etching step S62 can be performed, and as Figure 49 shown, the etching step S62 and the cleaning step S63 can be performed.

[0334] Therefore, as Figure 49 shown, a part of the polysilicon layer 170'A can be etched to expose the base region 10A of the semiconductor substrate 110A.

[0335] As described above, after completing the isolation step S16, as Figure 50 shown, the dopant layer formation step S14 of forming the dopant layer 190A on the other surface 110S2 of the semiconductor substrate 110A can be performed.

[0336] Thereafter, as Figure 51 shown, the heat treatment step S15 can be performed so that the first conductive type dopant contained in the polysilicon layer 170'A located on one surface 110S1 of the semiconductor substrate 110A can be activated to form the polysilicon layer 170'A into the first conductive region 170A, and the second conductive type dopant contained in the dopant layer 190A can diffuse into the other surface 110S2 of the semiconductor substrate 110A to form the second conductive region 120A at a part of the base region 10A of the semiconductor substrate 110A.

[0337] According to this embodiment, since the isolation step S16 is first performed between the polysilicon layer deposition step S13 and the heat treatment step S15, the first conductive region 170A and the second conductive region 120A can be electrically isolated from each other even after the heat treatment step S15.

[0338] After the heat treatment step S15, as Figure 47 shown, the passivation layer deposition step S17 and the electrode formation step S18 can be performed to fabricate a solar cell.

[0339] Therefore, since the first passivation layer 180A is deposited on the first conductive region 170A where the isolation line 200 is formed, the first passivation layer 180A can contact the base region 10A of the semiconductor substrate 110A through the first conductive region 170A at the portion where the isolation line 200 is located, and the first passivation layer 180A can contact the first conductive region 170A at the portion where the isolation line 200A is not located.

[0340] In addition, the second passivation layer 130A can be formed to contact the second conductive region 120A on one surface 110S1 of the semiconductor substrate 110A.

[0341] As described above, in the method for manufacturing a solar cell according to the present disclosure, since the isolation line 200 is formed by applying the etching paste 210 to an edge of one surface 110S1 or another surface of the semiconductor substrate 110A to etch elements located below the etching paste, contamination of semiconductor equipment can be minimized, and since the etching paste 210 is uniformly applied to each solar cell, the defect rate of the edge isolation structure can be minimized.

[0342] In addition, in the solar cell and its manufacturing method according to an embodiment of the present disclosure, since the edge isolation structure is formed by applying the etching paste 210 to perform etching, the manufacturing process can be simplified.

Claims

1. A method for manufacturing a solar cell, the method comprising the following steps: A polysilicon layer forming operation, which forms a polysilicon layer containing a first dopant on the back surface, side surface, and edge portion of the front surface of a semiconductor substrate formed of single-crystalline silicon material including a base region; A front surface texturing operation, which textures the front surface of the semiconductor substrate and simultaneously removes the polysilicon layer formed on the front surface of the semiconductor substrate and a part of the polysilicon layer on the side surface; A second conductive region forming operation, which diffuses a second dopant on the front surface of the semiconductor substrate to form a second conductive region; A passivation layer forming operation, which forms a first passivation layer on the polysilicon layer formed on the back surface of the semiconductor substrate and a second passivation layer on the second conductive region on the front surface of the semiconductor substrate; And An electrode forming operation, which forms a first electrode passing through the first passivation layer and connected to the polysilicon layer and a second electrode passing through the second passivation layer in the second conductive region, wherein the front surface texturing operation is performed by wet etching, in which, in a state where the front surface of the semiconductor substrate is in contact with a roller partially immersed in a texturing etching solution, when the roller rotates, the texturing etching solution present on the surface of the roller etches the front surface of the semiconductor substrate to form textured recesses and protrusions on the front surface of the semiconductor substrate, and the texturing etching solution present on the surface of the roller etches a part of the polysilicon layer formed on the side surface of the semiconductor substrate.

2. The method according to claim 1, wherein, The second conductive region forming operation includes: A dopant layer forming operation, which forms a dopant layer having a second dopant on the front surface of the semiconductor substrate; And A heat treatment operation, which performs heat treatment on the semiconductor substrate to diffuse the second dopant of the dopant layer to the front surface of the semiconductor substrate.

3. The method according to claim 1 or 2, the method further comprising the following steps: Before forming the polysilicon layer, a control passivation layer is formed on the entire surface of the semiconductor substrate.

4. The method according to claim 3, wherein, In the front surface texturing operation, the control passivation layer and the polysilicon layer formed on the front surface of the semiconductor substrate are simultaneously removed.

5. The method according to claim 3, the method further comprising the following steps: A mask forming operation, which forms a mask layer for preventing texturing etching on the polysilicon layer on the back surface of the semiconductor substrate between the polysilicon layer forming operation and the front surface texturing operation.

6. The method according to claim 5, wherein, The mask forming operation includes: Forming the mask layer on the entire surface of the polysilicon layer and the entire front surface of the semiconductor substrate; and Remove portions of the mask layer other than the portions formed on the polysilicon layer formed on the back surface of the semiconductor substrate.

7. The method according to claim 6, wherein the front surface texturing operation is performed with the mask layer formed on the back surface of the semiconductor substrate, and in a state where the front surface of the semiconductor substrate having the mask layer formed thereon is in contact with a roller partially immersed in a texturing etching solution, when the roller rotates, the texturing etching solution present on the roller etches the front surface of the semiconductor substrate to form textured recesses and protrusions on the front surface of the semiconductor substrate, or the semiconductor substrate having the mask layer is immersed in the texturing etching solution filled in a tank to form textured recesses and protrusions on the front surface of the semiconductor substrate.

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