Memory device and method for dynamic error monitoring and repairing

Abstract

A memory device comprises: a memory cell array including a plurality of memory cells, the plurality of memory cells comprising a plurality of data storage cells including a first data storage cell and a plurality of backup storage cells including a first backup storage cell; a storage device storing an error table configured to record errors in the plurality of data storage cells, the error table comprising a plurality of error table entries, each error table entry corresponding to one of the plurality of data storage cells and having an address and a failure count; and a controller configured to replace the first data storage cell with the first backup storage cell based on the error table.

Description

Technical Field

[0001] The techniques described in embodiments of the present invention relate generally to memory devices, and more particularly to memory devices and methods of dynamic error monitoring and repair. Background Art

[0002] Memory devices are used to store information in semiconductor devices and systems. Nonvolatile memory devices are able to retain data even after the power is turned off. Examples of nonvolatile memory devices include flash memory, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase-change memory (PCM). MRAM, RRAM, FRAM, and PCM are sometimes referred to as emerging memory devices. Summary of the invention

[0003] An embodiment of the present invention provides a memory device, comprising: a memory cell array, comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data storage cells including a first data storage cell and a plurality of backup storage cells including a first backup storage cell; a storage device, storing an error table configured to record errors associated with the plurality of data storage cells, the error table comprising a plurality of error table entries, each error table entry corresponding to one of the plurality of data storage cells and having an address and a fault count; and a controller, configured to replace the first data storage cell with the first backup storage cell based on the error table.

[0004] An embodiment of the present invention provides a memory device, comprising: a memory cell array, comprising a plurality of memory cells, wherein the plurality of memory cells include a plurality of data storage cells and M backup storage cells, where M is an integer greater than one; a storage device, storing a repair table, wherein the repair table contains M repair table entries corresponding to the M data storage cells replaced by the M backup storage cells, each repair table entry having an address and a fault count; and a controller, configured to: update the repair table to generate an updated repair table; and replace at least one of the M data storage cells with at least one of the M backup storage cells based on the updated repair table.

[0005] An embodiment of the present invention provides a method for dynamic error monitoring and repair, comprising: providing a storage cell array including a plurality of storage cells, the plurality of storage cells including a plurality of data storage cells and a plurality of backup storage cells; detecting errors in the plurality of data storage cells by an error correction code circuit; generating an error table, the error table comprising a plurality of error table entries, each error table entry corresponding to one of the plurality of data storage cells and having an address and a fault count; and replacing a first data storage cell among the plurality of data storage cells with a first backup storage cell among the plurality of backup storage cells based on the error table. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion. In addition, the drawings are illustrative as examples of embodiments of the present invention and are not intended to be limiting.

[0007] Figure 1 is a block diagram illustrating an example memory device incorporating dynamic error monitoring and repair in accordance with some embodiments.

[0008] Figure 2 is an example error table according to some embodiments.

[0009] Figure 3 is a flow chart illustrating a method of updating an error table according to some embodiments.

[0010] Figure 4 is a flow chart illustrating a method of dynamic error monitoring and repair according to some embodiments.

[0011] Figure 5A is a schematic diagram illustrating a memory cell array with dynamic error monitoring and repair prior to any replacement in accordance with some embodiments.

[0012] Figure 5B is a diagram showing the implementation of some embodiments Figure 4 After the method Figure 5A Schematic diagram of a memory cell array.

[0013] Fig. 6A is a repair table according to some embodiments.

[0014] Figure 6B is another repair table according to some embodiments.

[0015] Figure 6C is yet another repair table according to some embodiments.

[0016] Figure 7is a flow chart illustrating a method of updating a repair table according to some embodiments.

[0017] Fig. 8A is a flow chart illustrating a method of dynamic error monitoring and repair according to some embodiments.

[0018] Figure 8B is a diagram showing the implementation of some embodiments Fig. 8A Schematic diagram of a memory cell array before the method.

[0019] Figure 8C is a diagram showing the implementation of some embodiments Fig. 8A After the method Figure 8B Schematic diagram of a memory cell array.

[0020] Fig. 9 is a flow chart of a method of dynamic error monitoring and repair according to some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0023] The manufacturing process of emerging memory devices such as ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase change memory (PCM) is still immature. Due to differences in manufacturing processes, characteristics and usage conditions among storage cells, the durability and reliability of storage cells may be different. As a result, "healthy" cells that can store data satisfactorily may fail over time, thereby recording incorrect storage data. In other words, those "healthy" cells become "faulty" cells, and the data bits stored in those "faulty" cells become "faulty" bits. In order to solve this type of memory failure, error correction codes (ECC) are sometimes used to detect and correct data errors. Different ECC schemes can be used. Specifically, the ECC circuit can detect errors and correct these errors during the operation of the memory device. Among other things, the ECC circuit may include an ECC encoder and an ECC decoder. The ECC encoder is configured to generate parity bits and form codewords, and the ECC decoder is configured to decode the codewords and provide correction data.

[0024] As the complexity of data stored in memory devices increases, error correction code (ECC) capabilities also increase. For example, some ECC functions are capable of correcting multiple data bits. For example, an ECC with a five-bit capacity is capable of correcting up to five-bit errors. However, as the complexity of data continues to increase, ECC may have difficulty providing the required data error correction.

[0025] According to some aspects of the present disclosure, an error table is generated and updated. The error table records both the memory address and the fault count of the faulty cell corresponding to the fault bit. Having an updated error table helps to better understand the state of the memory cell of the memory cell array, which in turn can be used for dynamic error monitoring and repair. In the repair process, a portion of the data storage unit that is a faulty unit is replaced with a backup storage unit based on the error table. When replacing the faulty unit, the corresponding fault bit is repaired. In one embodiment, the data storage unit with a fault count higher than the threshold fault count is replaced with a backup storage unit. In another embodiment, the M data storage units with the highest M fault counts are replaced with backup storage units, and M is the number of backup storage units. Thus, the data storage unit with a higher fault count is replaced before the data storage unit with a lower fault count is replaced. In yet another embodiment, the repair table records the address and fault count of the replacement storage unit. The repair table is updated periodically or after the error table is updated. Due to the limited number of backup storage units, the repair table can be "full" (i.e., all backup storage units have been used) after the memory device operates for a certain period of time. Therefore, the repair table is updated to replace any existing entries in the repair table with lower fault counts with any new entries with higher fault counts. Thus, the repair table always keeps a record of the entries with the highest fault counts, according to its capacity. When the repair table has any changes after the update, the replacement storage unit corresponding to the address removed from the repair table is restored (i.e., becomes a data storage unit again), thereby releasing a backup storage unit. The data storage unit corresponding to the address added to the repair table is replaced by the released backup storage unit. Therefore, according to the above embodiment, dynamic monitoring and repair are implemented based on the error table and / or the repair table, and the limited backup storage units are effectively used and dynamically adjusted.

[0026] Figure 1 1 is a block diagram illustrating an example memory device 100 incorporating dynamic error monitoring and repair according to some embodiments. In the depicted example, the example memory device 100 includes, among other things, a memory cell array 102, a controller 106, a voltage generation circuit 116, a row decoder 118, a word line control circuit 120, a column decoder 122, a bit line control circuit 124, a read circuit 126, a write circuit 130, an input / output (I / O) circuit 132, an ECC circuit 134, an error monitoring circuit 136, and a repair circuit 140.

[0027] The memory cell array 102 includes a plurality of memory cells 104 arranged in rows and columns. The memory cells 104 may include MRAM cells, RRAM cells, FRAM cells, and / or PCM cells, but other types of memory cells may also be used. For simplicity, each memory cell 104 stores one data bit, but other arrangements (e.g., two memory cells 104 store one data bit) are also within the scope of the present disclosure. In other words, one bit cell (i.e., a cell for storing one data bit) includes one memory cell 104.

[0028] The controller 106 includes, among other things, a control circuit 108, a command address latch circuit 110, a pulse generator circuit 112, and a storage device 114. The command address latch circuit 110 temporarily holds as input a command and an address received by the memory device 100. The command address latch circuit 110 transmits the command to the control circuit 108. The command address latch circuit 110 transmits the address to the row decoder 118 and the column decoder 122.

[0029] Row decoder 118 decodes the row address contained in the address and sends the row address to word line control circuit 120. Word line control circuit 120 selects a word line (corresponding to a specific row) of memory cell array 102 based on the decoded row address. Specifically, memory cells 104 in that specific row are accessed.

[0030] On the other hand, the column decoder 120 decodes the column address included in the address and sends the column address to the bit line control circuit 124. The bit line control circuit 124 selects a bit line (corresponding to a specific column) of the memory cell array 102 based on the decoded column address. Specifically, among all the memory cells 104 in that specific row, the memory cells 104 in that specific column are accessed, and data can be written to or read from the memory cells 104 in that specific row and specific column.

[0031] During a write operation, the write circuit 130 supplies various voltages and currents for writing data to the memory cell 104 selected based on the decoded row address and the decoded column address. The write pulse (i.e., the write pulse width) required for the write operation is generated by the pulse generator circuit 112. Figure 1 In the illustrated example, the pulse generator circuit 112 is located in the controller 106, but the pulse generator circuit 112 may be a separate component external to the controller 106. The write circuit 130 includes, among other things, a write driver that is not shown.

[0032] During a read operation, the read circuit 126 supplies various voltages and currents for data read from the memory cell 104 selected based on the decoded row address and the decoded column address. The read circuit 126 includes, among other things, a read driver and a sense amplifier 128, not shown. The sense amplifier 128 senses the relatively small difference between the voltages of the two complementary bit lines (i.e., BL and BLB) and amplifies the difference at the output of the sense amplifier 128.

[0033] The I / O circuit 132 is coupled to both the write circuit 130 and the read circuit 126. During a write operation, the I / O circuit 132 temporarily holds data to be written and transmits the data to be written to the write circuit 130. On the other hand, during a read operation, the I / O circuit 132 temporarily holds data read by the read circuit 126.

[0034] The voltage generating circuit 116 generates various voltages for the operation of the memory device 100 by using a power supply voltage external to the memory device 100. The various voltages generated by the voltage generating circuit 116 may be applied to components of the memory device 100, such as the controller 106, the row decoder 118, the word line control circuit 120, the column decoder 122, the bit line control circuit 124, the read circuit 126, the write circuit 130, the I / O circuit 132, the ECC circuit 134, the error monitoring circuit 136, and the repair circuit 140.

[0035] The control circuit 108 receives commands from the command address latch circuit 110. In response to the commands, the control circuit 108 controls the operation of components of the memory device 100, such as the controller 106, the row decoder 118, the word line control circuit 120, the column decoder 122, the bit line control circuit 124, the read circuit 126, the write circuit 130, the I / O circuit 132, the pulse generator circuit 112, the storage device 114, the command address latch circuit 110, the voltage generation circuit 116, the ECC circuit 134, the error monitoring circuit 136, and the repair circuit 140.

[0036] The ECC circuit 134 may employ various methods of ECC error detection and ECC error correction, but other methods may also be employed. ECC schemes are used to detect and correct bit errors stored in a memory device. The ECC circuit 134 may encode data by generating ECC check bits (e.g., redundant bits or parity bits), which are stored in the memory device together with the data. The data bits and the check (e.g., parity) bits together form a codeword. Many schemes have been developed to implement ECC, including Hamming codes, triple modular redundancy, etc. For example, a Hamming code is a class of binary linear block codes that can detect up to two bit errors per codeword or correct one bit error without detecting an uncorrected error, depending on the number of parity bits utilized. Several schemes have been developed, but in general, if the parity bits are arranged within the codeword so that different incorrect bits produce different error results, then the bit in error can be identified. For a codeword with an error, the pattern of the error is called an (error) syndrome and the bit in error is identified. The Hamming code can be decoded using a syndrome decoding method. In the syndrome decoding method, the syndrome is calculated by multiplying the received codeword with the transposed matrix of the parity check matrix. Specifically, any valid codeword multiplied by the transposed matrix of the parity check matrix is ​​equal to zero, while any invalid codeword multiplied by the transposed matrix of the parity check matrix is ​​not equal to zero. The parity check matrix H of ECC is a matrix that describes the linear relationship that the components of the codeword must satisfy. The parity check matrix H can be used to determine whether a particular vector is a codeword. The parity check matrix H can also be used in a decoding algorithm. The calculation of the syndrome is performed by a syndrome calculation circuit, which can be implemented as an exclusive OR (XOR) tree. Each XOR tree has multiple data bits as input.

[0037] In one non-limiting example, an ECC that generates 8 parity bits for 64 data bits can typically detect two bit errors and correct one bit error among the 64 data bits, which is called a DED / SEC code, which means double-error detecting (DED) and single-error correcting (SEC). In another example, a DED / DEC scheme, which means double-error detecting (DED) and double-error correcting (DEC), can be used. In yet another example, a SED / SEC scheme, which means single-error detecting (SED) and single error correction (SEC), can be used. The ECC circuit 134 is configured to detect and correct errors that occur in a faulty cell during transmission or storage. Among other things, the ECC circuit 134 may include an unillustrated error detection module and an unillustrated error correction module.

[0038] The error monitoring circuit 136 is coupled to the ECC circuit 134, the controller 106, and the repair circuit 140. The error monitoring circuit 136 is configured to monitor errors that occur in failed cells during transmission or storage. Based on the errors monitored by the error monitoring circuit 136, the controller 106 may generate an error table 138 and / or a repair table 142 for dynamic error monitoring and repair. The error table 138 and the repair table 142 are referred to below, respectively. Figure 2 and FIG. 6A to FIG. 6C The error table 138 and the repair table 142 are both stored in the storage device 114. It should be noted that the error monitoring circuit 136 can be as follows: Figure 1 Although shown as a separate component in the example in FIG. 1 , in other embodiments, it may also be incorporated into the ECC circuit 134. In some embodiments, the error monitoring circuit 136 may be incorporated into the controller 106. In other words, the controller 106 may implement all functions of the error monitoring circuit 136.

[0039] The storage device 114 stores, among other things, an error table 138 and a repair table 142. In another example, the storage device 114 is a random-access memory (RAM). It should be noted that other types of storage devices may also be used. It should be noted that the storage device 114 may also be a separate component external to the controller 106.

[0040] The repair circuit 140 is coupled to the controller 106, the error monitoring circuit 136, and the I / O circuit 132. The repair circuit 140 is configured to replace the storage cell corresponding to the failed bit (i.e., the failed cell) with a backup storage cell based on the error table 138 and / or the repair table 142 to prevent a serious error from occurring. Figure 4 , Figure 5A , Figure 5B , FIG. 8A to FIG. 8C as well as Fig. 9 The operation of the repair circuit 140 is described in detail.

[0041] Figure 2 is an example error table 138 according to some embodiments. Figure 3 3 is a flow chart illustrating a method 300 of updating an error table according to some embodiments. Generally speaking, an error table is a table that records both the memory addresses of failed cells and the count of data errors (i.e., failure counts) for each failed cell as described above. Maintaining the error table in real time (i.e., recording the memory addresses of failed cells and the associated failure counts) helps to better understand the status of memory cells in a memory cell array.

[0042] exist Figure 2In the example illustrated in FIG. 1 , the error table 138 includes two columns. The first column 202 includes the addresses of the failed cells, and the second column 204 includes the failure counts of those failed cells. The illustrated error table 138 includes different entries 206, each of which corresponds to a failed cell. In the example error table 138, there are eleven entries 206-1 through 206-11 (collectively 206), meaning that a total of eleven failed bits have been monitored so far. For example, entry 206-5 corresponds to a failed bit (i.e., a failed cell) with address A5, and the failure count is N5 (e.g., 2), meaning that the failed bit has failed twice.

[0043] It should be noted that the error table 138 is a dynamic table that is updated in real time, which will be referred to below. Figure 3 When the memory device starts to function (e.g., immediately after a factory reset), the error table 138 may have very limited (e.g., only one) entries 206 or even be completely empty or vacant (i.e., no entries 206). After a while of functioning, the error table 138 may have more (e.g., Figure 2 As shown in FIG. 11 , there are eleven entries 206, which means that there are more failed bits. In other words, errors accumulate over time.

[0044] Reference Figure 3 , the method 300 starts at step 302. At step 302, the ECC circuit 134 is monitored by the error monitoring circuit 136. In one embodiment, the error monitoring circuit 136 monitors the ECC circuit 134. For example, the syndrome generator of the ECC circuit 134 may be specifically monitored. Subsequently, the method 300 proceeds to step 304, where the error monitoring circuit 136 determines whether there is a faulty bit. In one embodiment, when the ECC circuit 134 detects an error, the associated data bit is marked as a faulty bit. As explained above, the ECC circuit 134 can detect errors by calculating a syndrome, and the calculation of the syndrome is performed by a syndrome calculation circuit. Thus, the error monitoring circuit 136 can determine whether there is a faulty bit. When the error monitoring circuit 136 detects that the syndrome is equal to zero, the error monitoring circuit 136 determines that there is no faulty bit. When the error monitoring circuit 136 detects that the syndrome is not equal to zero, the error monitoring circuit 136 determines that there is a faulty bit. It should be noted that although the ECC scheme used for the above example is based on Hamming codes, other error detection schemes (eg, triple modular redundancy) are also within the scope of the present disclosure.

[0045] When the error monitoring circuit 136 determines at step 304 that there is no faulty bit, the method 300 loops back to step 302. Thus, the error monitoring circuit 136 keeps monitoring any faulty bits in real time. On the other hand, when the error monitoring circuit 136 determines at step 304 that there is a faulty bit, the method 300 proceeds to step 306. At step 306, the address of the faulty bit is determined. In one embodiment, the address of the faulty bit is determined by the ECC circuit 134 during the error correction process. For example, the error correction code is a Hamming or Hsiao code that provides single-bit error correction and double-bit error detection (i.e., the DED / SEC scheme as mentioned above). Other schemes may also be used, such as the DED / DEC scheme as mentioned above, the SED / SEC scheme as mentioned above, and the Reed-Solomon error correction code. In one embodiment, the error monitoring circuit 136 accesses the address of the faulty bit from the ECC circuit 134. In one embodiment, ECC circuit 134 passes along the address of the failed bit to error monitoring circuit 136 .

[0046] The method 300 then proceeds to step 308. At step 308, it is determined whether the address is in the error table 138. In one embodiment, the error monitoring circuit 136 passes along the address of the fault bit to the controller 106, and the controller 106 in turn determines whether the address of the fault bit is in the error table 138 by checking the error table 138 stored in the memory device 114.

[0047] When it is determined that the address of the faulty bit (i.e., the faulty cell) is in the error table (i.e., the existing faulty bit is in the error table), the method 300 proceeds to step 310. At step 310, the fault count of the faulty bit is increased by one. For example, when the address "A11" is in the error table 138, the fault count of the faulty bit is increased by one (i.e., from "N11" to "N11 plus one"). On the other hand, when it is determined that the address of the faulty bit is not in the error table (i.e., the new faulty bit is in the error table), the method 300 proceeds to step 312. At step 312, a new entry is added, and the new entry includes the address of the faulty bit (i.e., the faulty cell) and the fault count of one. For example, when the address "A12" is not in the error table 138, the new entry is added to the error table 138. The new entry, not shown, includes the address "A12" and the fault count of 1.

[0048] After either step 310 or step 312, method 300 loops back to step 302 where error monitoring circuit 136 monitors ECC circuit 134. Thus, error monitoring circuit 136 keeps monitoring any failed bits in real time and updates error table 138 accordingly.

[0049] Figure 4is a flow chart illustrating a method 400 of dynamic error monitoring and repair according to some embodiments. Figure 5A is a schematic diagram illustrating a memory cell array 102 with dynamic error monitoring and repair prior to any replacement in accordance with some embodiments. Figure 5B is a diagram showing the implementation of some embodiments Figure 4 Method 400 after Figure 5A 1 is a schematic diagram of a memory cell array 102. Generally speaking, the error table 138 is used for dynamic error monitoring and repair. When the fault count of a certain fault bit is higher than the threshold fault number, the associated faulty cell is replaced with a backup cell. In other words, the faulty cell is no longer used to store data, and the faulty cell is replaced by a backup storage cell.

[0050] The method 400 starts at step 402. At step 402, it is determined whether there are any fault counts above a threshold fault count. In one embodiment, the controller 106 reads all entries 206 of the error table 138 and compares all fault counts in the second column 204 of the error table 138 to a threshold fault number. In one non-limiting example, the threshold fault number is two. In another example, the threshold fault number is three. In yet another example, the threshold fault number is ten.

[0051] When there is no fault count above the threshold fault count, step 402 loops back to step 402. Thus, the controller 106 keeps monitoring any fault count above the threshold fault count. On the other hand, when there is a fault count above the threshold fault count, the method 400 proceeds to step 404. At step 404, the faulty cell corresponding to the fault count above the threshold fault count is replaced with a backup storage cell. Details of the implementation of step 404 are described below with reference to Figure 5A and Figure 5B Description. A failed cell corresponding to a failure count higher than a threshold failure count is more likely to have a severe failure than a healthy cell and other failed cells having a failure count not exceeding the threshold failure count because a higher failure count indicates a higher risk of an irreversible failure (i.e., a severe failure). Therefore, replacing a failed cell having a failure count higher than the threshold failure count with a backup memory cell can prevent a severe failure from occurring, thereby improving the reliability of the memory device 100.

[0052] refer to Figure 5A , the memory cell array 102 includes a plurality of memory cells 104 arranged in rows and columns. The memory cells 104 include two types: data storage cells 104d and backup storage cells 104b. Figure 5AIn the non-limiting example of FIG. 1 , there are eight backup storage cells 104 b arranged in a row, but other numbers and arrangements are within the scope of the present disclosure. The remaining storage cells 104 are data storage cells 104 d for storing data. Of those data storage cells 104 d, some are healthy and have no faults, and others have failed (i.e., failed cells with a fault count greater than zero). Figure 5A and Figure 2 In the example shown in FIG. 1 , there are eleven data storage cells 104d (ie, having addresses A1 to A11) that have failed in the memory cell array 102. The addresses of these data storage cells 104d are recorded together with the corresponding failure counts in Figure 2 Each of the eleven data storage units 104d has its corresponding fault count. Figure 5A In this example in , none of the eleven failure counts exceed the threshold failure count, and therefore, these cells are used to store data. Therefore, none of the backup storage cells have been used.

[0053] refer to Figure 5B , in this example, the storage cell 104 with address A6 has a failure count (e.g., 4) that exceeds a threshold failure count (e.g., 3). Therefore, the storage cell 104 with address A6 is replaced by the backup storage cell 104b, thereby becoming a replacement storage cell 104r that is not used to store data, and one of the eight backup storage cells 104b (i.e., the storage cell with address Ab1) is replaced with the storage cell 104 with address A6. The data stored in the replacement cell 104r is transferred to the backup storage cell 104b. In one embodiment, the data transfer is implemented using additional storage resources in the storage device 114 as a temporary memory. After the replacement, the previous backup storage cell with address Ab1 becomes the data storage cell 104d, and the previous data storage cell 104d with address A6 is not used to store data. Thus, the failed cell with address A6 is replaced by the backup storage cell 104b, thereby improving the reliability of the memory device 100. In one embodiment, the controller 106 may designate the replacement memory cell 104r as a "replacement memory cell" and designate the backup memory cell 104b used for replacement as "active". After the designation, other components of the memory device 100 (e.g., the control circuit 108 and the command address latch circuit 110) may act accordingly according to the replacement. In one embodiment, the controller 106 may instruct the repair circuit 140 to implement part or all of step 404.

[0054] Fig. 6A is repair table 142a according to some embodiments. Figure 6B is another repair table 142b according to some embodiments. Figure 6C is yet another repair table 142c according to some embodiments. Figure 7 is a flow chart illustrating a method 700 for updating a repair table according to some embodiments. In general, the repair table records replacement storage units 140r and their addresses and fault counts. The repair table may be updated periodically or after the error table is updated. Due to the limited number of backup storage units 104b, the repair table may be "full" (i.e., all backup storage units 104b have been used) after the memory device 100 operates for a certain period of time. Therefore, it may be necessary to update the repair table to replace any existing entries in the repair table with lower fault counts with any new entries with higher fault counts. Thus, according to its capacity (i.e., the number of backup storage units 104b), the repair table always keeps a record of the entry with the highest fault count.

[0055] like Fig. 6A As shown in the example of FIG. 1 , the repair table 142a includes two columns. The first column 602 includes the address of the replacement storage unit 104r, and the second column 604 includes the failure count of the replacement storage unit 104r. The repair table 142a includes different entries 606, each of which corresponds to a replacement storage unit 104r. The repair table 142a has a capacity of M entries 606, and M is the number of backup storage units 104b. Figure 5A In the example shown in FIG. , M is eight. Fig. 6A In this example illustrated in FIG. 1 , the repair table 142 a has seven entries 606 - 1 to 606 - 7 corresponding to seven replacement storage units 104 r , and the entry 606 - 8 is empty. In other words, the repair table 142 a is not “completely full.”

[0056] like Figure 6B As shown in the example in Fig. 6A The repair table 142a becomes the repair table 142b after the data storage unit 104d with address A4 becomes the replacement storage unit 104r. The previously empty entry 606-8 now corresponds to the replacement storage unit 104r with address A4 and failure count N4. The repair table 142b becomes full, meaning that all backup storage units 104b have been used.

[0057] After the repair table 142 becomes full, the repair table 142 may be updated according to Figure 7 The method 700 shown in FIG. Figure 7, method 700 begins at step 702. At step 702, the error table 138 and the repair table 142 are read. In one embodiment, the controller 106 reads both the error table 138 and the repair table 142 stored in the storage device 114. Subsequently, the method 700 proceeds to step 704. At step 704, it is determined whether there are any addresses in the error table 138 but not in the repair table 142 that have a fault count higher than the lowest fault count in the repair table 142. In one embodiment, the controller 106 reads the error table 138 and the repair table 142 stored in the storage device 114. Subsequently, the method 700 proceeds to step 704. At step 704, it is determined whether there are any addresses in the error table 138 but not in the repair table 142 that have a fault count higher than the lowest fault count in the repair table 142. Figure 2 The entry 206 shown in FIG. Figure 6B 142 to determine all addresses that are in the error table 138 but not in the repair table 142 . The controller 106 then compares the corresponding fault count to the lowest fault count in the repair table 142 .

[0058] If it is determined that there is no address in the error table 138 but not in the repair table 142 having a fault count higher than the lowest fault count in the repair table 142, then at the end of the method 700, the method 700 proceeds to step 708. In other words, the repair table 142 does not need to be updated. On the other hand, if it is determined that there is an address in the error table 138 but not in the repair table 142 having a fault count (e.g., five) higher than the lowest fault count (e.g., four) in the repair table 142, then the method 700 proceeds to step 706.

[0059] At step 706, the address with the lowest fault count in the repair table 142 is replaced with the address with the higher fault count in the error table 138. For example, it is determined that address A2 is Figure 2 The error table 138 shown in FIG. Figure 6B In the repair table 142b shown in FIG. 14, and the fault count N2 (eg, five) is higher than the fault count corresponding to Figure 6B The address A10 in the repair table 142b is then replaced with the address A2, as shown in FIG. Figure 6C . The fault count N10 (e.g., four) is also replaced with the fault count N2 (e.g., five). Thus, one entry 606 in the repair table 142b has been updated, and the address (in this example, A10) with the lowest fault count (in this example, N10) is replaced with the address (in this example, A2) with the higher fault count (in this example, N2).

[0060] Then, step 706 loops back to step 702 and method 700 continues until finally ending at step 708. In other words, method 700 continues and searches for all addresses in error table 138 but not in repair table 142 that have a fault count higher than the lowest fault count in the repair table. Figure 6C In the example shown in FIG. 7 , after address A10 is replaced with address A2, address A4 in repair table 142b is replaced with address A5 in the error table. Method 700 ends at step 708. Figure 6C In the example illustrated in , the repair table 142 still has eight entries 606 - 1 to 606 - 8 after the update, but two entries 606 - 7 and 606 - 8 have been updated.

[0061] It should be noted that Figure 7 The method 700 shown in FIG. 1 is a periodic update method. Therefore, multiple (e.g., two) addresses in the repair table 142 may be replaced in one update. It should be noted that the update of the repair table may also be Figure 7 The method 700 is performed in a real-time manner not shown in FIG. 7 (ie, once the error table 138 is updated, the method 700 is implemented).

[0062] Fig. 8A is a flow chart illustrating a method 800 of dynamic error monitoring and repair according to some embodiments. Figure 8B is a diagram showing the implementation of some embodiments Fig. 8A Schematic diagram of memory cell array 102 before method 800 . Figure 8C is a diagram showing the implementation of some embodiments Fig. 8A Methods after 800 Figure 8B Schematic diagram of the memory cell array 102 of FIG. 142. In general, the repair table 142 is used for dynamic error monitoring and repair. When the repair table 142 has any changes after being updated, the replacement memory cell 104r corresponding to the address removed from the repair table 142 is restored (i.e., becomes the data storage cell 104d again), thereby releasing one backup memory cell 104b. The data storage cell 104d corresponding to the address added to the repair table 142 is replaced by the released backup memory cell 104b.

[0063] Method 800 begins at step 802. At step 802, an updated repair table and a previous repair table are read. In one example, controller 106 reads the updated repair table (e.g., Figure 6C Repair table 142c) and previous repair table (e.g., Figure 6B Then, the method 800 proceeds to step 804. At step 804, the updated repair table is compared with the previous repair table to determine the addresses added to the updated repair table and the addresses removed from the updated table. Figure 6B and Figure 6C In the example illustrated in FIG. 1 , the addresses added to the updated repair table 142 c are A2 and A5 , while the addresses removed from the updated repair table 142 c are A10 and A4 , respectively.

[0064] Then, the method 800 proceeds to step 806. At step 806, the address corresponding to the address removed from the updated repair table 142c (in this example, Figure 8B The replacement storage unit 104r of A10 and A4 (shown in FIG. 1 ) is restored, and the corresponding backup storage unit (in this example, Figure 8B In other words, the backup storage unit 104d with address Ab7 and address Ab8 shown in FIG. 142 is released. In other words, the address corresponding to the address removed from the updated repair table 142c (in this example, Figure 8B The replacement storage unit 104r of A10 and A4) shown in FIG. 1 becomes the data storage unit 104d again for data storage, such as Figure 8C As shown in FIG. 1 , the backup storage unit 104 b (in this example, Figure 8B The backup storage unit 104b with address Ab7 and address Ab8 shown in FIG. 1 is released to become the backup storage unit 104b which can be used to replace other data storage units 104d later.

[0065] Then, the method 800 proceeds to step 808. At step 808, the address corresponding to the address added to the updated repair table 142c (in this example, Figure 8C The data storage unit 104d of A2 and A5 shown in FIG. 1 is used to release the backup storage unit 104b (in this example, as shown in FIG. 1 ). Figure 8C In other words, the address corresponding to the address added to the updated repair table 142c (in this example, as shown in FIG. Figure 8C The data storage unit 104d shown in A2 and A5 in FIG. 1 becomes as follows Figure 8C The replacement storage unit 104r shown in FIG. 1 and the backup storage unit 104b (in this example, Figure 8B The backup storage unit 104b with address Ab7 and address Ab8 shown in FIG. 1 becomes the data storage unit 104d again. Therefore, after implementing the method 800, Figure 8B The memory cell array 102 becomes Figure 8C The memory cell array 102 of FIG. 10 is a memory cell with an address A10 that becomes the data storage cell 104d, and the memory cell with an address A2 that becomes the replacement memory cell 104r. Similarly, the memory cell with an address A4 that becomes the data storage cell 104d, and the memory cell with an address A5 that becomes the replacement memory cell 104r. Therefore, based on Figure 6C Dynamic error monitoring and repair is performed by implementing method 800 by updating repair table 142 c which is updated to keep a record of the entry with the highest fault count.

[0066] Fig. 9 is a flow chart of a method 900 of dynamic error monitoring and repair according to some embodiments. In general, a repair table is generated / updated periodically and has M (i.e., the capacity of the repair table and the number of backup storage units) entries corresponding to the M addresses with the highest M fault counts in the error table. Therefore, the repair table always has M entries with the highest M fault counts after each update. Subsequently, dynamic error monitoring and repair are performed based on the repair table. Thus, the backup storage units are periodically released and used to replace the data storage units with the highest M fault counts (i.e., the M data storage units are most likely to have serious faults).

[0067] Method 900 begins at step 902. At step 902, an error table is read. In one embodiment, controller 106 reads error table 138 stored in storage device 114. Error table 138 may be Figure 2 The error table 138 is based on Figure 3 The method 300 is then updated. Subsequently, the method 900 proceeds to step 904. At step 904, the M addresses with the highest M fault counts are determined. In one embodiment, the controller 106 determines the addresses with Figure 2 In one non-limiting example, the determination can be made by looking at the M (e.g., eight) addresses of the highest M (e.g., eight) fault counts in the error table 138. Figure 2 Sorting the fault counts in the second column 204 of the error table 138 is accomplished.

[0068] Subsequently, the method 900 proceeds to step 906. At step 906, a repair table having M addresses and corresponding M fault counts is created. In one embodiment, the controller 106 overwrites the previous repair table (if any) with the M (e.g., eight) addresses and corresponding M (e.g., eight) fault counts determined at step 904. In another embodiment, the storage device 114 may store a plurality of repair tables 142, and the controller generates a new repair table 142 at step 906. By storing a plurality of repair tables 142, the repair history is archived and can be traced back later for purposes such as diagnosis and decision making.

[0069] Then, the method 900 proceeds to step 908. At step 908, the M backup storage units are used to generate M storage units corresponding to the M addresses in the repair table at step 906. In one embodiment, the controller 106 and / or the repair circuit 140 may implement a method similar to Fig. 8A Specifically, the controller 106 and / or the repair circuit 140 may restore all replacement storage cells 104r and release all backup storage cells 104b (after the restore and release operations, the storage cell array may look like Figure 5A Subsequently, the controller 106 and / or the repair circuit 140 may use M (eg, eight) released backup memory cells 104 b (eg, Figure 5A The eight backup storage units 104b) of FIG. 1 replace the M (e.g., eight) storage units 104d corresponding to the M (e.g., eight) addresses in the repair table 142. Therefore, the repair table 142 is periodically generated based on the error table 138, and dynamic error monitoring and repair are performed by implementing the method 900.

[0070] According to some disclosed embodiments, a memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells, the plurality of memory cells including a plurality of data storage cells including a first data storage cell and a plurality of backup storage cells including a first backup storage cell; a storage device storing an error table configured to record errors associated with the plurality of data storage cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data storage cells and having an address and a failure count; and a controller configured to replace the first data storage cell with the first backup storage cell based on the error table.

[0071] In a related embodiment, the plurality of memory cells are one of: ferroelectric random access memory cells, magnetic random access memory cells, resistive random access memory cells, and phase change memory cells.

[0072] In a related embodiment, the controller is configured to replace the first data storage unit when the failure count of the first data storage unit is above a threshold failure count.

[0073] In a related embodiment, the plurality of backup storage units are M backup storage units, M being an integer greater than one, and wherein the controller is configured to replace the M data storage units having the highest M failure counts with the M backup storage units.

[0074] In a related embodiment, replacing the first data storage unit with the first backup storage unit includes: transferring data stored in the first data storage unit to the first backup storage unit; and designating the first data storage unit as a replacement storage unit.

[0075] In a related embodiment, the memory device further includes an error correction code circuit configured to detect the errors in the plurality of data storage units.

[0076] In a related embodiment, the memory device further includes: a repair circuit configured to receive an instruction from the controller and replace the first data storage unit with the first backup storage unit according to the instruction.

[0077] According to some disclosed embodiments, another memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells, the plurality of memory cells including a plurality of data storage cells and M backup storage cells, M being an integer greater than one; a storage device storing a repair table, wherein the repair table includes M repair table entries corresponding to the M data storage cells replaced by the M backup storage cells, each repair table entry having an address and a fault count; and a controller configured to: update the repair table to generate an updated repair table; and replace at least one of the M data storage cells with at least one of the M backup storage cells based on the updated repair table.

[0078] In a related embodiment, the storage device is configured to store an error table, the error table is configured to record errors in the multiple data storage units, the error table includes multiple error table entries, each error table entry corresponds to one of the multiple data storage units and has an address and a fault count, and wherein updating the repair table is based on the error table and the repair table.

[0079] In a related embodiment, the plurality of memory cells are one of: ferroelectric random access memory cells, magnetic random access memory cells, resistive random access memory cells, and phase change memory cells.

[0080] In a related embodiment, updating the repair table based on the error table and the repair table includes: determining a first address, the first address is in the error table but not in the repair table, a first fault count corresponding to the first address is higher than a lowest fault count in the repair table, and the lowest fault count corresponds to a second address; and replacing the second address and the lowest fault count with the first address and the first fault count, respectively.

[0081] In a related embodiment, the repair table is updated periodically.

[0082] In a related embodiment, the repair table is updated once the error table is updated.

[0083] In a related embodiment, replacing at least one of the M data storage units with at least one of the M backup storage units based on the updated repair table includes: comparing the updated repair table with the repair table to determine a third address added to the updated repair table and a fourth address removed from the updated repair table; restoring the fourth storage unit with the fourth address and replacing the fourth storage unit with the first backup storage unit; releasing the first backup storage unit; and replacing the third storage unit having the third address with the first backup storage unit.

[0084] In a related embodiment, replacing the third storage unit with the first backup storage unit includes: transferring data stored in the third storage unit to the first backup storage unit; and designating the third storage unit as a replacement storage unit.

[0085] In a related embodiment, the memory device further includes an error correction code circuit configured to detect the errors in the plurality of data storage units.

[0086] According to another disclosed embodiment, a method for dynamic error monitoring and repair is provided. The method includes: providing a storage cell array including a plurality of storage cells, the plurality of storage cells including a plurality of data storage cells and a plurality of backup storage cells; detecting errors in the plurality of data storage cells by an ECC circuit; generating an error table, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data storage cells and having an address and a failure count; and replacing a first data storage cell among the plurality of data storage cells with a first backup storage cell among the plurality of backup storage cells based on the error table.

[0087] In a related embodiment, replacing the first data storage unit with the first backup storage unit based on the error table includes replacing the first data storage unit with the first backup storage unit when the failure count of the first data storage unit is above a threshold failure count.

[0088] In a related embodiment, replacing the first data storage unit with the first backup storage unit based on the error table includes: when the fault count of the first data storage unit is among the highest M fault counts, replacing the first data storage unit with the first backup storage unit, M being the number of the multiple backup storage units.

[0089] In a related embodiment, the plurality of memory cells are one of: ferroelectric random access memory cells, magnetic random access memory cells, resistive random access memory cells, and phase change memory cells.

[0090] The present disclosure summarizes various embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: A storage unit array, comprising a plurality of storage units, wherein the plurality of storage units include a plurality of data storage units and a plurality of backup storage units, wherein the plurality of data storage units are actively used to store data, and the plurality of backup storage units are inactively used to store data; a storage device storing an error table configured to record errors associated with the plurality of data storage units, the error table comprising a plurality of error table entries, each error table entry corresponding to one of the plurality of data storage units and having an address and a failure count; as well as The controller is configured to, in response to determining from the error table that a fault count of the data storage unit is higher than a threshold fault count: transferring the data stored in the data storage unit to the backup storage unit; designating the data storage unit as a deactivated data storage unit among the plurality of backup storage units, wherein the deactivated data storage unit is inactively used to store data; as well as designating the backup storage unit as an activated data storage unit of the plurality of data storage units, wherein the activated data storage unit is actively used to store data, wherein the storage device further stores a repair table configured to record errors associated with one or more deactivated data storage units, the repair table comprising a plurality of repair table entries, each repair table entry corresponding to a deactivated data storage unit and having an address and a failure count, and The controller is configured, in response to determining that the error table entry has a higher fault count than the repair table entry: designating the deactivated data storage unit associated with the repair table entry as a restored data storage unit among the plurality of data storage units; designating the data storage unit associated with the error table entry as a deactivated data storage unit belonging to the plurality of backup storage units; as well as The repair table is updated by replacing the repair table entry with the error table entry. 2 . The memory device of claim 1 , wherein the plurality of memory cells are one of: a ferroelectric random access memory cell, a magnetic random access memory cell, a resistive random access memory cell, and a phase change memory cell. 3 . The memory device of claim 1 , wherein the repair table has a plurality of entries corresponding to the number of the plurality of backup storage units.

4. The memory device of claim 1 , wherein the plurality of backup memory cells are M backup memory cells, M being an integer greater than 1, and wherein the controller is configured to replace M data storage cells having the highest M failure counts with the M backup memory cells.

5. The memory device according to claim 1, further comprising: An error correction code circuit is configured to detect the errors in the plurality of data storage cells.

6. The memory device according to claim 1, further comprising: The repair circuit is configured to receive an instruction from the controller and replace the data storage unit with the backup storage unit according to the instruction.

7. A memory device comprising: A storage unit array, comprising a plurality of storage units, the plurality of storage units comprising a plurality of data storage units and M backup storage units, M being an integer greater than one, wherein the plurality of data storage units are actively used to store data, and the M backup storage units are inactively used to store data; A storage device storing a repair table, wherein the repair table comprises M repair table entries, each repair table entry corresponds to a previous data storage unit replaced by a backup storage unit and changed to a deactivated data storage unit belonging to the plurality of backup storage units, each repair table entry having an address and a failure count, wherein the deactivated data storage unit is inactively used to store data; as well as The controller is configured to, in response to determining that the repair table entry has a fault count lower than the fault count of the data storage unit: designating a deactivated data storage unit associated with the repair table entry as a restored data storage unit among the plurality of data storage units; designating the data storage unit associated with the repair table entry as a deactivated data storage unit belonging to the plurality of backup storage units; as well as updating the repair table to indicate the address and the failure count of the data storage unit, wherein the storage device is configured to store an error table, the error table being configured to record errors of the plurality of data storage units, the error table comprising a plurality of error table entries, each error table entry corresponding to one of the plurality of data storage units and having an address and a failure count, and the controller is configured to update the repair table in response to determining that the repair table entry has a failure count lower than the failure count of the data error table entry, wherein the controller is configured to, in response to determining that the repair table entry has the fault count lower than the fault count of the data error table entry, determining a first address, the first address being in the error table but not in the repair table, a first fault count corresponding to the first address being higher than a lowest fault count in the repair table, the lowest fault count corresponding to a second address; as well as The controller is configured to update the repair table by: The second address and the lowest fail count are replaced with the first address and the first fail count, respectively. 8 . The memory device of claim 7 , wherein the plurality of memory cells are one of: a ferroelectric random access memory cell, a magnetic random access memory cell, a resistive random access memory cell, and a phase change memory cell.

9. The memory device of claim 7, wherein the repair table is updated periodically.

10. The memory device of claim 7, wherein the repair table is updated once the error table is updated.

11. The memory device of claim 7, wherein the controller is configured to generate the repair table based on M data storage cells having the highest failure counts. 12 . The memory device of claim 11 , wherein the repair table is configured to store a maximum of M repair table entries, which are limited according to M backup memory cells of the memory cell array.

13. The memory device according to claim 7, further comprising: An error correction code circuit is configured to detect the errors in the plurality of data storage cells.

14. A method for dynamic error monitoring and repair, comprising: Providing a storage unit array including a plurality of storage units, the plurality of storage units including a plurality of data storage units and a plurality of backup storage units; detecting errors in the plurality of data storage cells by an error correction code circuit; generating an error table, the error table comprising a plurality of error table entries, each error table entry corresponding to one of the plurality of data storage units and having an address and a failure count; as well as In response to determining from the error table that the fault count of the data storage unit is above a threshold fault count: transferring the data stored in the data storage unit to the backup storage unit; designating the data storage unit as a deactivated data storage unit belonging to the plurality of backup storage units; designating the backup storage unit as an activated data storage unit belonging to the plurality of data storage units, wherein the activated data storage unit is actively used to store data; generating a repair table, the repair table comprising a plurality of repair table entries, each repair table entry corresponding to a de-initialized data storage unit and having an address and a fault count; In response to determining that the error table entry has a higher fault count than the repair table entry: designating the deactivated data storage unit associated with the repair table entry as a restored data storage unit belonging to the plurality of data storage units; designating the data storage unit associated with the error table entry as a deactivated data storage unit belonging to the plurality of backup storage units; as well as The repair table is updated by replacing the repair table entry with the error table entry.

15. The method of claim 14, wherein the repair table has a plurality of entries corresponding to the number of the plurality of backup storage units.

16. The method of claim 14, wherein the plurality of memory cells are one of: a ferroelectric random access memory cell, a magnetic random access memory cell, a resistive random access memory cell, and a phase change memory cell.

Images